* [0/5] Introduce drm sharpening property
@ 2024-07-08 8:09 Nemesa Garg
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural details.
Intel has come up with Display Engine based adaptive sharpening filter
with minimal power and performance impact. From LNL onwards, the Display
hardware can use one of the pipe scaler for adaptive sharpness filter.
This can be used for both gaming and non-gaming use cases like photos,
image viewing. It works on a region of pixels depending on the tap size.
This is an attempt to introduce an adaptive sharpness solution which
helps in improving the image quality. For this new CRTC property is added.
The user can set this property with desired sharpness strength value with
0-255. A value of 1 representing minimum sharpening strength and 255
representing maximum sharpness strength. A strength value of 0 means no
sharpening or sharpening feature disabled.
It works on a region of pixels depending on the tap size. The coefficients
are used to generate an alpha value which is used to blend the sharpened
image to original image.
Middleware MR link: https://gitlab.gnome.org/GNOME/mutter/-/merge_requests/3665
IGT patchwork link: https://patchwork.freedesktop.org/series/130218/
--v3: Added uapi documentation.
Made sharpness word consistent.
Nemesa Garg (5):
drm: Introduce sharpness mode property
drm/i915/display: Compute the scaler filter coefficients
drm/i915/display: Enable the second scaler for sharpness
drm/i915/display: Add registers and compute the strength
drm/i915/display: Load the lut values and enable sharpness
drivers/gpu/drm/drm_atomic_uapi.c | 4 +
drivers/gpu/drm/drm_crtc.c | 35 +++
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 21 +-
.../drm/i915/display/intel_display_types.h | 11 +
.../drm/i915/display/intel_modeset_verify.c | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 4 +-
.../drm/i915/display/intel_sharpen_filter.c | 236 ++++++++++++++++++
.../drm/i915/display/intel_sharpen_filter.h | 33 +++
drivers/gpu/drm/i915/display/skl_scaler.c | 97 ++++++-
drivers/gpu/drm/i915/display/skl_scaler.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 19 ++
drivers/gpu/drm/xe/Makefile | 1 +
include/drm/drm_crtc.h | 17 ++
15 files changed, 470 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.c
create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.h
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [1/5] drm: Introduce sharpness mode property
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
@ 2024-07-08 8:09 ` Nemesa Garg
2024-08-29 8:33 ` Murthy, Arun R
2024-09-04 9:19 ` Shankar, Uma
2024-07-08 8:09 ` [v4 2/5] drm/i915/display: Compute the scaler filter coefficients Nemesa Garg
` (7 subsequent siblings)
8 siblings, 2 replies; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
sharpness level depending on the content displayed.
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++
drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++
include/drm/drm_crtc.h | 17 +++++++++++++++
3 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 22bbb2d83e30..825640ab39f6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
set_out_fence_for_crtc(state->state, crtc, fence_ptr);
} else if (property == crtc->scaling_filter_property) {
state->scaling_filter = val;
+ } else if (property == crtc->sharpness_strength_prop) {
+ state->sharpness_strength = val;
} else if (crtc->funcs->atomic_set_property) {
return crtc->funcs->atomic_set_property(crtc, state, property, val);
} else {
@@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = 0;
else if (property == crtc->scaling_filter_property)
*val = state->scaling_filter;
+ else if (property == crtc->sharpness_strength_prop)
+ *val = state->sharpness_strength;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property, val);
else {
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3488ff067c69..4ff18786a226 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -229,6 +229,24 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc)
* Driver's default scaling filter
* Nearest Neighbor:
* Nearest Neighbor scaling filter
+ * SHARPNESS_STRENGTH:
+ * Atomic property for setting the sharpness strength/intensity by userspace.
+ *
+ * The value of this property is set as an integer value ranging
+ * from 0 - 255 where:
+ *
+ * 0 means feature is disabled.
+ *
+ * 1 means minimum sharpness.
+ *
+ * 255 means maximum sharpness.
+ *
+ * User can gradually increase or decrease the sharpness level and can
+ * set the optimum value depending on content and this value will be
+ * passed to kernel through the Uapi.
+ * The sharpness effect takes place post blending on the final composed output.
+ * If the feature is disabled, the content remains same without any sharpening effect
+ * and when this feature is applied, it enhances the clarity of the content.
*/
__printf(6, 0)
@@ -939,3 +957,20 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
return 0;
}
EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
+
+int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+
+ struct drm_property *prop =
+ drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255);
+
+ if (!prop)
+ return -ENOMEM;
+
+ crtc->sharpness_strength_prop = prop;
+ drm_object_attach_property(&crtc->base, prop, 0);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8b48a1974da3..1cdca5c82753 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -317,6 +317,16 @@ struct drm_crtc_state {
*/
enum drm_scaling_filter scaling_filter;
+ /**
+ * @sharpness_strength
+ *
+ * Used by the user to set the sharpness intensity.
+ * The value ranges from 0-255.
+ * Any value greater than 0 means enabling the featuring
+ * along with setting the value for sharpness.
+ */
+ u8 sharpness_strength;
+
/**
* @event:
*
@@ -1088,6 +1098,12 @@ struct drm_crtc {
*/
struct drm_property *scaling_filter_property;
+ /**
+ * @sharpness_strength_prop: property to apply
+ * the intensity of the sharpness requested.
+ */
+ struct drm_property *sharpness_strength_prop;
+
/**
* @state:
*
@@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
unsigned int supported_filters);
+int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc);
#endif /* __DRM_CRTC_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
@ 2024-07-08 8:09 ` Nemesa Garg
2024-08-29 9:04 ` Murthy, Arun R
2024-07-08 8:09 ` [3/5] drm/i915/display: Enable the second scaler for sharpness Nemesa Garg
` (6 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 9091 bytes --]
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.
--v4: fix ifndef header naming issue reported by kernel test robot
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +
.../drm/i915/display/intel_display_types.h | 9 ++
.../drm/i915/display/intel_sharpen_filter.c | 121 ++++++++++++++++++
.../drm/i915/display/intel_sharpen_filter.h | 27 ++++
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/xe/Makefile | 1 +
7 files changed, 163 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.c
create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c63fa2133ccb..0021f0a372ab 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -280,6 +280,7 @@ i915-y += \
display/intel_pmdemand.o \
display/intel_psr.o \
display/intel_quirks.o \
+ display/intel_sharpen_filter.o \
display/intel_sprite.o \
display/intel_sprite_uapi.o \
display/intel_tc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c2c388212e2e..a62560a0c1a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5906,6 +5906,8 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
if (ret)
return ret;
+ intel_sharpness_scaler_compute_config(new_crtc_state);
+
/*
* On some platforms the number of active planes affects
* the planes' minimum cdclk calculation. Add such planes
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8713835e2307..1c3e031ab369 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -55,6 +55,7 @@
#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_dpll_mgr.h"
+#include "intel_sharpen_filter.h"
#include "intel_wm_types.h"
struct drm_printer;
@@ -828,6 +829,13 @@ struct intel_scaler {
u32 mode;
};
+struct intel_sharpness_filter {
+ struct scaler_filter_coeff coeff[7];
+ u32 scaler_coefficient[119];
+ bool strength_changed;
+ u8 win_size;
+};
+
struct intel_crtc_scaler_state {
#define SKL_NUM_SCALERS 2
struct intel_scaler scalers[SKL_NUM_SCALERS];
@@ -1072,6 +1080,7 @@ struct intel_crtc_state {
struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
struct drm_display_mode mode, pipe_mode, adjusted_mode;
enum drm_scaling_filter scaling_filter;
+ struct intel_sharpness_filter casf_params;
} hw;
/* actual state of LUTs */
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
new file mode 100644
index 000000000000..b3ebd72b4116
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ *
+ */
+
+#include "i915_reg.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "skl_scaler.h"
+
+#define MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER 7
+#define SCALER_FILTER_NUM_TAPS 7
+#define SCALER_FILTER_NUM_PHASES 17
+#define FILTER_COEFF_0_125 125
+#define FILTER_COEFF_0_25 250
+#define FILTER_COEFF_0_5 500
+#define FILTER_COEFF_1_0 1000
+#define FILTER_COEFF_0_0 0
+
+void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int id = crtc_state->scaler_state.scaler_id;
+
+ intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
+ PS_COEF_INDEX_AUTO_INC);
+
+ intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 1),
+ PS_COEF_INDEX_AUTO_INC);
+
+ for (int index = 0; index < 60; index++) {
+ intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0),
+ crtc_state->hw.casf_params.scaler_coefficient[index]);
+ intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1),
+ crtc_state->hw.casf_params. scaler_coefficient[index]);
+ }
+}
+
+static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
+ u16 coefficient)
+{
+ if (coefficient < 25) {
+ coeff->mantissa = (coefficient * 2048) / 100;
+ coeff->exp = 3;
+ }
+
+ else if (coefficient < 50) {
+ coeff->mantissa = (coefficient * 1024) / 100;
+ coeff->exp = 2;
+ }
+
+ else if (coefficient < 100) {
+ coeff->mantissa = (coefficient * 512) / 100;
+ coeff->exp = 1;
+ } else {
+ coeff->mantissa = (coefficient * 256) / 100;
+ coeff->exp = 0;
+ }
+}
+
+static void intel_sharpness_filter_coeff(struct intel_crtc_state *crtc_state)
+{
+ u16 filtercoeff[MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER];
+ u16 sumcoeff = 0;
+ u8 i;
+
+ if (crtc_state->hw.casf_params.win_size == 0) {
+ filtercoeff[0] = FILTER_COEFF_0_0;
+ filtercoeff[1] = FILTER_COEFF_0_0;
+ filtercoeff[2] = FILTER_COEFF_0_5;
+ filtercoeff[3] = FILTER_COEFF_1_0;
+ filtercoeff[4] = FILTER_COEFF_0_5;
+ filtercoeff[5] = FILTER_COEFF_0_0;
+ filtercoeff[6] = FILTER_COEFF_0_0;
+ }
+
+ else if (crtc_state->hw.casf_params.win_size == 1) {
+ filtercoeff[0] = FILTER_COEFF_0_0;
+ filtercoeff[1] = FILTER_COEFF_0_25;
+ filtercoeff[2] = FILTER_COEFF_0_5;
+ filtercoeff[3] = FILTER_COEFF_1_0;
+ filtercoeff[4] = FILTER_COEFF_0_5;
+ filtercoeff[5] = FILTER_COEFF_0_25;
+ filtercoeff[6] = FILTER_COEFF_0_0;
+ } else {
+ filtercoeff[0] = FILTER_COEFF_0_125;
+ filtercoeff[1] = FILTER_COEFF_0_25;
+ filtercoeff[2] = FILTER_COEFF_0_5;
+ filtercoeff[3] = FILTER_COEFF_1_0;
+ filtercoeff[4] = FILTER_COEFF_0_5;
+ filtercoeff[5] = FILTER_COEFF_0_25;
+ filtercoeff[6] = FILTER_COEFF_0_125;
+ }
+
+ for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++)
+ sumcoeff += filtercoeff[i];
+
+ for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++) {
+ filtercoeff[i] = (filtercoeff[i] * 100 / sumcoeff);
+ convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i],
+ filtercoeff[i]);
+ }
+}
+
+void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state)
+{
+ u16 phase, tapindex, phaseoffset;
+ u16 *coeff = (u16 *)crtc_state->hw.casf_params.scaler_coefficient;
+
+ intel_sharpness_filter_coeff(crtc_state);
+
+ for (phase = 0; phase < SCALER_FILTER_NUM_PHASES; phase++) {
+ phaseoffset = SCALER_FILTER_NUM_TAPS * phase;
+ for (tapindex = 0; tapindex < SCALER_FILTER_NUM_TAPS; tapindex++) {
+ coeff[phaseoffset + tapindex] =
+ SHARP_COEFF_TO_REG_FORMAT(crtc_state->hw.casf_params.coeff[tapindex]);
+ }
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
new file mode 100644
index 000000000000..6ab70a635e2f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_SHARPEN_FILTER_H__
+#define __INTEL_SHARPEN_FILTER_H__
+
+#include <linux/types.h>
+
+#define SHARP_COEFF_TO_REG_FORMAT(coefficient) ((u16)(coefficient.sign << 15 | \
+ coefficient.exp << 12 | coefficient.mantissa << 3))
+
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_atomic_state;
+
+struct scaler_filter_coeff {
+ u16 sign;
+ u16 exp;
+ u16 mantissa;
+};
+
+void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state);
+void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_SHARPEN_FILTER_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e3d79227e3c..9492fda15627 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2257,6 +2257,8 @@
#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
#define PS_PWRUP_PROGRESS REG_BIT(17)
+#define PS_BYPASS_ARMING REG_BIT(10)
+#define PS_DB_STALL REG_BIT(9)
#define PS_V_FILTER_BYPASS REG_BIT(8)
#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 0eb0acc4f198..8681ca89af27 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -278,6 +278,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_psr.o \
i915-display/intel_qp_tables.o \
i915-display/intel_quirks.o \
+ i915-display/intel_sharpen_filter.o \
i915-display/intel_snps_phy.o \
i915-display/intel_tc.o \
i915-display/intel_vblank.o \
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [3/5] drm/i915/display: Enable the second scaler for sharpness
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
2024-07-08 8:09 ` [v4 2/5] drm/i915/display: Compute the scaler filter coefficients Nemesa Garg
@ 2024-07-08 8:09 ` Nemesa Garg
2024-08-30 4:44 ` Murthy, Arun R
2024-07-08 8:09 ` [4/5] drm/i915/display: Add registers and compute the strength Nemesa Garg
` (5 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
As only second scaler can be used for sharpness check if it
is available and if panel fitting is also not enabled, the
set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Added the panel fitting check before enabling sharpness
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++-
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_modeset_verify.c | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 4 +-
.../drm/i915/display/intel_sharpen_filter.c | 10 +++
.../drm/i915/display/intel_sharpen_filter.h | 1 +
drivers/gpu/drm/i915/display/skl_scaler.c | 84 +++++++++++++++++--
drivers/gpu/drm/i915/display/skl_scaler.h | 1 +
8 files changed, 99 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a62560a0c1a9..385a254528f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2028,7 +2028,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
if (crtc_state->pch_pfit.enabled ||
- crtc_state->pch_pfit.force_thru)
+ crtc_state->pch_pfit.force_thru || crtc_state->hw.casf_params.need_scaler)
set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
drm_for_each_encoder_mask(encoder, &dev_priv->drm,
@@ -2284,7 +2284,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
* PF-ID we'll need to adjust the pixel_rate here.
*/
- if (!crtc_state->pch_pfit.enabled)
+ if (!crtc_state->pch_pfit.enabled || crtc_state->hw.casf_params.need_scaler)
return pixel_rate;
drm_rect_init(&src, 0, 0,
@@ -4295,7 +4295,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 9) {
if (intel_crtc_needs_modeset(crtc_state) ||
- intel_crtc_needs_fastset(crtc_state)) {
+ intel_crtc_needs_fastset(crtc_state) ||
+ crtc_state->hw.casf_params.need_scaler) {
ret = skl_update_scaler_crtc(crtc_state);
if (ret)
return ret;
@@ -5481,6 +5482,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
+ if (pipe_config->uapi.sharpness_strength > 0)
+ PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_LLI
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1c3e031ab369..130740aaaa21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -834,6 +834,7 @@ struct intel_sharpness_filter {
u32 scaler_coefficient[119];
bool strength_changed;
u8 win_size;
+ bool need_scaler;
};
struct intel_crtc_scaler_state {
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 3491db5cad31..ed75934bed6b 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -177,6 +177,7 @@ verify_crtc_state(struct intel_atomic_state *state,
crtc->base.name);
hw_crtc_state->hw.enable = sw_crtc_state->hw.enable;
+ hw_crtc_state->hw.casf_params.need_scaler = sw_crtc_state->hw.casf_params.need_scaler;
intel_crtc_get_pipe_config(hw_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 71454ddef20f..bfc725d2e178 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -451,7 +451,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
drm_rect_init(&crtc_state->pch_pfit.dst,
x, y, width, height);
- crtc_state->pch_pfit.enabled = true;
+
+ if (!crtc_state->hw.casf_params.need_scaler)
+ crtc_state->pch_pfit.enabled = true;
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
index b3ebd72b4116..627a0dbd3dfd 100644
--- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
@@ -36,6 +36,16 @@ void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state)
intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1),
crtc_state->hw.casf_params. scaler_coefficient[index]);
}
+
+ casf_scaler_enable(crtc_state);
+}
+
+int intel_filter_compute_config(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->pch_pfit.enabled)
+ crtc_state->hw.casf_params.need_scaler = true;
+
+ return 0;
}
static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
index 6ab70a635e2f..d20e65971a55 100644
--- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
@@ -23,5 +23,6 @@ struct scaler_filter_coeff {
void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state);
void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state);
+int intel_filter_compute_config(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_SHARPEN_FILTER_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index baa601d27815..9d8bc6c0ab2c 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -253,7 +253,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
drm_rect_width(&crtc_state->pipe_src),
drm_rect_height(&crtc_state->pipe_src),
width, height, NULL, 0,
- crtc_state->pch_pfit.enabled);
+ crtc_state->pch_pfit.enabled ||
+ crtc_state->hw.casf_params.need_scaler);
}
/**
@@ -353,9 +354,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
int num_scalers_need, struct intel_crtc *intel_crtc,
const char *name, int idx,
struct intel_plane_state *plane_state,
- int *scaler_id)
+ int *scaler_id, bool casf_scaler)
{
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(intel_crtc->base.state);
int j;
u32 mode;
@@ -365,6 +367,11 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
if (scaler_state->scalers[j].in_use)
continue;
+ if (!strcmp(name, "CRTC")) {
+ if (casf_scaler && j != 1)
+ continue;
+ }
+
*scaler_id = j;
scaler_state->scalers[*scaler_id].in_use = 1;
break;
@@ -375,6 +382,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
"Cannot find scaler for %s:%d\n", name, idx))
return -EINVAL;
+ if (crtc_state->hw.casf_params.need_scaler) {
+ mode = SKL_PS_SCALER_MODE_HQ;
+ }
+
/* set scaler mode */
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
@@ -598,7 +609,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
intel_crtc, name, idx,
- plane_state, scaler_id);
+ plane_state, scaler_id,
+ crtc_state->hw.casf_params.need_scaler);
if (ret < 0)
return ret;
}
@@ -678,6 +690,15 @@ static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
}
+static u32 scaler_filter_select(void)
+{
+ return (PS_FILTER_PROGRAMMED |
+ PS_Y_VERT_FILTER_SELECT(1) |
+ PS_Y_HORZ_FILTER_SELECT(0) |
+ PS_UV_VERT_FILTER_SELECT(1) |
+ PS_UV_HORZ_FILTER_SELECT(0));
+}
+
static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
{
if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
@@ -705,6 +726,48 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
}
}
+void casf_scaler_enable(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ struct intel_crtc_scaler_state *scaler_state =
+ &crtc_state->scaler_state;
+ struct drm_rect src, dest;
+ int id, width, height;
+ int x, y;
+ enum pipe pipe = crtc->pipe;
+ u32 ps_ctrl;
+
+ width = adjusted_mode->crtc_hdisplay;
+ height = adjusted_mode->crtc_vdisplay;
+
+ x = y = 0;
+ drm_rect_init(&dest, x, y, width, height);
+
+ struct drm_rect *dst = &dest;
+
+ x = dst->x1;
+ y = dst->y1;
+ width = drm_rect_width(dst);
+ height = drm_rect_height(dst);
+ id = scaler_state->scaler_id;
+
+ drm_rect_init(&src, 0, 0,
+ drm_rect_width(&crtc_state->pipe_src) << 16,
+ drm_rect_height(&crtc_state->pipe_src) << 16);
+
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
+ PS_BYPASS_ARMING | PS_DB_STALL | scaler_filter_select();
+
+ intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
+ intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
+ PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
+ intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
+ PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
+}
+
void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -875,16 +938,19 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
continue;
id = i;
- crtc_state->pch_pfit.enabled = true;
+
+ if (!crtc_state->hw.casf_params.need_scaler)
+ crtc_state->pch_pfit.enabled = true;
pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
- drm_rect_init(&crtc_state->pch_pfit.dst,
- REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
- REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
- REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
- REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
+ if (!crtc_state->hw.casf_params.need_scaler)
+ drm_rect_init(&crtc_state->pch_pfit.dst,
+ REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
+ REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
scaler_state->scalers[i].in_use = true;
break;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 63f93ca03c89..444527e6a15b 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -33,5 +33,6 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
+void casf_scaler_enable(struct intel_crtc_state *crtc_state);
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [4/5] drm/i915/display: Add registers and compute the strength
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (2 preceding siblings ...)
2024-07-08 8:09 ` [3/5] drm/i915/display: Enable the second scaler for sharpness Nemesa Garg
@ 2024-07-08 8:09 ` Nemesa Garg
2024-08-30 8:04 ` Murthy, Arun R
2024-07-08 8:09 ` [5/5] drm/i915/display: Load the lut values and enable sharpness Nemesa Garg
` (4 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_sharpen_filter.c | 105 ++++++++++++++++++
.../drm/i915/display/intel_sharpen_filter.h | 5 +
drivers/gpu/drm/i915/i915_reg.h | 17 +++
5 files changed, 132 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 385a254528f9..e0a82ab46d29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5910,7 +5910,10 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
if (ret)
return ret;
- intel_sharpness_scaler_compute_config(new_crtc_state);
+ if (sharp_compute(new_crtc_state)) {
+ intel_sharpness_scaler_compute_config(new_crtc_state);
+ intel_filter_compute_config(new_crtc_state);
+ }
/*
* On some platforms the number of active planes affects
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 130740aaaa21..782192f2b9ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -835,6 +835,7 @@ struct intel_sharpness_filter {
bool strength_changed;
u8 win_size;
bool need_scaler;
+ u8 strength;
};
struct intel_crtc_scaler_state {
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
index 627a0dbd3dfd..6600a66d3960 100644
--- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
@@ -18,11 +18,87 @@
#define FILTER_COEFF_1_0 1000
#define FILTER_COEFF_0_0 0
+/*
+ * Default LUT values to be loaded one time.
+ */
+static const u16 lut_data[] = {
+ 4095, 2047, 1364, 1022, 816, 678, 579,
+ 504, 444, 397, 357, 323, 293, 268, 244, 224,
+ 204, 187, 170, 154, 139, 125, 111, 98, 85,
+ 73, 60, 48, 36, 24, 12, 0
+};
+
+void intel_filter_lut_load(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int i;
+
+ intel_de_write(dev_priv, SHRPLUT_INDEX(crtc->pipe), INDEX_AUTO_INCR | INDEX_VALUE(0));
+
+ for (i = 0; i < ARRAY_SIZE(lut_data); i++)
+ intel_de_write(dev_priv, SHRPLUT_DATA(crtc->pipe), lut_data[i]);
+}
+
+static void intel_filter_size_compute(struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode;
+
+ if (mode->hdisplay <= 1920 && mode->vdisplay <= 1080)
+ crtc_state->hw.casf_params.win_size = 0;
+ else if (mode->hdisplay <= 3840 && mode->vdisplay <= 2160)
+ crtc_state->hw.casf_params.win_size = 1;
+ else
+ crtc_state->hw.casf_params.win_size = 2;
+}
+
+bool intel_sharpness_strength_changed(struct intel_atomic_state *state)
+{
+ int i;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_crtc *crtc;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (new_crtc_state->uapi.sharpness_strength !=
+ old_crtc_state->uapi.sharpness_strength)
+ return true;
+ }
+
+ return false;
+}
+
void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int id = crtc_state->scaler_state.scaler_id;
+ u32 sharpness_ctl;
+ u8 val;
+
+ if (crtc_state->uapi.sharpness_strength == 0) {
+ intel_sharpness_disable(crtc_state);
+
+ return;
+ }
+
+ /*
+ * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
+ * Strength is from 0.0-14.9375 ie from 0-239.
+ * User can give value from 0-255 but is clamped to 239.
+ * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
+ * 6.3125 in 4.4 format is 01100101 which is equal to 101.
+ * Also 85 + 16 = 101.
+ */
+ val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
+
+ drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", val);
+
+ sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) |
+ FILTER_SIZE(crtc_state->hw.casf_params.win_size);
+
+ intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe),
+ sharpness_ctl);
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0),
PS_COEF_INDEX_AUTO_INC);
@@ -42,9 +118,21 @@ void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state)
int intel_filter_compute_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+
+ if (crtc_state->uapi.sharpness_strength == 0) {
+ crtc_state->hw.casf_params.need_scaler = false;
+ return 0;
+ }
+
if (!crtc_state->pch_pfit.enabled)
crtc_state->hw.casf_params.need_scaler = true;
+ intel_filter_size_compute(crtc_state);
+ drm_dbg(&dev_priv->drm, "Tap Size: %d\n",
+ crtc_state->hw.casf_params.win_size);
+
return 0;
}
@@ -129,3 +217,20 @@ void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state)
}
}
}
+
+void intel_sharpness_disable(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe), 0);
+ drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", 0);
+}
+
+bool sharp_compute(struct intel_crtc_state *crtc_state)
+{
+ if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0)
+ return true;
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
index d20e65971a55..4fffdd99d0fb 100644
--- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
+++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
@@ -24,5 +24,10 @@ struct scaler_filter_coeff {
void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state);
void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state);
int intel_filter_compute_config(struct intel_crtc_state *crtc_state);
+void intel_filter_lut_load(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+bool intel_sharpness_strength_changed(struct intel_atomic_state *state);
+void intel_sharpness_disable(struct intel_crtc_state *crtc_state);
+bool sharp_compute(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_SHARPEN_FILTER_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9492fda15627..2fa42e10bb63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2396,6 +2396,23 @@
_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
+#define _SHARPNESS_CTL_A 0x682B0
+#define SHARPNESS_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _SHARPNESS_CTL_A)
+#define FILTER_EN REG_BIT(31)
+#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
+#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
+#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
+#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x))
+
+#define _SHRPLUT_DATA_A 0x682B8
+#define SHRPLUT_DATA(trans) _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_DATA_A)
+
+#define _SHRPLUT_INDEX_A 0x682B4
+#define SHRPLUT_INDEX(trans) _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_INDEX_A)
+#define INDEX_AUTO_INCR REG_BIT(10)
+#define INDEX_VALUE_MASK REG_GENMASK(4, 0)
+#define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
+
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [5/5] drm/i915/display: Load the lut values and enable sharpness
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (3 preceding siblings ...)
2024-07-08 8:09 ` [4/5] drm/i915/display: Add registers and compute the strength Nemesa Garg
@ 2024-07-08 8:09 ` Nemesa Garg
2024-07-08 8:49 ` ✗ Fi.CI.CHECKPATCH: warning for Introduce drm sharpening property (rev4) Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Nemesa Garg @ 2024-07-08 8:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Nemesa Garg
Load the lut values during pipe enable.
v2: Add the display version check
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
drivers/gpu/drm/i915/display/skl_scaler.c | 13 ++++++++++++-
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 1b578cad2813..a8aaea0d2932 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -379,6 +379,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
+ if (DISPLAY_VER(dev_priv) >= 20)
+ drm_crtc_create_sharpness_strength_property(&crtc->base);
+
return 0;
fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e0a82ab46d29..7464d5b92b4d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1771,6 +1771,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_crtc_wait_for_next_vblank(wa_crtc);
}
}
+
+ if (new_crtc_state->hw.casf_params.strength_changed)
+ intel_filter_lut_load(crtc, new_crtc_state);
}
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -6918,6 +6921,9 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_vrr_set_transcoder_timings(new_crtc_state);
}
+ if (intel_sharpness_strength_changed(state))
+ intel_sharpness_filter_enable(new_crtc_state);
+
intel_fbc_update(state, crtc);
drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 9d8bc6c0ab2c..be0ad6ce90b2 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -931,7 +931,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
/* find scaler attached to this pipe */
for (i = 0; i < crtc->num_scalers; i++) {
- u32 ctl, pos, size;
+ u32 ctl, pos, size, sharp;
ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
@@ -939,6 +939,17 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
id = i;
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ sharp = intel_de_read(dev_priv, SHARPNESS_CTL(crtc->pipe));
+ if (sharp & FILTER_EN) {
+ crtc_state->hw.casf_params.strength =
+ REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16;
+ crtc_state->hw.casf_params.need_scaler = true;
+ crtc_state->hw.casf_params.win_size =
+ REG_FIELD_GET(FILTER_SIZE_MASK, sharp);
+ }
+ }
+
if (!crtc_state->hw.casf_params.need_scaler)
crtc_state->pch_pfit.enabled = true;
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Introduce drm sharpening property (rev4)
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (4 preceding siblings ...)
2024-07-08 8:09 ` [5/5] drm/i915/display: Load the lut values and enable sharpness Nemesa Garg
@ 2024-07-08 8:49 ` Patchwork
2024-07-08 8:49 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2024-07-08 8:49 UTC (permalink / raw)
To: Nemesa Garg; +Cc: intel-gfx
== Series Details ==
Series: Introduce drm sharpening property (rev4)
URL : https://patchwork.freedesktop.org/series/129888/
State : warning
== Summary ==
Error: dim checkpatch failed
752c31d74f74 drm: Introduce sharpness mode property
6f1bbf74c46d drm/i915/display: Compute the scaler filter coefficients
-:76: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#76:
new file mode 100644
-:198: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#198: FILE: drivers/gpu/drm/i915/display/intel_sharpen_filter.c:118:
+ SHARP_COEFF_TO_REG_FORMAT(crtc_state->hw.casf_params.coeff[tapindex]);
-:218: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'coefficient' - possible side-effects?
#218: FILE: drivers/gpu/drm/i915/display/intel_sharpen_filter.h:11:
+#define SHARP_COEFF_TO_REG_FORMAT(coefficient) ((u16)(coefficient.sign << 15 | \
+ coefficient.exp << 12 | coefficient.mantissa << 3))
total: 0 errors, 2 warnings, 1 checks, 205 lines checked
81e96028fb8d drm/i915/display: Enable the second scaler for sharpness
-:224: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#224: FILE: drivers/gpu/drm/i915/display/skl_scaler.c:746:
+ x = y = 0;
total: 0 errors, 0 warnings, 1 checks, 224 lines checked
43dba0cb02ef drm/i915/display: Add registers and compute the strength
617fde77bbb3 drm/i915/display: Load the lut values and enable sharpness
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Introduce drm sharpening property (rev4)
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (5 preceding siblings ...)
2024-07-08 8:49 ` ✗ Fi.CI.CHECKPATCH: warning for Introduce drm sharpening property (rev4) Patchwork
@ 2024-07-08 8:49 ` Patchwork
2024-07-08 8:57 ` ✓ Fi.CI.BAT: success " Patchwork
2024-07-08 10:10 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2024-07-08 8:49 UTC (permalink / raw)
To: Nemesa Garg; +Cc: intel-gfx
== Series Details ==
Series: Introduce drm sharpening property (rev4)
URL : https://patchwork.freedesktop.org/series/129888/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.BAT: success for Introduce drm sharpening property (rev4)
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (6 preceding siblings ...)
2024-07-08 8:49 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-07-08 8:57 ` Patchwork
2024-07-08 10:10 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2024-07-08 8:57 UTC (permalink / raw)
To: Nemesa Garg; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3222 bytes --]
== Series Details ==
Series: Introduce drm sharpening property (rev4)
URL : https://patchwork.freedesktop.org/series/129888/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15038 -> Patchwork_129888v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/index.html
Participating hosts (39 -> 36)
------------------------------
Additional (2): fi-cfl-8109u fi-pnv-d510
Missing (5): bat-dg1-7 bat-kbl-2 bat-atsm-1 bat-dg2-11 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_129888v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-pnv-d510: NOTRUN -> [SKIP][2] +32 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/fi-pnv-d510/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#11379])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/bat-dg2-8/igt@kms_pipe_crc_basic@hang-read-crc@pipe-b-dp-1.html
* igt@kms_pm_backlight@basic-brightness:
- fi-cfl-8109u: NOTRUN -> [SKIP][6] +11 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/fi-cfl-8109u/igt@kms_pm_backlight@basic-brightness.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg2-8: [DMESG-FAIL][7] ([i915#9500]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
[i915#11379]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11379
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
Build changes
-------------
* Linux: CI_DRM_15038 -> Patchwork_129888v4
CI-20190529: 20190529
CI_DRM_15038: 70f1d41b827fa9d1275748e655912f991635f595 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7918: aab1a4b6a9b7855fe6e38ea3b3987a1399ee5816 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129888v4: 70f1d41b827fa9d1275748e655912f991635f595 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/index.html
[-- Attachment #2: Type: text/html, Size: 3966 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.IGT: failure for Introduce drm sharpening property (rev4)
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
` (7 preceding siblings ...)
2024-07-08 8:57 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-07-08 10:10 ` Patchwork
8 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2024-07-08 10:10 UTC (permalink / raw)
To: Nemesa Garg; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 76182 bytes --]
== Series Details ==
Series: Introduce drm sharpening property (rev4)
URL : https://patchwork.freedesktop.org/series/129888/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15038_full -> Patchwork_129888v4_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_129888v4_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_129888v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_129888v4_full:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- shard-snb: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb4/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb4/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-glk4/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk3/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-tglu-3/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-5/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
#### Warnings ####
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
- shard-snb: [FAIL][7] ([i915#11462]) -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb4/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb4/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
New tests
---------
New tests have been introduced between CI_DRM_15038_full and Patchwork_129888v4_full:
### New IGT tests (8) ###
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
- Statuses : 1 pass(s)
- Exec time: [30.89] s
* igt@kms_flip@2x-flip-vs-fences-interruptible@ab-vga1-hdmi-a1:
- Statuses : 1 pass(s)
- Exec time: [30.33] s
* igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1:
- Statuses : 1 pass(s)
- Exec time: [30.70] s
* igt@kms_flip@absolute-wf_vblank-interruptible@d-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [7.64] s
* igt@kms_flip@flip-vs-absolute-wf_vblank@d-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [7.94] s
* igt@kms_flip@flip-vs-rmfb@d-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [7.69] s
* igt@kms_flip@modeset-vs-vblank-race-interruptible@d-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [2.95] s
* igt@kms_flip@wf_vblank-ts-check-interruptible@d-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [7.93] s
Known issues
------------
Here are the changes found in Patchwork_129888v4_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8411])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@device_reset@cold-reset-bound:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#11078])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@device_reset@cold-reset-bound.html
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#11078])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-idle@vcs1:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#8414]) +4 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@drm_fdinfo@busy-idle@vcs1.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][13] -> [FAIL][14] ([i915#7742])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-rkl-5/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#7697]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_ctx_persistence@legacy-engines-hang:
- shard-snb: NOTRUN -> [SKIP][16] ([i915#1099])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hang.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#280]) +2 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@gem_ctx_sseu@engines.html
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#280]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][19] -> [FAIL][20] ([i915#5784]) +1 other test fail
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-16/igt@gem_eio@reset-stress.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#4525])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html
* igt@gem_exec_capture@capture-invisible@lmem0:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#6334]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@gem_exec_capture@capture-invisible@lmem0.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#6334])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: NOTRUN -> [FAIL][24] ([i915#2846])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow:
- shard-mtlp: NOTRUN -> [SKIP][25] ([i915#4473] / [i915#4771]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@gem_exec_fair@basic-flow.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: NOTRUN -> [FAIL][26] ([i915#2842]) +1 other test fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-rkl: NOTRUN -> [FAIL][27] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#3281]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#3281]) +6 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3281]) +12 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3281]) +5 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4537] / [i915#4812])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][33] ([i915#4860]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_huc_copy@huc-copy:
- shard-glk: NOTRUN -> [SKIP][34] ([i915#2190])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#4613] / [i915#7582])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@gem_lmem_evict@dontneed-evict-race.html
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#4613])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: [PASS][37] -> [FAIL][38] ([i915#10378])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-17/igt@gem_lmem_swapping@heavy-random@lmem0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-17/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#4613]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][40] ([i915#4613]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk4/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_vme:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#284])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_media_vme.html
* igt@gem_mmap_gtt@big-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#4077]) +3 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@gem_mmap_gtt@big-copy-xy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-odd:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#4077]) +11 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
* igt@gem_mmap_gtt@flink-race:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4077]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_mmap_gtt@flink-race.html
* igt@gem_mmap_wc@bad-offset:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4083]) +4 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@gem_mmap_wc@bad-offset.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][46] ([i915#2658])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk4/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4270])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#4270]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#4270])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_readwrite@read-write:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#3282]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@gem_readwrite@read-write.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-snb: NOTRUN -> [SKIP][51] +35 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#8428]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][53] ([i915#8411]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#3282]) +10 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@relocations:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#3281] / [i915#3297])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-tglu: NOTRUN -> [SKIP][56] ([i915#3297])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#2527] / [i915#2856])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#2527]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-chained:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#2856]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@gen9_exec_parse@bb-chained.html
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#2856])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#2527])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [PASS][63] -> [ABORT][64] ([i915#9820])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: [PASS][65] -> [ABORT][66] ([i915#9820])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#8399]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_selftest@mock@memory_region:
- shard-glk: NOTRUN -> [DMESG-WARN][68] ([i915#9311])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: NOTRUN -> [FAIL][69] ([i915#10031] / [i915#11279])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4212])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#8709]) +7 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#8709]) +11 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc.html
* igt@kms_async_flips@invalid-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#6228])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][74] ([i915#1769])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#5286])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5286])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#5286]) +5 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3638]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][79] ([i915#4538] / [i915#5190])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3638])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: NOTRUN -> [SKIP][81] +6 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_joiner@invalid-modeset:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#10656])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_big_joiner@invalid-modeset.html
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#10656])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#6095]) +51 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-18/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][86] ([i915#6095]) +7 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#6095]) +15 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#10307] / [i915#6095]) +197 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#6095]) +67 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@mode-transition@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#7213] / [i915#9010]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#3742]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#4087]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_edid@dp-edid-change-during-suspend:
- shard-tglu: NOTRUN -> [SKIP][93] ([i915#7828]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#7828]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#7828]) +2 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#7828]) +6 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#7828])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#7118] / [i915#9424])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#3116])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-tglu: NOTRUN -> [SKIP][100] ([i915#3116] / [i915#3299])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#9424])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#8063])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_content_protection@mei-interface.html
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#8063] / [i915#9433])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#6944] / [i915#9424])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_content_protection@uevent.html
- shard-rkl: NOTRUN -> [SKIP][105] ([i915#7118] / [i915#9424])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#3555])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#3555]) +6 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
- shard-mtlp: NOTRUN -> [SKIP][108] ([i915#3555] / [i915#8814])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#8814]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#9809]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#4103])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#4103] / [i915#4213])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: NOTRUN -> [FAIL][113] ([i915#2346])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-mtlp: NOTRUN -> [SKIP][114] ([i915#9067])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#9067])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#3555] / [i915#8812])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][117] ([i915#3840])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-formats:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#3555] / [i915#3840])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_dsc@dsc-with-formats.html
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#3555] / [i915#3840])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_dsc@dsc-with-formats.html
* igt@kms_feature_discovery@display-4x:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#1839])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@psr1:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#658]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_feature_discovery@psr1.html
* igt@kms_fence_pin_leak:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#4881])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [PASS][123] -> [FAIL][124] ([i915#2122])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb7/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#3637]) +5 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@kms_flip@2x-flip-vs-expired-vblank.html
- shard-dg2: NOTRUN -> [SKIP][126] +2 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#9934]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#8381])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@plain-flip-ts-check@d-hdmi-a4:
- shard-dg1: [PASS][129] -> [FAIL][130] ([i915#2122]) +1 other test fail
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-18/igt@kms_flip@plain-flip-ts-check@d-hdmi-a4.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-15/igt@kms_flip@plain-flip-ts-check@d-hdmi-a4.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#2672]) +4 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#8810])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#2587] / [i915#2672]) +2 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][134] ([i915#2672]) +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#5274])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [PASS][136] -> [FAIL][137] ([i915#6880])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#1825]) +15 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#8708]) +3 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#3458]) +2 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][141] +34 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][142] ([i915#1825]) +38 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
- shard-tglu: NOTRUN -> [SKIP][143] +10 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#3458]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3023]) +30 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][146] +12 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#5354]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#8708]) +4 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#8708]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_hdr@static-swap:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#3555] / [i915#8228])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-suspend:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#3555] / [i915#8228]) +2 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][152] ([i915#4816])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][153] ([i915#7862]) +1 other test fail
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][154] ([i915#10647]) +1 other test fail
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk4/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-x@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#10226] / [i915#3582]) +2 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_plane_lowres@tiling-x@pipe-a-edp-1.html
* igt@kms_plane_lowres@tiling-x@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#3582])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_plane_lowres@tiling-x@pipe-d-edp-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][157] ([i915#8292])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#9423]) +11 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#9423]) +3 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#9423]) +7 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][161] ([i915#5176]) +5 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#5235] / [i915#9423]) +15 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#5235]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][165] ([i915#5235]) +3 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][166] ([i915#3555] / [i915#5235]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#5235]) +5 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-edp-1.html
* igt@kms_pm_backlight@bad-brightness:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#5354]) +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_dc@dc5-psr:
- shard-rkl: NOTRUN -> [SKIP][169] ([i915#9685]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#9340])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [PASS][171] -> [SKIP][172] ([i915#9519])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][173] -> [SKIP][174] ([i915#9519]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#9519])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][176] ([i915#6524])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#11520]) +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#11520]) +4 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html
* igt@kms_psr@fbc-pr-no-drrs:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#1072] / [i915#9732]) +24 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_psr@fbc-pr-no-drrs.html
* igt@kms_psr@fbc-psr-primary-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9732])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
* igt@kms_psr@fbc-psr-primary-render:
- shard-tglu: NOTRUN -> [SKIP][181] ([i915#9732]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_psr@fbc-psr-primary-render.html
* igt@kms_psr@fbc-psr2-cursor-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][182] +356 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk8/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html
* igt@kms_psr@pr-no-drrs:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#9688]) +6 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_psr@pr-no-drrs.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#1072] / [i915#9732]) +4 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr2-sprite-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#4077] / [i915#9688])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_psr@psr2-sprite-mmap-gtt@edp-1.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#4235]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#5289])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-glk: NOTRUN -> [FAIL][188] ([i915#10959])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk4/igt@kms_tiled_display@basic-test-pattern.html
- shard-rkl: NOTRUN -> [SKIP][189] ([i915#8623])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [PASS][190] -> [FAIL][191] ([i915#9196])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_vrr@flip-basic:
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#3555])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@kms_vrr@flip-basic.html
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#3555] / [i915#8808])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@flip-basic-fastset:
- shard-mtlp: NOTRUN -> [SKIP][194] ([i915#8808] / [i915#9906]) +1 other test skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#9906]) +2 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][196] ([i915#2437]) +2 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk2/igt@kms_writeback@writeback-fb-id.html
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#2437])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_writeback@writeback-fb-id.html
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#2437])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#2437] / [i915#9412])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf@global-sseu-config-invalid:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#7387])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-3/igt@perf@global-sseu-config-invalid.html
* igt@perf_pmu@busy-idle@ccs0:
- shard-dg2: [PASS][201] -> [INCOMPLETE][202] ([i915#9853])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-10/igt@perf_pmu@busy-idle@ccs0.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-3/igt@perf_pmu@busy-idle@ccs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#8850])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@perf_pmu@cpu-hotplug.html
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#8850])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@perf_pmu@cpu-hotplug.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#3708])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@fence-read-hang:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#3708])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-3/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#9917])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg1: NOTRUN -> [SKIP][208] ([i915#9917])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][209] ([i915#9781])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-4/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-glk: NOTRUN -> [FAIL][210] ([i915#9781])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk2/igt@syncobj_wait@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][211] ([i915#7742]) -> [PASS][212]
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-5/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][213] ([i915#2842]) -> [PASS][214]
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-rkl: [FAIL][215] ([i915#2842]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-rkl-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked:
- shard-mtlp: [INCOMPLETE][217] ([i915#9857]) -> [PASS][218]
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-mtlp-3/igt@gem_exec_whisper@basic-queues-forked.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-4/igt@gem_exec_whisper@basic-queues-forked.html
* igt@gem_lmem_swapping@heavy-multi@lmem0:
- shard-dg1: [FAIL][219] ([i915#10378]) -> [PASS][220]
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-18/igt@gem_lmem_swapping@heavy-multi@lmem0.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-16/igt@gem_lmem_swapping@heavy-multi@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [FAIL][221] ([i915#10378]) -> [PASS][222]
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-5/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][223] ([i915#10131] / [i915#10887] / [i915#9820]) -> [PASS][224]
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [ABORT][225] ([i915#9820]) -> [PASS][226]
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][227] ([i915#7790]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb7/igt@i915_pm_rps@reset.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-mtlp: [ABORT][229] ([i915#10354]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-mtlp-1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-mtlp-7/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_color@ctm-0-75@pipe-a-hdmi-a-1:
- shard-tglu: [ABORT][231] -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-tglu-6/igt@kms_color@ctm-0-75@pipe-a-hdmi-a-1.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-tglu-8/igt@kms_color@ctm-0-75@pipe-a-hdmi-a-1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
- shard-snb: [INCOMPLETE][233] ([i915#4839]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-dg2: [FAIL][235] ([i915#6880]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-snb: [SKIP][237] -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [SKIP][239] ([i915#9519]) -> [PASS][240] +2 other tests pass
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@kms_pm_rpm@dpms-lpsp.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [FAIL][241] ([i915#9196]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4:
- shard-dg1: [FAIL][243] ([i915#9196]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-17/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-17/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-4.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [FAIL][245] ([i915#4349]) -> [PASS][246] +3 other tests pass
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
#### Warnings ####
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: [SKIP][247] ([i915#4565]) -> [SKIP][248] ([i915#4423] / [i915#4565])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-13/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-18/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][249] ([i915#7118] / [i915#7162] / [i915#9424]) -> [SKIP][250] ([i915#7118] / [i915#9424])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@kms_content_protection@type1.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: [SKIP][251] ([i915#11453] / [i915#3359]) -> [SKIP][252] ([i915#11453])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x170.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-5/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg1: [SKIP][253] ([i915#9934]) -> [SKIP][254] ([i915#4423] / [i915#9934])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-13/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-18/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
- shard-dg1: [SKIP][255] -> [SKIP][256] ([i915#4423])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2: [SKIP][257] ([i915#10433] / [i915#3458]) -> [SKIP][258] ([i915#3458]) +2 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-slowdraw.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: [SKIP][259] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][260] ([i915#1072] / [i915#9732]) +14 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@kms_psr@psr-cursor-mmap-cpu.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: [SKIP][261] ([i915#1072] / [i915#9732]) -> [SKIP][262] ([i915#1072] / [i915#9673] / [i915#9732]) +15 other tests skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-7/igt@kms_psr@psr-cursor-render.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: [SKIP][263] ([i915#11131] / [i915#4235]) -> [SKIP][264] ([i915#11131])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@kms_rotation_crc@bad-tiling.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2: [SKIP][265] ([i915#11131] / [i915#5190]) -> [SKIP][266] ([i915#11131] / [i915#4235] / [i915#5190])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: [SKIP][267] ([i915#11131]) -> [SKIP][268] ([i915#11131] / [i915#4235])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-10/igt@kms_rotation_crc@sprite-rotation-90.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][269] ([i915#9100]) -> [FAIL][270] ([i915#7484])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15038/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
[i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10226
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11279]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11279
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11462
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
[i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#9010]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9010
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9853]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9853
[i915#9857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9857
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15038 -> Patchwork_129888v4
CI-20190529: 20190529
CI_DRM_15038: 70f1d41b827fa9d1275748e655912f991635f595 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7918: aab1a4b6a9b7855fe6e38ea3b3987a1399ee5816 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129888v4: 70f1d41b827fa9d1275748e655912f991635f595 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129888v4/index.html
[-- Attachment #2: Type: text/html, Size: 92516 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [1/5] drm: Introduce sharpness mode property
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
@ 2024-08-29 8:33 ` Murthy, Arun R
2024-09-04 9:19 ` Shankar, Uma
1 sibling, 0 replies; 20+ messages in thread
From: Murthy, Arun R @ 2024-08-29 8:33 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: [1/5] drm: Introduce sharpness mode property
>
> Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user
> to set the intensity so as to get the sharpness effect.
> The value of this property can be set from 0-255.
> It is useful in scenario when the output is blurry and user want to sharpen the
> pixels. User can increase/decrease the sharpness level depending on the
> content displayed.
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++
> drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++
> include/drm/drm_crtc.h | 17 +++++++++++++++
> 3 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 22bbb2d83e30..825640ab39f6 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct
> drm_crtc *crtc,
> set_out_fence_for_crtc(state->state, crtc, fence_ptr);
> } else if (property == crtc->scaling_filter_property) {
> state->scaling_filter = val;
> + } else if (property == crtc->sharpness_strength_prop) {
Just in order to maintain similarity in the naming conventions can this be changed to either "prop_sharpness_strength" or "sharpness_strength_property"
> + state->sharpness_strength = val;
> } else if (crtc->funcs->atomic_set_property) {
> return crtc->funcs->atomic_set_property(crtc, state, property,
> val);
> } else {
> @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
> *val = 0;
> else if (property == crtc->scaling_filter_property)
> *val = state->scaling_filter;
> + else if (property == crtc->sharpness_strength_prop)
> + *val = state->sharpness_strength;
> else if (crtc->funcs->atomic_get_property)
> return crtc->funcs->atomic_get_property(crtc, state, property,
> val);
> else {
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index
> 3488ff067c69..4ff18786a226 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -229,6 +229,24 @@ struct dma_fence *drm_crtc_create_fence(struct
> drm_crtc *crtc)
> * Driver's default scaling filter
> * Nearest Neighbor:
> * Nearest Neighbor scaling filter
> + * SHARPNESS_STRENGTH:
> + * Atomic property for setting the sharpness strength/intensity by
> userspace.
> + *
> + * The value of this property is set as an integer value ranging
> + * from 0 - 255 where:
> + *
> + * 0 means feature is disabled.
> + *
> + * 1 means minimum sharpness.
> + *
> + * 255 means maximum sharpness.
> + *
> + * User can gradually increase or decrease the sharpness level and can
> + * set the optimum value depending on content and this value will be
> + * passed to kernel through the Uapi.
> + * The sharpness effect takes place post blending on the final composed
> output.
> + * If the feature is disabled, the content remains same without any
> sharpening effect
> + * and when this feature is applied, it enhances the clarity of the content.
> */
>
> __printf(6, 0)
> @@ -939,3 +957,20 @@ int drm_crtc_create_scaling_filter_property(struct
> drm_crtc *crtc,
> return 0;
> }
> EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
> +
> +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> +
No blank line over here.
> + struct drm_property *prop =
> + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH",
> 0, 255);
> +
> + if (!prop)
> + return -ENOMEM;
> +
> + crtc->sharpness_strength_prop = prop;
> + drm_object_attach_property(&crtc->base, prop, 0);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> 8b48a1974da3..1cdca5c82753 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -317,6 +317,16 @@ struct drm_crtc_state {
> */
> enum drm_scaling_filter scaling_filter;
>
> + /**
> + * @sharpness_strength
> + *
> + * Used by the user to set the sharpness intensity.
> + * The value ranges from 0-255.
> + * Any value greater than 0 means enabling the featuring
> + * along with setting the value for sharpness.
> + */
> + u8 sharpness_strength;
> +
> /**
> * @event:
> *
> @@ -1088,6 +1098,12 @@ struct drm_crtc {
> */
> struct drm_property *scaling_filter_property;
>
> + /**
> + * @sharpness_strength_prop: property to apply
> + * the intensity of the sharpness requested.
> + */
> + struct drm_property *sharpness_strength_prop;
> +
> /**
> * @state:
> *
> @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct
> drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc
> *crtc,
> unsigned int supported_filters);
>
> +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc);
> #endif /* __DRM_CRTC_H__ */
> --
> 2.25.1
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
2024-07-08 8:09 ` [v4 2/5] drm/i915/display: Compute the scaler filter coefficients Nemesa Garg
@ 2024-08-29 9:04 ` Murthy, Arun R
2024-09-09 5:26 ` Garg, Nemesa
0 siblings, 1 reply; 20+ messages in thread
From: Murthy, Arun R @ 2024-08-29 9:04 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
>
> The sharpness property requires the use of one of the scaler so need to set the
> sharpness scaler coefficient values.
> These values are based on experiments and vary for different tap value/win
> size. These values are normalized by taking the sum of all values and then
> dividing each value with a sum.
>
> --v4: fix ifndef header naming issue reported by kernel test robot
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 2 +
> .../drm/i915/display/intel_display_types.h | 9 ++
> .../drm/i915/display/intel_sharpen_filter.c | 121 ++++++++++++++++++
> .../drm/i915/display/intel_sharpen_filter.h | 27 ++++
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/xe/Makefile | 1 +
> 7 files changed, 163 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_sharpen_filter.h
Can a unified name be used across the patches. -> intel_sharpness_filter.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index c63fa2133ccb..0021f0a372ab 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -280,6 +280,7 @@ i915-y += \
> display/intel_pmdemand.o \
> display/intel_psr.o \
> display/intel_quirks.o \
> + display/intel_sharpen_filter.o \
> display/intel_sprite.o \
> display/intel_sprite_uapi.o \
> display/intel_tc.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c2c388212e2e..a62560a0c1a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5906,6 +5906,8 @@ static int intel_atomic_check_planes(struct
> intel_atomic_state *state)
> if (ret)
> return ret;
>
> + intel_sharpness_scaler_compute_config(new_crtc_state);
> +
> /*
> * On some platforms the number of active planes affects
> * the planes' minimum cdclk calculation. Add such planes diff -
> -git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8713835e2307..1c3e031ab369 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -55,6 +55,7 @@
> #include "intel_display_limits.h"
> #include "intel_display_power.h"
> #include "intel_dpll_mgr.h"
> +#include "intel_sharpen_filter.h"
> #include "intel_wm_types.h"
>
> struct drm_printer;
> @@ -828,6 +829,13 @@ struct intel_scaler {
> u32 mode;
> };
>
> +struct intel_sharpness_filter {
> + struct scaler_filter_coeff coeff[7];
> + u32 scaler_coefficient[119];
What is this magic number 119 and 7?
> + bool strength_changed;
> + u8 win_size;
> +};
Better to have this struct in intel_sharpness_filter.c as this is not used elsewhere.
> +
> struct intel_crtc_scaler_state {
> #define SKL_NUM_SCALERS 2
> struct intel_scaler scalers[SKL_NUM_SCALERS]; @@ -1072,6 +1080,7
> @@ struct intel_crtc_state {
> struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> struct drm_display_mode mode, pipe_mode, adjusted_mode;
> enum drm_scaling_filter scaling_filter;
> + struct intel_sharpness_filter casf_params;
> } hw;
>
> /* actual state of LUTs */
> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> new file mode 100644
> index 000000000000..b3ebd72b4116
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2024 Intel Corporation
> + *
> + */
> +
> +#include "i915_reg.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "skl_scaler.h"
> +
> +#define MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER 7 #define
> +SCALER_FILTER_NUM_TAPS 7 #define SCALER_FILTER_NUM_PHASES 17
> #define
> +FILTER_COEFF_0_125 125 #define FILTER_COEFF_0_25 250 #define
> +FILTER_COEFF_0_5 500 #define FILTER_COEFF_1_0 1000 #define
> +FILTER_COEFF_0_0 0
> +
> +void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Can i915 be used instead of dev_priv?
> + int id = crtc_state->scaler_state.scaler_id;
> +
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> 0),
> + PS_COEF_INDEX_AUTO_INC);
> +
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> 1),
> + PS_COEF_INDEX_AUTO_INC);
> +
> + for (int index = 0; index < 60; index++) {
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> >pipe, id, 0),
> + crtc_state-
> >hw.casf_params.scaler_coefficient[index]);
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> >pipe, id, 1),
> + crtc_state->hw.casf_params.
> scaler_coefficient[index]);
This is an array of 119 elements any reason of using only 60 over here.
> + }
> +}
> +
> +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
> + u16 coefficient)
> +{
> + if (coefficient < 25) {
> + coeff->mantissa = (coefficient * 2048) / 100;
> + coeff->exp = 3;
> + }
If () {
} else {
} if () {
}
> +
> + else if (coefficient < 50) {
> + coeff->mantissa = (coefficient * 1024) / 100;
> + coeff->exp = 2;
> + }
> +
> + else if (coefficient < 100) {
> + coeff->mantissa = (coefficient * 512) / 100;
> + coeff->exp = 1;
> + } else {
> + coeff->mantissa = (coefficient * 256) / 100;
> + coeff->exp = 0;
> + }
> +}
> +
> +static void intel_sharpness_filter_coeff(struct intel_crtc_state
> +*crtc_state) {
> + u16 filtercoeff[MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER];
> + u16 sumcoeff = 0;
> + u8 i;
> +
> + if (crtc_state->hw.casf_params.win_size == 0) {
> + filtercoeff[0] = FILTER_COEFF_0_0;
> + filtercoeff[1] = FILTER_COEFF_0_0;
> + filtercoeff[2] = FILTER_COEFF_0_5;
> + filtercoeff[3] = FILTER_COEFF_1_0;
> + filtercoeff[4] = FILTER_COEFF_0_5;
> + filtercoeff[5] = FILTER_COEFF_0_0;
> + filtercoeff[6] = FILTER_COEFF_0_0;
> + }
> +
> + else if (crtc_state->hw.casf_params.win_size == 1) {
> + filtercoeff[0] = FILTER_COEFF_0_0;
> + filtercoeff[1] = FILTER_COEFF_0_25;
> + filtercoeff[2] = FILTER_COEFF_0_5;
> + filtercoeff[3] = FILTER_COEFF_1_0;
> + filtercoeff[4] = FILTER_COEFF_0_5;
> + filtercoeff[5] = FILTER_COEFF_0_25;
> + filtercoeff[6] = FILTER_COEFF_0_0;
> + } else {
> + filtercoeff[0] = FILTER_COEFF_0_125;
> + filtercoeff[1] = FILTER_COEFF_0_25;
> + filtercoeff[2] = FILTER_COEFF_0_5;
> + filtercoeff[3] = FILTER_COEFF_1_0;
> + filtercoeff[4] = FILTER_COEFF_0_5;
> + filtercoeff[5] = FILTER_COEFF_0_25;
> + filtercoeff[6] = FILTER_COEFF_0_125;
> + }
If this is always a constant, then can this be in a lookup table?
> +
> + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++)
> + sumcoeff += filtercoeff[i];
> +
> + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++)
> {
> + filtercoeff[i] = (filtercoeff[i] * 100 / sumcoeff);
> + convert_sharpness_coef_binary(&crtc_state-
> >hw.casf_params.coeff[i],
> + filtercoeff[i]);
> + }
> +}
> +
> +void intel_sharpness_scaler_compute_config(struct intel_crtc_state
> +*crtc_state) {
> + u16 phase, tapindex, phaseoffset;
> + u16 *coeff = (u16 *)crtc_state->hw.casf_params.scaler_coefficient;
> +
> + intel_sharpness_filter_coeff(crtc_state);
> +
> + for (phase = 0; phase < SCALER_FILTER_NUM_PHASES; phase++) {
> + phaseoffset = SCALER_FILTER_NUM_TAPS * phase;
> + for (tapindex = 0; tapindex < SCALER_FILTER_NUM_TAPS;
> tapindex++) {
> + coeff[phaseoffset + tapindex] =
> + SHARP_COEFF_TO_REG_FORMAT(crtc_state-
> >hw.casf_params.coeff[tapindex]);
> + }
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> new file mode 100644
> index 000000000000..6ab70a635e2f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_SHARPEN_FILTER_H__
> +#define __INTEL_SHARPEN_FILTER_H__
> +
> +#include <linux/types.h>
> +
> +#define SHARP_COEFF_TO_REG_FORMAT(coefficient) ((u16)(coefficient.sign <<
> 15 | \
> + coefficient.exp << 12 | coefficient.mantissa << 3))
> +
> +struct intel_crtc;
> +struct intel_crtc_state;
> +struct intel_atomic_state;
> +
> +struct scaler_filter_coeff {
> + u16 sign;
> + u16 exp;
> + u16 mantissa;
> +};
> +
> +void intel_sharpness_filter_enable(struct intel_crtc_state
> +*crtc_state); void intel_sharpness_scaler_compute_config(struct
> +intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_SHARPEN_FILTER_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 0e3d79227e3c..9492fda15627
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2257,6 +2257,8 @@
> #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
> #define PS_PWRUP_PROGRESS REG_BIT(17)
> +#define PS_BYPASS_ARMING REG_BIT(10)
> +#define PS_DB_STALL REG_BIT(9)
> #define PS_V_FILTER_BYPASS REG_BIT(8)
> #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt
> */
> #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5)
> /* skl/bxt */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> 0eb0acc4f198..8681ca89af27 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -278,6 +278,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> i915-display/intel_psr.o \
> i915-display/intel_qp_tables.o \
> i915-display/intel_quirks.o \
> + i915-display/intel_sharpen_filter.o \
> i915-display/intel_snps_phy.o \
> i915-display/intel_tc.o \
> i915-display/intel_vblank.o \
> --
> 2.25.1
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [3/5] drm/i915/display: Enable the second scaler for sharpness
2024-07-08 8:09 ` [3/5] drm/i915/display: Enable the second scaler for sharpness Nemesa Garg
@ 2024-08-30 4:44 ` Murthy, Arun R
2024-09-09 10:23 ` Garg, Nemesa
0 siblings, 1 reply; 20+ messages in thread
From: Murthy, Arun R @ 2024-08-30 4:44 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: [3/5] drm/i915/display: Enable the second scaler for sharpness
>
> As only second scaler can be used for sharpness check if it is available and if
> panel fitting is also not enabled, the set the sharpness. Panel fitting will have
> the preference over sharpness property.
Can you reframe the commit message, it's a bit difficult to understand.
>
> v2: Added the panel fitting check before enabling sharpness
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++-
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_modeset_verify.c | 1 +
> drivers/gpu/drm/i915/display/intel_panel.c | 4 +-
> .../drm/i915/display/intel_sharpen_filter.c | 10 +++
> .../drm/i915/display/intel_sharpen_filter.h | 1 +
> drivers/gpu/drm/i915/display/skl_scaler.c | 84 +++++++++++++++++--
> drivers/gpu/drm/i915/display/skl_scaler.h | 1 +
> 8 files changed, 99 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a62560a0c1a9..385a254528f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2028,7 +2028,7 @@ static void get_crtc_power_domains(struct
> intel_crtc_state *crtc_state,
> set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
> set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
> if (crtc_state->pch_pfit.enabled ||
> - crtc_state->pch_pfit.force_thru)
> + crtc_state->pch_pfit.force_thru ||
> +crtc_state->hw.casf_params.need_scaler)
> set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask-
> >bits);
>
> drm_for_each_encoder_mask(encoder, &dev_priv->drm, @@ -2284,7
> +2284,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state
> *crtc_state)
> * PF-ID we'll need to adjust the pixel_rate here.
> */
>
> - if (!crtc_state->pch_pfit.enabled)
> + if (!crtc_state->pch_pfit.enabled ||
> +crtc_state->hw.casf_params.need_scaler)
> return pixel_rate;
>
> drm_rect_init(&src, 0, 0,
> @@ -4295,7 +4295,8 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> if (intel_crtc_needs_modeset(crtc_state) ||
> - intel_crtc_needs_fastset(crtc_state)) {
> + intel_crtc_needs_fastset(crtc_state) ||
> + crtc_state->hw.casf_params.need_scaler) {
> ret = skl_update_scaler_crtc(crtc_state);
> if (ret)
> return ret;
> @@ -5481,6 +5482,9 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(cmrr.enable);
> }
>
> + if (pipe_config->uapi.sharpness_strength > 0)
> + PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler);
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_LLI
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1c3e031ab369..130740aaaa21 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -834,6 +834,7 @@ struct intel_sharpness_filter {
> u32 scaler_coefficient[119];
> bool strength_changed;
> u8 win_size;
> + bool need_scaler;
Always for sharpness filter scaler is required, so does this need_scaler make sense?
Rather should we not check for sharpness_filter enabled?
> };
>
> struct intel_crtc_scaler_state {
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 3491db5cad31..ed75934bed6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -177,6 +177,7 @@ verify_crtc_state(struct intel_atomic_state *state,
> crtc->base.name);
>
> hw_crtc_state->hw.enable = sw_crtc_state->hw.enable;
> + hw_crtc_state->hw.casf_params.need_scaler =
> +sw_crtc_state->hw.casf_params.need_scaler;
>
> intel_crtc_get_pipe_config(hw_crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 71454ddef20f..bfc725d2e178 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -451,7 +451,9 @@ static int pch_panel_fitting(struct intel_crtc_state
> *crtc_state,
>
> drm_rect_init(&crtc_state->pch_pfit.dst,
> x, y, width, height);
> - crtc_state->pch_pfit.enabled = true;
> +
> + if (!crtc_state->hw.casf_params.need_scaler)
> + crtc_state->pch_pfit.enabled = true;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> index b3ebd72b4116..627a0dbd3dfd 100644
> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> @@ -36,6 +36,16 @@ void intel_sharpness_filter_enable(struct intel_crtc_state
> *crtc_state)
> intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> >pipe, id, 1),
> crtc_state->hw.casf_params.
> scaler_coefficient[index]);
> }
> +
> + casf_scaler_enable(crtc_state);
> +}
> +
> +int intel_filter_compute_config(struct intel_crtc_state *crtc_state) {
> + if (!crtc_state->pch_pfit.enabled)
> + crtc_state->hw.casf_params.need_scaler = true;
> +
> + return 0;
> }
>
> static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, diff
> --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> index 6ab70a635e2f..d20e65971a55 100644
> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> @@ -23,5 +23,6 @@ struct scaler_filter_coeff {
>
> void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); void
> intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state);
> +int intel_filter_compute_config(struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git
> a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> index baa601d27815..9d8bc6c0ab2c 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -253,7 +253,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state
> *crtc_state)
> drm_rect_width(&crtc_state->pipe_src),
> drm_rect_height(&crtc_state->pipe_src),
> width, height, NULL, 0,
> - crtc_state->pch_pfit.enabled);
> + crtc_state->pch_pfit.enabled ||
> + crtc_state->hw.casf_params.need_scaler);
> }
>
> /**
> @@ -353,9 +354,10 @@ static int intel_atomic_setup_scaler(struct
> intel_crtc_scaler_state *scaler_stat
> int num_scalers_need, struct intel_crtc
> *intel_crtc,
> const char *name, int idx,
> struct intel_plane_state *plane_state,
> - int *scaler_id)
> + int *scaler_id, bool casf_scaler)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> + struct intel_crtc_state *crtc_state =
> +to_intel_crtc_state(intel_crtc->base.state);
> int j;
> u32 mode;
>
> @@ -365,6 +367,11 @@ static int intel_atomic_setup_scaler(struct
> intel_crtc_scaler_state *scaler_stat
> if (scaler_state->scalers[j].in_use)
> continue;
>
> + if (!strcmp(name, "CRTC")) {
> + if (casf_scaler && j != 1)
Should the scaler id used for sharpness filter be stored and the same be used here to check if its in use?
> + continue;
> + }
> +
> *scaler_id = j;
> scaler_state->scalers[*scaler_id].in_use = 1;
> break;
> @@ -375,6 +382,10 @@ static int intel_atomic_setup_scaler(struct
> intel_crtc_scaler_state *scaler_stat
> "Cannot find scaler for %s:%d\n", name, idx))
> return -EINVAL;
>
> + if (crtc_state->hw.casf_params.need_scaler) {
> + mode = SKL_PS_SCALER_MODE_HQ;
> + }
> +
> /* set scaler mode */
> if (plane_state && plane_state->hw.fb &&
> plane_state->hw.fb->format->is_yuv && @@ -598,7 +609,8 @@ int
> intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>
> ret = intel_atomic_setup_scaler(scaler_state,
> num_scalers_need,
> intel_crtc, name, idx,
> - plane_state, scaler_id);
> + plane_state, scaler_id,
> + crtc_state-
> >hw.casf_params.need_scaler);
> if (ret < 0)
> return ret;
> }
> @@ -678,6 +690,15 @@ static void glk_program_nearest_filter_coefs(struct
> drm_i915_private *dev_priv,
> intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
> }
>
> +static u32 scaler_filter_select(void)
> +{
> + return (PS_FILTER_PROGRAMMED |
> + PS_Y_VERT_FILTER_SELECT(1) |
> + PS_Y_HORZ_FILTER_SELECT(0) |
> + PS_UV_VERT_FILTER_SELECT(1) |
> + PS_UV_HORZ_FILTER_SELECT(0));
> +}
This looks to be a constant value, can it be a macro?
> +
> static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) {
> if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { @@ -705,6
> +726,48 @@ static void skl_scaler_setup_filter(struct drm_i915_private
> *dev_priv, enum pipe
> }
> }
>
> +void casf_scaler_enable(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
dev_priv => i915
> + struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + struct intel_crtc_scaler_state *scaler_state =
> + &crtc_state->scaler_state;
> + struct drm_rect src, dest;
> + int id, width, height;
> + int x, y;
> + enum pipe pipe = crtc->pipe;
> + u32 ps_ctrl;
> +
> + width = adjusted_mode->crtc_hdisplay;
> + height = adjusted_mode->crtc_vdisplay;
> +
> + x = y = 0;
> + drm_rect_init(&dest, x, y, width, height);
> +
> + struct drm_rect *dst = &dest;
Declaration to be in the beginning of the function.
Also I don't see the value of dst being changed and dest being used elsewhere in this function. In that case why is a copy of dest made?
> +
> + x = dst->x1;
> + y = dst->y1;
> + width = drm_rect_width(dst);
> + height = drm_rect_height(dst);
> + id = scaler_state->scaler_id;
> +
> + drm_rect_init(&src, 0, 0,
> + drm_rect_width(&crtc_state->pipe_src) << 16,
> + drm_rect_height(&crtc_state->pipe_src) << 16);
> +
> + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state-
> >scalers[id].mode |
> + PS_BYPASS_ARMING | PS_DB_STALL | scaler_filter_select();
> +
> + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> + PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); }
> +
> void skl_pfit_enable(const struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -875,16 +938,19 @@ void skl_scaler_get_config(struct intel_crtc_state
> *crtc_state)
> continue;
>
> id = i;
> - crtc_state->pch_pfit.enabled = true;
> +
> + if (!crtc_state->hw.casf_params.need_scaler)
> + crtc_state->pch_pfit.enabled = true;
>
> pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
> size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
>
> - drm_rect_init(&crtc_state->pch_pfit.dst,
> - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
> - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
> - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
> - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
> + if (!crtc_state->hw.casf_params.need_scaler)
> + drm_rect_init(&crtc_state->pch_pfit.dst,
> + REG_FIELD_GET(PS_WIN_XPOS_MASK,
> pos),
> + REG_FIELD_GET(PS_WIN_YPOS_MASK,
> pos),
> + REG_FIELD_GET(PS_WIN_XSIZE_MASK,
> size),
> + REG_FIELD_GET(PS_WIN_YSIZE_MASK,
> size));
>
> scaler_state->scalers[i].in_use = true;
> break;
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h
> b/drivers/gpu/drm/i915/display/skl_scaler.h
> index 63f93ca03c89..444527e6a15b 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.h
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.h
> @@ -33,5 +33,6 @@ void skl_detach_scalers(const struct intel_crtc_state
> *crtc_state); void skl_scaler_disable(const struct intel_crtc_state
> *old_crtc_state);
>
> void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
> +void casf_scaler_enable(struct intel_crtc_state *crtc_state);
>
> #endif
> --
> 2.25.1
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [4/5] drm/i915/display: Add registers and compute the strength
2024-07-08 8:09 ` [4/5] drm/i915/display: Add registers and compute the strength Nemesa Garg
@ 2024-08-30 8:04 ` Murthy, Arun R
2024-08-30 8:33 ` Jani Nikula
0 siblings, 1 reply; 20+ messages in thread
From: Murthy, Arun R @ 2024-08-30 8:04 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: [4/5] drm/i915/display: Add registers and compute the strength
>
> Add new registers and related bits. Compute the strength value and tap value
> based on display mode.
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_sharpen_filter.c | 105 ++++++++++++++++++
> .../drm/i915/display/intel_sharpen_filter.h | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 17 +++
> 5 files changed, 132 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 385a254528f9..e0a82ab46d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5910,7 +5910,10 @@ static int intel_atomic_check_planes(struct
> intel_atomic_state *state)
> if (ret)
> return ret;
>
> - intel_sharpness_scaler_compute_config(new_crtc_state);
> + if (sharp_compute(new_crtc_state)) {
> +
> intel_sharpness_scaler_compute_config(new_crtc_state);
> + intel_filter_compute_config(new_crtc_state);
> + }
>
> /*
> * On some platforms the number of active planes affects diff --
> git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 130740aaaa21..782192f2b9ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -835,6 +835,7 @@ struct intel_sharpness_filter {
> bool strength_changed;
> u8 win_size;
> bool need_scaler;
> + u8 strength;
> };
>
> struct intel_crtc_scaler_state {
> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> index 627a0dbd3dfd..6600a66d3960 100644
> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> @@ -18,11 +18,87 @@
> #define FILTER_COEFF_1_0 1000
> #define FILTER_COEFF_0_0 0
>
> +/*
> + * Default LUT values to be loaded one time.
> + */
Single line comment style /* */
> +static const u16 lut_data[] = {
> + 4095, 2047, 1364, 1022, 816, 678, 579,
> + 504, 444, 397, 357, 323, 293, 268, 244, 224,
> + 204, 187, 170, 154, 139, 125, 111, 98, 85,
> + 73, 60, 48, 36, 24, 12, 0
> +};
> +
> +void intel_filter_lut_load(struct intel_crtc *crtc,
> + const struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
dev_priv => i915
> + int i;
> +
> + intel_de_write(dev_priv, SHRPLUT_INDEX(crtc->pipe),
> INDEX_AUTO_INCR |
> +INDEX_VALUE(0));
> +
> + for (i = 0; i < ARRAY_SIZE(lut_data); i++)
> + intel_de_write(dev_priv, SHRPLUT_DATA(crtc->pipe),
> lut_data[i]); }
Sharpness LUT is from bit[0:11] and lut_data is u16.
> +
> +static void intel_filter_size_compute(struct intel_crtc_state
Can the same function naming convention be used
intel_filter_size_compute => intel_sharpness_filter_size_compute
> +*crtc_state) {
> + const struct drm_display_mode *mode = &crtc_state-
> >hw.adjusted_mode;
> +
> + if (mode->hdisplay <= 1920 && mode->vdisplay <= 1080)
> + crtc_state->hw.casf_params.win_size = 0;
> + else if (mode->hdisplay <= 3840 && mode->vdisplay <= 2160)
> + crtc_state->hw.casf_params.win_size = 1;
> + else
> + crtc_state->hw.casf_params.win_size = 2; }
> +
> +bool intel_sharpness_strength_changed(struct intel_atomic_state *state)
> +{
> + int i;
> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> + struct intel_crtc *crtc;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (new_crtc_state->uapi.sharpness_strength !=
> + old_crtc_state->uapi.sharpness_strength)
> + return true;
> + }
> +
> + return false;
> +}
> +
> void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int id = crtc_state->scaler_state.scaler_id;
> + u32 sharpness_ctl;
> + u8 val;
> +
> + if (crtc_state->uapi.sharpness_strength == 0) {
> + intel_sharpness_disable(crtc_state);
> +
> + return;
> + }
> +
> + /*
> + * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> + * Strength is from 0.0-14.9375 ie from 0-239.
> + * User can give value from 0-255 but is clamped to 239.
> + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
> + * 6.3125 in 4.4 format is 01100101 which is equal to 101.
> + * Also 85 + 16 = 101.
> + */
> + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
> +
> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", val);
> +
> + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) |
> + FILTER_SIZE(crtc_state->hw.casf_params.win_size);
> +
> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe),
> + sharpness_ctl);
>
> intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> 0),
> PS_COEF_INDEX_AUTO_INC);
> @@ -42,9 +118,21 @@ void intel_sharpness_filter_enable(struct
> intel_crtc_state *crtc_state)
>
> int intel_filter_compute_config(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> +
> + if (crtc_state->uapi.sharpness_strength == 0) {
> + crtc_state->hw.casf_params.need_scaler = false;
> + return 0;
> + }
> +
> if (!crtc_state->pch_pfit.enabled)
> crtc_state->hw.casf_params.need_scaler = true;
>
> + intel_filter_size_compute(crtc_state);
> + drm_dbg(&dev_priv->drm, "Tap Size: %d\n",
> + crtc_state->hw.casf_params.win_size);
> +
> return 0;
> }
>
> @@ -129,3 +217,20 @@ void intel_sharpness_scaler_compute_config(struct
> intel_crtc_state *crtc_state)
> }
> }
> }
> +
> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe), 0);
> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", 0); }
> +
> +bool sharp_compute(struct intel_crtc_state *crtc_state) {
> + if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0)
> + return true;
> +
> + return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> index d20e65971a55..4fffdd99d0fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> @@ -24,5 +24,10 @@ struct scaler_filter_coeff { void
> intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); void
> intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state); int
> intel_filter_compute_config(struct intel_crtc_state *crtc_state);
> +void intel_filter_lut_load(struct intel_crtc *crtc,
> + const struct intel_crtc_state *crtc_state); bool
> +intel_sharpness_strength_changed(struct intel_atomic_state *state);
> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state); bool
> +sharp_compute(struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 9492fda15627..2fa42e10bb63 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2396,6 +2396,23 @@
> _ID(id, _PS_COEF_SET0_DATA_1A,
> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> _ID(id, _PS_COEF_SET0_DATA_1B,
> _PS_COEF_SET0_DATA_2B) + (set) * 8)
>
> +#define _SHARPNESS_CTL_A 0x682B0
> +#define SHARPNESS_CTL(trans) _MMIO_PIPE2(dev_priv, trans,
> _SHARPNESS_CTL_A)
> +#define FILTER_EN REG_BIT(31)
> +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
> +#define FILTER_STRENGTH(x)
> REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> +#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
> +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x))
> +
> +#define _SHRPLUT_DATA_A 0x682B8
> +#define SHRPLUT_DATA(trans) _MMIO_PIPE2(dev_priv, trans,
> _SHRPLUT_DATA_A)
> +
> +#define _SHRPLUT_INDEX_A 0x682B4
> +#define SHRPLUT_INDEX(trans) _MMIO_PIPE2(dev_priv, trans,
> _SHRPLUT_INDEX_A)
> +#define INDEX_AUTO_INCR REG_BIT(10)
> +#define INDEX_VALUE_MASK REG_GENMASK(4, 0)
> +#define INDEX_VALUE(x)
> REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
> +
> /* Display Internal Timeout Register */
> #define RM_TIMEOUT _MMIO(0x42060)
> #define MMIO_TIMEOUT_US(us) ((us) << 0)
> --
> 2.25.1
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [4/5] drm/i915/display: Add registers and compute the strength
2024-08-30 8:04 ` Murthy, Arun R
@ 2024-08-30 8:33 ` Jani Nikula
2024-09-09 10:26 ` Garg, Nemesa
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2024-08-30 8:33 UTC (permalink / raw)
To: Murthy, Arun R, Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
On Fri, 30 Aug 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
>> Garg
>> Sent: Monday, July 8, 2024 1:39 PM
>> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
>> Cc: Garg, Nemesa <nemesa.garg@intel.com>
>> Subject: [4/5] drm/i915/display: Add registers and compute the strength
>>
>> Add new registers and related bits. Compute the strength value and tap value
>> based on display mode.
>>
>> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
>> .../drm/i915/display/intel_display_types.h | 1 +
>> .../drm/i915/display/intel_sharpen_filter.c | 105 ++++++++++++++++++
>> .../drm/i915/display/intel_sharpen_filter.h | 5 +
>> drivers/gpu/drm/i915/i915_reg.h | 17 +++
>> 5 files changed, 132 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 385a254528f9..e0a82ab46d29 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5910,7 +5910,10 @@ static int intel_atomic_check_planes(struct
>> intel_atomic_state *state)
>> if (ret)
>> return ret;
>>
>> - intel_sharpness_scaler_compute_config(new_crtc_state);
>> + if (sharp_compute(new_crtc_state)) {
>> +
>> intel_sharpness_scaler_compute_config(new_crtc_state);
>> + intel_filter_compute_config(new_crtc_state);
>> + }
>>
>> /*
>> * On some platforms the number of active planes affects diff --
>> git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 130740aaaa21..782192f2b9ae 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -835,6 +835,7 @@ struct intel_sharpness_filter {
>> bool strength_changed;
>> u8 win_size;
>> bool need_scaler;
>> + u8 strength;
>> };
>>
>> struct intel_crtc_scaler_state {
>> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
>> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
>> index 627a0dbd3dfd..6600a66d3960 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
>> @@ -18,11 +18,87 @@
>> #define FILTER_COEFF_1_0 1000
>> #define FILTER_COEFF_0_0 0
>>
>> +/*
>> + * Default LUT values to be loaded one time.
>> + */
> Single line comment style /* */
>
>> +static const u16 lut_data[] = {
>> + 4095, 2047, 1364, 1022, 816, 678, 579,
>> + 504, 444, 397, 357, 323, 293, 268, 244, 224,
>> + 204, 187, 170, 154, 139, 125, 111, 98, 85,
>> + 73, 60, 48, 36, 24, 12, 0
>> +};
>> +
>> +void intel_filter_lut_load(struct intel_crtc *crtc,
>> + const struct intel_crtc_state *crtc_state) {
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> dev_priv => i915
Actually,
struct intel_display *display = to_intel_display(crtc);
everywhere instead of dev_priv or i915.
>
>> + int i;
>> +
>> + intel_de_write(dev_priv, SHRPLUT_INDEX(crtc->pipe),
>> INDEX_AUTO_INCR |
>> +INDEX_VALUE(0));
>> +
>> + for (i = 0; i < ARRAY_SIZE(lut_data); i++)
>> + intel_de_write(dev_priv, SHRPLUT_DATA(crtc->pipe),
>> lut_data[i]); }
> Sharpness LUT is from bit[0:11] and lut_data is u16.
>
>> +
>> +static void intel_filter_size_compute(struct intel_crtc_state
> Can the same function naming convention be used
> intel_filter_size_compute => intel_sharpness_filter_size_compute
>
>> +*crtc_state) {
>> + const struct drm_display_mode *mode = &crtc_state-
>> >hw.adjusted_mode;
>> +
>> + if (mode->hdisplay <= 1920 && mode->vdisplay <= 1080)
>> + crtc_state->hw.casf_params.win_size = 0;
>> + else if (mode->hdisplay <= 3840 && mode->vdisplay <= 2160)
>> + crtc_state->hw.casf_params.win_size = 1;
>> + else
>> + crtc_state->hw.casf_params.win_size = 2; }
>> +
>> +bool intel_sharpness_strength_changed(struct intel_atomic_state *state)
>> +{
>> + int i;
>> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>> + struct intel_crtc *crtc;
>> +
>> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> + new_crtc_state, i) {
>> + if (new_crtc_state->uapi.sharpness_strength !=
>> + old_crtc_state->uapi.sharpness_strength)
>> + return true;
>> + }
>> +
>> + return false;
>> +}
>> +
>> void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> int id = crtc_state->scaler_state.scaler_id;
>> + u32 sharpness_ctl;
>> + u8 val;
>> +
>> + if (crtc_state->uapi.sharpness_strength == 0) {
>> + intel_sharpness_disable(crtc_state);
>> +
>> + return;
>> + }
>> +
>> + /*
>> + * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
>> + * Strength is from 0.0-14.9375 ie from 0-239.
>> + * User can give value from 0-255 but is clamped to 239.
>> + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
>> + * 6.3125 in 4.4 format is 01100101 which is equal to 101.
>> + * Also 85 + 16 = 101.
>> + */
>> + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
>> +
>> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", val);
>> +
>> + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) |
>> + FILTER_SIZE(crtc_state->hw.casf_params.win_size);
>> +
>> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe),
>> + sharpness_ctl);
>>
>> intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
>> 0),
>> PS_COEF_INDEX_AUTO_INC);
>> @@ -42,9 +118,21 @@ void intel_sharpness_filter_enable(struct
>> intel_crtc_state *crtc_state)
>>
>> int intel_filter_compute_config(struct intel_crtc_state *crtc_state) {
>> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>> +
>> + if (crtc_state->uapi.sharpness_strength == 0) {
>> + crtc_state->hw.casf_params.need_scaler = false;
>> + return 0;
>> + }
>> +
>> if (!crtc_state->pch_pfit.enabled)
>> crtc_state->hw.casf_params.need_scaler = true;
>>
>> + intel_filter_size_compute(crtc_state);
>> + drm_dbg(&dev_priv->drm, "Tap Size: %d\n",
>> + crtc_state->hw.casf_params.win_size);
>> +
>> return 0;
>> }
>>
>> @@ -129,3 +217,20 @@ void intel_sharpness_scaler_compute_config(struct
>> intel_crtc_state *crtc_state)
>> }
>> }
>> }
>> +
>> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state) {
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +
>> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe), 0);
>> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", 0); }
>> +
>> +bool sharp_compute(struct intel_crtc_state *crtc_state) {
>> + if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0)
>> + return true;
>> +
>> + return false;
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
>> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
>> index d20e65971a55..4fffdd99d0fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
>> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
>> @@ -24,5 +24,10 @@ struct scaler_filter_coeff { void
>> intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); void
>> intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state); int
>> intel_filter_compute_config(struct intel_crtc_state *crtc_state);
>> +void intel_filter_lut_load(struct intel_crtc *crtc,
>> + const struct intel_crtc_state *crtc_state); bool
>> +intel_sharpness_strength_changed(struct intel_atomic_state *state);
>> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state); bool
>> +sharp_compute(struct intel_crtc_state *crtc_state);
>>
>> #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git
>> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>> 9492fda15627..2fa42e10bb63 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2396,6 +2396,23 @@
>> _ID(id, _PS_COEF_SET0_DATA_1A,
>> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
>> _ID(id, _PS_COEF_SET0_DATA_1B,
>> _PS_COEF_SET0_DATA_2B) + (set) * 8)
>>
>> +#define _SHARPNESS_CTL_A 0x682B0
>> +#define SHARPNESS_CTL(trans) _MMIO_PIPE2(dev_priv, trans,
>> _SHARPNESS_CTL_A)
>> +#define FILTER_EN REG_BIT(31)
>> +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
>> +#define FILTER_STRENGTH(x)
>> REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
>> +#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
>> +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x))
>> +
>> +#define _SHRPLUT_DATA_A 0x682B8
>> +#define SHRPLUT_DATA(trans) _MMIO_PIPE2(dev_priv, trans,
>> _SHRPLUT_DATA_A)
>> +
>> +#define _SHRPLUT_INDEX_A 0x682B4
>> +#define SHRPLUT_INDEX(trans) _MMIO_PIPE2(dev_priv, trans,
>> _SHRPLUT_INDEX_A)
>> +#define INDEX_AUTO_INCR REG_BIT(10)
>> +#define INDEX_VALUE_MASK REG_GENMASK(4, 0)
>> +#define INDEX_VALUE(x)
>> REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
>> +
>> /* Display Internal Timeout Register */
>> #define RM_TIMEOUT _MMIO(0x42060)
>> #define MMIO_TIMEOUT_US(us) ((us) << 0)
>> --
>> 2.25.1
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [1/5] drm: Introduce sharpness mode property
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
2024-08-29 8:33 ` Murthy, Arun R
@ 2024-09-04 9:19 ` Shankar, Uma
1 sibling, 0 replies; 20+ messages in thread
From: Shankar, Uma @ 2024-09-04 9:19 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Garg, Nemesa
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Nemesa
> Garg
> Sent: Monday, July 8, 2024 1:39 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: [1/5] drm: Introduce sharpness mode property
Nit: Rename it to sharpness strength instead of mode.
> Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user
> to set the intensity so as to get the sharpness effect.
> The value of this property can be set from 0-255.
> It is useful in scenario when the output is blurry and user want to sharpen the
> pixels. User can increase/decrease the sharpness level depending on the content
> displayed.
>
> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++
> drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++
> include/drm/drm_crtc.h | 17 +++++++++++++++
> 3 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 22bbb2d83e30..825640ab39f6 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
> *crtc,
> set_out_fence_for_crtc(state->state, crtc, fence_ptr);
> } else if (property == crtc->scaling_filter_property) {
> state->scaling_filter = val;
> + } else if (property == crtc->sharpness_strength_prop) {
Agree with Arun, spell property fully for consistency.
> + state->sharpness_strength = val;
> } else if (crtc->funcs->atomic_set_property) {
> return crtc->funcs->atomic_set_property(crtc, state, property,
> val);
> } else {
> @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
> *val = 0;
> else if (property == crtc->scaling_filter_property)
> *val = state->scaling_filter;
> + else if (property == crtc->sharpness_strength_prop)
> + *val = state->sharpness_strength;
> else if (crtc->funcs->atomic_get_property)
> return crtc->funcs->atomic_get_property(crtc, state, property,
> val);
> else {
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index
> 3488ff067c69..4ff18786a226 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -229,6 +229,24 @@ struct dma_fence *drm_crtc_create_fence(struct
> drm_crtc *crtc)
> * Driver's default scaling filter
> * Nearest Neighbor:
> * Nearest Neighbor scaling filter
> + * SHARPNESS_STRENGTH:
> + * Atomic property for setting the sharpness strength/intensity by
> userspace.
> + *
> + * The value of this property is set as an integer value ranging
> + * from 0 - 255 where:
> + *
> + * 0 means feature is disabled.
> + *
> + * 1 means minimum sharpness.
> + *
> + * 255 means maximum sharpness.
> + *
> + * User can gradually increase or decrease the sharpness level and can
> + * set the optimum value depending on content and this value will be
> + * passed to kernel through the Uapi.
> + * The sharpness effect takes place post blending on the final composed
> output.
> + * If the feature is disabled, the content remains same without any
> sharpening effect
> + * and when this feature is applied, it enhances the clarity of the content.
Can you also mention the modeset requirement that this can be done with no modeset
and can be managed as normal flip.
> */
>
> __printf(6, 0)
> @@ -939,3 +957,20 @@ int drm_crtc_create_scaling_filter_property(struct
> drm_crtc *crtc,
> return 0;
> }
> EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
> +
> +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> +
> + struct drm_property *prop =
> + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0,
> 255);
> +
> + if (!prop)
> + return -ENOMEM;
> +
> + crtc->sharpness_strength_prop = prop;
> + drm_object_attach_property(&crtc->base, prop, 0);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> 8b48a1974da3..1cdca5c82753 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -317,6 +317,16 @@ struct drm_crtc_state {
> */
> enum drm_scaling_filter scaling_filter;
>
> + /**
> + * @sharpness_strength
> + *
> + * Used by the user to set the sharpness intensity.
> + * The value ranges from 0-255.
> + * Any value greater than 0 means enabling the featuring
> + * along with setting the value for sharpness.
> + */
> + u8 sharpness_strength;
> +
> /**
> * @event:
> *
> @@ -1088,6 +1098,12 @@ struct drm_crtc {
> */
> struct drm_property *scaling_filter_property;
>
> + /**
> + * @sharpness_strength_prop: property to apply
> + * the intensity of the sharpness requested.
> + */
> + struct drm_property *sharpness_strength_prop;
> +
> /**
> * @state:
> *
> @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct
> drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc
> *crtc,
> unsigned int supported_filters);
>
> +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc);
> #endif /* __DRM_CRTC_H__ */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
2024-08-29 9:04 ` Murthy, Arun R
@ 2024-09-09 5:26 ` Garg, Nemesa
2024-09-10 7:22 ` Murthy, Arun R
0 siblings, 1 reply; 20+ messages in thread
From: Garg, Nemesa @ 2024-09-09 5:26 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@intel.com>
> Sent: Thursday, August 29, 2024 2:34 PM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org;
> dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: RE: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Nemesa Garg
> > Sent: Monday, July 8, 2024 1:39 PM
> > To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> > Cc: Garg, Nemesa <nemesa.garg@intel.com>
> > Subject: [v4 2/5] drm/i915/display: Compute the scaler filter
> > coefficients
> >
> > The sharpness property requires the use of one of the scaler so need
> > to set the sharpness scaler coefficient values.
> > These values are based on experiments and vary for different tap
> > value/win size. These values are normalized by taking the sum of all
> > values and then dividing each value with a sum.
> >
> > --v4: fix ifndef header naming issue reported by kernel test robot
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +
> > .../drm/i915/display/intel_display_types.h | 9 ++
> > .../drm/i915/display/intel_sharpen_filter.c | 121 ++++++++++++++++++
> > .../drm/i915/display/intel_sharpen_filter.h | 27 ++++
> > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > drivers/gpu/drm/xe/Makefile | 1 +
> > 7 files changed, 163 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > create mode 100644
> > drivers/gpu/drm/i915/display/intel_sharpen_filter.h
>
> Can a unified name be used across the patches. -> intel_sharpness_filter.c
>
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..0021f0a372ab
> > 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -280,6 +280,7 @@ i915-y += \
> > display/intel_pmdemand.o \
> > display/intel_psr.o \
> > display/intel_quirks.o \
> > + display/intel_sharpen_filter.o \
> > display/intel_sprite.o \
> > display/intel_sprite_uapi.o \
> > display/intel_tc.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index c2c388212e2e..a62560a0c1a9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5906,6 +5906,8 @@ static int intel_atomic_check_planes(struct
> > intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > + intel_sharpness_scaler_compute_config(new_crtc_state);
> > +
> > /*
> > * On some platforms the number of active planes affects
> > * the planes' minimum cdclk calculation. Add such planes diff -
> > -git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 8713835e2307..1c3e031ab369 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -55,6 +55,7 @@
> > #include "intel_display_limits.h"
> > #include "intel_display_power.h"
> > #include "intel_dpll_mgr.h"
> > +#include "intel_sharpen_filter.h"
> > #include "intel_wm_types.h"
> >
> > struct drm_printer;
> > @@ -828,6 +829,13 @@ struct intel_scaler {
> > u32 mode;
> > };
> >
> > +struct intel_sharpness_filter {
> > + struct scaler_filter_coeff coeff[7];
> > + u32 scaler_coefficient[119];
> What is this magic number 119 and 7?
> For each win size there are 7 coefficients, so coeff[7] is used to store these values which are further used in calculating scaler coefficients.
As we need to compute scaler coefficients for 17 phases of 7 taps I have used scaler_coefficient[119] .
> > + bool strength_changed;
> > + u8 win_size;
> > +};
> Better to have this struct in intel_sharpness_filter.c as this is not used elsewhere.
>
> > +
> > struct intel_crtc_scaler_state {
> > #define SKL_NUM_SCALERS 2
> > struct intel_scaler scalers[SKL_NUM_SCALERS]; @@ -1072,6 +1080,7
> @@
> > struct intel_crtc_state {
> > struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> > struct drm_display_mode mode, pipe_mode, adjusted_mode;
> > enum drm_scaling_filter scaling_filter;
> > + struct intel_sharpness_filter casf_params;
> > } hw;
> >
> > /* actual state of LUTs */
> > diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > new file mode 100644
> > index 000000000000..b3ebd72b4116
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2024 Intel Corporation
> > + *
> > + */
> > +
> > +#include "i915_reg.h"
> > +#include "intel_de.h"
> > +#include "intel_display_types.h"
> > +#include "skl_scaler.h"
> > +
> > +#define MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER 7 #define
> > +SCALER_FILTER_NUM_TAPS 7 #define SCALER_FILTER_NUM_PHASES 17
> > #define
> > +FILTER_COEFF_0_125 125 #define FILTER_COEFF_0_25 250 #define
> > +FILTER_COEFF_0_5 500 #define FILTER_COEFF_1_0 1000 #define
> > +FILTER_COEFF_0_0 0
> > +
> > +void intel_sharpness_filter_enable(struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> Can i915 be used instead of dev_priv?
> Will use struct intel_display *display = to_intel_display(crtc);
> > + int id = crtc_state->scaler_state.scaler_id;
> > +
> > + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> > 0),
> > + PS_COEF_INDEX_AUTO_INC);
> > +
> > + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> > 1),
> > + PS_COEF_INDEX_AUTO_INC);
> > +
> > + for (int index = 0; index < 60; index++) {
> > + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> > >pipe, id, 0),
> > + crtc_state-
> > >hw.casf_params.scaler_coefficient[index]);
> > + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> > >pipe, id, 1),
> > + crtc_state->hw.casf_params.
> > scaler_coefficient[index]);
> This is an array of 119 elements any reason of using only 60 over here.
> There are two sets of programmed coefficients are available for each scaler and these 119 coefficients need to be filled in form of 60
Dwords per set.
> > + }
> > +}
> > +
> > +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff,
> > + u16 coefficient)
> > +{
> > + if (coefficient < 25) {
> > + coeff->mantissa = (coefficient * 2048) / 100;
> > + coeff->exp = 3;
> > + }
>
> If () {
> } else {
> } if () {
> }
> Thanks for pointing out.
> > +
> > + else if (coefficient < 50) {
> > + coeff->mantissa = (coefficient * 1024) / 100;
> > + coeff->exp = 2;
> > + }
> > +
> > + else if (coefficient < 100) {
> > + coeff->mantissa = (coefficient * 512) / 100;
> > + coeff->exp = 1;
> > + } else {
> > + coeff->mantissa = (coefficient * 256) / 100;
> > + coeff->exp = 0;
> > + }
> > +}
> > +
> > +static void intel_sharpness_filter_coeff(struct intel_crtc_state
> > +*crtc_state) {
> > + u16 filtercoeff[MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER];
> > + u16 sumcoeff = 0;
> > + u8 i;
> > +
> > + if (crtc_state->hw.casf_params.win_size == 0) {
> > + filtercoeff[0] = FILTER_COEFF_0_0;
> > + filtercoeff[1] = FILTER_COEFF_0_0;
> > + filtercoeff[2] = FILTER_COEFF_0_5;
> > + filtercoeff[3] = FILTER_COEFF_1_0;
> > + filtercoeff[4] = FILTER_COEFF_0_5;
> > + filtercoeff[5] = FILTER_COEFF_0_0;
> > + filtercoeff[6] = FILTER_COEFF_0_0;
> > + }
> > +
> > + else if (crtc_state->hw.casf_params.win_size == 1) {
> > + filtercoeff[0] = FILTER_COEFF_0_0;
> > + filtercoeff[1] = FILTER_COEFF_0_25;
> > + filtercoeff[2] = FILTER_COEFF_0_5;
> > + filtercoeff[3] = FILTER_COEFF_1_0;
> > + filtercoeff[4] = FILTER_COEFF_0_5;
> > + filtercoeff[5] = FILTER_COEFF_0_25;
> > + filtercoeff[6] = FILTER_COEFF_0_0;
> > + } else {
> > + filtercoeff[0] = FILTER_COEFF_0_125;
> > + filtercoeff[1] = FILTER_COEFF_0_25;
> > + filtercoeff[2] = FILTER_COEFF_0_5;
> > + filtercoeff[3] = FILTER_COEFF_1_0;
> > + filtercoeff[4] = FILTER_COEFF_0_5;
> > + filtercoeff[5] = FILTER_COEFF_0_25;
> > + filtercoeff[6] = FILTER_COEFF_0_125;
> > + }
> If this is always a constant, then can this be in a lookup table?
Sure.
Thanks and Regards,
Nemesa
> > +
> > + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++)
> > + sumcoeff += filtercoeff[i];
> > +
> > + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++)
> > {
> > + filtercoeff[i] = (filtercoeff[i] * 100 / sumcoeff);
> > + convert_sharpness_coef_binary(&crtc_state-
> > >hw.casf_params.coeff[i],
> > + filtercoeff[i]);
> > + }
> > +}
> > +
> > +void intel_sharpness_scaler_compute_config(struct intel_crtc_state
> > +*crtc_state) {
> > + u16 phase, tapindex, phaseoffset;
> > + u16 *coeff = (u16 *)crtc_state->hw.casf_params.scaler_coefficient;
> > +
> > + intel_sharpness_filter_coeff(crtc_state);
> > +
> > + for (phase = 0; phase < SCALER_FILTER_NUM_PHASES; phase++) {
> > + phaseoffset = SCALER_FILTER_NUM_TAPS * phase;
> > + for (tapindex = 0; tapindex < SCALER_FILTER_NUM_TAPS;
> > tapindex++) {
> > + coeff[phaseoffset + tapindex] =
> > + SHARP_COEFF_TO_REG_FORMAT(crtc_state-
> > >hw.casf_params.coeff[tapindex]);
> > + }
> > + }
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > new file mode 100644
> > index 000000000000..6ab70a635e2f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > @@ -0,0 +1,27 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2024 Intel Corporation */
> > +
> > +#ifndef __INTEL_SHARPEN_FILTER_H__
> > +#define __INTEL_SHARPEN_FILTER_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define SHARP_COEFF_TO_REG_FORMAT(coefficient)
> > +((u16)(coefficient.sign <<
> > 15 | \
> > + coefficient.exp << 12 | coefficient.mantissa << 3))
> > +
> > +struct intel_crtc;
> > +struct intel_crtc_state;
> > +struct intel_atomic_state;
> > +
> > +struct scaler_filter_coeff {
> > + u16 sign;
> > + u16 exp;
> > + u16 mantissa;
> > +};
> > +
> > +void intel_sharpness_filter_enable(struct intel_crtc_state
> > +*crtc_state); void intel_sharpness_scaler_compute_config(struct
> > +intel_crtc_state *crtc_state);
> > +
> > +#endif /* __INTEL_SHARPEN_FILTER_H__ */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 0e3d79227e3c..9492fda15627
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2257,6 +2257,8 @@
> > #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> > #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
> > #define PS_PWRUP_PROGRESS REG_BIT(17)
> > +#define PS_BYPASS_ARMING REG_BIT(10)
> > +#define PS_DB_STALL REG_BIT(9)
> > #define PS_V_FILTER_BYPASS REG_BIT(8)
> > #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt
> > */
> > #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5)
> > /* skl/bxt */
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index
> > 0eb0acc4f198..8681ca89af27 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -278,6 +278,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> > i915-display/intel_psr.o \
> > i915-display/intel_qp_tables.o \
> > i915-display/intel_quirks.o \
> > + i915-display/intel_sharpen_filter.o \
> > i915-display/intel_snps_phy.o \
> > i915-display/intel_tc.o \
> > i915-display/intel_vblank.o \
> > --
> > 2.25.1
> Thanks and Regards,
> Arun R Murthy
> --------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [3/5] drm/i915/display: Enable the second scaler for sharpness
2024-08-30 4:44 ` Murthy, Arun R
@ 2024-09-09 10:23 ` Garg, Nemesa
0 siblings, 0 replies; 20+ messages in thread
From: Garg, Nemesa @ 2024-09-09 10:23 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@intel.com>
> Sent: Friday, August 30, 2024 10:14 AM
> To: Garg, Nemesa <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org;
> dri-devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: RE: [3/5] drm/i915/display: Enable the second scaler for sharpness
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Nemesa Garg
> > Sent: Monday, July 8, 2024 1:39 PM
> > To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> > Cc: Garg, Nemesa <nemesa.garg@intel.com>
> > Subject: [3/5] drm/i915/display: Enable the second scaler for
> > sharpness
> >
> > As only second scaler can be used for sharpness check if it is
> > available and if panel fitting is also not enabled, the set the
> > sharpness. Panel fitting will have the preference over sharpness property.
> Can you reframe the commit message, it's a bit difficult to understand.
> Sure. Will do.
> >
> > v2: Added the panel fitting check before enabling sharpness
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 ++-
> > .../drm/i915/display/intel_display_types.h | 1 +
> > .../drm/i915/display/intel_modeset_verify.c | 1 +
> > drivers/gpu/drm/i915/display/intel_panel.c | 4 +-
> > .../drm/i915/display/intel_sharpen_filter.c | 10 +++
> > .../drm/i915/display/intel_sharpen_filter.h | 1 +
> > drivers/gpu/drm/i915/display/skl_scaler.c | 84 +++++++++++++++++--
> > drivers/gpu/drm/i915/display/skl_scaler.h | 1 +
> > 8 files changed, 99 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a62560a0c1a9..385a254528f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2028,7 +2028,7 @@ static void get_crtc_power_domains(struct
> > intel_crtc_state *crtc_state,
> > set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
> > set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
> > if (crtc_state->pch_pfit.enabled ||
> > - crtc_state->pch_pfit.force_thru)
> > + crtc_state->pch_pfit.force_thru ||
> > +crtc_state->hw.casf_params.need_scaler)
> > set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask-
> > >bits);
> >
> > drm_for_each_encoder_mask(encoder, &dev_priv->drm, @@ -2284,7
> > +2284,7 @@ static u32 ilk_pipe_pixel_rate(const struct
> > +intel_crtc_state
> > *crtc_state)
> > * PF-ID we'll need to adjust the pixel_rate here.
> > */
> >
> > - if (!crtc_state->pch_pfit.enabled)
> > + if (!crtc_state->pch_pfit.enabled ||
> > +crtc_state->hw.casf_params.need_scaler)
> > return pixel_rate;
> >
> > drm_rect_init(&src, 0, 0,
> > @@ -4295,7 +4295,8 @@ static int intel_crtc_atomic_check(struct
> > intel_atomic_state *state,
> >
> > if (DISPLAY_VER(dev_priv) >= 9) {
> > if (intel_crtc_needs_modeset(crtc_state) ||
> > - intel_crtc_needs_fastset(crtc_state)) {
> > + intel_crtc_needs_fastset(crtc_state) ||
> > + crtc_state->hw.casf_params.need_scaler) {
> > ret = skl_update_scaler_crtc(crtc_state);
> > if (ret)
> > return ret;
> > @@ -5481,6 +5482,9 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_BOOL(cmrr.enable);
> > }
> >
> > + if (pipe_config->uapi.sharpness_strength > 0)
> > + PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler);
> > +
> > #undef PIPE_CONF_CHECK_X
> > #undef PIPE_CONF_CHECK_I
> > #undef PIPE_CONF_CHECK_LLI
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1c3e031ab369..130740aaaa21 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -834,6 +834,7 @@ struct intel_sharpness_filter {
> > u32 scaler_coefficient[119];
> > bool strength_changed;
> > u8 win_size;
> > + bool need_scaler;
> Always for sharpness filter scaler is required, so does this need_scaler make
> sense?
> Rather should we not check for sharpness_filter enabled?
> need_scaler is getting set during compute config when sharpness strength is not 0 and pch_panel_fitting is not enabled.
If any of the above condition is not met then sharpness cannot be enabled.
So I need to rename this flag?
> > };
> >
> > struct intel_crtc_scaler_state {
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > index 3491db5cad31..ed75934bed6b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > @@ -177,6 +177,7 @@ verify_crtc_state(struct intel_atomic_state *state,
> > crtc->base.name);
> >
> > hw_crtc_state->hw.enable = sw_crtc_state->hw.enable;
> > + hw_crtc_state->hw.casf_params.need_scaler =
> > +sw_crtc_state->hw.casf_params.need_scaler;
> >
> > intel_crtc_get_pipe_config(hw_crtc_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> > b/drivers/gpu/drm/i915/display/intel_panel.c
> > index 71454ddef20f..bfc725d2e178 100644
> > --- a/drivers/gpu/drm/i915/display/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> > @@ -451,7 +451,9 @@ static int pch_panel_fitting(struct
> > intel_crtc_state *crtc_state,
> >
> > drm_rect_init(&crtc_state->pch_pfit.dst,
> > x, y, width, height);
> > - crtc_state->pch_pfit.enabled = true;
> > +
> > + if (!crtc_state->hw.casf_params.need_scaler)
> > + crtc_state->pch_pfit.enabled = true;
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > index b3ebd72b4116..627a0dbd3dfd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > @@ -36,6 +36,16 @@ void intel_sharpness_filter_enable(struct
> > intel_crtc_state
> > *crtc_state)
> > intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(crtc-
> > >pipe, id, 1),
> > crtc_state->hw.casf_params.
> > scaler_coefficient[index]);
> > }
> > +
> > + casf_scaler_enable(crtc_state);
> > +}
> > +
> > +int intel_filter_compute_config(struct intel_crtc_state *crtc_state) {
> > + if (!crtc_state->pch_pfit.enabled)
> > + crtc_state->hw.casf_params.need_scaler = true;
> > +
> > + return 0;
> > }
> >
> > static void convert_sharpness_coef_binary(struct scaler_filter_coeff
> > *coeff, diff --git
> > a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > index 6ab70a635e2f..d20e65971a55 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> > @@ -23,5 +23,6 @@ struct scaler_filter_coeff {
> >
> > void intel_sharpness_filter_enable(struct intel_crtc_state
> > *crtc_state); void intel_sharpness_scaler_compute_config(struct
> > intel_crtc_state *crtc_state);
> > +int intel_filter_compute_config(struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/skl_scaler.c
> > b/drivers/gpu/drm/i915/display/skl_scaler.c
> > index baa601d27815..9d8bc6c0ab2c 100644
> > --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> > @@ -253,7 +253,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state
> > *crtc_state)
> > drm_rect_width(&crtc_state->pipe_src),
> > drm_rect_height(&crtc_state->pipe_src),
> > width, height, NULL, 0,
> > - crtc_state->pch_pfit.enabled);
> > + crtc_state->pch_pfit.enabled ||
> > + crtc_state->hw.casf_params.need_scaler);
> > }
> >
> > /**
> > @@ -353,9 +354,10 @@ static int intel_atomic_setup_scaler(struct
> > intel_crtc_scaler_state *scaler_stat
> > int num_scalers_need, struct intel_crtc
> *intel_crtc,
> > const char *name, int idx,
> > struct intel_plane_state *plane_state,
> > - int *scaler_id)
> > + int *scaler_id, bool casf_scaler)
> > {
> > struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> > + struct intel_crtc_state *crtc_state =
> > +to_intel_crtc_state(intel_crtc->base.state);
> > int j;
> > u32 mode;
> >
> > @@ -365,6 +367,11 @@ static int intel_atomic_setup_scaler(struct
> > intel_crtc_scaler_state *scaler_stat
> > if (scaler_state->scalers[j].in_use)
> > continue;
> >
> > + if (!strcmp(name, "CRTC")) {
> > + if (casf_scaler && j != 1)
> Should the scaler id used for sharpness filter be stored and the same be used here
> to check if its in use?
> Instead of j do I need to use some variable representing scaler id for sharpness.
Here need to check if scaler is assigned for crtc or plane and if it is for crtc and if sharpness is enabled then, whether second scaler is
available or not. If second scaler is free then set scaler id as 1.
> > + continue;
> > + }
> > +
> > *scaler_id = j;
> > scaler_state->scalers[*scaler_id].in_use = 1;
> > break;
> > @@ -375,6 +382,10 @@ static int intel_atomic_setup_scaler(struct
> > intel_crtc_scaler_state *scaler_stat
> > "Cannot find scaler for %s:%d\n", name, idx))
> > return -EINVAL;
> >
> > + if (crtc_state->hw.casf_params.need_scaler) {
> > + mode = SKL_PS_SCALER_MODE_HQ;
> > + }
> > +
> > /* set scaler mode */
> > if (plane_state && plane_state->hw.fb &&
> > plane_state->hw.fb->format->is_yuv && @@ -598,7 +609,8 @@ int
> > intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> >
> > ret = intel_atomic_setup_scaler(scaler_state,
> > num_scalers_need,
> > intel_crtc, name, idx,
> > - plane_state, scaler_id);
> > + plane_state, scaler_id,
> > + crtc_state-
> > >hw.casf_params.need_scaler);
> > if (ret < 0)
> > return ret;
> > }
> > @@ -678,6 +690,15 @@ static void
> > glk_program_nearest_filter_coefs(struct
> > drm_i915_private *dev_priv,
> > intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
> > 0); }
> >
> > +static u32 scaler_filter_select(void) {
> > + return (PS_FILTER_PROGRAMMED |
> > + PS_Y_VERT_FILTER_SELECT(1) |
> > + PS_Y_HORZ_FILTER_SELECT(0) |
> > + PS_UV_VERT_FILTER_SELECT(1) |
> > + PS_UV_HORZ_FILTER_SELECT(0));
> > +}
> This looks to be a constant value, can it be a macro?
> Noted.
> > +
> > static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) {
> > if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { @@ -705,6
> > +726,48 @@ static void skl_scaler_setup_filter(struct drm_i915_private
> > *dev_priv, enum pipe
> > }
> > }
> >
> > +void casf_scaler_enable(struct intel_crtc_state *crtc_state) {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> dev_priv => i915
>
> > + struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + struct intel_crtc_scaler_state *scaler_state =
> > + &crtc_state->scaler_state;
> > + struct drm_rect src, dest;
> > + int id, width, height;
> > + int x, y;
> > + enum pipe pipe = crtc->pipe;
> > + u32 ps_ctrl;
> > +
> > + width = adjusted_mode->crtc_hdisplay;
> > + height = adjusted_mode->crtc_vdisplay;
> > +
> > + x = y = 0;
> > + drm_rect_init(&dest, x, y, width, height);
> > +
> > + struct drm_rect *dst = &dest;
> Declaration to be in the beginning of the function.
> Also I don't see the value of dst being changed and dest being used elsewhere in
> this function. In that case why is a copy of dest made?
> Will remove extra declaration.
Thanks and Regards,
Nemesa
> > +
> > + x = dst->x1;
> > + y = dst->y1;
> > + width = drm_rect_width(dst);
> > + height = drm_rect_height(dst);
> > + id = scaler_state->scaler_id;
> > +
> > + drm_rect_init(&src, 0, 0,
> > + drm_rect_width(&crtc_state->pipe_src) << 16,
> > + drm_rect_height(&crtc_state->pipe_src) << 16);
> > +
> > + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state-
> > >scalers[id].mode |
> > + PS_BYPASS_ARMING | PS_DB_STALL | scaler_filter_select();
> > +
> > + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
> > + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > + PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
> > + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); }
> > +
> > void skl_pfit_enable(const struct intel_crtc_state *crtc_state) {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -875,16 +938,19 @@ void skl_scaler_get_config(struct
> > intel_crtc_state
> > *crtc_state)
> > continue;
> >
> > id = i;
> > - crtc_state->pch_pfit.enabled = true;
> > +
> > + if (!crtc_state->hw.casf_params.need_scaler)
> > + crtc_state->pch_pfit.enabled = true;
> >
> > pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
> > size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
> >
> > - drm_rect_init(&crtc_state->pch_pfit.dst,
> > - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
> > - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
> > - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
> > - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
> > + if (!crtc_state->hw.casf_params.need_scaler)
> > + drm_rect_init(&crtc_state->pch_pfit.dst,
> > + REG_FIELD_GET(PS_WIN_XPOS_MASK,
> > pos),
> > + REG_FIELD_GET(PS_WIN_YPOS_MASK,
> > pos),
> > + REG_FIELD_GET(PS_WIN_XSIZE_MASK,
> > size),
> > + REG_FIELD_GET(PS_WIN_YSIZE_MASK,
> > size));
> >
> > scaler_state->scalers[i].in_use = true;
> > break;
> > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h
> > b/drivers/gpu/drm/i915/display/skl_scaler.h
> > index 63f93ca03c89..444527e6a15b 100644
> > --- a/drivers/gpu/drm/i915/display/skl_scaler.h
> > +++ b/drivers/gpu/drm/i915/display/skl_scaler.h
> > @@ -33,5 +33,6 @@ void skl_detach_scalers(const struct
> > intel_crtc_state *crtc_state); void skl_scaler_disable(const struct
> > intel_crtc_state *old_crtc_state);
> >
> > void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
> > +void casf_scaler_enable(struct intel_crtc_state *crtc_state);
> >
> > #endif
> > --
> > 2.25.1
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [4/5] drm/i915/display: Add registers and compute the strength
2024-08-30 8:33 ` Jani Nikula
@ 2024-09-09 10:26 ` Garg, Nemesa
0 siblings, 0 replies; 20+ messages in thread
From: Garg, Nemesa @ 2024-09-09 10:26 UTC (permalink / raw)
To: Jani Nikula, Murthy, Arun R, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, August 30, 2024 2:04 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; Garg, Nemesa
> <nemesa.garg@intel.com>; intel-gfx@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> Subject: RE: [4/5] drm/i915/display: Add registers and compute the strength
>
> On Fri, 30 Aug 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Nemesa Garg
> >> Sent: Monday, July 8, 2024 1:39 PM
> >> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> >> Cc: Garg, Nemesa <nemesa.garg@intel.com>
> >> Subject: [4/5] drm/i915/display: Add registers and compute the
> >> strength
> >>
> >> Add new registers and related bits. Compute the strength value and
> >> tap value based on display mode.
> >>
> >> Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> >> .../drm/i915/display/intel_display_types.h | 1 +
> >> .../drm/i915/display/intel_sharpen_filter.c | 105 ++++++++++++++++++
> >> .../drm/i915/display/intel_sharpen_filter.h | 5 +
> >> drivers/gpu/drm/i915/i915_reg.h | 17 +++
> >> 5 files changed, 132 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 385a254528f9..e0a82ab46d29 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -5910,7 +5910,10 @@ static int intel_atomic_check_planes(struct
> >> intel_atomic_state *state)
> >> if (ret)
> >> return ret;
> >>
> >> - intel_sharpness_scaler_compute_config(new_crtc_state);
> >> + if (sharp_compute(new_crtc_state)) {
> >> +
> >> intel_sharpness_scaler_compute_config(new_crtc_state);
> >> + intel_filter_compute_config(new_crtc_state);
> >> + }
> >>
> >> /*
> >> * On some platforms the number of active planes affects diff --
> >> git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 130740aaaa21..782192f2b9ae 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -835,6 +835,7 @@ struct intel_sharpness_filter {
> >> bool strength_changed;
> >> u8 win_size;
> >> bool need_scaler;
> >> + u8 strength;
> >> };
> >>
> >> struct intel_crtc_scaler_state {
> >> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> >> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> >> index 627a0dbd3dfd..6600a66d3960 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> >> @@ -18,11 +18,87 @@
> >> #define FILTER_COEFF_1_0 1000
> >> #define FILTER_COEFF_0_0 0
> >>
> >> +/*
> >> + * Default LUT values to be loaded one time.
> >> + */
> > Single line comment style /* */
> >Sure.
> >> +static const u16 lut_data[] = {
> >> + 4095, 2047, 1364, 1022, 816, 678, 579,
> >> + 504, 444, 397, 357, 323, 293, 268, 244, 224,
> >> + 204, 187, 170, 154, 139, 125, 111, 98, 85,
> >> + 73, 60, 48, 36, 24, 12, 0
> >> +};
> >> +
> >> +void intel_filter_lut_load(struct intel_crtc *crtc,
> >> + const struct intel_crtc_state *crtc_state) {
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > dev_priv => i915
>
> Actually,
>
> struct intel_display *display = to_intel_display(crtc);
>
> everywhere instead of dev_priv or i915.
> Will replace dev_priv or i915 with intel_display *display in series.
Thanks and Regards,
Nemesa
> >
> >> + int i;
> >> +
> >> + intel_de_write(dev_priv, SHRPLUT_INDEX(crtc->pipe),
> >> INDEX_AUTO_INCR |
> >> +INDEX_VALUE(0));
> >> +
> >> + for (i = 0; i < ARRAY_SIZE(lut_data); i++)
> >> + intel_de_write(dev_priv, SHRPLUT_DATA(crtc->pipe),
> >> lut_data[i]); }
> > Sharpness LUT is from bit[0:11] and lut_data is u16.
> >
> >> +
> >> +static void intel_filter_size_compute(struct intel_crtc_state
> > Can the same function naming convention be used
> > intel_filter_size_compute => intel_sharpness_filter_size_compute
> >
> >> +*crtc_state) {
> >> + const struct drm_display_mode *mode = &crtc_state-
> >> >hw.adjusted_mode;
> >> +
> >> + if (mode->hdisplay <= 1920 && mode->vdisplay <= 1080)
> >> + crtc_state->hw.casf_params.win_size = 0;
> >> + else if (mode->hdisplay <= 3840 && mode->vdisplay <= 2160)
> >> + crtc_state->hw.casf_params.win_size = 1;
> >> + else
> >> + crtc_state->hw.casf_params.win_size = 2; }
> >> +
> >> +bool intel_sharpness_strength_changed(struct intel_atomic_state
> >> +*state) {
> >> + int i;
> >> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> >> + struct intel_crtc *crtc;
> >> +
> >> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> >> + new_crtc_state, i) {
> >> + if (new_crtc_state->uapi.sharpness_strength !=
> >> + old_crtc_state->uapi.sharpness_strength)
> >> + return true;
> >> + }
> >> +
> >> + return false;
> >> +}
> >> +
> >> void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) {
> >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> int id = crtc_state->scaler_state.scaler_id;
> >> + u32 sharpness_ctl;
> >> + u8 val;
> >> +
> >> + if (crtc_state->uapi.sharpness_strength == 0) {
> >> + intel_sharpness_disable(crtc_state);
> >> +
> >> + return;
> >> + }
> >> +
> >> + /*
> >> + * HW takes a value in form (1.0 + strength) in 4.4 fixed format.
> >> + * Strength is from 0.0-14.9375 ie from 0-239.
> >> + * User can give value from 0-255 but is clamped to 239.
> >> + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125.
> >> + * 6.3125 in 4.4 format is 01100101 which is equal to 101.
> >> + * Also 85 + 16 = 101.
> >> + */
> >> + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10;
> >> +
> >> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", val);
> >> +
> >> + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) |
> >> + FILTER_SIZE(crtc_state->hw.casf_params.win_size);
> >> +
> >> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe),
> >> + sharpness_ctl);
> >>
> >> intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(crtc->pipe, id,
> >> 0),
> >> PS_COEF_INDEX_AUTO_INC);
> >> @@ -42,9 +118,21 @@ void intel_sharpness_filter_enable(struct
> >> intel_crtc_state *crtc_state)
> >>
> >> int intel_filter_compute_config(struct intel_crtc_state *crtc_state)
> >> {
> >> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> >> +
> >> + if (crtc_state->uapi.sharpness_strength == 0) {
> >> + crtc_state->hw.casf_params.need_scaler = false;
> >> + return 0;
> >> + }
> >> +
> >> if (!crtc_state->pch_pfit.enabled)
> >> crtc_state->hw.casf_params.need_scaler = true;
> >>
> >> + intel_filter_size_compute(crtc_state);
> >> + drm_dbg(&dev_priv->drm, "Tap Size: %d\n",
> >> + crtc_state->hw.casf_params.win_size);
> >> +
> >> return 0;
> >> }
> >>
> >> @@ -129,3 +217,20 @@ void
> >> intel_sharpness_scaler_compute_config(struct
> >> intel_crtc_state *crtc_state)
> >> }
> >> }
> >> }
> >> +
> >> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state) {
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> +
> >> + intel_de_write(dev_priv, SHARPNESS_CTL(crtc->pipe), 0);
> >> + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", 0); }
> >> +
> >> +bool sharp_compute(struct intel_crtc_state *crtc_state) {
> >> + if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0)
> >> + return true;
> >> +
> >> + return false;
> >> +}
> >> diff --git a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> >> b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> >> index d20e65971a55..4fffdd99d0fb 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> >> @@ -24,5 +24,10 @@ struct scaler_filter_coeff { void
> >> intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state);
> >> void intel_sharpness_scaler_compute_config(struct intel_crtc_state
> >> *crtc_state); int intel_filter_compute_config(struct
> >> intel_crtc_state *crtc_state);
> >> +void intel_filter_lut_load(struct intel_crtc *crtc,
> >> + const struct intel_crtc_state *crtc_state); bool
> >> +intel_sharpness_strength_changed(struct intel_atomic_state *state);
> >> +void intel_sharpness_disable(struct intel_crtc_state *crtc_state);
> >> +bool sharp_compute(struct intel_crtc_state *crtc_state);
> >>
> >> #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git
> >> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index
> >> 9492fda15627..2fa42e10bb63 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2396,6 +2396,23 @@
> >> _ID(id, _PS_COEF_SET0_DATA_1A,
> >> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> >> _ID(id, _PS_COEF_SET0_DATA_1B,
> >> _PS_COEF_SET0_DATA_2B) + (set) * 8)
> >>
> >> +#define _SHARPNESS_CTL_A 0x682B0
> >> +#define SHARPNESS_CTL(trans) _MMIO_PIPE2(dev_priv, trans,
> >> _SHARPNESS_CTL_A)
> >> +#define FILTER_EN REG_BIT(31)
> >> +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8)
> >> +#define FILTER_STRENGTH(x)
> >> REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x))
> >> +#define FILTER_SIZE_MASK REG_GENMASK(1, 0)
> >> +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x))
> >> +
> >> +#define _SHRPLUT_DATA_A 0x682B8
> >> +#define SHRPLUT_DATA(trans) _MMIO_PIPE2(dev_priv, trans,
> >> _SHRPLUT_DATA_A)
> >> +
> >> +#define _SHRPLUT_INDEX_A 0x682B4
> >> +#define SHRPLUT_INDEX(trans) _MMIO_PIPE2(dev_priv, trans,
> >> _SHRPLUT_INDEX_A)
> >> +#define INDEX_AUTO_INCR REG_BIT(10)
> >> +#define INDEX_VALUE_MASK REG_GENMASK(4, 0)
> >> +#define INDEX_VALUE(x)
> >> REG_FIELD_PREP(INDEX_VALUE_MASK, (x))
> >> +
> >> /* Display Internal Timeout Register */
> >> #define RM_TIMEOUT _MMIO(0x42060)
> >> #define MMIO_TIMEOUT_US(us) ((us) << 0)
> >> --
> >> 2.25.1
> >
> > Thanks and Regards,
> > Arun R Murthy
> > --------------------
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [v4 2/5] drm/i915/display: Compute the scaler filter coefficients
2024-09-09 5:26 ` Garg, Nemesa
@ 2024-09-10 7:22 ` Murthy, Arun R
0 siblings, 0 replies; 20+ messages in thread
From: Murthy, Arun R @ 2024-09-10 7:22 UTC (permalink / raw)
To: Garg, Nemesa, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
> > > The sharpness property requires the use of one of the scaler so need
> > > to set the sharpness scaler coefficient values.
> > > These values are based on experiments and vary for different tap
> > > value/win size. These values are normalized by taking the sum of all
> > > values and then dividing each value with a sum.
> > >
> > > --v4: fix ifndef header naming issue reported by kernel test robot
> > >
> > > Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/Makefile | 1 +
> > > drivers/gpu/drm/i915/display/intel_display.c | 2 +
> > > .../drm/i915/display/intel_display_types.h | 9 ++
> > > .../drm/i915/display/intel_sharpen_filter.c | 121 ++++++++++++++++++
> > > .../drm/i915/display/intel_sharpen_filter.h | 27 ++++
> > > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > > drivers/gpu/drm/xe/Makefile | 1 +
> > > 7 files changed, 163 insertions(+)
> > > create mode 100644
> > > drivers/gpu/drm/i915/display/intel_sharpen_filter.c
> > > create mode 100644
> > > drivers/gpu/drm/i915/display/intel_sharpen_filter.h
> >
> > Can a unified name be used across the patches. ->
> > intel_sharpness_filter.c
> >
> > >
> > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..0021f0a372ab
> > > 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -280,6 +280,7 @@ i915-y += \
> > > display/intel_pmdemand.o \
> > > display/intel_psr.o \
> > > display/intel_quirks.o \
> > > + display/intel_sharpen_filter.o \
> > > display/intel_sprite.o \
> > > display/intel_sprite_uapi.o \
> > > display/intel_tc.o \
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index c2c388212e2e..a62560a0c1a9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -5906,6 +5906,8 @@ static int intel_atomic_check_planes(struct
> > > intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > + intel_sharpness_scaler_compute_config(new_crtc_state);
> > > +
> > > /*
> > > * On some platforms the number of active planes affects
> > > * the planes' minimum cdclk calculation. Add such planes diff -
> > > -git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 8713835e2307..1c3e031ab369 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -55,6 +55,7 @@
> > > #include "intel_display_limits.h"
> > > #include "intel_display_power.h"
> > > #include "intel_dpll_mgr.h"
> > > +#include "intel_sharpen_filter.h"
> > > #include "intel_wm_types.h"
> > >
> > > struct drm_printer;
> > > @@ -828,6 +829,13 @@ struct intel_scaler {
> > > u32 mode;
> > > };
> > >
> > > +struct intel_sharpness_filter {
> > > + struct scaler_filter_coeff coeff[7];
> > > + u32 scaler_coefficient[119];
> > What is this magic number 119 and 7?
> > For each win size there are 7 coefficients, so coeff[7] is used to store these
> values which are further used in calculating scaler coefficients.
> As we need to compute scaler coefficients for 17 phases of 7 taps I have used
> scaler_coefficient[119] .
Can these magic numbers be replaced with a meaningful macros?
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2024-09-10 7:23 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-08 8:09 [0/5] Introduce drm sharpening property Nemesa Garg
2024-07-08 8:09 ` [1/5] drm: Introduce sharpness mode property Nemesa Garg
2024-08-29 8:33 ` Murthy, Arun R
2024-09-04 9:19 ` Shankar, Uma
2024-07-08 8:09 ` [v4 2/5] drm/i915/display: Compute the scaler filter coefficients Nemesa Garg
2024-08-29 9:04 ` Murthy, Arun R
2024-09-09 5:26 ` Garg, Nemesa
2024-09-10 7:22 ` Murthy, Arun R
2024-07-08 8:09 ` [3/5] drm/i915/display: Enable the second scaler for sharpness Nemesa Garg
2024-08-30 4:44 ` Murthy, Arun R
2024-09-09 10:23 ` Garg, Nemesa
2024-07-08 8:09 ` [4/5] drm/i915/display: Add registers and compute the strength Nemesa Garg
2024-08-30 8:04 ` Murthy, Arun R
2024-08-30 8:33 ` Jani Nikula
2024-09-09 10:26 ` Garg, Nemesa
2024-07-08 8:09 ` [5/5] drm/i915/display: Load the lut values and enable sharpness Nemesa Garg
2024-07-08 8:49 ` ✗ Fi.CI.CHECKPATCH: warning for Introduce drm sharpening property (rev4) Patchwork
2024-07-08 8:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-07-08 8:57 ` ✓ Fi.CI.BAT: success " Patchwork
2024-07-08 10:10 ` ✗ Fi.CI.IGT: failure " Patchwork
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