From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Modify CAGF functions for MTL
Date: Fri, 14 Oct 2022 20:34:52 -0700 [thread overview]
Message-ID: <87wn91ep43.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <YyidgzOwS5CT+RVN@alfio.lan>
On Mon, 19 Sep 2022 09:49:07 -0700, Andi Shyti wrote:
>
> Hi Badal,
Hi Andi,
Badal is out for a bit so I am sending out this version.
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
>
> can you please use the imperative form? "Update" and not
> "Updated".
> Besides I don't really understand what you did from the
> commit, can you please bea bit more descriptive?
Done in series version v5. Please take a look.
> > Bspec: 66300
> >
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++++++
> > drivers/gpu/drm/i915/gt/intel_rps.c | 6 +++++-
> > 2 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 2275ee47da95..7819d32db956 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1510,6 +1510,14 @@
> > #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
> >
> > +/*
> > + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
> > + * 3D - 0x0C60 , SAMedia - 0x380C60
> > + * Intel uncore handler redirects transactions for SAMedia to MTL_MEDIA_GSI_BASE
> > + */
>
> This comment is not understandable... we don't have limits in
> space, you can be a bit more explicit :)
Based on Matt R's comment the comment has been deleted (except for the
first line). There is an explanation at the bottom of gt/intel_gt_regs.h.
Thanks.
--
Ashutosh
next prev parent reply other threads:[~2022-10-15 3:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 11:59 [Intel-gfx] [PATCH 0/2] i915: CAGF and RC6 changes for MTL Badal Nilawar
2022-09-19 11:59 ` [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Modify CAGF functions " Badal Nilawar
2022-09-19 16:49 ` Andi Shyti
2022-09-19 17:21 ` Nilawar, Badal
2022-10-15 3:34 ` Dixit, Ashutosh [this message]
2022-09-19 22:46 ` Matt Roper
2022-09-19 22:49 ` Matt Roper
2022-10-15 3:34 ` Dixit, Ashutosh
2022-09-19 11:59 ` [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add C6 residency support for MTL SAMedia Badal Nilawar
2022-09-19 12:13 ` Jani Nikula
2022-09-20 3:33 ` Dixit, Ashutosh
2022-09-20 8:06 ` Jani Nikula
2022-10-15 3:38 ` Dixit, Ashutosh
2022-09-19 12:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev4) Patchwork
2022-09-19 14:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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