From: Eric Anholt <eric@anholt.net>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Prefer setting PTE cache age to 3
Date: Fri, 22 Nov 2013 10:38:41 -0800 [thread overview]
Message-ID: <87wqk0gu32.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <1385116673-21675-1-git-send-email-chris@chris-wilson.co.uk>
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Chris Wilson <chris@chris-wilson.co.uk> writes:
> We have conflicting benchmark data that suggest either age 0 or age 3 is
> better. However, the earlier benchmark on which we based the switch to
> age 0
>
> (commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
> Author: Ben Widawsky <benjamin.widawsky@intel.com>
> Date: Thu Jul 4 11:02:03 2013 -0700
>
> drm/i915/hsw: Set correct Haswell PTE encodings)
>
> actually seems to prefer the default PTE encoding as age 3. Presumably,
> this is in part due to the use of MOCS to override the PTE encodings
> when appropriate.
This bothered me when reviewing the kernel code for hsw. Thanks.
Reviewed-by: Eric Anholt <eric@anholt.net>
Note that userspace doesn't currently set MOCS other than the L3 bit.
I'm hoping we end up not having to, since we don't have a WT option in
MOCS other than "just listen to the PTEs".
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next prev parent reply other threads:[~2013-11-22 18:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-22 10:37 [PATCH] drm/i915: Prefer setting PTE cache age to 3 Chris Wilson
2013-11-22 17:53 ` Jesse Barnes
2013-11-22 18:26 ` Ville Syrjälä
2013-11-22 18:38 ` Eric Anholt [this message]
2013-11-25 8:50 ` Daniel Vetter
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