Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names

From: Jani Nikula <jani.nikula@intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>,
	Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
Date: Fri, 02 Nov 2018 09:14:35 +0200	[thread overview]
Message-ID: <87y3acdk84.fsf@intel.com> (raw)
In-Reply-To: <20181102050824.GA27559@intel.com>

On Thu, 01 Nov 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> Pushed to the dinq, thanks for the patch.

Thanks, sorry for the trouble.

BR,
Jani.

>
> Manasi
>
> On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote:
>> On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
>> > This patch fixes the naming of the registers:
>> > 
>> > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>> > 
>> > And also fix the hex values to lower case, to match
>> > rest of the definitions.
>> > 
>> > Manasi noticed this with the patch that was merged.
>> > 
>> > v2: fix "Fixes" tag.
>> > 
>> > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
>> > Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
>> > Cc: Jani Nikula <jani.nikula@intel.com>
>> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> 
>> Looks good.
>> 
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> 
>> Manasi
>> 
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
>> >  1 file changed, 11 insertions(+), 11 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index aef1a30ff9f6..c0e6e14fe9fa 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -10050,7 +10050,7 @@ enum skl_power_gate {
>> >  #define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
>> >  #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
>> >  #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
>> > -#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5A0
>> > +#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
>> >  
>> >  #define DSS_CTL2				_MMIO(0x67404)
>> >  #define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
>> > @@ -10058,20 +10058,20 @@ enum skl_power_gate {
>> >  #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
>> >  #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
>> >  
>> > -#define _PIPE_DSS_CTL1_PB			0x78200
>> > -#define _PIPE_DSS_CTL1_PC			0x78400
>> > -#define PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>> > -							   _PIPE_DSS_CTL1_PB, \
>> > -							   _PIPE_DSS_CTL1_PC)
>> > +#define _ICL_PIPE_DSS_CTL1_PB			0x78200
>> > +#define _ICL_PIPE_DSS_CTL1_PC			0x78400
>> > +#define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>> > +							   _ICL_PIPE_DSS_CTL1_PB, \
>> > +							   _ICL_PIPE_DSS_CTL1_PC)
>> >  #define  BIG_JOINER_ENABLE			(1 << 29)
>> >  #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
>> >  #define  VGA_CENTERING_ENABLE			(1 << 27)
>> >  
>> > -#define _PIPE_DSS_CTL2_PB			0x78204
>> > -#define _PIPE_DSS_CTL2_PC			0x78404
>> > -#define PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>> > -							   _PIPE_DSS_CTL2_PB, \
>> > -							   _PIPE_DSS_CTL2_PC)
>> > +#define _ICL_PIPE_DSS_CTL2_PB			0x78204
>> > +#define _ICL_PIPE_DSS_CTL2_PC			0x78404
>> > +#define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
>> > +							   _ICL_PIPE_DSS_CTL2_PB, \
>> > +							   _ICL_PIPE_DSS_CTL2_PC)
>> >  
>> >  #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
>> >  #define  STAP_SELECT					(1 << 0)
>> > -- 
>> > 2.17.1
>> > 
>> _______________________________________________
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-- 
Jani Nikula, Intel Open Source Graphics Center
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