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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/selftests: Break out of the lrc layout test after register mismatch
Date: Wed, 6 Jan 2021 15:10:02 +0000	[thread overview]
Message-ID: <8b055b6d-e260-e8df-2ef2-b4898b874dc9@linux.intel.com> (raw)
In-Reply-To: <20210106123939.18435-1-chris@chris-wilson.co.uk>


On 06/01/2021 12:39, Chris Wilson wrote:
> AFter detecting a register mismatch between the protocontext and the
> image generated by HW, immediately break out of the double loop.
> (Otherwise we end up a second configuing error message.)

s/configuing/confusing/?

No use of dumping all differences? Why it is confusing?

Regards,

Tvrtko

> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index 3485cb7c431d..920979a89413 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -164,7 +164,7 @@ static int live_lrc_layout(void *arg)
>   
>   		dw = 0;
>   		do {
> -			u32 lri = hw[dw];
> +			u32 lri = READ_ONCE(hw[dw]);
>   
>   			if (lri == 0) {
>   				dw++;
> @@ -197,9 +197,11 @@ static int live_lrc_layout(void *arg)
>   			dw++;
>   
>   			while (lri) {
> -				if (hw[dw] != lrc[dw]) {
> +				u32 offset = READ_ONCE(hw[dw]);
> +
> +				if (offset != lrc[dw]) {
>   					pr_err("%s: Different registers found at dword %d, expected %x, found %x\n",
> -					       engine->name, dw, hw[dw], lrc[dw]);
> +					       engine->name, dw, offset, lrc[dw]);
>   					err = -EINVAL;
>   					break;
>   				}
> @@ -211,7 +213,7 @@ static int live_lrc_layout(void *arg)
>   				dw += 2;
>   				lri -= 2;
>   			}
> -		} while ((lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
> +		} while (!err && (lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
>   
>   		if (err) {
>   			pr_info("%s: HW register image:\n", engine->name);
> 
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  parent reply	other threads:[~2021-01-06 15:10 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-06 12:39 [Intel-gfx] [PATCH 1/4] drm/i915/selftests: Break out of the lrc layout test after register mismatch Chris Wilson
2021-01-06 12:39 ` [Intel-gfx] [PATCH 2/4] drm/i915/selftests: Improve handling of iomem around stolen Chris Wilson
2021-01-06 15:12   ` Tvrtko Ursulin
2021-01-06 12:39 ` [Intel-gfx] [PATCH 3/4] drm/i915/gt: Restore ce->signal flush before releasing virtual engine Chris Wilson
2021-01-06 12:39 ` [Intel-gfx] [PATCH 4/4] drm/i915/gt: Remove timeslice suppression Chris Wilson
2021-01-06 15:57   ` Tvrtko Ursulin
2021-01-06 16:08     ` Chris Wilson
2021-01-06 16:19       ` Chris Wilson
2021-01-07 10:16       ` Tvrtko Ursulin
2021-01-07 10:27         ` Chris Wilson
2021-01-07 12:52           ` Tvrtko Ursulin
2021-01-06 13:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/selftests: Break out of the lrc layout test after register mismatch Patchwork
2021-01-06 13:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-06 13:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-06 15:10 ` Tvrtko Ursulin [this message]
2021-01-06 15:17   ` [Intel-gfx] [PATCH 1/4] " Chris Wilson
2021-01-06 15:28     ` Tvrtko Ursulin
2021-01-06 16:38 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork

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