* [PATCH v10 01/17] drm/i915/display: Add source param for dc balance
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 02/17] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
` (16 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Add source param for dc balance enablement.
--v2:
- Arrange in alphabetic order. (Ankit)
- Update name. (Ankit)
--v3:
- Commit message update. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..7ad49e9529f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -200,6 +200,7 @@ struct intel_display_platforms {
#define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \
DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
#define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
+#define HAS_VRR_DC_BALANCE(__display) (DISPLAY_VER(__display) >= 30)
#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
#define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical)
#define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv)
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 02/17] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-12-02 7:36 ` [PATCH v10 01/17] drm/i915/display: Add source param for dc balance Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 03/17] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
` (15 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add pipe dmc registers and access bits for DC Balance params
configuration and enablement.
--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)
--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.
--v4:
- Add DCB Flip count and balance reset registers.
--v5:
- Correct macro usage for flip count. (Ankit)
- Use register offset in lower case.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index c5aa49921cb9..38e342b45af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -584,4 +584,64 @@ enum pipedmc_event_id {
#define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
#define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
+#define _PIPEDMC_DCB_CTL_A 0x5f1a0
+#define _PIPEDMC_DCB_CTL_B 0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+ _PIPEDMC_DCB_CTL_B)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+ _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+ _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+ _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+ _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+ _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A 0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B 0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+ _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A 0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B 0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+ _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+ _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A 0x5f040
+#define _PIPEDMC_EVT_CTL_3_B 0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+ _PIPEDMC_EVT_CTL_3_B)
+
+#define _PIPEDMC_DCB_FLIP_COUNT_A 0x906a4
+#define _PIPEDMC_DCB_FLIP_COUNT_B 0x986a4
+#define PIPEDMC_DCB_FLIP_COUNT(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_FLIP_COUNT_A,\
+ _PIPEDMC_DCB_FLIP_COUNT_B)
+
+#define _PIPEDMC_DCB_BALANCE_RESET_A 0x906a8
+#define _PIPEDMC_DCB_BALANCE_RESET_B 0x986a8
+#define PIPEDMC_DCB_BALANCE_RESET(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\
+ _PIPEDMC_DCB_BALANCE_RESET_B)
#endif /* __INTEL_DMC_REGS_H__ */
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 03/17] drm/i915/vrr: Add VRR DC balance registers
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-12-02 7:36 ` [PATCH v10 01/17] drm/i915/display: Add source param for dc balance Mitul Golani
2025-12-02 7:36 ` [PATCH v10 02/17] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
` (14 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Add VRR register offsets and bits to access DC Balance configuration.
--v2:
- Separate register definitions. (Ankit)
- Remove usage of dev_priv. (Jani, Nikula)
--v3:
- Convert register address offset, from capital to small. (Ankit)
- Move mask bits near to register offsets. (Ankit)
--v4:
- Use _MMIO_TRANS wherever possible. (Jani)
--v5:
- Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw
- For pipe B it is temporary and expected to change later once finalised.
--v6:
- Add live value registers for DCB VMAX/FLIPLINE.
--v7:
- Correct commit message file. (Jani Nikula)
- Add bits in highest to lowest order. (Jani Nikula)
--v8:
- Register/bitfields indentation changes as per i915_reg.h
mentioned format (Jani, Ankit)
--v9:
- Remove comment. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index ba9b9215dc11..427ada0d3973 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,73 @@
#include "intel_display_reg_defs.h"
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
+ (flipline))
+
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A 0x90700
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B 0x98700
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \
+ _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A 0x906f8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B 0x986f8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B)
+
+#define _TRANS_VRR_DCB_FLIPLINE_A 0x60418
+#define _TRANS_VRR_DCB_FLIPLINE_B 0x61418
+#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_FLIPLINE_A, \
+ _TRANS_VRR_DCB_FLIPLINE_B)
+#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
+ (flipline))
+
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_A 0x906fc
+#define _TRANS_VRR_DCB_FLIPLINE_LIVE_B 0x986fc
+#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \
+ _TRANS_VRR_DCB_FLIPLINE_LIVE_B)
+
+#define _TRANS_VRR_DCB_VMAX_A 0x60414
+#define _TRANS_VRR_DCB_VMAX_B 0x61414
+#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_VMAX_A, \
+ _TRANS_VRR_DCB_VMAX_B)
+#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
+
+#define _TRANS_VRR_DCB_VMAX_LIVE_A 0x906f4
+#define _TRANS_VRR_DCB_VMAX_LIVE_B 0x986f4
+#define TRANS_VRR_DCB_VMAX_LIVE(trans) _MMIO_TRANS(trans, \
+ _TRANS_VRR_DCB_VMAX_LIVE_A, \
+ _TRANS_VRR_DCB_VMAX_LIVE_B)
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \
+ _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
+ _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
+#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
+
#define _TRANS_VRR_CTL_A 0x60420
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
@@ -19,6 +86,7 @@
#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (2 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 03/17] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 6:22 ` Shankar, Uma
2025-12-16 12:33 ` Nautiyal, Ankit K
2025-12-02 7:36 ` [PATCH v10 05/17] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
` (13 subsequent siblings)
17 siblings, 2 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.
--v2:
- Correct Author details.
--v3:
- Separate register details from this patch.
--v4:
- Add mask macros.
--v5:
- As live prefix params indicate timings for current frame,
read just _live prefix values instead of next frame timings as
done previously.
- Squash Refactor vrr params patch.
--v6:
- Use error code while returning invalid values. (Jani, Nikula)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++
2 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b92c42fde937..31f3a7b6e00d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
return value - crtc_state->set_context_latency;
}
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+ int vmin_vmax)
+{
+ return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;
+}
+
/*
* For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
* Vtotal value.
@@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
return intel_vrr_vmin_vblank_start(crtc_state) -
crtc_state->set_context_latency;
}
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
+
+ if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+ return -EINVAL;
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
+
+ if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+ return -EINVAL;
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 tmp = 0;
+
+ tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
+
+ return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..66fb9ad846f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_VRR_H__ */
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff
2025-12-02 7:36 ` [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
@ 2025-12-15 6:22 ` Shankar, Uma
2025-12-16 12:33 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 6:22 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax
> stuff
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Calculate delayed vblank start position with the help of added vmin/vmax stuff for
> next frame and final computation.
>
> --v2:
> - Correct Author details.
>
> --v3:
> - Separate register details from this patch.
>
> --v4:
> - Add mask macros.
>
> --v5:
> - As live prefix params indicate timings for current frame, read just _live prefix
> values instead of next frame timings as done previously.
> - Squash Refactor vrr params patch.
>
> --v6:
> - Use error code while returning invalid values. (Jani, Nikula)
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b92c42fde937..31f3a7b6e00d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct
> intel_crtc_state *crtc_state,
> return value - crtc_state->set_context_latency; }
>
> +static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
> + int vmin_vmax)
> +{
> + return intel_vrr_hw_value(crtc_state, vmin_vmax) -
> +crtc_state->vrr.guardband; }
> +
> /*
> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
> * Vtotal value.
> @@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct
> intel_crtc_state *crtc_state)
> return intel_vrr_vmin_vblank_start(crtc_state) -
> crtc_state->set_context_latency; }
> +
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display,
> +TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
> +
> + if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> + return -EINVAL;
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp)
> +
> +1); }
> +
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display,
> +TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
> +
> + if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
> + return -EINVAL;
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) +
> 1);
> +}
> +
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display,
> +TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display,
> TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1); }
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
> b/drivers/gpu/drm/i915/display/intel_vrr.h
> index bc9044621635..66fb9ad846f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display
> *display); int intel_vrr_safe_window_start(const struct intel_crtc_state
> *crtc_state); int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state
> *crtc_state);
>
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state
> +*crtc_state); int intel_vrr_dcb_vmax_vblank_start_next(const struct
> +intel_crtc_state *crtc_state); int
> +intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state
> +*crtc_state); int intel_vrr_dcb_vmax_vblank_start_final(const struct
> +intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_VRR_H__ */
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff
2025-12-02 7:36 ` [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-12-15 6:22 ` Shankar, Uma
@ 2025-12-16 12:33 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Nautiyal, Ankit K @ 2025-12-16 12:33 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: intel-xe, ville.syrjala, uma.shankar, jani.nikula
On 12/2/2025 1:06 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Calculate delayed vblank start position with the help of added
> vmin/vmax stuff for next frame and final computation.
>
> --v2:
> - Correct Author details.
>
> --v3:
> - Separate register details from this patch.
>
> --v4:
> - Add mask macros.
>
> --v5:
> - As live prefix params indicate timings for current frame,
> read just _live prefix values instead of next frame timings as
> done previously.
> - Squash Refactor vrr params patch.
>
> --v6:
> - Use error code while returning invalid values. (Jani, Nikula)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b92c42fde937..31f3a7b6e00d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
> return value - crtc_state->set_context_latency;
> }
>
> +static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
> + int vmin_vmax)
> +{
> + return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;
> +}
> +
> /*
> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
> * Vtotal value.
> @@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
> return intel_vrr_vmin_vblank_start(crtc_state) -
> crtc_state->set_context_latency;
> }
> +
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
> +
> + if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> + return -EINVAL;
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
> +
> + if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
> + return -EINVAL;
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 tmp = 0;
> +
> + tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
> +
> + return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index bc9044621635..66fb9ad846f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
> int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
>
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_VRR_H__ */
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v10 05/17] drm/i915/vrr: Add DC Balance params to crtc_state
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (3 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 06/17] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
` (12 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Add DC Balance params to crtc_state, also add state checker
params for related properties.
--v3:
- Seggregate crtc_state params with this patch. (Ankit)
--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)
--v5:
- Add headers in sorted order. (Jani Nikula)
--v6:
- Add a separate function to get and check dc_balance params.
- Avoid repeatative use of MMIO read. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++++
.../drm/i915/display/intel_display_types.h | 7 ++++
drivers/gpu/drm/i915/display/intel_vrr.c | 32 +++++++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5563ff7ee10e..0a16c37b1dc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5462,6 +5462,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(cmrr.enable);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
}
if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ed0f7448e6cd..85de0e417c8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1357,6 +1357,13 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
+ struct {
+ bool enable;
+ u16 vmin, vmax;
+ u16 guardband, slope;
+ u16 max_increase, max_decrease;
+ u16 vblank_target;
+ } dc_balance;
} vrr;
/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 31f3a7b6e00d..427ef1741051 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_dmc_regs.h"
#include "intel_dp.h"
#include "intel_psr.h"
#include "intel_vrr.h"
@@ -785,6 +786,35 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.flipline == crtc_state->vrr.vmin;
}
+static
+void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
+{
+ u32 reg_val;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ if (!HAS_VRR_DC_BALANCE(display))
+ return;
+
+ reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
+ crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;
+
+ reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
+ crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;
+
+ crtc_state->vrr.dc_balance.guardband =
+ intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
+ crtc_state->vrr.dc_balance.max_increase =
+ intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
+ crtc_state->vrr.dc_balance.max_decrease =
+ intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
+ crtc_state->vrr.dc_balance.slope =
+ intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
+ crtc_state->vrr.dc_balance.vblank_target =
+ intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
+}
+
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -866,6 +896,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
else
crtc_state->vrr.enable = vrr_enable;
+ intel_vrr_get_dc_balance_config(crtc_state);
+
/*
* #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
* Since CMRR is currently disabled, set this flag for VRR for now.
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 06/17] drm/i915/vrr: Add state dump for DC Balance params
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (4 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 05/17] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 07/17] drm/i915/vrr: Add compute config " Mitul Golani
` (11 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Add state dump for dc balance params to track DC Balance
crtc state config.
-v1:
-- nitpick: s/Vblank target/vblank target. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index c2a6217c2262..234843b8f83a 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -303,6 +303,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
+ drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d vblank target: %d\n",
+ str_yes_no(pipe_config->vrr.dc_balance.enable),
+ pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+ pipe_config->vrr.dc_balance.guardband,
+ pipe_config->vrr.dc_balance.slope,
+ pipe_config->vrr.dc_balance.max_increase,
+ pipe_config->vrr.dc_balance.max_decrease,
+ pipe_config->vrr.dc_balance.vblank_target);
drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(&pipe_config->hw.mode));
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 07/17] drm/i915/vrr: Add compute config for DC Balance params
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (5 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 06/17] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 6:25 ` Shankar, Uma
2025-12-02 7:36 ` [PATCH v10 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params Mitul Golani
` (10 subsequent siblings)
17 siblings, 1 reply; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Compute DC Balance parameters and tunable params based on
experiments.
--v2:
- Document tunable params. (Ankit)
--v3:
- Add line spaces to compute config. (Ankit)
- Remove redundancy checks.
--v4:
- Separate out conpute config to separate function.
- As all the valuse are being computed in scanlines, and slope
is still in usec, convert and store it to scanlines.
--v5:
- Update and add comments for slope calculation. (Ankit)
- Update early return conditions for dc balance compute. (Ankit)
--v6:
- Early return condition simplified for dc balance compute config. (Ankit)
- Make use of pipe restrictions to this patch. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 427ef1741051..74ad661f2654 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,6 +6,7 @@
#include <drm/drm_print.h>
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
@@ -20,6 +21,14 @@
#define FIXED_POINT_PRECISION 100
#define CMRR_PRECISION_TOLERANCE 10
+/*
+ * Tunable parameters for DC Balance correction.
+ * These are captured based on experimentations.
+ */
+#define DCB_CORRECTION_SENSITIVITY 30
+#define DCB_CORRECTION_AGGRESSIVENESS 1000 /* ms × 100; 10 ms */
+#define DCB_BLANK_TARGET 50
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
@@ -342,6 +351,55 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
return vmax;
}
+static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+ * FIXME: Currently Firmware supports DC Balancing on PIPE A
+ * and PIPE B. Account those limitation while computing DC
+ * Balance parameters.
+ */
+ return (HAS_VRR_DC_BALANCE(display) &&
+ ((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
+static void
+intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
+{
+ int guardband_usec, adjustment_usec;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)
+ return;
+
+ crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+ crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_increase =
+ crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_decrease =
+ crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.guardband =
+ DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
+ DCB_CORRECTION_SENSITIVITY, 100);
+ guardband_usec =
+ intel_scanlines_to_usecs(adjusted_mode,
+ crtc_state->vrr.dc_balance.guardband);
+ /*
+ * The correction_aggressiveness/100 is the number of milliseconds to
+ * adjust by when the balance is at twice the guardband.
+ * guardband_slope = correction_aggressiveness / (guardband * 100)
+ */
+ adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
+ crtc_state->vrr.dc_balance.slope =
+ DIV_ROUND_UP(adjustment_usec, guardband_usec);
+ crtc_state->vrr.dc_balance.vblank_target =
+ DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
+ DCB_BLANK_TARGET, 100);
+}
+
void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -399,6 +457,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
(crtc_state->hw.adjusted_mode.crtc_vtotal -
crtc_state->hw.adjusted_mode.crtc_vsync_end);
}
+
+ intel_vrr_dc_balance_compute_config(crtc_state);
}
static int
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 07/17] drm/i915/vrr: Add compute config for DC Balance params
2025-12-02 7:36 ` [PATCH v10 07/17] drm/i915/vrr: Add compute config " Mitul Golani
@ 2025-12-15 6:25 ` Shankar, Uma
0 siblings, 0 replies; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 6:25 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 07/17] drm/i915/vrr: Add compute config for DC Balance
> params
>
> Compute DC Balance parameters and tunable params based on experiments.
>
> --v2:
> - Document tunable params. (Ankit)
>
> --v3:
> - Add line spaces to compute config. (Ankit)
> - Remove redundancy checks.
>
> --v4:
> - Separate out conpute config to separate function.
> - As all the valuse are being computed in scanlines, and slope is still in usec,
> convert and store it to scanlines.
>
> --v5:
> - Update and add comments for slope calculation. (Ankit)
> - Update early return conditions for dc balance compute. (Ankit)
>
> --v6:
> - Early return condition simplified for dc balance compute config. (Ankit)
> - Make use of pipe restrictions to this patch. (Ankit)
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 427ef1741051..74ad661f2654 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -6,6 +6,7 @@
>
> #include <drm/drm_print.h>
>
> +#include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> @@ -20,6 +21,14 @@
> #define FIXED_POINT_PRECISION 100
> #define CMRR_PRECISION_TOLERANCE 10
>
> +/*
> + * Tunable parameters for DC Balance correction.
> + * These are captured based on experimentations.
> + */
> +#define DCB_CORRECTION_SENSITIVITY 30
> +#define DCB_CORRECTION_AGGRESSIVENESS 1000 /* ms × 100; 10 ms
> */
> +#define DCB_BLANK_TARGET 50
> +
> bool intel_vrr_is_capable(struct intel_connector *connector) {
> struct intel_display *display = to_intel_display(connector); @@ -342,6
> +351,55 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
> return vmax;
> }
>
> +static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum pipe pipe = crtc->pipe;
> +
> + /*
> + * FIXME: Currently Firmware supports DC Balancing on PIPE A
> + * and PIPE B. Account those limitation while computing DC
> + * Balance parameters.
> + */
> + return (HAS_VRR_DC_BALANCE(display) &&
> + ((pipe == PIPE_A) || (pipe == PIPE_B))); }
> +
> +static void
> +intel_vrr_dc_balance_compute_config(struct intel_crtc_state
> +*crtc_state) {
> + int guardband_usec, adjustment_usec;
> + struct drm_display_mode *adjusted_mode =
> +&crtc_state->hw.adjusted_mode;
> +
> + if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable)
> + return;
> +
> + crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> + crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.max_increase =
> + crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.max_decrease =
> + crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> + crtc_state->vrr.dc_balance.guardband =
> + DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax *
> + DCB_CORRECTION_SENSITIVITY, 100);
> + guardband_usec =
> + intel_scanlines_to_usecs(adjusted_mode,
> + crtc_state->vrr.dc_balance.guardband);
> + /*
> + * The correction_aggressiveness/100 is the number of milliseconds to
> + * adjust by when the balance is at twice the guardband.
> + * guardband_slope = correction_aggressiveness / (guardband * 100)
> + */
> + adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10;
> + crtc_state->vrr.dc_balance.slope =
> + DIV_ROUND_UP(adjustment_usec, guardband_usec);
> + crtc_state->vrr.dc_balance.vblank_target =
> + DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> + DCB_BLANK_TARGET, 100);
> +}
> +
> void
> intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state) @@ -399,6
> +457,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> (crtc_state->hw.adjusted_mode.crtc_vtotal -
> crtc_state->hw.adjusted_mode.crtc_vsync_end);
> }
> +
> + intel_vrr_dc_balance_compute_config(crtc_state);
> }
>
> static int
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v10 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (6 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 07/17] drm/i915/vrr: Add compute config " Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 09/17] drm/i915/display: Add DC Balance flip count operations Mitul Golani
` (9 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Add function which resets all accumulated DC Balance parameters
whenever adaptive mode of VRR goes off. This helps to give a
fresh start when VRR is re-enabled.
--v2:
- Typo, change crtc_state to old_crtc_state. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0a16c37b1dc6..798cb10ea3a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1158,6 +1158,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
if (intel_crtc_vrr_disabling(state, crtc)) {
intel_vrr_disable(old_crtc_state);
+ intel_vrr_dcb_reset(old_crtc_state, crtc);
intel_crtc_update_active_timings(old_crtc_state, false);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 74ad661f2654..637e4144cbea 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -646,6 +646,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
}
+void
+intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(old_crtc_state);
+ enum pipe pipe = crtc->pipe;
+
+ if (!old_crtc_state->vrr.dc_balance.enable)
+ return;
+
+ intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
+}
+
void intel_vrr_send_push(struct intel_dsb *dsb,
const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 66fb9ad846f2..d40ed5504180 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -11,6 +11,7 @@
struct drm_connector_state;
struct intel_atomic_state;
struct intel_connector;
+struct intel_crtc;
struct intel_crtc_state;
struct intel_dsb;
struct intel_display;
@@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc *crtc);
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 09/17] drm/i915/display: Add DC Balance flip count operations
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (7 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 10/17] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
` (8 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Track dc balance flip count with params per crtc. Increment
DC Balance Flip count before every flip to indicate DMC
firmware about new flip occurrence which needs to be adjusted
for dc balancing. This is tracked separately from legacy
FLIP_COUNT register also Reset DC balance flip count value
while disabling VRR adaptive mode, this is to start with
fresh counts when VRR adaptive refresh mode is triggered again.
--v2:
- Call during intel_update_crtc.(Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
.../gpu/drm/i915/display/intel_display_types.h | 4 ++++
drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 798cb10ea3a1..f9a779c555cc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6858,6 +6858,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
+ if (new_crtc_state->vrr.dc_balance.enable)
+ intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
+
/*
* We usually enable FIFO underrun interrupts as part of the
* CRTC enable sequence during modesets. But when we inherit a
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 85de0e417c8e..3cb972305d3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1501,6 +1501,10 @@ struct intel_crtc {
struct intel_link_m_n m_n, m2_n2;
} drrs;
+ struct {
+ u64 flip_count;
+ } dc_balance;
+
int scanline_offset;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 637e4144cbea..54ae9bb6b071 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -646,6 +646,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
}
+void
+intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+ struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum pipe pipe = crtc->pipe;
+
+ if (!crtc_state->vrr.dc_balance.enable)
+ return;
+
+ intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
+ ++crtc->dc_balance.flip_count);
+}
+
void
intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc *crtc)
@@ -656,6 +670,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
if (!old_crtc_state->vrr.dc_balance.enable)
return;
+ intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index d40ed5504180..bedcc8c4bff2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
const struct intel_crtc_state *crtc_state);
void intel_vrr_check_push_sent(struct intel_dsb *dsb,
const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+ struct intel_crtc *crtc);
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 10/17] drm/i915/vrr: Write DC balance params to hw registers
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (8 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 09/17] drm/i915/display: Add DC Balance flip count operations Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 11/17] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
` (7 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Write DC Balance parameters to hw registers.
--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)
--v3:
- Write registers at compute config.
- Update condition for write.
--v4:
- Address issue with state checker.
--v5:
- Initialise some more dc balance register while enabling VRR.
--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.
--v7:
- Initialise and reset live value of vmax and vmin as well.
--v8:
- Add separate functions while writing hw registers. (Ankit)
--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)
--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 54ae9bb6b071..3db61d1f0124 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -781,6 +781,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
intel_vrr_hw_flipline(crtc_state) - 1);
}
+static void
+intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ if (!crtc_state->vrr.dc_balance.enable)
+ return;
+
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
+ VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+ VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
+ VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+ VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
+ VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
+ VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+ crtc_state->vrr.dc_balance.vmin - 1);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+ crtc_state->vrr.dc_balance.vmax - 1);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+ crtc_state->vrr.dc_balance.max_increase);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+ crtc_state->vrr.dc_balance.max_decrease);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+ crtc_state->vrr.dc_balance.guardband);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+ crtc_state->vrr.dc_balance.slope);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+ crtc_state->vrr.dc_balance.vblank_target);
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+ ADAPTIVE_SYNC_COUNTER_EN);
+}
+
+static void
+intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_display *display = to_intel_display(old_crtc_state);
+ enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ if (!old_crtc_state->vrr.dc_balance.enable)
+ return;
+
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+}
+
static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
bool cmrr_enable)
{
@@ -827,6 +901,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
return;
intel_vrr_set_vrr_timings(crtc_state);
+ intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
@@ -842,6 +917,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
if (!intel_vrr_always_use_vrr_tg(display))
intel_vrr_tg_disable(old_crtc_state);
+ intel_vrr_disable_dc_balancing(old_crtc_state);
intel_vrr_set_fixed_rr_timings(old_crtc_state);
}
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 11/17] drm/i915/vblank: Extract vrr_vblank_start()
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (9 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 10/17] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 12/17] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
` (6 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Initialise delayed vblank position for evasion logic.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 671f357c6563..de20baeb9d99 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -652,6 +652,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
}
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+ if (intel_vrr_is_push_sent(crtc_state))
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state,
struct intel_vblank_evade_ctx *evade)
@@ -678,10 +686,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr);
- if (intel_vrr_is_push_sent(crtc_state))
- evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
- else
- evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+ evade->vblank_start = vrr_vblank_start(crtc_state);
vblank_delay = crtc_state->set_context_latency;
} else {
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 12/17] drm/i915/vrr: Implement vblank evasion with DC balancing
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (10 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 11/17] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
` (5 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ec2a3fb171ab..91060e2a5762 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -704,7 +704,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+ int vblank_delay = crtc_state->set_context_latency;
+ int vmin_vblank_start, vmax_vblank_start;
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+ if (vmin_vblank_start >= 0) {
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vmax_vblank_start >= 0) {
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ } else if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = crtc_state->set_context_latency;
end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index de20baeb9d99..df5879489963 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -654,10 +654,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
{
- if (intel_vrr_is_push_sent(crtc_state))
- return intel_vrr_vmin_vblank_start(crtc_state);
+ bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+ int vblank_start;
+
+ if (!crtc_state->vrr.dc_balance.enable) {
+ if (is_push_sent)
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+ }
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
else
- return intel_vrr_vmax_vblank_start(crtc_state);
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vblank_start >= 0)
+ return vblank_start;
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ else
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+ return vblank_start;
}
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (11 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 12/17] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 6:27 ` Shankar, Uma
2025-12-16 12:34 ` Nautiyal, Ankit K
2025-12-02 7:36 ` [PATCH v10 14/17] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
` (4 subsequent siblings)
17 siblings, 2 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
After VRR Push is sent, need to wait till flipline decision boundary
to get Push bit to get cleared.
--v2:
- Adjust delays to vrr vmin vblank delays. (Ankit)
--v3:
- Change intel_vrr_vmin_safe_window_end() so that
intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)
--v4:
- Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3db61d1f0124..4c1470dcd3bb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -1095,10 +1095,21 @@ int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
return crtc_state->hw.adjusted_mode.crtc_vdisplay;
}
+static int
+intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+ return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
+ intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
+ intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+}
+
int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_vmin_vblank_start(crtc_state) -
- crtc_state->set_context_latency;
+ int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
+ intel_vrr_dcb_vmin_vblank_start(crtc_state) :
+ intel_vrr_vmin_vblank_start(crtc_state);
+
+ return vmin_vblank_start - crtc_state->set_context_latency;
}
int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update
2025-12-02 7:36 ` [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
@ 2025-12-15 6:27 ` Shankar, Uma
2025-12-16 12:34 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 6:27 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update
>
> After VRR Push is sent, need to wait till flipline decision boundary to get Push bit
> to get cleared.
>
> --v2:
> - Adjust delays to vrr vmin vblank delays. (Ankit)
>
> --v3:
> - Change intel_vrr_vmin_safe_window_end() so that
> intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)
>
> --v4:
> - Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit)
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 3db61d1f0124..4c1470dcd3bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1095,10 +1095,21 @@ int intel_vrr_safe_window_start(const struct
> intel_crtc_state *crtc_state)
> return crtc_state->hw.adjusted_mode.crtc_vdisplay;
> }
>
> +static int
> +intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state
> +*crtc_state) {
> + return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
> + intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
> + intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
> +}
> +
> int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state) {
> - return intel_vrr_vmin_vblank_start(crtc_state) -
> - crtc_state->set_context_latency;
> + int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
> + intel_vrr_dcb_vmin_vblank_start(crtc_state) :
> + intel_vrr_vmin_vblank_start(crtc_state);
> +
> + return vmin_vblank_start - crtc_state->set_context_latency;
> }
>
> int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state
> *crtc_state)
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update
2025-12-02 7:36 ` [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-12-15 6:27 ` Shankar, Uma
@ 2025-12-16 12:34 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Nautiyal, Ankit K @ 2025-12-16 12:34 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: intel-xe, ville.syrjala, uma.shankar, jani.nikula
On 12/2/2025 1:06 PM, Mitul Golani wrote:
> After VRR Push is sent, need to wait till flipline decision boundary
> to get Push bit to get cleared.
>
> --v2:
> - Adjust delays to vrr vmin vblank delays. (Ankit)
>
> --v3:
> - Change intel_vrr_vmin_safe_window_end() so that
> intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit)
>
> --v4:
> - Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 3db61d1f0124..4c1470dcd3bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -1095,10 +1095,21 @@ int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
> return crtc_state->hw.adjusted_mode.crtc_vdisplay;
> }
>
> +static int
> +intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> + return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ?
> + intel_vrr_dcb_vmin_vblank_start_final(crtc_state) :
> + intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
> +}
> +
> int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
> {
> - return intel_vrr_vmin_vblank_start(crtc_state) -
> - crtc_state->set_context_latency;
> + int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ?
> + intel_vrr_dcb_vmin_vblank_start(crtc_state) :
> + intel_vrr_vmin_vblank_start(crtc_state);
> +
> + return vmin_vblank_start - crtc_state->set_context_latency;
> }
>
> int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v10 14/17] drm/i915/dsb: Add pipedmc dc balance enable/disable
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (12 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 13/17] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-02 7:36 ` [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
` (3 subsequent siblings)
17 siblings, 0 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add function to control DC balance enable/disable bit via DSB.
--v2:
Remove redundant forward declaration.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2fb6fec6dc99..e076ba7e0f28 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1755,3 +1755,20 @@ u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
}
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+ PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 40e9dcb033cc..9c6a42fc820e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -15,6 +15,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dmc_snapshot;
+struct intel_dsb;
void intel_dmc_init(struct intel_display *display);
void intel_dmc_load_program(struct intel_display *display);
@@ -39,6 +40,8 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
void assert_main_dmc_loaded(struct intel_display *display);
void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
void intel_pipedmc_enable_event(struct intel_crtc *crtc,
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (13 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 14/17] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 7:40 ` Shankar, Uma
2025-12-16 12:35 ` Nautiyal, Ankit K
2025-12-02 7:36 ` [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance Mitul Golani
` (2 subsequent siblings)
17 siblings, 2 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)
--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.
--v4:
- Move events to separate function.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9a779c555cc..3dbad592832e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7321,6 +7321,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
if (new_crtc_state->use_flipq)
intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
+ if (new_crtc_state->vrr.dc_balance.enable) {
+ /*
+ * Pause the DMC DC balancing for the remainder of
+ * the commit so that vmin/vmax won't change after
+ * we've baked them into the DSB vblank evasion
+ * commands.
+ *
+ * FIXME maybe need a small delay here to make sure
+ * DMC has finished updating the values? Or we need
+ * a better DMC<->driver protocol that gives is real
+ * guarantees about that...
+ */
+ intel_pipedmc_dcb_disable(NULL, crtc);
+ }
+
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_noarm(new_crtc_state->dsb_commit,
new_crtc_state);
@@ -7374,6 +7389,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
new_crtc_state);
+
+ if (new_crtc_state->vrr.dc_balance.enable)
+ intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
+
intel_dsb_interrupt(new_crtc_state->dsb_commit);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4c1470dcd3bb..38dc4f87e6fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dmc_regs.h"
#include "intel_dp.h"
#include "intel_psr.h"
@@ -824,6 +825,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.dc_balance.vblank_target);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
+ intel_pipedmc_dcb_enable(NULL, crtc);
}
static void
@@ -837,6 +839,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->vrr.dc_balance.enable)
return;
+ intel_pipedmc_dcb_disable(NULL, crtc);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits
2025-12-02 7:36 ` [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
@ 2025-12-15 7:40 ` Shankar, Uma
2025-12-16 12:35 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 7:40 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax
> won't change after we've baked them into the DSB vblank evasion commands.
>
> --v2:
> - Remove typo. (Ankit)
> - Separate vrr enable structuring. (Ankit)
>
> --v3:
> - Add gaurd before accessing DC balance bits.
> - Remove redundancy checks.
>
> --v4:
> - Move events to separate function.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f9a779c555cc..3dbad592832e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7321,6 +7321,21 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
> if (new_crtc_state->use_flipq)
> intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit,
> crtc);
>
> + if (new_crtc_state->vrr.dc_balance.enable) {
> + /*
> + * Pause the DMC DC balancing for the remainder of
> + * the commit so that vmin/vmax won't change after
> + * we've baked them into the DSB vblank evasion
> + * commands.
> + *
> + * FIXME maybe need a small delay here to make sure
> + * DMC has finished updating the values? Or we need
> + * a better DMC<->driver protocol that gives is real
> + * guarantees about that...
> + */
> + intel_pipedmc_dcb_disable(NULL, crtc);
> + }
> +
> if (intel_crtc_needs_color_update(new_crtc_state))
> intel_color_commit_noarm(new_crtc_state->dsb_commit,
> new_crtc_state);
> @@ -7374,6 +7389,10 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
> intel_dsb_wait_for_delayed_vblank(state, new_crtc_state-
> >dsb_commit);
> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> new_crtc_state);
> +
> + if (new_crtc_state->vrr.dc_balance.enable)
> + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit,
> crtc);
> +
> intel_dsb_interrupt(new_crtc_state->dsb_commit);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 4c1470dcd3bb..38dc4f87e6fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> +#include "intel_dmc.h"
> #include "intel_dmc_regs.h"
> #include "intel_dp.h"
> #include "intel_psr.h"
> @@ -824,6 +825,7 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.vblank_target);
> intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> + intel_pipedmc_dcb_enable(NULL, crtc);
> }
>
> static void
> @@ -837,6 +839,7 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> if (!old_crtc_state->vrr.dc_balance.enable)
> return;
>
> + intel_pipedmc_dcb_disable(NULL, crtc);
> intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits
2025-12-02 7:36 ` [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-12-15 7:40 ` Shankar, Uma
@ 2025-12-16 12:35 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Nautiyal, Ankit K @ 2025-12-16 12:35 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: intel-xe, ville.syrjala, uma.shankar, jani.nikula
On 12/2/2025 1:06 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pause the DMC DC Balancing for the remainder of the
> commit so that vmin/vmax won't change after we've baked
> them into the DSB vblank evasion commands.
>
> --v2:
> - Remove typo. (Ankit)
> - Separate vrr enable structuring. (Ankit)
>
> --v3:
> - Add gaurd before accessing DC balance bits.
> - Remove redundancy checks.
>
> --v4:
> - Move events to separate function.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 3 +++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f9a779c555cc..3dbad592832e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7321,6 +7321,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> if (new_crtc_state->use_flipq)
> intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
>
> + if (new_crtc_state->vrr.dc_balance.enable) {
> + /*
> + * Pause the DMC DC balancing for the remainder of
> + * the commit so that vmin/vmax won't change after
> + * we've baked them into the DSB vblank evasion
> + * commands.
> + *
> + * FIXME maybe need a small delay here to make sure
> + * DMC has finished updating the values? Or we need
> + * a better DMC<->driver protocol that gives is real
> + * guarantees about that...
> + */
> + intel_pipedmc_dcb_disable(NULL, crtc);
> + }
> +
> if (intel_crtc_needs_color_update(new_crtc_state))
> intel_color_commit_noarm(new_crtc_state->dsb_commit,
> new_crtc_state);
> @@ -7374,6 +7389,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
> intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> new_crtc_state);
> +
> + if (new_crtc_state->vrr.dc_balance.enable)
> + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
> +
> intel_dsb_interrupt(new_crtc_state->dsb_commit);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 4c1470dcd3bb..38dc4f87e6fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> +#include "intel_dmc.h"
> #include "intel_dmc_regs.h"
> #include "intel_dp.h"
> #include "intel_psr.h"
> @@ -824,6 +825,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.vblank_target);
> intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> + intel_pipedmc_dcb_enable(NULL, crtc);
> }
>
> static void
> @@ -837,6 +839,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> if (!old_crtc_state->vrr.dc_balance.enable)
> return;
>
> + intel_pipedmc_dcb_disable(NULL, crtc);
> intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (14 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 7:42 ` Shankar, Uma
2025-12-16 12:36 ` Nautiyal, Ankit K
2025-12-02 7:36 ` [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-12-02 8:40 ` ✗ i915.CI.BAT: failure for Enable/Disable DC balance along with VRR DSB Patchwork
17 siblings, 2 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Configure pipe dmc event for dc balance enable/disable.
--v2:
- Keeping function and removing unnecessary comments. (Jani, Nikula)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 8 ++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index e076ba7e0f28..1182bc9a2e6d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -859,6 +859,14 @@ static void dmc_configure_event(struct intel_display *display,
dmc_id, num_handlers, event_id);
}
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+ enum pipe pipe, bool enable)
+{
+ enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
+
+ dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
+}
+
/**
* intel_dmc_block_pkgc() - block PKG C-state
* @display: display instance
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 9c6a42fc820e..3d8a9a593319 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
bool block);
+void intel_dmc_configure_dc_balance_event(struct intel_display *display,
+ enum pipe pipe, bool enable);
void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
enum pipe pipe, bool enable);
void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 38dc4f87e6fe..ba8b3c664e70 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -823,6 +823,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.dc_balance.slope);
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
crtc_state->vrr.dc_balance.vblank_target);
+ intel_dmc_configure_dc_balance_event(display, pipe, true);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
intel_pipedmc_dcb_enable(NULL, crtc);
@@ -840,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
return;
intel_pipedmc_dcb_disable(NULL, crtc);
+ intel_dmc_configure_dc_balance_event(display, pipe, false);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance
2025-12-02 7:36 ` [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance Mitul Golani
@ 2025-12-15 7:42 ` Shankar, Uma
2025-12-16 12:36 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 7:42 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 16/17] drm/i915/display: Add function to configure event for
> dc balance
>
> Configure pipe dmc event for dc balance enable/disable.
>
> --v2:
> - Keeping function and removing unnecessary comments. (Jani, Nikula)
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
> 3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index e076ba7e0f28..1182bc9a2e6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -859,6 +859,14 @@ static void dmc_configure_event(struct intel_display
> *display,
> dmc_id, num_handlers, event_id); }
>
> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> + enum pipe pipe, bool enable)
> +{
> + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> +
> + dmc_configure_event(display, dmc_id,
> +PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); }
> +
> /**
> * intel_dmc_block_pkgc() - block PKG C-state
> * @display: display instance
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 9c6a42fc820e..3d8a9a593319 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state
> *crtc_state); void intel_dmc_disable_pipe(const struct intel_crtc_state
> *crtc_state); void intel_dmc_block_pkgc(struct intel_display *display, enum pipe
> pipe,
> bool block);
> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> + enum pipe pipe, bool enable);
> void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display
> *display,
> enum pipe pipe, bool
> enable); void intel_dmc_fini(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 38dc4f87e6fe..ba8b3c664e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -823,6 +823,7 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.slope);
> intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> crtc_state->vrr.dc_balance.vblank_target);
> + intel_dmc_configure_dc_balance_event(display, pipe, true);
> intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> intel_pipedmc_dcb_enable(NULL, crtc);
> @@ -840,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> return;
>
> intel_pipedmc_dcb_disable(NULL, crtc);
> + intel_dmc_configure_dc_balance_event(display, pipe, false);
> intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance
2025-12-02 7:36 ` [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-12-15 7:42 ` Shankar, Uma
@ 2025-12-16 12:36 ` Nautiyal, Ankit K
1 sibling, 0 replies; 32+ messages in thread
From: Nautiyal, Ankit K @ 2025-12-16 12:36 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: intel-xe, ville.syrjala, uma.shankar, jani.nikula
On 12/2/2025 1:06 PM, Mitul Golani wrote:
> Configure pipe dmc event for dc balance enable/disable.
>
> --v2:
> - Keeping function and removing unnecessary comments. (Jani, Nikula)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
> 3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index e076ba7e0f28..1182bc9a2e6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -859,6 +859,14 @@ static void dmc_configure_event(struct intel_display *display,
> dmc_id, num_handlers, event_id);
> }
>
> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> + enum pipe pipe, bool enable)
> +{
> + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> +
> + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable);
> +}
> +
> /**
> * intel_dmc_block_pkgc() - block PKG C-state
> * @display: display instance
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 9c6a42fc820e..3d8a9a593319 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state);
> void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state);
> void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
> bool block);
> +void intel_dmc_configure_dc_balance_event(struct intel_display *display,
> + enum pipe pipe, bool enable);
> void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
> enum pipe pipe, bool enable);
> void intel_dmc_fini(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 38dc4f87e6fe..ba8b3c664e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -823,6 +823,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.slope);
> intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
> crtc_state->vrr.dc_balance.vblank_target);
> + intel_dmc_configure_dc_balance_event(display, pipe, true);
> intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> intel_pipedmc_dcb_enable(NULL, crtc);
> @@ -840,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> return;
>
> intel_pipedmc_dcb_disable(NULL, crtc);
> + intel_dmc_configure_dc_balance_event(display, pipe, false);
> intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
> intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
> intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (15 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 16/17] drm/i915/display: Add function to configure event for dc balance Mitul Golani
@ 2025-12-02 7:36 ` Mitul Golani
2025-12-15 7:47 ` Shankar, Uma
2025-12-16 12:30 ` Nautiyal, Ankit K
2025-12-02 8:40 ` ✗ i915.CI.BAT: failure for Enable/Disable DC balance along with VRR DSB Patchwork
17 siblings, 2 replies; 32+ messages in thread
From: Mitul Golani @ 2025-12-02 7:36 UTC (permalink / raw)
To: intel-gfx
Cc: intel-xe, mitulkumar.ajitkumar.golani, ankit.k.nautiyal,
ville.syrjala, uma.shankar, jani.nikula
Enable DC Balance from vrr compute config and related hw flag.
Also to add pipe restrictions along with this.
--v2:
- Use dc balance check instead of source restriction.
--v3:
- Club pipe restriction check with dc balance enablement. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ba8b3c664e70..db74744ddb31 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.dc_balance.vblank_target =
DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
DCB_BLANK_TARGET, 100);
+ crtc_state->vrr.dc_balance.enable = true;
}
void
@@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
if (!crtc_state->vrr.dc_balance.enable)
return;
@@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
ADAPTIVE_SYNC_COUNTER_EN);
intel_pipedmc_dcb_enable(NULL, crtc);
+
+ vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
}
static void
@@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
if (!old_crtc_state->vrr.dc_balance.enable)
return;
@@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+
+ vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
}
static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
@@ -963,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- if (!HAS_VRR_DC_BALANCE(display))
+ if (!intel_vrr_dc_balance_possible(crtc_state))
return;
reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
--
2.48.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* RE: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
2025-12-02 7:36 ` [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance Mitul Golani
@ 2025-12-15 7:47 ` Shankar, Uma
2025-12-23 10:56 ` Golani, Mitulkumar Ajitkumar
2025-12-16 12:30 ` Nautiyal, Ankit K
1 sibling, 1 reply; 32+ messages in thread
From: Shankar, Uma @ 2025-12-15 7:47 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Tuesday, December 2, 2025 1:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
>
> Enable DC Balance from vrr compute config and related hw flag.
> Also to add pipe restrictions along with this.
>
> --v2:
> - Use dc balance check instead of source restriction.
> --v3:
> - Club pipe restriction check with dc balance enablement. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ba8b3c664e70..db74744ddb31 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct
> intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.vblank_target =
> DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> DCB_BLANK_TARGET, 100);
> + crtc_state->vrr.dc_balance.enable = true;
> }
>
> void
> @@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> +cpu_transcoder));
It would be good to update the state and program everything together at one place,
to avoid this read and update here.
With above fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> if (!crtc_state->vrr.dc_balance.enable)
> return;
> @@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> intel_pipedmc_dcb_enable(NULL, crtc);
> +
> + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +vrr_ctl);
> }
>
> static void
> @@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> +cpu_transcoder));
>
> if (!old_crtc_state->vrr.dc_balance.enable)
> return;
> @@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> intel_de_write(display,
> TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
> +
> + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +vrr_ctl);
> }
>
> static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, @@ -
> 963,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state
> *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> - if (!HAS_VRR_DC_BALANCE(display))
> + if (!intel_vrr_dc_balance_possible(crtc_state))
> return;
>
> reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
> --
> 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
2025-12-15 7:47 ` Shankar, Uma
@ 2025-12-23 10:56 ` Golani, Mitulkumar Ajitkumar
0 siblings, 0 replies; 32+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2025-12-23 10:56 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
ville.syrjala@linux.intel.com, Nikula, Jani
> -----Original Message-----
> From: Shankar, Uma <uma.shankar@intel.com>
> Sent: 15 December 2025 13:17
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: RE: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
>
>
>
> > -----Original Message-----
> > From: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>
> > Sent: Tuesday, December 2, 2025 1:07 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: intel-xe@lists.freedesktop.org; Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> > <ankit.k.nautiyal@intel.com>; ville.syrjala@linux.intel.com; Shankar,
> > Uma <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> > Subject: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
> >
> > Enable DC Balance from vrr compute config and related hw flag.
> > Also to add pipe restrictions along with this.
> >
> > --v2:
> > - Use dc balance check instead of source restriction.
> > --v3:
> > - Club pipe restriction check with dc balance enablement. (Ankit)
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index ba8b3c664e70..db74744ddb31 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct
> > intel_crtc_state *crtc_state)
> > crtc_state->vrr.dc_balance.vblank_target =
> > DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> > DCB_BLANK_TARGET, 100);
> > + crtc_state->vrr.dc_balance.enable = true;
> > }
> >
> > void
> > @@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct
> > intel_crtc_state *crtc_state)
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> > +cpu_transcoder));
>
> It would be good to update the state and program everything together at one
> place, to avoid this read and update here.
Hi Uma,
As currently we are not specifically tracking vrr_enable as part of trans_vrr_ctl and in crtc_state. Possibly can we add this as future action item if it works ?
Regards,
Mitul
>
> With above fixed, this is
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> >
> > if (!crtc_state->vrr.dc_balance.enable)
> > return;
> > @@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct
> > intel_crtc_state *crtc_state)
> > intel_de_write(display,
> > TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> > ADAPTIVE_SYNC_COUNTER_EN);
> > intel_pipedmc_dcb_enable(NULL, crtc);
> > +
> > + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
> > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > +vrr_ctl);
> > }
> >
> > static void
> > @@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct
> > intel_crtc_state *old_crtc_state)
> > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> > +cpu_transcoder));
> >
> > if (!old_crtc_state->vrr.dc_balance.enable)
> > return;
> > @@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct
> > intel_crtc_state *old_crtc_state)
> > intel_de_write(display,
> > TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> > intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> > intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
> 0);
> > +
> > + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
> > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > +vrr_ctl);
> > }
> >
> > static void intel_vrr_tg_enable(const struct intel_crtc_state
> > *crtc_state, @@ -
> > 963,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct
> > intel_crtc_state
> > *crtc_state)
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> >
> > - if (!HAS_VRR_DC_BALANCE(display))
> > + if (!intel_vrr_dc_balance_possible(crtc_state))
> > return;
> >
> > reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
> > --
> > 2.48.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
2025-12-02 7:36 ` [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-12-15 7:47 ` Shankar, Uma
@ 2025-12-16 12:30 ` Nautiyal, Ankit K
2025-12-23 10:57 ` Golani, Mitulkumar Ajitkumar
1 sibling, 1 reply; 32+ messages in thread
From: Nautiyal, Ankit K @ 2025-12-16 12:30 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: intel-xe, ville.syrjala, uma.shankar, jani.nikula
On 12/2/2025 1:06 PM, Mitul Golani wrote:
> Enable DC Balance from vrr compute config and related hw flag.
> Also to add pipe restrictions along with this.
>
> --v2:
> - Use dc balance check instead of source restriction.
> --v3:
> - Club pipe restriction check with dc balance enablement. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ba8b3c664e70..db74744ddb31 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.dc_balance.vblank_target =
> DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> DCB_BLANK_TARGET, 100);
> + crtc_state->vrr.dc_balance.enable = true;
> }
>
> void
> @@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
As Uma pointed out, it would be better to use trans_vrr_ctl() here.
>
> if (!crtc_state->vrr.dc_balance.enable)
> return;
> @@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
> intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> ADAPTIVE_SYNC_COUNTER_EN);
> intel_pipedmc_dcb_enable(NULL, crtc);
> +
> + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
> }
>
> static void
> @@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));
>
> if (!old_crtc_state->vrr.dc_balance.enable)
> return;
> @@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
> intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
> +
> + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
> }
>
> static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
> @@ -963,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> - if (!HAS_VRR_DC_BALANCE(display))
> + if (!intel_vrr_dc_balance_possible(crtc_state))
> return;
This change looks out of place.
Hmm .. In Patch#5, intel_vrr_get_dc_balance_config() is added, but at
that point intel_vrr_dc_balance_possible() is not yet defined.
I think the above update should either:
Move to Patch#7 (where the helper is introduced), or
Introduce the helper in a separate patch placed right after Patch#7 but
before the enablement patch.
PS:
My earlier suggestion in [1] was to introduce the helper sooner to avoid
having it as the last patch.
This was to make sure we have pipe restriction in place before the
enablement logic lands, to avoid any risk enabling DC balancing on
unsupported pipes.
Given the current series structure, moving this change to Patch#7 or
introducing a separate patch right after Patch#7 (before enablement)
seems a better idea.
[1] https://patchwork.freedesktop.org/patch/690789/?series=158156&rev=1
Regards,
Ankit
>
> reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
2025-12-16 12:30 ` Nautiyal, Ankit K
@ 2025-12-23 10:57 ` Golani, Mitulkumar Ajitkumar
0 siblings, 0 replies; 32+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2025-12-23 10:57 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, ville.syrjala@linux.intel.com,
Shankar, Uma, Nikula, Jani
> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: 16 December 2025 18:01
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; ville.syrjala@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance
>
>
> On 12/2/2025 1:06 PM, Mitul Golani wrote:
> > Enable DC Balance from vrr compute config and related hw flag.
> > Also to add pipe restrictions along with this.
> >
> > --v2:
> > - Use dc balance check instead of source restriction.
> > --v3:
> > - Club pipe restriction check with dc balance enablement. (Ankit)
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index ba8b3c664e70..db74744ddb31 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct
> intel_crtc_state *crtc_state)
> > crtc_state->vrr.dc_balance.vblank_target =
> > DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) *
> > DCB_BLANK_TARGET, 100);
> > + crtc_state->vrr.dc_balance.enable = true;
> > }
> >
> > void
> > @@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> > +cpu_transcoder));
>
> As Uma pointed out, it would be better to use trans_vrr_ctl() here.
>
>
> >
> > if (!crtc_state->vrr.dc_balance.enable)
> > return;
> > @@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct
> intel_crtc_state *crtc_state)
> > intel_de_write(display,
> TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
> > ADAPTIVE_SYNC_COUNTER_EN);
> > intel_pipedmc_dcb_enable(NULL, crtc);
> > +
> > + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE;
> > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > +vrr_ctl);
> > }
> >
> > static void
> > @@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display,
> > +cpu_transcoder));
> >
> > if (!old_crtc_state->vrr.dc_balance.enable)
> > return;
> > @@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct
> intel_crtc_state *old_crtc_state)
> > intel_de_write(display,
> TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
> > intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
> > intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
> 0);
> > +
> > + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE;
> > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> > +vrr_ctl);
> > }
> >
> > static void intel_vrr_tg_enable(const struct intel_crtc_state
> > *crtc_state, @@ -963,7 +972,7 @@ void
> intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > enum pipe pipe = crtc->pipe;
> >
> > - if (!HAS_VRR_DC_BALANCE(display))
> > + if (!intel_vrr_dc_balance_possible(crtc_state))
> > return;
> This change looks out of place.
> Hmm .. In Patch#5, intel_vrr_get_dc_balance_config() is added, but at that
> point intel_vrr_dc_balance_possible() is not yet defined.
> I think the above update should either:
>
> Move to Patch#7 (where the helper is introduced), or Introduce the helper in
> a separate patch placed right after Patch#7 but before the enablement patch.
>
> PS:
> My earlier suggestion in [1] was to introduce the helper sooner to avoid
> having it as the last patch.
> This was to make sure we have pipe restriction in place before the
> enablement logic lands, to avoid any risk enabling DC balancing on
> unsupported pipes.
> Given the current series structure, moving this change to Patch#7 or
> introducing a separate patch right after Patch#7 (before enablement) seems a
> better idea.
>
> [1] https://patchwork.freedesktop.org/patch/690789/?series=158156&rev=1
Sure Ankit,
I will a separate patch after patch 7. Thanks for the reviews..
Regards,
Mitul
>
>
> Regards,
> Ankit
> >
> > reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✗ i915.CI.BAT: failure for Enable/Disable DC balance along with VRR DSB
2025-12-02 7:36 [PATCH v10 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
` (16 preceding siblings ...)
2025-12-02 7:36 ` [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance Mitul Golani
@ 2025-12-02 8:40 ` Patchwork
17 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2025-12-02 8:40 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8041 bytes --]
== Series Details ==
Series: Enable/Disable DC balance along with VRR DSB
URL : https://patchwork.freedesktop.org/series/158360/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_17617 -> Patchwork_158360v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_158360v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_158360v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/index.html
Participating hosts (42 -> 43)
------------------------------
Additional (2): fi-kbl-guc bat-adls-6
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_158360v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@dmabuf:
- bat-mtlp-8: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-mtlp-8/igt@i915_selftest@live@dmabuf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-mtlp-8/igt@i915_selftest@live@dmabuf.html
Known issues
------------
Here are the changes found in Patchwork_158360v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][3] ([i915#1849])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/fi-kbl-guc/igt@fbdev@info.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-guc: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/fi-kbl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- bat-adls-6: NOTRUN -> [SKIP][6] ([i915#3282])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@gem_tiled_pread_basic.html
* igt@intel_hwmon@hwmon-read:
- bat-adls-6: NOTRUN -> [SKIP][7] ([i915#7707]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@intel_hwmon@hwmon-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adls-6: NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-kbl-guc: NOTRUN -> [SKIP][9] ([i915#11190]) +16 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/fi-kbl-guc/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adls-6: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#3840])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adls-6: NOTRUN -> [SKIP][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adls-6: NOTRUN -> [SKIP][12] ([i915#5354])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-adls-6: NOTRUN -> [SKIP][13] ([i915#1072] / [i915#9732]) +3 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adls-6: NOTRUN -> [SKIP][14] ([i915#3555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-guc: NOTRUN -> [SKIP][15] +18 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/fi-kbl-guc/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- bat-adls-6: NOTRUN -> [SKIP][16] ([i915#3291]) +2 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-adls-6/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [DMESG-FAIL][17] ([i915#12061]) -> [PASS][18] +1 other test pass
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-dg2-11: [DMESG-FAIL][19] ([i915#12061]) -> [PASS][20] +1 other test pass
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-dg2-11/igt@i915_selftest@live@workarounds.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-dg2-11/igt@i915_selftest@live@workarounds.html
- bat-dg2-14: [DMESG-FAIL][21] ([i915#12061]) -> [PASS][22] +1 other test pass
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html
- bat-mtlp-8: [DMESG-FAIL][23] ([i915#12061]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live:
- bat-mtlp-8: [DMESG-FAIL][25] ([i915#12061]) -> [INCOMPLETE][26] ([i915#15176])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17617/bat-mtlp-8/igt@i915_selftest@live.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/bat-mtlp-8/igt@i915_selftest@live.html
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#15176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15176
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
Build changes
-------------
* Linux: CI_DRM_17617 -> Patchwork_158360v1
CI-20190529: 20190529
CI_DRM_17617: 639f325d8cbdc690de963db2fe5840444ac7ea65 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8647: 8647
Patchwork_158360v1: 639f325d8cbdc690de963db2fe5840444ac7ea65 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158360v1/index.html
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