* [PATCH v4 1/3] drm/fourcc: Add 64 bpp half float formats
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
@ 2019-02-06 18:02 ` Kevin Strasser
2019-02-08 14:16 ` [Intel-gfx] " Maarten Lankhorst
2019-02-06 18:02 ` [PATCH v4 2/3] drm/i915: Refactor icl_is_hdr_plane Kevin Strasser
` (5 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Kevin Strasser @ 2019-02-06 18:02 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter, Tina Zhang, Uma Shankar
Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
formatted in IEEE-754 half-precision float (binary16) 1:5:10
MSb-sign:exponent:fraction form.
This patch attempts to address the feedback provided when 2 of these
formats were previosly proposed:
https://patchwork.kernel.org/patch/10072545/
v2:
- Fixed cpp (Ville)
- Added detail pixel formatting (Ville)
- Ordered formats in header (Ville)
Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 4 ++++
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..c866452 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 93a341d..d323c73 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -144,6 +144,17 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
+/*
+ * Floating point 64bpp RGB
+ * IEEE 754-2008 binary16 half-precision float
+ * [15:0] sign:exponent:mantissa 1:5:10
+ */
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH v4 1/3] drm/fourcc: Add 64 bpp half float formats
2019-02-06 18:02 ` [PATCH v4 1/3] drm/fourcc: Add " Kevin Strasser
@ 2019-02-08 14:16 ` Maarten Lankhorst
2019-02-08 18:30 ` Strasser, Kevin
0 siblings, 1 reply; 12+ messages in thread
From: Maarten Lankhorst @ 2019-02-08 14:16 UTC (permalink / raw)
To: Kevin Strasser, intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter
Op 06-02-2019 om 19:02 schreef Kevin Strasser:
> Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is
> formatted in IEEE-754 half-precision float (binary16) 1:5:10
> MSb-sign:exponent:fraction form.
>
> This patch attempts to address the feedback provided when 2 of these
> formats were previosly proposed:
> https://patchwork.kernel.org/patch/10072545/
>
> v2:
> - Fixed cpp (Ville)
> - Added detail pixel formatting (Ville)
> - Ordered formats in header (Ville)
>
> Cc: Tina Zhang <tina.zhang@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 4 ++++
> include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03..c866452 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> { .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
Hmmm, from include/drm/drm_fourcc.h
* @depth:
*
* Color depth (number of bits per pixel excluding padding bits),
* valid for a subset of RGB formats only. This is a legacy field, do
* not use in new code and set to 0 for new formats.
*/
u8 depth;
Otherwise looks good. :)
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 93a341d..d323c73 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -144,6 +144,17 @@ extern "C" {
> #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
> #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
>
> +/*
> + * Floating point 64bpp RGB
> + * IEEE 754-2008 binary16 half-precision float
> + * [15:0] sign:exponent:mantissa 1:5:10
> + */
> +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
> +
> +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
> +
> /* packed YCbCr */
> #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
> #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [Intel-gfx] [PATCH v4 1/3] drm/fourcc: Add 64 bpp half float formats
2019-02-08 14:16 ` [Intel-gfx] " Maarten Lankhorst
@ 2019-02-08 18:30 ` Strasser, Kevin
0 siblings, 0 replies; 12+ messages in thread
From: Strasser, Kevin @ 2019-02-08 18:30 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: David Airlie, Daniel Vetter
Maarten Lankhorst wrote:
> Hmmm, from include/drm/drm_fourcc.h
> * @depth:
> *
> * Color depth (number of bits per pixel excluding padding bits),
> * valid for a subset of RGB formats only. This is a legacy field, do
> * not use in new code and set to 0 for new formats.
> */
> u8 depth;
>
> Otherwise looks good. :)
Ah, I missed that detail. I will respin with this fixed.
Thanks,
Kevin
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 2/3] drm/i915: Refactor icl_is_hdr_plane
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
2019-02-06 18:02 ` [PATCH v4 1/3] drm/fourcc: Add " Kevin Strasser
@ 2019-02-06 18:02 ` Kevin Strasser
2019-02-06 18:02 ` [PATCH v4 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Kevin Strasser @ 2019-02-06 18:02 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter, Uma Shankar
Change the api in order to enable callers that can't supply a valid
intel_plane pointer, as would be the case prior to calling
drm_universal_plane_init.
v4:
- Rename variables and move a declaration (Ville)
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 5 +++--
drivers/gpu/drm/i915/intel_drv.h | 7 ++++---
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
4 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 16263ad..d845950 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -232,10 +232,11 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->base.fb &&
plane_state->base.fb->format->is_yuv &&
plane_state->base.fb->format->num_planes > 1) {
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
- } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
+ } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
/*
* On gen11+'s HDR planes we only use the scaler for
* scaling. They have a dedicated chroma upsampler, so
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d5ec92..2d9639d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3726,7 +3726,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
- if (fb->format->is_yuv && !icl_is_hdr_plane(plane)) {
+ if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
else
@@ -5052,13 +5052,14 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
{
struct intel_plane *intel_plane =
to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
bool force_detach = !fb || !plane_state->base.visible;
bool need_scaler = false;
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
- if (!icl_is_hdr_plane(intel_plane) &&
+ if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
fb && fb->format->format == DRM_FORMAT_NV12)
need_scaler = true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 90ba543..e7fb278 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2313,12 +2313,13 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
return false;
}
-static inline bool icl_is_hdr_plane(struct intel_plane *plane)
+static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
+ enum plane_id plane_id)
{
- if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
+ if (INTEL_GEN(dev_priv) < 11)
return false;
- return plane->id < PLANE_SPRITE2;
+ return plane_id < PLANE_SPRITE2;
}
/* intel_tv.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index cd42e81..10b37e8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -336,7 +336,7 @@ skl_program_scaler(struct intel_plane *plane,
/* TODO: handle sub-pixel coordinates */
if (plane_state->base.fb->format->format == DRM_FORMAT_NV12 &&
- !icl_is_hdr_plane(plane)) {
+ !icl_is_hdr_plane(dev_priv, plane->id)) {
y_hphase = skl_scaler_calc_phase(1, hscale, false);
y_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -511,7 +511,7 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
(plane_state->color_plane[1].offset - surf_addr) | aux_stride);
- if (icl_is_hdr_plane(plane)) {
+ if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
if (linked) {
@@ -536,7 +536,7 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
plane_state->color_ctl);
- if (fb->format->is_yuv && icl_is_hdr_plane(plane))
+ if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
skl_write_plane_wm(plane, crtc_state);
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 3/3] drm/i915/icl: Implement half float formats
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
2019-02-06 18:02 ` [PATCH v4 1/3] drm/fourcc: Add " Kevin Strasser
2019-02-06 18:02 ` [PATCH v4 2/3] drm/i915: Refactor icl_is_hdr_plane Kevin Strasser
@ 2019-02-06 18:02 ` Kevin Strasser
2019-02-08 14:48 ` Maarten Lankhorst
2019-02-06 18:23 ` ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev5) Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Kevin Strasser @ 2019-02-06 18:02 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter
64 bpp half float formats are supported on hdr planes only and are subject
to the following restrictions:
* 90/270 rotation not supported
* Yf Tiling not supported
* Frame Buffer Compression not supported
* Color Keying not supported
v2:
- Drop handling pixel normalize register
- Don't use icl_is_hdr_plane too early
v3:
- Use refactored icl_is_hdr_plane (Ville)
- Use u32 instead of uint32_t (Ville)
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 67 ++++++++++++++++++++++++++++++++----
2 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2d9639d..1124502 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2668,6 +2668,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR16161616F;
+ else
+ return DRM_FORMAT_XBGR16161616F;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB16161616F;
+ else
+ return DRM_FORMAT_XRGB16161616F;
+ }
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3566,6 +3578,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ return PLANE_CTL_FORMAT_XRGB_16161616F;
default:
MISSING_CASE(pixel_format);
}
@@ -5097,6 +5115,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 10b37e8..55ee677 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1450,8 +1450,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
/*
* 90/270 is not allowed with RGB64 16:16:16:16 and
* Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
- * TBD: Add RGB64 case once its added in supported format
- * list.
*/
switch (fb->format->format) {
case DRM_FORMAT_RGB565:
@@ -1459,6 +1457,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
break;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
drm_get_format_name(fb->format->format,
&format_name));
@@ -1774,6 +1776,45 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const u32 icl_hdr_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
+static const u32 icl_hdr_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
+ DRM_FORMAT_ARGB16161616F,
+ DRM_FORMAT_ABGR16161616F,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1917,6 +1958,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
return true;
/* fall through */
case DRM_FORMAT_C8:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED)
@@ -2053,11 +2098,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
- formats = skl_planar_formats;
- num_formats = ARRAY_SIZE(skl_planar_formats);
+ if (icl_is_hdr_plane(dev_priv, plane_id)) {
+ formats = icl_hdr_planar_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+ } else {
+ formats = skl_planar_formats;
+ num_formats = ARRAY_SIZE(skl_planar_formats);
+ }
} else {
- formats = skl_plane_formats;
- num_formats = ARRAY_SIZE(skl_plane_formats);
+ if (icl_is_hdr_plane(dev_priv, plane_id)) {
+ formats = icl_hdr_plane_formats;
+ num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+ } else {
+ formats = skl_plane_formats;
+ num_formats = ARRAY_SIZE(skl_plane_formats);
+ }
}
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 3/3] drm/i915/icl: Implement half float formats
2019-02-06 18:02 ` [PATCH v4 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
@ 2019-02-08 14:48 ` Maarten Lankhorst
0 siblings, 0 replies; 12+ messages in thread
From: Maarten Lankhorst @ 2019-02-08 14:48 UTC (permalink / raw)
To: Kevin Strasser, intel-gfx, dri-devel; +Cc: David Airlie, Daniel Vetter
Op 06-02-2019 om 19:02 schreef Kevin Strasser:
> 64 bpp half float formats are supported on hdr planes only and are subject
> to the following restrictions:
> * 90/270 rotation not supported
> * Yf Tiling not supported
> * Frame Buffer Compression not supported
> * Color Keying not supported
>
> v2:
> - Drop handling pixel normalize register
> - Don't use icl_is_hdr_plane too early
>
> v3:
> - Use refactored icl_is_hdr_plane (Ville)
> - Use u32 instead of uint32_t (Ville)
>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Shashank Sharma <shashank.sharma@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
For the whole series, with the depth change to patch 1:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev5)
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
` (2 preceding siblings ...)
2019-02-06 18:02 ` [PATCH v4 3/3] drm/i915/icl: Implement half float formats Kevin Strasser
@ 2019-02-06 18:23 ` Patchwork
2019-02-06 18:41 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-02-06 18:23 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev5)
URL : https://patchwork.freedesktop.org/series/53212/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6ee4ac0d854 drm/fourcc: Add 64 bpp half float formats
-:40: WARNING:LONG_LINE: line over 100 characters
#40: FILE: drivers/gpu/drm/drm_fourcc.c:201:
+ { .format = DRM_FORMAT_XRGB16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:41: WARNING:LONG_LINE: line over 100 characters
#41: FILE: drivers/gpu/drm/drm_fourcc.c:202:
+ { .format = DRM_FORMAT_XBGR16161616F, .depth = 48, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
-:42: WARNING:LONG_LINE: line over 100 characters
#42: FILE: drivers/gpu/drm/drm_fourcc.c:203:
+ { .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/drm_fourcc.c:204:
+ { .format = DRM_FORMAT_ABGR16161616F, .depth = 64, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
-:60: WARNING:LONG_LINE_COMMENT: line over 100 characters
#60: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
-:61: WARNING:LONG_LINE_COMMENT: line over 100 characters
#61: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
-:63: WARNING:LONG_LINE_COMMENT: line over 100 characters
#63: FILE: include/uapi/drm/drm_fourcc.h:155:
+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
-:64: WARNING:LONG_LINE_COMMENT: line over 100 characters
#64: FILE: include/uapi/drm/drm_fourcc.h:156:
+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
total: 0 errors, 8 warnings, 0 checks, 27 lines checked
31ca604aaa2c drm/i915: Refactor icl_is_hdr_plane
336123ac186a drm/i915/icl: Implement half float formats
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for Support 64 bpp half float formats (rev5)
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
` (3 preceding siblings ...)
2019-02-06 18:23 ` ✗ Fi.CI.CHECKPATCH: warning for Support 64 bpp half float formats (rev5) Patchwork
@ 2019-02-06 18:41 ` Patchwork
2019-02-06 20:06 ` ✓ Fi.CI.IGT: " Patchwork
2019-02-08 14:49 ` [Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats Maarten Lankhorst
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-02-06 18:41 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev5)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5552 -> Patchwork_12158
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53212/revisions/5/mbox/
Known issues
------------
Here are the changes found in Patchwork_12158 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109567]: https://bugs.freedesktop.org/show_bug.cgi?id=109567
Participating hosts (48 -> 45)
------------------------------
Additional (2): fi-ilk-650 fi-snb-2520m
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_5552 -> Patchwork_12158
CI_DRM_5552: b7cd857f32e0b1d5ea61e5eeebc0334bafb34eaa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4812: 592b854fead32c2b0dac7198edfb9a6bffd66932 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12158: 336123ac186ad0cd27db764b912b7c54aff0767e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
336123ac186a drm/i915/icl: Implement half float formats
31ca604aaa2c drm/i915: Refactor icl_is_hdr_plane
e6ee4ac0d854 drm/fourcc: Add 64 bpp half float formats
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12158/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for Support 64 bpp half float formats (rev5)
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
` (4 preceding siblings ...)
2019-02-06 18:41 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-02-06 20:06 ` Patchwork
2019-02-08 14:49 ` [Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats Maarten Lankhorst
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-02-06 20:06 UTC (permalink / raw)
To: Kevin Strasser; +Cc: intel-gfx
== Series Details ==
Series: Support 64 bpp half float formats (rev5)
URL : https://patchwork.freedesktop.org/series/53212/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5552_full -> Patchwork_12158_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12158_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: PASS -> FAIL [fdo#109350]
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_setmode@basic:
- shard-glk: NOTRUN -> FAIL [fdo#99912]
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- shard-apl: PASS -> FAIL [fdo#103166]
#### Possible fixes ####
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@plain-flip-fb-recreate:
- shard-kbl: DMESG-WARN [fdo#103558] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@system-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] / [fdo#107807] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-snb: INCOMPLETE [fdo#105411] / [fdo#106886] -> DMESG-WARN [fdo#109244]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5552 -> Patchwork_12158
CI_DRM_5552: b7cd857f32e0b1d5ea61e5eeebc0334bafb34eaa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4812: 592b854fead32c2b0dac7198edfb9a6bffd66932 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12158: 336123ac186ad0cd27db764b912b7c54aff0767e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12158/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats
2019-02-06 18:02 [PATCH v4 0/3] Support 64 bpp half float formats Kevin Strasser
` (5 preceding siblings ...)
2019-02-06 20:06 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-02-08 14:49 ` Maarten Lankhorst
2019-02-08 18:53 ` Strasser, Kevin
6 siblings, 1 reply; 12+ messages in thread
From: Maarten Lankhorst @ 2019-02-08 14:49 UTC (permalink / raw)
To: Kevin Strasser, intel-gfx, dri-devel; +Cc: Daniel Vetter
Op 06-02-2019 om 19:02 schreef Kevin Strasser:
> This series defines new formats and adds implementation to the i915 driver.
> Since posting v1 I have removed the pixel normalize property, as it's not needed
> for basic functionality. Also, I have been working on adding support to
> userspace, but we can't land any patches until drm_fourcc.h has been updated
> here.
>
> I have submitted a series to Mesa to make use of the RGBA ordered formats:
> https://patchwork.freedesktop.org/series/54759/
>
> My igt branch is reworked to drop usage of pixel normalize and includes use
> of f16c intrinsics to speed up conversion:
> https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commits/fp16
>
> I also have a libdrm branch with fp16 coverage added to modetest:
> https://gitlab.freedesktop.org/strassek/drm/commits/fp16
>
> To serve as a smoke test of the whole stack I have a modified version of
> kmscube:
> https://gitlab.freedesktop.org/strassek/kmscube/commits/fp16
>
> Kevin Strasser (3):
> drm/fourcc: Add 64 bpp half float formats
> drm/i915: Refactor icl_is_hdr_plane
> drm/i915/icl: Implement half float formats
>
> drivers/gpu/drm/drm_fourcc.c | 4 ++
> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
> drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++-
> drivers/gpu/drm/i915/intel_drv.h | 7 ++--
> drivers/gpu/drm/i915/intel_sprite.c | 73 +++++++++++++++++++++++++++++++-----
> include/uapi/drm/drm_fourcc.h | 11 ++++++
> 6 files changed, 110 insertions(+), 15 deletions(-)
>
It's nice that the igt parts are almost done. I think this might need rebasing on top of
I'm glad there are tests, but the internal accuracy of the CAIRO_FORMAT_RGB24 is only 8 bits, so it wouldn't test this properly.
Fortunately we will start using CAIRO_FORMAT_RGB96F and RGBA128F soon. :)
See https://patchwork.freedesktop.org/patch/284507/
We should be able to convert native float to half float with an intrinsic.
~Maarten
_______________________________________________
dri-devel mailing list
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats
2019-02-08 14:49 ` [Intel-gfx] [PATCH v4 0/3] Support 64 bpp half float formats Maarten Lankhorst
@ 2019-02-08 18:53 ` Strasser, Kevin
0 siblings, 0 replies; 12+ messages in thread
From: Strasser, Kevin @ 2019-02-08 18:53 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Daniel Vetter
Maarten Lankhorst wrote:
> It's nice that the igt parts are almost done. I think this might need rebasing
> on top of
>
> I'm glad there are tests, but the internal accuracy of the CAIRO_FORMAT_RGB24
> is only 8 bits, so it wouldn't test this properly.
>
> Fortunately we will start using CAIRO_FORMAT_RGB96F and RGBA128F soon. :)
>
> See https://patchwork.freedesktop.org/patch/284507/
>
> We should be able to convert native float to half float with an intrinsic.
Thanks for the pointer, native fp32 formats should make for fewer conversions
too.
I just updated my gitlab branch with a more recent rebase. I already have
non-simd f16c instrinsics working, you can take a look at [1]. I experimented
with the simd intrinsics too, but they were a bit slower, I would expect better
results with pixel data that is already stored in fp32.
Thanks,
Kevin
[1] https://gitlab.freedesktop.org/strassek/igt-gpu-tools/commit/910551867376b8ead3ab738056247486d422fff9
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