Re: [Intel-gfx] [PATCH 2/7] drm/i915: Implement Wa_1508744258

["Souza, Jose" <jose.souza@intel.com>]

On Thu, 2021-08-12 at 09:29 +0300, Timo Aaltonen wrote:
> On 12.8.2021 6.27, Timo Aaltonen wrote:
> > On 9.7.2021 0.18, José Roberto de Souza wrote:
> > > Same bit was required for Wa_14012131227 in DG1 now it is also
> > > required as Wa_1508744258 to TGL, RKL, DG1, ADL-S and ADL-P.
> > > 
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
> > >   1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index e5e3f820074a9..c346229e2be00 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -670,6 +670,13 @@ static void gen12_ctx_workarounds_init(struct 
> > > intel_engine_cs *engine,
> > >              FF_MODE2_GS_TIMER_MASK,
> > >              FF_MODE2_GS_TIMER_224,
> > >              0);
> > > +
> > > +    /*
> > > +     * Wa_14012131227:dg1
> > > +     * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p
> > > +     */
> > > +    wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
> > > +             GEN9_RHWO_OPTIMIZATION_DISABLE);
> > >   }
> > >   static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > 
> > 
> > Hi, I don't see this (or patches 3, 4) in drm-intel-next, are they not 
> > needed anymore?
> 
> but is in drm-intel-gt-next..

Yep, display code can go to drm-intel-next and gt code goes to drm-intel-gt-next

> 
>