From: Clinton Taylor <Clinton.A.Taylor@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/i915: Add Wa_1409120013:icl,ehl
Date: Wed, 12 Jun 2019 11:40:53 -0700 [thread overview]
Message-ID: <957c710d-78bb-0e03-4937-e467f3803854@intel.com> (raw)
In-Reply-To: <20190612183631.30540-1-matthew.d.roper@intel.com>
Looks good now.
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
-Clint
On 6/12/19 11:36 AM, Matt Roper wrote:
> This chicken bit should be set before enabling FBC to avoid screen
> corruption when the plane size has odd vertical and horizontal
> dimensions. It is safe to leave the bit set even when FBC is disabled.
>
> v2:
> - The bspec's name for this bit on these platforms ("Spare 14") is
> pretty meaningless. Let's rename the bit definition to something
> that more accurately reflects what the bit really does. (Clint)
>
> v3:
> - The chicken register was already defined (along with a few other
> gen9-specific bits) farther down. Just add the new bit definition
> there. (Clint)
>
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_fbc.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index edf9f93934a1..368ee717580c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3163,6 +3163,7 @@ enum i915_power_well_id {
> #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
> +#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 5679f2fffb7c..d36cada2cc7d 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -344,6 +344,10 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> HSW_FBCQ_DIS);
> }
>
> + if (IS_GEN(dev_priv, 11))
> + /* Wa_1409120013:icl,ehl */
> + I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> +
> I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>
> intel_fbc_recompress(dev_priv);
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next prev parent reply other threads:[~2019-06-12 19:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 22:27 [PATCH] drm/i915: Add Wa_1409120013:icl,ehl Matt Roper
2019-06-10 23:19 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-06-12 6:52 ` ✓ Fi.CI.IGT: " Patchwork
2019-06-12 17:03 ` [PATCH] " Clinton Taylor
2019-06-12 18:16 ` [PATCH v2] " Matt Roper
2019-06-12 18:27 ` Matt Roper
2019-06-12 18:36 ` [PATCH v3] " Matt Roper
2019-06-12 18:40 ` Clinton Taylor [this message]
2019-06-14 14:27 ` Matt Roper
2019-06-12 19:28 ` ✓ Fi.CI.BAT: success for drm/i915: Add Wa_1409120013:icl,ehl (rev3) Patchwork
2019-06-14 13:31 ` ✓ Fi.CI.IGT: " Patchwork
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