Re: [PATCH] drm/i915: Add Wa_1409120013:icl,ehl

[Clinton Taylor <Clinton.A.Taylor@intel.com>]

On 6/10/19 3:27 PM, Matt Roper wrote:
> This chicken bit should be set before enabling FBC to avoid screen
> corruption when the plane size has odd vertical and horizontal
> dimensions.  It is safe to leave the bit set even when FBC is disabled.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>   drivers/gpu/drm/i915/intel_fbc.c | 4 ++++
>   2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7a26766ba84d..2af04568449e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3150,6 +3150,8 @@ enum i915_power_well_id {
>   
>   /* Framebuffer compression for Ironlake */
>   #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
> +#define ILK_DPFC_CHICKEN	_MMIO(0x43224)
Duplicate define, 0x43224 is already defined ~12 lines lower.
> +#define   ILK_DPFC_CHICKEN_SPARE14	REG_BIT(14)

Any way we can incorporate COMP_DUMMY_PIXEL into this bit definition?

-Clint


>   #define ILK_DPFC_CONTROL	_MMIO(0x43208)
>   #define   FBC_CTL_FALSE_COLOR	(1 << 10)
>   /* The bit 28-8 is reserved */
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 5679f2fffb7c..875ad83c3d32 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -344,6 +344,10 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>   			   HSW_FBCQ_DIS);
>   	}
>   
> +	if (IS_GEN(dev_priv, 11))
> +		/* Wa_1409120013:icl,ehl */
> +		I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_SPARE14);
> +
>   	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>   
>   	intel_fbc_recompress(dev_priv);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx