* [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-08 21:34 ` Ville Syrjälä
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 02/14] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap Ankit Nautiyal
` (14 subsequent siblings)
15 siblings, 1 reply; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new member to crtc_state to represent the final
output_format to the sink. In case of a DFP this can be different than
the output_format, as per the format conversion done via the PCON.
This will help to store only the format conversion capabilities of the
DP device in intel_dp->dfp, and use crtc_state to compute and store the
configuration for color/format conversion for a given mode.
v2: modified the new member to crtc_state to represent the final
output_format that eaches the sink, after possible conversion by
PCON kind of devices. (Ville)
v3: Addressed comments from Ville:
-Added comments to clarify difference between sink_format and
output_format.
-Corrected the order of setting sink_format and output_format.
-Added readout for sink_format in get_pipe_config hooks.
v4: Set sink_format for intel_sdvo too. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3)
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
.../drm/i915/display/intel_crtc_state_dump.c | 5 +--
drivers/gpu/drm/i915/display/intel_display.c | 5 +++
.../drm/i915/display/intel_display_types.h | 11 +++++-
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 24 +++++++------
drivers/gpu/drm/i915/display/intel_lvds.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/display/intel_tv.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
13 files changed, 62 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d16b30a2dded..0ca0d23f42c6 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1667,6 +1667,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
&pipe_config->hw.adjusted_mode;
int ret;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
ret = intel_panel_compute_config(intel_connector, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 797ad9489f7e..eb5964b3ff95 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -393,6 +393,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index e3273fe8ddac..9b61884851fc 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
drm_dbg_kms(&i915->drm,
- "active: %s, output_types: %s (0x%x), output format: %s\n",
+ "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
str_yes_no(pipe_config->hw.active),
buf, pipe_config->output_types,
- output_formats(pipe_config->output_format));
+ output_formats(pipe_config->output_format),
+ output_formats(pipe_config->sink_format));
drm_dbg_kms(&i915->drm,
"cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 32b257157186..789667e1b2cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3242,6 +3242,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
return false;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ pipe_config->sink_format = pipe_config->output_format;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
@@ -3701,6 +3702,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
break;
}
+ pipe_config->sink_format = pipe_config->output_format;
+
pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
@@ -4099,6 +4102,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
bdw_get_pipemisc_output_format(crtc);
}
+ pipe_config->sink_format = pipe_config->output_format;
+
pipe_config->gamma_mode = intel_de_read(dev_priv,
GAMMA_MODE(crtc->pipe));
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff3ef37d099e..136866615223 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1267,9 +1267,18 @@ struct intel_crtc_state {
/* HDMI High TMDS char rate ratio */
bool hdmi_high_tmds_clock_ratio;
- /* Output format RGB/YCBCR etc */
+ /*
+ * Output format RGB/YCBCR etc., that is coming out
+ * at the end of the pipe.
+ */
enum intel_output_format output_format;
+ /*
+ * Sink output format RGB/YCBCR etc., that is going
+ * into the sink.
+ */
+ enum intel_output_format sink_format;
+
/* enable pipe gamma? */
bool gamma_enable;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1607c86af025..3ec8a248a928 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -788,11 +788,12 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
- bool ycbcr_420_output)
+ enum intel_output_format sink_format)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
- if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
+ if (!connector->base.ycbcr_420_allowed ||
+ sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return INTEL_OUTPUT_FORMAT_RGB;
if (intel_dp->dfp.rgb_to_ycbcr &&
@@ -831,8 +832,14 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
const struct drm_display_mode *mode)
{
const struct drm_display_info *info = &connector->base.display_info;
- enum intel_output_format output_format =
- intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
+ enum intel_output_format output_format, sink_format;
+
+ if (drm_mode_is_420_only(info, mode))
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
+ output_format = intel_dp_output_format(connector, sink_format);
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}
@@ -1985,23 +1992,28 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
- crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
-
- if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
+ if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
drm_dbg_kms(&i915->drm,
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
- crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
+ } else if (ycbcr_420_only) {
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ } else {
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
}
+ crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
+
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
if (ret) {
- if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
- !connector->base.ycbcr_420_allowed ||
+ if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
- crtc_state->output_format = intel_dp_output_format(connector, true);
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ crtc_state->output_format = intel_dp_output_format(connector,
+ crtc_state->sink_format);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4077a979a924..e53e7ece624c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -148,6 +148,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->has_pch_encoder = false;
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 4aeae0f3ac91..68ba70751527 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -271,6 +271,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e82f8a07e2b0..0dd60bb9d7e8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2190,13 +2190,13 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
static enum intel_output_format
intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
- struct intel_connector *connector,
- bool ycbcr_420_output)
+ struct intel_connector *connector)
{
if (!crtc_state->has_hdmi_sink)
return INTEL_OUTPUT_FORMAT_RGB;
- if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
+ if (connector->base.ycbcr_420_allowed &&
+ crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return INTEL_OUTPUT_FORMAT_YCBCR420;
else
return INTEL_OUTPUT_FORMAT_RGB;
@@ -2214,23 +2214,25 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
int ret;
- crtc_state->output_format =
- intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
-
- if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
+ if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
drm_dbg_kms(&i915->drm,
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
- crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
+ } else if (ycbcr_420_only) {
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ } else {
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
}
+ crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
if (ret) {
- if (intel_hdmi_is_ycbcr420(crtc_state) ||
- !connector->base.ycbcr_420_allowed ||
+ if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
- crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
+ crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
}
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 7bf1bdfd03ec..ee526fef2276 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -440,6 +440,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
pipe_config->pipe_bpp = lvds_bpp;
}
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 329b9d9af667..f6b09412da5a 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1327,6 +1327,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index b986bf075889..2a205a21d0c2 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1206,6 +1206,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 84481030883a..1958774860dc 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -280,6 +280,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
int ret;
drm_dbg_kms(&dev_priv->drm, "\n");
+ pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
ret = intel_panel_compute_config(intel_connector, adjusted_mode);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion
2022-12-02 10:10 ` [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
@ 2022-12-08 21:34 ` Ville Syrjälä
2022-12-10 13:00 ` Nautiyal, Ankit K
0 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjälä @ 2022-12-08 21:34 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
On Fri, Dec 02, 2022 at 03:40:15PM +0530, Ankit Nautiyal wrote:
> The decision to use DFP output format conversion capabilities should be
> during compute_config phase.
>
> This patch adds new member to crtc_state to represent the final
> output_format to the sink. In case of a DFP this can be different than
> the output_format, as per the format conversion done via the PCON.
>
> This will help to store only the format conversion capabilities of the
> DP device in intel_dp->dfp, and use crtc_state to compute and store the
> configuration for color/format conversion for a given mode.
>
> v2: modified the new member to crtc_state to represent the final
> output_format that eaches the sink, after possible conversion by
> PCON kind of devices. (Ville)
>
> v3: Addressed comments from Ville:
> -Added comments to clarify difference between sink_format and
> output_format.
> -Corrected the order of setting sink_format and output_format.
> -Added readout for sink_format in get_pipe_config hooks.
>
> v4: Set sink_format for intel_sdvo too. (Ville)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3)
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> .../drm/i915/display/intel_crtc_state_dump.c | 5 +--
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> .../drm/i915/display/intel_display_types.h | 11 +++++-
> drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
> drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 24 +++++++------
> drivers/gpu/drm/i915/display/intel_lvds.c | 1 +
> drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
> drivers/gpu/drm/i915/display/intel_tv.c | 1 +
> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
> 13 files changed, 62 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index d16b30a2dded..0ca0d23f42c6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1667,6 +1667,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> &pipe_config->hw.adjusted_mode;
> int ret;
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 797ad9489f7e..eb5964b3ff95 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -393,6 +393,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index e3273fe8ddac..9b61884851fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>
> snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> drm_dbg_kms(&i915->drm,
> - "active: %s, output_types: %s (0x%x), output format: %s\n",
> + "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
> str_yes_no(pipe_config->hw.active),
> buf, pipe_config->output_types,
> - output_formats(pipe_config->output_format));
> + output_formats(pipe_config->output_format),
> + output_formats(pipe_config->sink_format));
>
> drm_dbg_kms(&i915->drm,
> "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 32b257157186..789667e1b2cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3242,6 +3242,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> return false;
>
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> + pipe_config->sink_format = pipe_config->output_format;
> pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> pipe_config->shared_dpll = NULL;
>
> @@ -3701,6 +3702,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> break;
> }
>
> + pipe_config->sink_format = pipe_config->output_format;
> +
> pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
>
> pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
> @@ -4099,6 +4102,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> bdw_get_pipemisc_output_format(crtc);
> }
>
> + pipe_config->sink_format = pipe_config->output_format;
> +
> pipe_config->gamma_mode = intel_de_read(dev_priv,
> GAMMA_MODE(crtc->pipe));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ff3ef37d099e..136866615223 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1267,9 +1267,18 @@ struct intel_crtc_state {
> /* HDMI High TMDS char rate ratio */
> bool hdmi_high_tmds_clock_ratio;
>
> - /* Output format RGB/YCBCR etc */
> + /*
> + * Output format RGB/YCBCR etc., that is coming out
> + * at the end of the pipe.
> + */
> enum intel_output_format output_format;
>
> + /*
> + * Sink output format RGB/YCBCR etc., that is going
> + * into the sink.
> + */
> + enum intel_output_format sink_format;
> +
> /* enable pipe gamma? */
> bool gamma_enable;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1607c86af025..3ec8a248a928 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -788,11 +788,12 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>
> static enum intel_output_format
> intel_dp_output_format(struct intel_connector *connector,
> - bool ycbcr_420_output)
> + enum intel_output_format sink_format)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
>
> - if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
> + if (!connector->base.ycbcr_420_allowed ||
> + sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
> return INTEL_OUTPUT_FORMAT_RGB;
>
> if (intel_dp->dfp.rgb_to_ycbcr &&
> @@ -831,8 +832,14 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
> const struct drm_display_mode *mode)
> {
> const struct drm_display_info *info = &connector->base.display_info;
> - enum intel_output_format output_format =
> - intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
> + enum intel_output_format output_format, sink_format;
> +
> + if (drm_mode_is_420_only(info, mode))
> + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + else
> + sink_format = INTEL_OUTPUT_FORMAT_RGB;
> +
> + output_format = intel_dp_output_format(connector, sink_format);
>
> return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
> }
> @@ -1985,23 +1992,28 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>
> ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>
> - crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
> -
> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
> drm_dbg_kms(&i915->drm,
> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> + } else if (ycbcr_420_only) {
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + } else {
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> }
>
> + crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
> +
> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> respect_downstream_limits);
> if (ret) {
> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
> - !connector->base.ycbcr_420_allowed ||
Hmm. Where did that ycbcr_420_allowed check go? It seems we'll now try
to enable things thinking we can somehow output 4:2:0 when in fact we
can't. Same issue in the HDMI path.
> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> !drm_mode_is_420_also(info, adjusted_mode))
> return ret;
>
> - crtc_state->output_format = intel_dp_output_format(connector, true);
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + crtc_state->output_format = intel_dp_output_format(connector,
> + crtc_state->sink_format);
> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> respect_downstream_limits);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 4077a979a924..e53e7ece624c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -148,6 +148,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->has_pch_encoder = false;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 4aeae0f3ac91..68ba70751527 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -271,6 +271,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index e82f8a07e2b0..0dd60bb9d7e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2190,13 +2190,13 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
>
> static enum intel_output_format
> intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
> - struct intel_connector *connector,
> - bool ycbcr_420_output)
> + struct intel_connector *connector)
> {
> if (!crtc_state->has_hdmi_sink)
> return INTEL_OUTPUT_FORMAT_RGB;
>
> - if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
> + if (connector->base.ycbcr_420_allowed &&
> + crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> return INTEL_OUTPUT_FORMAT_YCBCR420;
> else
> return INTEL_OUTPUT_FORMAT_RGB;
> @@ -2214,23 +2214,25 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
> bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
> int ret;
>
> - crtc_state->output_format =
> - intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
> -
> - if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
> drm_dbg_kms(&i915->drm,
> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> + } else if (ycbcr_420_only) {
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + } else {
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> }
>
> + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
> if (ret) {
> - if (intel_hdmi_is_ycbcr420(crtc_state) ||
> - !connector->base.ycbcr_420_allowed ||
> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> !drm_mode_is_420_also(info, adjusted_mode))
> return ret;
>
> - crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 7bf1bdfd03ec..ee526fef2276 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -440,6 +440,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> pipe_config->pipe_bpp = lvds_bpp;
> }
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 329b9d9af667..f6b09412da5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1327,6 +1327,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> pipe_config->pipe_bpp = 8*3;
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index b986bf075889..2a205a21d0c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -1206,6 +1206,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 84481030883a..1958774860dc 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -280,6 +280,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
> int ret;
>
> drm_dbg_kms(&dev_priv->drm, "\n");
> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
> --
> 2.25.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion
2022-12-08 21:34 ` Ville Syrjälä
@ 2022-12-10 13:00 ` Nautiyal, Ankit K
0 siblings, 0 replies; 19+ messages in thread
From: Nautiyal, Ankit K @ 2022-12-10 13:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On 12/9/2022 3:04 AM, Ville Syrjälä wrote:
> On Fri, Dec 02, 2022 at 03:40:15PM +0530, Ankit Nautiyal wrote:
>> The decision to use DFP output format conversion capabilities should be
>> during compute_config phase.
>>
>> This patch adds new member to crtc_state to represent the final
>> output_format to the sink. In case of a DFP this can be different than
>> the output_format, as per the format conversion done via the PCON.
>>
>> This will help to store only the format conversion capabilities of the
>> DP device in intel_dp->dfp, and use crtc_state to compute and store the
>> configuration for color/format conversion for a given mode.
>>
>> v2: modified the new member to crtc_state to represent the final
>> output_format that eaches the sink, after possible conversion by
>> PCON kind of devices. (Ville)
>>
>> v3: Addressed comments from Ville:
>> -Added comments to clarify difference between sink_format and
>> output_format.
>> -Corrected the order of setting sink_format and output_format.
>> -Added readout for sink_format in get_pipe_config hooks.
>>
>> v4: Set sink_format for intel_sdvo too. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3)
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
>> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
>> .../drm/i915/display/intel_crtc_state_dump.c | 5 +--
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
>> .../drm/i915/display/intel_display_types.h | 11 +++++-
>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
>> drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
>> drivers/gpu/drm/i915/display/intel_hdmi.c | 24 +++++++------
>> drivers/gpu/drm/i915/display/intel_lvds.c | 1 +
>> drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
>> drivers/gpu/drm/i915/display/intel_tv.c | 1 +
>> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
>> 13 files changed, 62 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index d16b30a2dded..0ca0d23f42c6 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -1667,6 +1667,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>> &pipe_config->hw.adjusted_mode;
>> int ret;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
>> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
>> index 797ad9489f7e..eb5964b3ff95 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
>> @@ -393,6 +393,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> index e3273fe8ddac..9b61884851fc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> @@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>>
>> snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
>> drm_dbg_kms(&i915->drm,
>> - "active: %s, output_types: %s (0x%x), output format: %s\n",
>> + "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
>> str_yes_no(pipe_config->hw.active),
>> buf, pipe_config->output_types,
>> - output_formats(pipe_config->output_format));
>> + output_formats(pipe_config->output_format),
>> + output_formats(pipe_config->sink_format));
>>
>> drm_dbg_kms(&i915->drm,
>> "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 32b257157186..789667e1b2cb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3242,6 +3242,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>> return false;
>>
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + pipe_config->sink_format = pipe_config->output_format;
>> pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
>> pipe_config->shared_dpll = NULL;
>>
>> @@ -3701,6 +3702,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>> break;
>> }
>>
>> + pipe_config->sink_format = pipe_config->output_format;
>> +
>> pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
>>
>> pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
>> @@ -4099,6 +4102,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> bdw_get_pipemisc_output_format(crtc);
>> }
>>
>> + pipe_config->sink_format = pipe_config->output_format;
>> +
>> pipe_config->gamma_mode = intel_de_read(dev_priv,
>> GAMMA_MODE(crtc->pipe));
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index ff3ef37d099e..136866615223 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1267,9 +1267,18 @@ struct intel_crtc_state {
>> /* HDMI High TMDS char rate ratio */
>> bool hdmi_high_tmds_clock_ratio;
>>
>> - /* Output format RGB/YCBCR etc */
>> + /*
>> + * Output format RGB/YCBCR etc., that is coming out
>> + * at the end of the pipe.
>> + */
>> enum intel_output_format output_format;
>>
>> + /*
>> + * Sink output format RGB/YCBCR etc., that is going
>> + * into the sink.
>> + */
>> + enum intel_output_format sink_format;
>> +
>> /* enable pipe gamma? */
>> bool gamma_enable;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 1607c86af025..3ec8a248a928 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -788,11 +788,12 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>>
>> static enum intel_output_format
>> intel_dp_output_format(struct intel_connector *connector,
>> - bool ycbcr_420_output)
>> + enum intel_output_format sink_format)
>> {
>> struct intel_dp *intel_dp = intel_attached_dp(connector);
>>
>> - if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
>> + if (!connector->base.ycbcr_420_allowed ||
>> + sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
>> return INTEL_OUTPUT_FORMAT_RGB;
>>
>> if (intel_dp->dfp.rgb_to_ycbcr &&
>> @@ -831,8 +832,14 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
>> const struct drm_display_mode *mode)
>> {
>> const struct drm_display_info *info = &connector->base.display_info;
>> - enum intel_output_format output_format =
>> - intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
>> + enum intel_output_format output_format, sink_format;
>> +
>> + if (drm_mode_is_420_only(info, mode))
>> + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + else
>> + sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> +
>> + output_format = intel_dp_output_format(connector, sink_format);
>>
>> return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
>> }
>> @@ -1985,23 +1992,28 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>
>> ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>>
>> - crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>> -
>> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
>> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
>> drm_dbg_kms(&i915->drm,
>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> + } else if (ycbcr_420_only) {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + } else {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> }
>>
>> + crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
>> +
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> if (ret) {
>> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
>> - !connector->base.ycbcr_420_allowed ||
> Hmm. Where did that ycbcr_420_allowed check go? It seems we'll now try
> to enable things thinking we can somehow output 4:2:0 when in fact we
> can't. Same issue in the HDMI path.
We are setting sink_format as YCbCr420 only when the mode is YCbCr420
only, and connector->base.ycbcr420_allowed is true.
So in condition below we just check that whether we have already tried
with YCbCr420 as sink format, if thats the case, we just return.
We also return if the sink_format was other than YCBCR420, but the mode
is not Ycbcr420_also.
So IMHO, with the check for sink_format for YCbCr420, the check for
ycbcr_420_allowed is no more required.
Regards,
Ankit
>
>> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> !drm_mode_is_420_also(info, adjusted_mode))
>> return ret;
>>
>> - crtc_state->output_format = intel_dp_output_format(connector, true);
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + crtc_state->output_format = intel_dp_output_format(connector,
>> + crtc_state->sink_format);
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> index 4077a979a924..e53e7ece624c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>> @@ -148,6 +148,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->has_pch_encoder = false;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
>> index 4aeae0f3ac91..68ba70751527 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
>> @@ -271,6 +271,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index e82f8a07e2b0..0dd60bb9d7e8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -2190,13 +2190,13 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
>>
>> static enum intel_output_format
>> intel_hdmi_output_format(const struct intel_crtc_state *crtc_state,
>> - struct intel_connector *connector,
>> - bool ycbcr_420_output)
>> + struct intel_connector *connector)
>> {
>> if (!crtc_state->has_hdmi_sink)
>> return INTEL_OUTPUT_FORMAT_RGB;
>>
>> - if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
>> + if (connector->base.ycbcr_420_allowed &&
>> + crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>> return INTEL_OUTPUT_FORMAT_YCBCR420;
>> else
>> return INTEL_OUTPUT_FORMAT_RGB;
>> @@ -2214,23 +2214,25 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>> bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>> int ret;
>>
>> - crtc_state->output_format =
>> - intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only);
>> -
>> - if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
>> + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
>> drm_dbg_kms(&i915->drm,
>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>> - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> + } else if (ycbcr_420_only) {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + } else {
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> }
>>
>> + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
>> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>> if (ret) {
>> - if (intel_hdmi_is_ycbcr420(crtc_state) ||
>> - !connector->base.ycbcr_420_allowed ||
>> + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> !drm_mode_is_420_also(info, adjusted_mode))
>> return ret;
>>
>> - crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true);
>> + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
>> ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
>> index 7bf1bdfd03ec..ee526fef2276 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
>> @@ -440,6 +440,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>> pipe_config->pipe_bpp = lvds_bpp;
>> }
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> /*
>> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
>> index 329b9d9af667..f6b09412da5a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
>> @@ -1327,6 +1327,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
>>
>> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
>> pipe_config->pipe_bpp = 8*3;
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
>> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
>> index b986bf075889..2a205a21d0c2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tv.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
>> @@ -1206,6 +1206,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
>> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>> return -EINVAL;
>>
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> index 84481030883a..1958774860dc 100644
>> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> @@ -280,6 +280,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
>> int ret;
>>
>> drm_dbg_kms(&dev_priv->drm, "\n");
>> + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
>> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>
>> ret = intel_panel_compute_config(intel_connector, adjusted_mode);
>> --
>> 2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v5 02/14] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v2 03/14] drm/i915/dp: Add Scaler constraint for YCbCr420 output Ankit Nautiyal
` (13 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
New member to store the YCBCR20 Pass through capability of the DP sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 136866615223..212f4aa8fba1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1730,6 +1730,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v2 03/14] drm/i915/dp: Add Scaler constraint for YCbCr420 output
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v6 01/14] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 02/14] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v7 04/14] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format Ankit Nautiyal
` (12 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
For YCbCr420 output, scaler is required for downsampling.
Scaler can be used only when source size smaller than 5120x4096.
So go for native YCbCr420 only if there are no scaler constraints.
v2: Corrected max-width based on Display Version.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3ec8a248a928..b22018fa1230 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -786,11 +786,27 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
return 0;
}
+static bool
+ycbcr420_scaler_constraints(struct drm_i915_private *i915,
+ const struct drm_display_mode *mode)
+{
+ /* FIXME: Use macros for max_w and max_h from intel_scaler */
+ int max_w = 4096;
+ int max_h = 4096;
+
+ if (DISPLAY_VER(i915) > 11)
+ max_w = 5120;
+
+ return mode->hdisplay > max_w || mode->vdisplay > max_h;
+}
+
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
+ const struct drm_display_mode *mode,
enum intel_output_format sink_format)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
if (!connector->base.ycbcr_420_allowed ||
sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
@@ -802,8 +818,15 @@ intel_dp_output_format(struct intel_connector *connector,
if (intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_YCBCR444;
- else
+
+ /*
+ * For YCbCr420 output, scaler is required for downsampling
+ * So go for native YCbCr420 only if there are no scaler constraints.
+ */
+ if (!ycbcr420_scaler_constraints(i915, mode))
return INTEL_OUTPUT_FORMAT_YCBCR420;
+
+ return INTEL_OUTPUT_FORMAT_RGB;
}
int intel_dp_min_bpp(enum intel_output_format output_format)
@@ -839,7 +862,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, sink_format);
+ output_format = intel_dp_output_format(connector, mode, sink_format);
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}
@@ -2002,7 +2025,8 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
}
- crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
+ crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
+ crtc_state->sink_format);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
@@ -2012,7 +2036,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
return ret;
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- crtc_state->output_format = intel_dp_output_format(connector,
+ crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
crtc_state->sink_format);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v7 04/14] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (2 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v2 03/14] drm/i915/dp: Add Scaler constraint for YCbCr420 output Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v2 05/14] drm/i915/dp: Compute output format with/without DSC Ankit Nautiyal
` (11 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
sink_format member, to program the protocol-converter for
colorspace/format conversion.
v2: Use sink_format to determine the color conversion config for the
pcon (Ville).
v3: Fix typo: missing 'break' in switch case (lkp kernel test robot).
v4: Add helper to check if DP supports YCBCR420.
v5: Simplify logic for computing output_format, based on the given
sink_format. (Ville).
Added scaler constraint for YCbCr420 output.
v6: Split the patch for Scaler constraint for Ycbcr420.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 192 +++++++++++++++++-------
1 file changed, 135 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b22018fa1230..e3ba84e7fda6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -786,6 +786,67 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
return 0;
}
+static bool source_can_output(struct intel_dp *intel_dp,
+ enum intel_output_format format)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool is_branch = drm_dp_is_branch(intel_dp->dpcd);
+
+ if (format == INTEL_OUTPUT_FORMAT_RGB)
+ return true;
+
+ /*
+ * No YCbCr output support on gmch platforms.
+ * Also, ILK doesn't seem capable of DP YCbCr output.
+ * The displayed image is severly corrupted. SNB+ is fine.
+ */
+ if (HAS_GMCH(i915) || IS_IRONLAKE(i915))
+ return false;
+
+ if (format == INTEL_OUTPUT_FORMAT_YCBCR444)
+ return true;
+
+ /* Platform < Gen 11 cannot output YCbCr420 format */
+ if (DISPLAY_VER(i915) < 11)
+ return false;
+
+ /* If branch device then PCONs should support YCbCr420 Passthrough */
+ if (format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return !is_branch || intel_dp->dfp.ycbcr420_passthrough;
+
+ return false;
+}
+
+static bool
+dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
+ enum intel_output_format sink_format)
+{
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return false;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+ return intel_dp->dfp.rgb_to_ycbcr;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return intel_dp->dfp.rgb_to_ycbcr &&
+ intel_dp->dfp.ycbcr_444_to_420;
+
+ return false;
+}
+
+static bool
+dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
+ enum intel_output_format sink_format)
+{
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return false;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return intel_dp->dfp.ycbcr_444_to_420;
+
+ return false;
+}
+
static bool
ycbcr420_scaler_constraints(struct drm_i915_private *i915,
const struct drm_display_mode *mode)
@@ -808,24 +869,23 @@ intel_dp_output_format(struct intel_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- if (!connector->base.ycbcr_420_allowed ||
- sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- return INTEL_OUTPUT_FORMAT_RGB;
+ /*
+ * For YCbCr420 output, scaler is required for downsampling.
+ * So go for native YCbCr420 only if there are no scaler constraints.
+ */
+ if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ !ycbcr420_scaler_constraints(i915, mode)) &&
+ source_can_output(intel_dp, sink_format))
+ return sink_format;
- if (intel_dp->dfp.rgb_to_ycbcr &&
- intel_dp->dfp.ycbcr_444_to_420)
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
+ dfp_can_convert_from_rgb(intel_dp, sink_format))
return INTEL_OUTPUT_FORMAT_RGB;
- if (intel_dp->dfp.ycbcr_444_to_420)
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
+ dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
return INTEL_OUTPUT_FORMAT_YCBCR444;
- /*
- * For YCbCr420 output, scaler is required for downsampling
- * So go for native YCbCr420 only if there are no scaler constraints.
- */
- if (!ycbcr420_scaler_constraints(i915, mode))
- return INTEL_OUTPUT_FORMAT_YCBCR420;
-
return INTEL_OUTPUT_FORMAT_RGB;
}
@@ -2712,6 +2772,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool ycbcr444_to_420 = false;
+ bool rgb_to_ycbcr = false;
u8 tmp;
if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
@@ -2728,8 +2790,35 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
- tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
- intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
+ if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ /*
+ * sink_format is YCbCr420, output_format is also YCbCr420:
+ * Passthrough.
+ */
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ /*
+ * sink_format is YCbCr420, output_format is YCbCr444:
+ * Downsample.
+ */
+ ycbcr444_to_420 = true;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ /*
+ * sink_format is YCbCr420, output_format is RGB:
+ * Convert to YCbCr444 and Downsample.
+ */
+ rgb_to_ycbcr = true;
+ ycbcr444_to_420 = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
@@ -2737,13 +2826,12 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
- tmp = intel_dp->dfp.rgb_to_ycbcr ?
- DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
+ tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
drm_dbg_kms(&i915->drm,
- "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
- str_enable_disable(tmp));
+ "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
+ str_enable_disable(tmp));
}
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
@@ -4588,57 +4676,47 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
intel_dp_get_pcon_dsc_cap(intel_dp);
}
+static bool
+intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
+{
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
+ return true;
+ /*
+ * If source cannot support YCbCr420, and PCON has color conv. support:
+ * Source sends YCbCr444, PCON converts YCbCr444->420 Or
+ * Source sends RGB444, PCON converts RGB->YCbCr444 + YCbCr444->YCbCr420)
+ */
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
+ dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
+ return true;
+
+ if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
+ dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
+ return INTEL_OUTPUT_FORMAT_YCBCR444;
+
+ return false;
+}
+
static void
intel_dp_update_420(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_connector *connector = intel_dp->attached_connector;
- bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
-
- /* No YCbCr output support on gmch platforms */
- if (HAS_GMCH(i915))
- return;
-
- /*
- * ILK doesn't seem capable of DP YCbCr output. The
- * displayed image is severly corrupted. SNB+ is fine.
- */
- if (IS_IRONLAKE(i915))
- return;
- is_branch = drm_dp_is_branch(intel_dp->dpcd);
- ycbcr_420_passthrough =
+ intel_dp->dfp.ycbcr420_passthrough =
drm_dp_downstream_420_passthrough(intel_dp->dpcd,
intel_dp->downstream_ports);
/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
- ycbcr_444_to_420 =
+ intel_dp->dfp.ycbcr_444_to_420 =
dp_to_dig_port(intel_dp)->lspcon.active ||
drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
intel_dp->downstream_ports);
- rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
- intel_dp->downstream_ports,
- DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
-
- if (DISPLAY_VER(i915) >= 11) {
- /* Let PCON convert from RGB->YCbCr if possible */
- if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
- intel_dp->dfp.rgb_to_ycbcr = true;
- intel_dp->dfp.ycbcr_444_to_420 = true;
- connector->base.ycbcr_420_allowed = true;
- } else {
- /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
- intel_dp->dfp.ycbcr_444_to_420 =
- ycbcr_444_to_420 && !ycbcr_420_passthrough;
+ intel_dp->dfp.rgb_to_ycbcr =
+ drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
+ intel_dp->downstream_ports,
+ DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
- connector->base.ycbcr_420_allowed =
- !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
- }
- } else {
- /* 4:4:4->4:2:0 conversion is the only way */
- intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
-
- connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
- }
+ connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
drm_dbg_kms(&i915->drm,
"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v2 05/14] drm/i915/dp: Compute output format with/without DSC
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (3 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v7 04/14] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 06/14] drm/i915/display: Use sink_format instead of ycbcr420_output flag Ankit Nautiyal
` (10 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Currently we compute the output format first and later try DSC if the
bandwidth without compression is not sufficient for that output format.
Since we do not support DSC with YCbCr420 format, this creates problem
for YCbCr420 only modes, that can be still be set if DFP has color
conversion and DSC capabilities.
So compute output format, first without DSC and inturn compute the link
config without DSC. If cannot be supported without DSC, compute the
output format with DSC and continue.
With this apporach, check can be added for YCbCr420 output, which cannot
be supported with DSC.
v2: Rebased
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++++++++++-------
1 file changed, 61 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e3ba84e7fda6..4789d3c3cb2e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -861,20 +861,37 @@ ycbcr420_scaler_constraints(struct drm_i915_private *i915,
return mode->hdisplay > max_w || mode->vdisplay > max_h;
}
+static bool
+ycbcr420_constraints(struct drm_i915_private *i915,
+ const struct drm_display_mode *mode,
+ bool with_dsc)
+{
+ /*
+ * DSC with YCbCr420 is a constraint as currently we do not support compression
+ * with 420 format.
+ */
+ if (with_dsc)
+ return true;
+
+ return ycbcr420_scaler_constraints(i915, mode);
+}
+
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
const struct drm_display_mode *mode,
- enum intel_output_format sink_format)
+ enum intel_output_format sink_format,
+ bool with_dsc)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
/*
* For YCbCr420 output, scaler is required for downsampling.
- * So go for native YCbCr420 only if there are no scaler constraints.
+ * DSC1.1 supports compression only with 444 formats.
+ * So go for native YCbCr420 only if there are no scaler and dsc constraints.
*/
if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
- !ycbcr420_scaler_constraints(i915, mode)) &&
+ !ycbcr420_constraints(i915, mode, with_dsc)) &&
source_can_output(intel_dp, sink_format))
return sink_format;
@@ -922,7 +939,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, mode, sink_format);
+ output_format = intel_dp_output_format(connector, mode, sink_format, false);
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}
@@ -1671,7 +1688,8 @@ static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -1682,6 +1700,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool joiner_needs_dsc = false;
int ret;
+ if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_clock))
+ pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
+
+ /*
+ * Pipe joiner needs compression up to display 12 due to bandwidth
+ * limitation. DG2 onwards pipe joiner can be enabled without
+ * compression.
+ */
+ joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
+
+ if (joiner_needs_dsc && !with_dsc)
+ return -EINVAL;
+
limits.min_rate = intel_dp_common_rate(intel_dp, 0);
limits.max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1711,23 +1743,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_clock))
- pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
-
- /*
- * Pipe joiner needs compression up to display 12 due to bandwidth
- * limitation. DG2 onwards pipe joiner can be enabled without
- * compression.
- */
- joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
-
/*
* Optimize for slow and wide for everything, because there are some
* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
*/
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
+ if (ret && !with_dsc)
+ return -EINVAL;
+
if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
@@ -2063,7 +2087,8 @@ static int
intel_dp_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2086,10 +2111,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
}
crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
- crtc_state->sink_format);
+ crtc_state->sink_format, with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
if (ret) {
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, adjusted_mode))
@@ -2097,9 +2122,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
- crtc_state->sink_format);
+ crtc_state->sink_format,
+ with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
}
return ret;
@@ -2163,9 +2189,21 @@ intel_dp_compute_config(struct intel_encoder *encoder,
* Try to respect downstream TMDS clock limits first, if
* that fails assume the user might know something we don't.
*/
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, true, false);
if (ret)
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, false, false);
+
+ /* Try with DSC */
+ if (ret) {
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, true, true);
+ if (ret)
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, false, true);
+ }
+
if (ret)
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 06/14] drm/i915/display: Use sink_format instead of ycbcr420_output flag
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (4 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v2 05/14] drm/i915/dp: Compute output format with/without DSC Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 07/14] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid Ankit Nautiyal
` (9 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support later.
Suggested-by: Ville Syrj_l_ <ville.syrjala@linux.intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++--------
drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ++++++++++++-----------
drivers/gpu/drm/i915/display/intel_hdmi.h | 5 ++-
3 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4789d3c3cb2e..67132ed4ed29 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -978,7 +978,8 @@ static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
- int clock, int bpc, bool ycbcr420_output,
+ int clock, int bpc,
+ enum intel_output_format sink_format,
bool respect_downstream_limits)
{
int tmds_clock, min_tmds_clock, max_tmds_clock;
@@ -986,7 +987,7 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
if (!respect_downstream_limits)
return MODE_OK;
- tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+ tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
min_tmds_clock = intel_dp->dfp.min_tmds_clock;
max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
@@ -1009,6 +1010,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only;
+ enum intel_output_format sink_format;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
@@ -1035,18 +1037,22 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, ycbcr_420_only, true);
+ 8, sink_format, true);
if (status != MODE_OK) {
- if (ycbcr_420_only ||
- !connector->base.ycbcr_420_allowed ||
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
-
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, true, true);
+ 8, sink_format, true);
if (status != MODE_OK)
return status;
}
@@ -1285,19 +1291,10 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
-static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
- intel_dp->dfp.ycbcr_444_to_420);
-}
-
static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int bpc, bool respect_downstream_limits)
{
- bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
/*
@@ -1317,8 +1314,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
for (; bpc >= 8; bpc -= 2) {
if (intel_hdmi_bpc_possible(crtc_state, bpc,
- intel_dp->has_hdmi_sink, ycbcr420_output) &&
- intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
+ intel_dp->has_hdmi_sink) &&
+ intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
respect_downstream_limits) == MODE_OK)
return bpc;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0dd60bb9d7e8..3f9450ed5241 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1809,11 +1809,6 @@ static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
}
-static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
-{
- return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
-}
-
static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
bool respect_downstream_limits,
bool has_hdmi_sink)
@@ -1887,10 +1882,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_OK;
}
-int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
+int intel_hdmi_tmds_clock(int clock, int bpc,
+ enum intel_output_format sink_format)
{
/* YCBCR420 TMDS rate requirement is half the pixel clock */
- if (ycbcr420_output)
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
clock /= 2;
/*
@@ -1917,7 +1913,8 @@ static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bp
}
static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
- int bpc, bool has_hdmi_sink, bool ycbcr420_output)
+ int bpc, bool has_hdmi_sink,
+ enum intel_output_format sink_format)
{
const struct drm_display_info *info = &connector->display_info;
const struct drm_hdmi_info *hdmi = &info->hdmi;
@@ -1927,7 +1924,7 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
if (!has_hdmi_sink)
return false;
- if (ycbcr420_output)
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
else
return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
@@ -1935,7 +1932,7 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
if (!has_hdmi_sink)
return false;
- if (ycbcr420_output)
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
else
return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
@@ -1949,7 +1946,8 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
static enum drm_mode_status
intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
- bool has_hdmi_sink, bool ycbcr420_output)
+ bool has_hdmi_sink,
+ enum intel_output_format sink_format)
{
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
@@ -1962,12 +1960,12 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
* least one color depth is accepted.
*/
for (bpc = 12; bpc >= 8; bpc -= 2) {
- int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
if (!intel_hdmi_source_bpc_possible(i915, bpc))
continue;
- if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
+ if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
continue;
status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
@@ -1992,6 +1990,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
bool ycbcr_420_only;
+ enum intel_output_format sink_format;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -2019,14 +2018,17 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
- status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
+ sink_format = ycbcr_420_only ? INTEL_OUTPUT_FORMAT_YCBCR420 : INTEL_OUTPUT_FORMAT_RGB;
+
+ status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
if (status != MODE_OK) {
if (ycbcr_420_only ||
!connector->ycbcr_420_allowed ||
!drm_mode_is_420_also(&connector->display_info, mode))
return status;
- status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
if (status != MODE_OK)
return status;
}
@@ -2035,7 +2037,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
}
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
- int bpc, bool has_hdmi_sink, bool ycbcr420_output)
+ int bpc, bool has_hdmi_sink)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_connector_state *connector_state;
@@ -2046,7 +2048,8 @@ bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
if (connector_state->crtc != crtc_state->uapi.crtc)
continue;
- if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
+ if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
+ crtc_state->sink_format))
return false;
}
@@ -2064,14 +2067,13 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc
return false;
/* Display Wa_1405510057:icl,ehl */
- if (intel_hdmi_is_ycbcr420(crtc_state) &&
+ if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
adjusted_mode->crtc_hblank_start) % 8 == 2)
return false;
- return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
- intel_hdmi_is_ycbcr420(crtc_state));
+ return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
}
static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
@@ -2079,7 +2081,6 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
int clock, bool respect_downstream_limits)
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
- bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
int bpc;
/*
@@ -2097,7 +2098,8 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
bpc = 8;
for (; bpc >= 8; bpc -= 2) {
- int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
+ crtc_state->sink_format);
if (hdmi_bpc_possible(crtc_state, bpc) &&
hdmi_port_clock_valid(intel_hdmi, tmds_clock,
@@ -2127,7 +2129,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
return bpc;
crtc_state->port_clock =
- intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
+ intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
/*
* pipe_bpp could already be below 8bpc due to
@@ -2287,7 +2289,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
return ret;
}
- if (intel_hdmi_is_ycbcr420(pipe_config)) {
+ if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
ret = intel_panel_fitting(pipe_config, conn_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 774dda2376ed..d1e27247b657 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
enum hdmi_infoframe_type;
+enum intel_output_format;
enum port;
struct drm_connector;
struct drm_connector_state;
@@ -45,8 +46,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
- int bpc, bool has_hdmi_sink, bool ycbcr420_output);
-int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output);
+ int bpc, bool has_hdmi_sink);
+int intel_hdmi_tmds_clock(int clock, int bpc, enum intel_output_format sink_format);
int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
int num_slices, int output_format, bool hdmi_all_bpp,
int hdmi_max_chunk_bytes);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v1 07/14] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (5 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 06/14] drm/i915/display: Use sink_format instead of ycbcr420_output flag Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 08/14] drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid Ankit Nautiyal
` (8 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Check for MODE_H_ILLEGAL before calculating max rates, lanes etc.
Move comments about compressed bpp U6.4 format closer to where it is used.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67132ed4ed29..2d7135cfb225 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1112,6 +1112,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
+ if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
+ return MODE_H_ILLEGAL;
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
@@ -1119,13 +1122,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode_rate = intel_dp_link_required(target_clock,
intel_dp_mode_min_output_bpp(connector, mode));
- if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
- return MODE_H_ILLEGAL;
-
- /*
- * Output bpp is stored in 6.4 format so right shift by 4 to get the
- * integer value since we support only integer values of bpp.
- */
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
/*
@@ -1134,6 +1130,10 @@ intel_dp_mode_valid(struct drm_connector *_connector,
*/
int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ /*
+ * Output bpp is stored in 6.4 format so right shift by 4 to get the
+ * integer value since we support only integer values of bpp.
+ */
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v1 08/14] drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (6 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 07/14] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 09/14] drm/i915/dp: Check if mode can be supported with dsc compressed bpp Ankit Nautiyal
` (7 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
During modevalid step, the pipe bpp is computed assuming RGB output
format. When checking with DSC, consider the output_format and compute
the input bpp for DSC appropriately.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++++++++++++++++++------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2d7135cfb225..d333583e3894 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -117,7 +117,9 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp,
+ enum intel_output_format output_format,
+ u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1124,11 +1126,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ int pipe_bpp;
+ enum intel_output_format output_format, sink_format;
+ const struct drm_display_info *info = &connector->base.display_info;
+
+ if (drm_mode_is_420_only(info, mode))
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
+ output_format = intel_dp_output_format(connector, mode, sink_format, true);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, output_format, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1468,12 +1480,15 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp,
+ enum intel_output_format output_format,
+ u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
+ int pipe_bpp = 0;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -1484,11 +1499,13 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
for (i = 0; i < num_bpc; i++) {
- if (dsc_max_bpc >= dsc_bpc[i])
- return dsc_bpc[i] * 3;
+ if (dsc_max_bpc >= dsc_bpc[i]) {
+ pipe_bpp = dsc_bpc[i] * 3;
+ break;
+ }
}
- return 0;
+ return intel_dp_output_bpp(output_format, pipe_bpp);
}
static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
@@ -1587,7 +1604,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format,
+ conn_state->max_requested_bpc);
if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v1 09/14] drm/i915/dp: Check if mode can be supported with dsc compressed bpp
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (7 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 08/14] drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 10/14] drm/i915/display: Add helper function to check if sink_format is 420 Ankit Nautiyal
` (6 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Use compressed bpp to calculate mode_rate during dp_mode_valid.
Check if this can be supported with max lane count and link rate
combination.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d333583e3894..920be0fd39c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1121,8 +1121,6 @@ intel_dp_mode_valid(struct drm_connector *_connector,
max_lanes = intel_dp_max_lane_count(intel_dp);
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
- mode_rate = intel_dp_link_required(target_clock,
- intel_dp_mode_min_output_bpp(connector, mode));
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
@@ -1178,7 +1176,12 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
return MODE_CLOCK_HIGH;
- if (mode_rate > max_rate && !dsc)
+ if (dsc)
+ mode_rate = intel_dp_link_required(target_clock, dsc_max_output_bpp);
+ else
+ mode_rate = intel_dp_link_required(target_clock,
+ intel_dp_mode_min_output_bpp(connector, mode));
+ if (mode_rate > max_rate)
return MODE_CLOCK_HIGH;
status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 10/14] drm/i915/display: Add helper function to check if sink_format is 420
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (8 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v1 09/14] drm/i915/dp: Check if mode can be supported with dsc compressed bpp Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 11/14] drm/i915/dp: Avoid DSC with output_format YCBCR420 Ankit Nautiyal
` (5 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Add an inline helper function to check if the sink_format is set to
YCBCR420 format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++---
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 212f4aa8fba1..883cab869e1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2064,4 +2064,10 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline bool
+intel_crtc_has_420_sink_format(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 920be0fd39c1..8c5480cd2f65 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2134,7 +2134,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits, with_dsc);
if (ret) {
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
@@ -2846,7 +2846,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (intel_crtc_has_420_sink_format(crtc_state)) {
switch (crtc_state->output_format) {
case INTEL_OUTPUT_FORMAT_YCBCR420:
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3f9450ed5241..3de2416f70ce 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2067,7 +2067,7 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc
return false;
/* Display Wa_1405510057:icl,ehl */
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+ if (intel_crtc_has_420_sink_format(crtc_state) &&
bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
adjusted_mode->crtc_hblank_start) % 8 == 2)
@@ -2229,7 +2229,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector);
ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
if (ret) {
- if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
@@ -2289,7 +2289,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
return ret;
}
- if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (intel_crtc_has_420_sink_format(pipe_config)) {
ret = intel_panel_fitting(pipe_config, conn_state);
if (ret)
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 11/14] drm/i915/dp: Avoid DSC with output_format YCBCR420
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (9 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 10/14] drm/i915/display: Add helper function to check if sink_format is 420 Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 12/14] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
` (4 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Currently, DSC with YCBCR420 is not supported.
Return -EINVAL when trying with DSC with output_format as YCBCR420.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c5480cd2f65..7cb77f399c64 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1607,6 +1607,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ /* Currently DSC with YCBCR420 format is not supported */
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format,
conn_state->max_requested_bpc);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 12/14] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (10 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 11/14] drm/i915/dp: Avoid DSC with output_format YCBCR420 Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 13/14] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
` (3 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work even with the maximum FRL rate supported by HDMI2.1
sink.
This patch calculates the max BPC that can be sufficient with either
RGB or YCBCR420 format for the maximum FRL rate supported.
v2: Rebase
v3: Use the sink_format in the functions instead of ycbcr420 flag.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 63 +++++++++++++++++++++++--
1 file changed, 59 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7cb77f399c64..f79b6dff02e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -120,6 +120,7 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp,
enum intel_output_format output_format,
u8 dsc_max_bpc);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1589,12 +1590,47 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int max_bpc)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+ int req_rate_gbps;
+ int max_frl_rate = connector->display_info.hdmi.max_lanes *
+ connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if (dsc_bpc[i] > max_bpc)
+ continue;
+
+ req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000);
+
+ /* YCBCR420 reduces data rate by 2 */
+ if (intel_crtc_has_420_sink_format(pipe_config))
+ req_rate_gbps /= 2;
+
+ if (req_rate_gbps < max_frl_rate)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1611,12 +1647,31 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format,
- conn_state->max_requested_bpc);
-
- if (intel_dp->force_dsc_bpc) {
+ /*
+ * In cases where PCON with HDMI2.1 as branch device, if PCON supports
+ * DSC but HDMI2.1 sink does not supports DSC, there can be issues due
+ * to the bpc used.
+ * With DSC, a source-PCON pair can support the mode with higher bpcs.
+ * But PCON->Sink pair, cannot support the same bpc without sink having
+ * DSC support.
+ * So use the max BPC as input BPC that will be sufficient to show the
+ * mode without DSC from PCON->HDMI2.1
+ */
+ if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+ !connector->display_info.hdmi.dsc_cap.v_1p2) {
+ pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config,
+ conn_state->max_requested_bpc);
+ if (!pipe_bpp) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No BPC possible to support the mode without HDMI2.1 DSC\n");
+ return -EINVAL;
+ }
+ } else if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format,
+ conn_state->max_requested_bpc);
}
/* Min Input BPC for ICL+ is 8 */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 13/14] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (11 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 12/14] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 14/14] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints Ankit Nautiyal
` (2 subsequent siblings)
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Rebase
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++++++--------
1 file changed, 45 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f79b6dff02e2..4b6a70cae851 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -121,6 +121,7 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp,
enum intel_output_format output_format,
u8 dsc_max_bpc);
static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1004,6 +1005,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, enum intel_output_format sink_format)
+{
+ int target_bw;
+ int max_frl_bw;
+ int bpp = bpc * 3;
+
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ target_clock /= 2;
+
+ target_bw = bpp * target_clock;
+
+ /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+ max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+ intel_dp_hdmi_sink_max_frl(intel_dp));
+
+ /* converting bw from Gbps to Kbps*/
+ max_frl_bw = max_frl_bw * 1000000;
+
+ if (target_bw > max_frl_bw)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1012,24 +1039,30 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
- bool ycbcr_420_only;
+ bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
enum intel_output_format sink_format;
+ ycbcr_420_only = drm_mode_is_420_only(info, mode);
+
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
- int target_bw;
- int max_frl_bw;
- int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
- target_bw = bpp * target_clock;
- max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
-
- /* converting bw from Gbps to Kbps*/
- max_frl_bw = max_frl_bw * 1000000;
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
- if (target_bw > max_frl_bw)
- return MODE_CLOCK_HIGH;
+ /* Assume 8bpc for the HDMI2.1 FRL BW check */
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
+ if (status != MODE_OK) {
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ !drm_mode_is_420_also(info, mode))
+ return status;
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
+ if (status != MODE_OK)
+ return status;
+ }
return MODE_OK;
}
@@ -1038,13 +1071,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
-
- if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- else
- sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
8, sink_format, true);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v5 14/14] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (12 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 13/14] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
@ 2022-12-02 10:10 ` Ankit Nautiyal
2022-12-02 11:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8) Patchwork
2022-12-02 23:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Ankit Nautiyal @ 2022-12-02 10:10 UTC (permalink / raw)
To: intel-gfx
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 +++++++++++--------------
1 file changed, 23 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4b6a70cae851..00d3ed156bbf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1031,6 +1031,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
return MODE_OK;
}
+static enum drm_mode_status
+intel_dp_hdmi_bw_check(struct intel_dp *intel_dp,
+ int target_clock, int bpc,
+ enum intel_output_format sink_format,
+ bool is_frl)
+{
+ if (is_frl)
+ return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
+
+ return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true);
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -1040,48 +1052,31 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ bool is_frl;
enum intel_output_format sink_format;
+ int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw heck */
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
+ if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+ sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ else
+ sink_format = INTEL_OUTPUT_FORMAT_RGB;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
- if (intel_dp->dfp.pcon_max_frl_bw) {
-
- if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- else
- sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
- /* Assume 8bpc for the HDMI2.1 FRL BW check */
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
- if (status != MODE_OK) {
- if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
- !drm_mode_is_420_also(info, mode))
- return status;
- sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format);
- if (status != MODE_OK)
- return status;
- }
+ is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false;
- return MODE_OK;
- }
-
- if (intel_dp->dfp.max_dotclock &&
+ if (!is_frl && intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl);
if (status != MODE_OK) {
if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
- 8, sink_format, true);
+ status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl);
+ } else {
if (status != MODE_OK)
return status;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8)
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (13 preceding siblings ...)
2022-12-02 10:10 ` [Intel-gfx] [PATCH v5 14/14] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints Ankit Nautiyal
@ 2022-12-02 11:16 ` Patchwork
2022-12-02 23:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-12-02 11:16 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6223 bytes --]
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12462 -> Patchwork_107550v8
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/index.html
Participating hosts (42 -> 40)
------------------------------
Additional (1): bat-dg1-7
Missing (3): fi-ilk-m540 fi-apl-guc bat-dg1-6
Known issues
------------
Here are the changes found in Patchwork_107550v8 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-6700k2: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][3] ([i915#2582]) -> [PASS][4] +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/bat-rpls-2/igt@fbdev@read.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/bat-rpls-2/igt@fbdev@read.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][5] ([i915#2867]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/bat-rplp-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][7] ([i915#5334]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [INCOMPLETE][9] ([i915#4983] / [i915#6257]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/bat-rpls-2/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_psr@primary_page_flip:
- fi-kbl-soraka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
Build changes
-------------
* Linux: CI_DRM_12462 -> Patchwork_107550v8
CI-20190529: 20190529
CI_DRM_12462: 00b10bdfd8b9edc9b2c681d806fbb6ae2e5f31a3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7078: 71bce31c26998d5d53cff3138049261fd6c4fbaf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107550v8: 00b10bdfd8b9edc9b2c681d806fbb6ae2e5f31a3 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0ba6bef0af3e drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
ffb5435c2164 drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
b407783aee5a drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
2e474682091b drm/i915/dp: Avoid DSC with output_format YCBCR420
81d704d195c2 drm/i915/display: Add helper function to check if sink_format is 420
618a2a42e598 drm/i915/dp: Check if mode can be supported with dsc compressed bpp
4581cb5a9441 drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid
a9474182ce45 drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid
6bb87b27e81c drm/i915/display: Use sink_format instead of ycbcr420_output flag
362850bf8e5f drm/i915/dp: Compute output format with/without DSC
7e3aad1b7d37 drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format
3030cded43d8 drm/i915/dp: Add Scaler constraint for YCbCr420 output
def98e46e1b8 drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap
a137557b7d21 drm/i915/display: Add new member to configure PCON color conversion
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/index.html
[-- Attachment #2: Type: text/html, Size: 5898 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8)
2022-12-02 10:10 [Intel-gfx] [PATCH v8 00/14] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (14 preceding siblings ...)
2022-12-02 11:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8) Patchwork
@ 2022-12-02 23:24 ` Patchwork
15 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-12-02 23:24 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 39023 bytes --]
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev8)
URL : https://patchwork.freedesktop.org/series/107550/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12462_full -> Patchwork_107550v8_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_107550v8_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107550v8_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 14)
------------------------------
Additional (1): shard-tglu-9
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107550v8_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@nonexisting-fb@d-edp1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-tglb1/igt@kms_flip@nonexisting-fb@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb6/igt@kms_flip@nonexisting-fb@d-edp1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@cursor-suspend:
- {shard-tglu-9}: NOTRUN -> [SKIP][3] +25 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglu-9/igt@kms_cursor_crc@cursor-suspend.html
* {igt@v3d/v3d_get_param@get-bad-flags}:
- {shard-dg1}: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-dg1-18/igt@v3d/v3d_get_param@get-bad-flags.html
Known issues
------------
Here are the changes found in Patchwork_107550v8_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#1839])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@feature_discovery@display-3x.html
* igt@gem_ctx_persistence@hang:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +46 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@gem_ctx_persistence@hang.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-tglb: NOTRUN -> [FAIL][11] ([i915#2842]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#4270])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gen3_render_linear_blits:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109289])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#5566] / [i915#716])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl9/igt@gen9_exec_parse@allowed-all.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl9/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#5566] / [i915#716])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-glk9/igt@gen9_exec_parse@allowed-single.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-glk4/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#3989] / [i915#454])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109303])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][22] ([i915#1759])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#2521]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#5286]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#111615])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#6095]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#3689] / [i915#6095])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3689] / [i915#3886])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111615] / [i915#3689])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#3689])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-tglb: NOTRUN -> [SKIP][33] ([fdo#109284] / [fdo#111827]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_color_chamelium@ctm-0-50:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl7/igt@kms_color_chamelium@ctm-0-50.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-apl: [PASS][37] -> [FAIL][38] ([i915#2346])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-iclb: [PASS][39] -> [FAIL][40] ([i915#2346]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109274] / [fdo#111825] / [i915#3637]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#79])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#2122])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#2587] / [i915#2672])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#2672] / [i915#3555])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][48] ([i915#2587] / [i915#2672]) +4 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][49] ([i915#3555]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#2672]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#6497]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109280] / [fdo#111825]) +8 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109642] / [fdo#111068] / [i915#658])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb7/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_primary_blt:
- shard-tglb: NOTRUN -> [FAIL][55] ([i915#132] / [i915#3467])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@kms_psr@psr2_primary_blt.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [PASS][58] -> [SKIP][59] ([i915#5519]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-tglb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [PASS][60] -> [SKIP][61] ([i915#5519])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2437])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl7/igt@kms_writeback@writeback-check-output.html
* igt@perf_pmu@interrupts:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#7318])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl7/igt@perf_pmu@interrupts.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl10/igt@perf_pmu@interrupts.html
* igt@sysfs_clients@recycle-many:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#2994])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb5/igt@sysfs_clients@recycle-many.html
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl6/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- shard-skl: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl1/igt@fbdev@nullptr.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl10/igt@fbdev@nullptr.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][69] ([i915#4525]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb5/igt@gem_exec_balancer@parallel-out-fence.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_endless@dispatch@bcs0:
- {shard-rkl}: [SKIP][71] ([i915#6247]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][73] ([i915#2846]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][75] ([i915#2842]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- {shard-rkl}: [SKIP][79] ([i915#3281]) -> [PASS][80] +9 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-1/igt@gem_exec_reloc@basic-wc-read-noreloc.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-5/igt@gem_exec_reloc@basic-wc-read-noreloc.html
* igt@gem_set_tiling_vs_pwrite:
- {shard-rkl}: [SKIP][81] ([i915#3282]) -> [PASS][82] +9 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-1/igt@gem_set_tiling_vs_pwrite.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html
* igt@gen9_exec_parse@batch-without-end:
- {shard-rkl}: [SKIP][83] ([i915#2527]) -> [PASS][84] +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-1/igt@gen9_exec_parse@batch-without-end.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-5/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][85] ([fdo#109308]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@i915_pm_rpm@i2c.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@i915_suspend@forcewake:
- shard-skl: [INCOMPLETE][87] ([i915#4817] / [i915#7233]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@i915_suspend@forcewake.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl7/igt@i915_suspend@forcewake.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][89] ([i915#79]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][91] ([i915#79]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][93] ([i915#2122]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- {shard-rkl}: [SKIP][95] ([i915#1849] / [i915#4098]) -> [PASS][96] +4 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_plane@plane-position-hole-dpms@pipe-b-planes:
- {shard-rkl}: [SKIP][97] ([i915#1849] / [i915#3558]) -> [PASS][98] +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html
* igt@kms_properties@plane-properties-legacy:
- {shard-rkl}: [SKIP][99] ([i915#1849]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@kms_properties@plane-properties-legacy.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@kms_properties@plane-properties-legacy.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][101] ([fdo#109441]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb8/igt@kms_psr@psr2_primary_blt.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_psr@sprite_render:
- {shard-rkl}: [SKIP][103] ([i915#1072]) -> [PASS][104] +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@kms_psr@sprite_render.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@kms_psr@sprite_render.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [SKIP][105] ([i915#5519]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_sequence@queue-busy@edp-1-pipe-b:
- shard-skl: [FAIL][107] ([i915#7413]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl7/igt@kms_sequence@queue-busy@edp-1-pipe-b.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl4/igt@kms_sequence@queue-busy@edp-1-pipe-b.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][109] ([i915#7404]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-skl1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-b-query-forked:
- {shard-rkl}: [SKIP][111] ([i915#1845] / [i915#4098]) -> [PASS][112] +13 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-5/igt@kms_vblank@pipe-b-query-forked.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-6/igt@kms_vblank@pipe-b-query-forked.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][113] ([i915#2434]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-1/igt@perf@mi-rpc.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-5/igt@perf@mi-rpc.html
* igt@prime_vgem@basic-fence-read:
- {shard-rkl}: [SKIP][115] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-rkl-1/igt@prime_vgem@basic-fence-read.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
#### Warnings ####
* igt@gem_pread@exhaustion:
- shard-apl: [INCOMPLETE][117] ([i915#7248]) -> [WARN][118] ([i915#2658])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl6/igt@gem_pread@exhaustion.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl2/igt@gem_pread@exhaustion.html
- shard-tglb: [INCOMPLETE][119] ([i915#7248]) -> [WARN][120] ([i915#2658]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-tglb6/igt@gem_pread@exhaustion.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-tglb7/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: [WARN][121] ([i915#2658]) -> [INCOMPLETE][122] ([i915#7248])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-glk6/igt@gem_pwrite@basic-exhaustion.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-glk1/igt@gem_pwrite@basic-exhaustion.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][123] ([i915#2920]) -> [SKIP][124] ([i915#658])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][125] ([i915#658]) -> [SKIP][126] ([i915#2920])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][127], [FAIL][128]) ([i915#3002] / [i915#4312]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#180] / [i915#3002] / [i915#4312])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12462/shard-apl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl7/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl8/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/shard-apl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7233]: https://gitlab.freedesktop.org/drm/intel/issues/7233
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318
[i915#7404]: https://gitlab.freedesktop.org/drm/intel/issues/7404
[i915#7413]: https://gitlab.freedesktop.org/drm/intel/issues/7413
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12462 -> Patchwork_107550v8
CI-20190529: 20190529
CI_DRM_12462: 00b10bdfd8b9edc9b2c681d806fbb6ae2e5f31a3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7078: 71bce31c26998d5d53cff3138049261fd6c4fbaf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107550v8: 00b10bdfd8b9edc9b2c681d806fbb6ae2e5f31a3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v8/index.html
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