* [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout
@ 2023-07-13 6:29 Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
` (10 more replies)
0 siblings, 11 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
Up until now we only verified one or two of the dsc pps
params like bits_per_component and bits_per_pixel this
patch series aim to readout almost all PPS param and get
them compared.
Along with that some work on making a common function to
read and write PPS param regiters is also done.
--v2
-Remove duplicated code and create function that fetches register
and reuse that [Jani]
-move WARN_ON one abstraction layer up [Jani]
-Split patch so that refactor and a new functionality is not added
in the same patch [Jani]
-Add a new refactor patch so that bit shifting can be done in a
clean way [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (6):
drm/i915/vdsc: Refactor dsc register field macro
drm/i915/vdsc: Add a check for dsc split cases
drm/i915/vdsc: Add function to read any PPS register
drm/i915/vdsc: Add function to write in PPS register
drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
drm/i915/display: Compare the readout dsc pps params
drivers/gpu/drm/i915/display/intel_display.c | 31 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 622 ++++++++++--------
.../gpu/drm/i915/display/intel_vdsc_regs.h | 101 ++-
3 files changed, 463 insertions(+), 291 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 1/6] drm/i915/vdsc: Refactor dsc register field macro
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
` (9 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_vdsc_regs.h | 98 +++++++++++++------
1 file changed, 70 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index b71f00b5c761..8945eb1d493a 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -57,7 +57,8 @@
#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
-#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
+#define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27)
+#define DSC_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
@@ -69,8 +70,10 @@
#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
-#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
-#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
+#define DSC_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
+#define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0)
+#define DSC_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
+#define DSC_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
/* Icelake Display Stream Compression Registers */
#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
@@ -123,8 +126,10 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
-#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
-#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
+#define DSC_PIC_WIDTH_MASK REG_GENMASK(31, 16)
+#define DSC_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define DSC_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
+#define DSC_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
@@ -138,8 +143,10 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
-#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
-#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
+#define DSC_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
+#define DSC_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
+#define DSC_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
+#define DSC_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
@@ -153,8 +160,12 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
-#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
-#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
+#define DSC_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16)
+#define DSC_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0)
+#define DSC_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
+ dec_delay)
+#define DSC_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
+ xmit_delay)
#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
@@ -168,8 +179,10 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
-#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
-#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
+#define DSC_SCALE_DEC_INT_MASK REG_GENMASK(27, 16)
+#define DSC_SCALE_INC_INT_MASK REG_GENMASK(15, 0)
+#define DSC_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
+#define DSC_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
@@ -183,10 +196,16 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
-#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
-#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
-#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
-#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
+#define DSC_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24)
+#define DSC_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16)
+#define DSC_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8)
+#define DSC_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0)
+#define DSC_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
+#define DSC_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
+#define DSC_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
+ offset)
+#define DSC_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
+ value)
#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
@@ -200,8 +219,11 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
-#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
-#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
+#define DSC_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
+#define DSC_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0)
+#define DSC_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
+#define DSC_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
+ bpg_offset)
#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
@@ -215,8 +237,12 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
-#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
-#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
+#define DSC_INITIAL_OFFSET_MASK REG_GENMASK(31, 16)
+#define DSC_FINAL_OFFSET_MASK REG_GENMASK(15, 0)
+#define DSC_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
+ initial_offset)
+#define DSC_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
+ final_offset)
#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
@@ -230,8 +256,12 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
-#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
-#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
+#define DSC_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16)
+#define DSC_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0)
+#define DSC_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
+ rc_edge_fact)
+#define DSC_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
+ rc_model_size)
#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
@@ -245,10 +275,16 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
-#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
-#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
-#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
-#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
+#define DSC_RC_TARGET_OFF_LOW_MASK REG_GENMASK(23, 20)
+#define DSC_RC_TARGET_OFF_HIGH_MASK REG_GENMASK(19, 16)
+#define DSC_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8)
+#define DSC_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0)
+#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_RC_TARGET_OFF_LOW_MASK, \
+ rc_tgt_off_low)
+#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_RC_TARGET_OFF_HIGH_MASK, \
+ rc_tgt_off_high)
+#define DSC_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
+#define DSC_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
@@ -327,9 +363,15 @@
#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
-#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
-#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
-#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
+#define DSC_SLICE_ROW_PER_FRAME_MASK REG_GENMASK(31, 20)
+#define DSC_SLICE_PER_LINE_MASK REG_GENMASK(18, 16)
+#define DSC_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0)
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_SLICE_ROW_PER_FRAME_MASK, \
+ slice_row_per_frame)
+#define DSC_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
+ slice_per_line)
+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
+ slice_chunk_size)
/* Icelake Rate Control Buffer Threshold Registers */
#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 12:29 ` Jani Nikula
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
` (8 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 530f3c08a172..d48b8306bfc3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -939,7 +939,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
- u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
+ u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
if (!intel_dsc_source_support(crtc_state))
return;
@@ -965,11 +965,24 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
/* PPS0 & PPS1 */
if (!is_pipe_dsc(crtc, cpu_transcoder)) {
pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+ if (crtc_state->dsc.dsc_split) {
+ pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
+ drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+ }
+
} else {
pps0 = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
pps1 = intel_de_read(dev_priv,
ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+ if (crtc_state->dsc.dsc_split) {
+ pps_temp0 = intel_de_read(dev_priv,
+ ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
+ pps_temp1 = intel_de_read(dev_priv,
+ ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+ drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
+ drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+ }
}
vdsc_cfg->bits_per_pixel = pps1;
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 12:38 ` Jani Nikula
2023-07-13 12:47 ` Jani Nikula
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/vdsc: Add function to write in " Suraj Kandpal
` (7 subsequent siblings)
10 siblings, 2 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.
--v2
-Changes in read function as PPS enum is removed
-Initialize pps_val as 0 in pps_read func itself [Jani]
-Create a function that gets the required register and call that
in the common read function [Jani]
-Move the drm_WARN_ON one abstraction layer above [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 276 +++++++++++++++++++---
1 file changed, 242 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d48b8306bfc3..48273a3618c5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
return num_vdsc_instances;
}
+static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
+ int dsc_eng_no, i915_reg_t *dsc_reg)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ bool pipe_dsc;
+
+ pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
+
+ switch (pps) {
+ case 0:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_0;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_0;
+ }
+ break;
+ case 1:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_1;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_1;
+ }
+ break;
+ case 2:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_2;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_2;
+ }
+ break;
+ case 3:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_3;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_3;
+ }
+ break;
+ case 4:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_4;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_4;
+ }
+ break;
+ case 5:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_5;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_5;
+ }
+ break;
+ case 6:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_6;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_6;
+ }
+ break;
+ case 7:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_7;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_7;
+ }
+ break;
+ case 8:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_8;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_8;
+ }
+ break;
+ case 9:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_9;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_9;
+ }
+ break;
+ case 10:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_10;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_10;
+ }
+ break;
+ case 16:
+ if (pipe_dsc) {
+ if (dsc_eng_no == 2)
+ *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
+ else
+ *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
+ } else {
+ if (dsc_eng_no == 2)
+ *dsc_reg = DSCA_PICTURE_PARAMETER_SET_16;
+ else
+ *dsc_reg = DSCC_PICTURE_PARAMETER_SET_16;
+ }
+ break;
+ /*
+ * Since PPS_17 and PPS_18 were introduced from MTL dsc check
+ * need not be done
+ */
+ case 17:
+ if (dsc_eng_no == 2)
+ *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
+ else
+ *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
+ break;
+ case 18:
+ if (dsc_eng_no == 2)
+ *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
+ else
+ *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
+ break;
+ default:
+ drm_err(&i915->drm, "PPS register does not exist\n");
+ break;
+ }
+}
+
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
}
}
+static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
+ int pps, u32 *pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ i915_reg_t dsc_reg;
+ u32 pps_temp;
+
+ *pps_val = 0;
+
+ intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
+ *pps_val = intel_de_read(i915, dsc_reg);
+ if (num_vdsc_instances > 1) {
+ intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
+ pps_temp = intel_de_read(i915, dsc_reg);
+ if (*pps_val != pps_temp)
+ return true;
+ }
+ return false;
+}
+
+static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
+ int pps, u32 *pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ bool is_dsc_diff;
+
+ is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+ drm_WARN_ON(&i915->drm, is_dsc_diff);
+}
+
+static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
+{
+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ u32 pps_temp1, pps_temp2;
+
+ /* Readout PPS_0 and PPS_1 registers */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+
+ vdsc_cfg->bits_per_pixel = pps_temp2;
+
+ if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+ vdsc_cfg->bits_per_pixel >>= 1;
+
+ crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+}
+
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- enum pipe pipe = crtc->pipe;
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
- u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
+ u32 dss_ctl1, dss_ctl2;
if (!intel_dsc_source_support(crtc_state))
return;
@@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
(dss_ctl1 & JOINER_ENABLE);
- /* FIXME: add more state readout as needed */
-
- /* PPS0 & PPS1 */
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
- if (crtc_state->dsc.dsc_split) {
- pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
- drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
- }
-
- } else {
- pps0 = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
- pps1 = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
- if (crtc_state->dsc.dsc_split) {
- pps_temp0 = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
- pps_temp1 = intel_de_read(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
- drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
- drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
- }
- }
-
- vdsc_cfg->bits_per_pixel = pps1;
-
- if (pps0 & DSC_NATIVE_420_ENABLE)
- vdsc_cfg->bits_per_pixel >>= 1;
-
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+ intel_dsc_get_pps_config(crtc_state);
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 4/6] drm/i915/vdsc: Add function to write in PPS register
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (2 preceding siblings ...)
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
` (6 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.
--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 274 +++-------------------
1 file changed, 31 insertions(+), 243 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 48273a3618c5..9d885fce9428 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -303,7 +303,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
return num_vdsc_instances;
}
-static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
+static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
int dsc_eng_no, i915_reg_t *dsc_reg)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -493,6 +493,22 @@ static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
}
}
+static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
+ int pps, u32 pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ i915_reg_t dsc_reg;
+
+ intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
+ intel_de_write(i915, dsc_reg, pps_val);
+ if (num_vdsc_instances > 1) {
+ intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
+ intel_de_write(i915, dsc_reg, pps_val);
+ }
+}
+
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -527,149 +543,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_VBR_ENABLE;
drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
/* Populate PICTURE_PARAMETER_SET_1 registers */
pps_val = 0;
pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
/* Populate PICTURE_PARAMETER_SET_2 registers */
pps_val = 0;
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 2, pps_val);
/* Populate PICTURE_PARAMETER_SET_3 registers */
pps_val = 0;
pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 3, pps_val);
/* Populate PICTURE_PARAMETER_SET_4 registers */
pps_val = 0;
pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 4, pps_val);
/* Populate PICTURE_PARAMETER_SET_5 registers */
pps_val = 0;
pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 5, pps_val);
/* Populate PICTURE_PARAMETER_SET_6 registers */
pps_val = 0;
@@ -678,100 +586,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 6, pps_val);
/* Populate PICTURE_PARAMETER_SET_7 registers */
pps_val = 0;
pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 7, pps_val);
/* Populate PICTURE_PARAMETER_SET_8 registers */
pps_val = 0;
pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 8, pps_val);
/* Populate PICTURE_PARAMETER_SET_9 registers */
pps_val = 0;
pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 9, pps_val);
/* Populate PICTURE_PARAMETER_SET_10 registers */
pps_val = 0;
@@ -780,25 +616,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- DSCC_PICTURE_PARAMETER_SET_10, pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 10, pps_val);
/* Populate Picture parameter set 16 */
pps_val = 0;
@@ -808,51 +626,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- DSCC_PICTURE_PARAMETER_SET_16, pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 16, pps_val);
if (DISPLAY_VER(dev_priv) >= 14) {
/* Populate PICTURE_PARAMETER_SET_17 registers */
pps_val = 0;
pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
- intel_de_write(dev_priv,
- MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
- pps_val);
+ intel_dsc_write_pps_reg(crtc_state, 17, pps_val);
/* Populate PICTURE_PARAMETER_SET_18 registers */
pps_val = 0;
pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
- intel_de_write(dev_priv,
- MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
- pps_val);
+ intel_dsc_write_pps_reg(crtc_state, 18, pps_val);
}
/* Populate the RC_BUF_THRESH registers */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 5/6] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (3 preceding siblings ...)
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/vdsc: Add function to write in " Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
` (5 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.
--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 99 +++++++++++++++++--
.../gpu/drm/i915/display/intel_vdsc_regs.h | 3 +
2 files changed, 96 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9d885fce9428..29978fca8d97 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -944,18 +944,105 @@ static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_stat
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- u32 pps_temp1, pps_temp2;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ u32 pps_temp;
+
+ /* PPS_0 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
- /* Readout PPS_0 and PPS_1 registers */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
- intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+ vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
+ vdsc_cfg->line_buf_depth =
+ (pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;
+ vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
+ vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
+ vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
+ vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
+ vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
+ vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
- vdsc_cfg->bits_per_pixel = pps_temp2;
+ /* PPS_1 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
- if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+ vdsc_cfg->bits_per_pixel = pps_temp;
+
+ if (vdsc_cfg->native_420)
vdsc_cfg->bits_per_pixel >>= 1;
crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+
+ /* PPS_2 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
+
+ vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp);
+ vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
+
+ /* PPS_3 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
+
+ vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
+ vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
+
+ /* PPS_4 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
+
+ vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
+ vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
+
+ /* PPS_5 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
+
+ vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
+ vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
+
+ /* PPS_6 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
+
+ vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
+ vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
+ vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
+ vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
+
+ /* PPS_7 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
+
+ vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
+ vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
+
+ /* PPS_8 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
+
+ vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
+ vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
+
+ /* PPS_9 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
+
+ vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
+
+ /* PPS_10 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
+
+ vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
+ vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
+
+ /* PPS_16 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
+
+ vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
+
+ if (DISPLAY_VER(i915) >= 14) {
+ /* PPS_17 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
+
+ vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
+
+ /* PPS_18 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
+
+ vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
+ vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
+ }
}
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 8945eb1d493a..8605d36253ab 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -99,6 +99,9 @@
#define DSC_BPC_SHIFT 8
#define DSC_VER_MIN_SHIFT 4
#define DSC_VER_MAJ (0x1 << 0)
+#define DSC_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
+#define DSC_BPC_MASK REG_GENMASK(11, 8)
+
#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Compare the readout dsc pps params
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (4 preceding siblings ...)
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
@ 2023-07-13 6:29 ` Suraj Kandpal
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev2) Patchwork
` (4 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Suraj Kandpal @ 2023-07-13 6:29 UTC (permalink / raw)
To: intel-gfx
With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.
--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..9c407ceb082e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5376,6 +5376,37 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(master_transcoder);
PIPE_CONF_CHECK_X(bigjoiner_pipes);
+ PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
+ PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
+ PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
+ PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
+ PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
+ PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
+ PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
+ PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
+ PIPE_CONF_CHECK_I(dsc.config.pic_width);
+ PIPE_CONF_CHECK_I(dsc.config.pic_height);
+ PIPE_CONF_CHECK_I(dsc.config.slice_width);
+ PIPE_CONF_CHECK_I(dsc.config.slice_height);
+ PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
+ PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
+ PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
+ PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
+ PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
+ PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
+ PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
+ PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
+ PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
+ PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
+ PIPE_CONF_CHECK_I(dsc.config.initial_offset);
+ PIPE_CONF_CHECK_I(dsc.config.final_offset);
+ PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
+ PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
+ PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
+ PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
+ PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
+ PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
+
PIPE_CONF_CHECK_I(dsc.compression_enable);
PIPE_CONF_CHECK_I(dsc.dsc_split);
PIPE_CONF_CHECK_I(dsc.compressed_bpp);
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev2)
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (5 preceding siblings ...)
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
@ 2023-07-13 9:36 ` Patchwork
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-13 9:36 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim checkpatch failed
522b07084859 drm/i915/vdsc: Refactor dsc register field macro
-:174: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:284:
+#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_RC_TARGET_OFF_HIGH_MASK, \
-:191: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#191: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:369:
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_SLICE_ROW_PER_FRAME_MASK, \
total: 0 errors, 2 warnings, 0 checks, 170 lines checked
f292bef24a4f drm/i915/vdsc: Add a check for dsc split cases
3d1649bffa43 drm/i915/vdsc: Add function to read any PPS register
56955c412ac8 drm/i915/vdsc: Add function to write in PPS register
4783180b2833 drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
6b6e60445265 drm/i915/display: Compare the readout dsc pps params
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC PPS readout (rev2)
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (6 preceding siblings ...)
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev2) Patchwork
@ 2023-07-13 9:36 ` Patchwork
2023-07-13 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-13 9:36 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:17: warning: unreplaced symbol 'encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:9: warning: unreplaced symbol 'break'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:9: warning: unreplaced symbol 'case'
+drivers/gpu/drm/i915/display/intel_display_types.h:1885:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1885:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1886:9: warning: too many warnings
+drivers/gpu/drm/i915/display/intel_display_types.h:1886:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1887:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1888:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1889:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1890:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1891:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1910:9: warning: unreplaced symbol 'intel_encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1957:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1957:24: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC PPS readout (rev2)
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (7 preceding siblings ...)
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-13 9:49 ` Patchwork
2023-07-13 12:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-13 13:15 ` [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Jani Nikula
10 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-13 9:49 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 49953 bytes --]
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13380 -> Patchwork_120456v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/index.html
Participating hosts (18 -> 41)
------------------------------
Additional (23): fi-kbl-soraka fi-rkl-11600 fi-apl-guc bat-rpls-1 fi-blb-e6850 bat-adlm-1 bat-dg2-9 fi-ilk-650 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-skl-guc fi-glk-j4005 bat-jsl-1 bat-mtlp-8 bat-mtlp-6 bat-adlp-11 fi-tgl-1115g4 fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_120456v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- bat-adlp-11: NOTRUN -> [ABORT][1] ([i915#8011])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlp-11/igt@core_auth@basic-auth.html
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][2] ([i915#8298])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@core_hotunplug@unbind-rebind.html
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#7456])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#7456])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@debugfs_test@basic-hwmon.html
- bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#7456])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#7456])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@debugfs_test@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#7456])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#7456])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
- bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#7456])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@debugfs_test@basic-hwmon.html
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#7456])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@eof:
- bat-adlm-1: NOTRUN -> [SKIP][11] ([i915#2582]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@fbdev@eof.html
* igt@fbdev@info:
- bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#1849] / [i915#2582])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@fbdev@info.html
- fi-kbl-x1275: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1849])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-x1275/igt@fbdev@info.html
- fi-kbl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1849])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-guc/igt@fbdev@info.html
- bat-rpls-1: NOTRUN -> [SKIP][15] ([i915#1849] / [i915#2582])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@fbdev@info.html
- fi-kbl-8809g: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1849])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@fbdev@info.html
- bat-adlm-1: NOTRUN -> [SKIP][17] ([i915#1849] / [i915#2582])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@fbdev@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#1849] / [i915#2582])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@nullptr:
- bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#2582]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@fbdev@nullptr.html
* igt@fbdev@write:
- bat-rpls-1: NOTRUN -> [SKIP][20] ([i915#2582]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@fbdev@write.html
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#2582]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_exec_suspend@basic-s0@smem:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][22] ([i915#8841]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][23] ([i915#8504] / [i915#8841])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@gem_exec_suspend@basic-s3@lmem0.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2190])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#2190])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][26] ([i915#2190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
- bat-jsl-1: NOTRUN -> [SKIP][27] ([i915#2190])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
- fi-rkl-11600: NOTRUN -> [SKIP][28] ([i915#2190])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
- bat-jsl-3: NOTRUN -> [SKIP][29] ([i915#2190])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#2190])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2190])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2190])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#4613]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html
- bat-jsl-3: NOTRUN -> [SKIP][34] ([i915#4613]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@gem_lmem_swapping@basic.html
- fi-glk-j4005: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#4613]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-glk-j4005/igt@gem_lmem_swapping@basic.html
- fi-skl-guc: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#4613]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-skl-guc/igt@gem_lmem_swapping@basic.html
- fi-kbl-soraka: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#4613]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
- fi-kbl-8809g: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#4613]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][39] ([i915#4613]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-rkl-11600: NOTRUN -> [SKIP][40] ([i915#4613]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][41] ([i915#4613]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- bat-rpls-1: NOTRUN -> [SKIP][42] ([i915#4613]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-guc: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#4613]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-guc/igt@gem_lmem_swapping@verify-random.html
- bat-mtlp-6: NOTRUN -> [SKIP][44] ([i915#4613]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-x1275: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#4613]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-x1275/igt@gem_lmem_swapping@verify-random.html
- fi-cfl-8109u: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#4613]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
- bat-mtlp-8: NOTRUN -> [SKIP][47] ([i915#4613]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
- fi-kbl-guc: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#4613]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-guc/igt@gem_lmem_swapping@verify-random.html
- bat-jsl-1: NOTRUN -> [SKIP][49] ([i915#4613]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][50] ([i915#4083])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@gem_mmap@basic.html
- bat-dg2-9: NOTRUN -> [SKIP][51] ([i915#4083])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][52] ([i915#4083])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@gem_mmap@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][53] ([i915#4083])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][54] ([i915#4077]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][55] ([i915#4077]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][56] ([i915#4079]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][57] ([i915#4079]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][58] ([i915#4077]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-atsm-1: NOTRUN -> [SKIP][59] ([i915#4077]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][60] ([i915#3282])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- bat-atsm-1: NOTRUN -> [SKIP][61] ([i915#4079]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@gem_tiled_pread_basic.html
- bat-adlm-1: NOTRUN -> [SKIP][62] ([i915#3282])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@gem_tiled_pread_basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][63] ([i915#4079]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html
- bat-rpls-1: NOTRUN -> [SKIP][64] ([i915#3282])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@load:
- bat-adlp-11: NOTRUN -> [DMESG-WARN][65] ([i915#4423])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlp-11/igt@i915_module_load@load.html
* igt@i915_pm_backlight@basic-brightness:
- bat-adlm-1: NOTRUN -> [SKIP][66] ([i915#7561])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@i915_pm_backlight@basic-brightness.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][67] ([i915#3546] / [i915#7561])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
- bat-rpls-1: NOTRUN -> [SKIP][68] ([i915#7561])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@i915_pm_backlight@basic-brightness.html
- bat-mtlp-6: NOTRUN -> [SKIP][69] ([i915#3546])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@i915_pm_backlight@basic-brightness.html
- fi-rkl-11600: NOTRUN -> [SKIP][70] ([i915#7561])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
- bat-dg2-9: NOTRUN -> [SKIP][71] ([i915#5354] / [i915#7561])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: NOTRUN -> [SKIP][72] ([fdo#109271]) +34 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-cfl-8700k: [PASS][73] -> [FAIL][74] ([i915#7940])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-guc: NOTRUN -> [FAIL][75] ([i915#7940]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-kbl-8809g: NOTRUN -> [FAIL][76] ([i915#8843])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html
- fi-kbl-guc: NOTRUN -> [FAIL][77] ([i915#7940])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-skl-guc: NOTRUN -> [FAIL][78] ([i915#7940]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][79] ([fdo#109271]) +38 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-blb-e6850/igt@i915_pm_rpm@module-reload.html
- fi-rkl-11600: NOTRUN -> [FAIL][80] ([i915#7940])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
- fi-cfl-8109u: NOTRUN -> [FAIL][81] ([i915#7940])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][82] ([i915#7940])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][83] ([i915#6621])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@i915_pm_rps@basic-api.html
- bat-dg2-9: NOTRUN -> [SKIP][84] ([i915#6621])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][85] ([i915#6621])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-adlm-1: NOTRUN -> [SKIP][86] ([i915#6621])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@i915_pm_rps@basic-api.html
- bat-rpls-1: NOTRUN -> [SKIP][87] ([i915#6621])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@i915_pm_rps@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][88] ([i915#6621])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: NOTRUN -> [DMESG-FAIL][89] ([i915#7059])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
- bat-mtlp-6: NOTRUN -> [DMESG-FAIL][90] ([i915#7059])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][91] ([i915#1886] / [i915#7913])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [PASS][92] -> [ABORT][93] ([i915#7913])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-11/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][94] ([i915#6367])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-ivb-3770: NOTRUN -> [DMESG-WARN][95] ([i915#8841]) +6 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-ivb-3770/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][96] ([i915#7443] / [i915#8102])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
- bat-atsm-1: NOTRUN -> [SKIP][97] ([i915#6645])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html
- bat-mtlp-6: NOTRUN -> [SKIP][98] ([i915#6645])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][99] ([i915#6645])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
- bat-rpls-1: NOTRUN -> [ABORT][100] ([i915#6687] / [i915#7978] / [i915#8668])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][101] ([i915#4212]) +8 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][102] ([i915#5190])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][103] ([i915#5190])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][104] ([i915#5190])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][105] ([i915#4215] / [i915#5190])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][106] ([i915#4212]) +8 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][107] ([i915#4212]) +7 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@size-max:
- bat-atsm-1: NOTRUN -> [SKIP][108] ([i915#6077]) +36 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_addfb_basic@size-max.html
* igt@kms_addfb_basic@too-high:
- fi-kbl-8809g: NOTRUN -> [FAIL][109] ([i915#8296]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html
* igt@kms_chamelium_edid@dp-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][110] ([fdo#109271]) +29 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-ilk-650/igt@kms_chamelium_edid@dp-edid-read.html
- bat-jsl-1: NOTRUN -> [SKIP][111] ([i915#7828]) +8 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@kms_chamelium_edid@dp-edid-read.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][112] ([i915#7828]) +7 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- fi-cfl-guc: NOTRUN -> [SKIP][113] ([fdo#109271]) +18 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-guc/igt@kms_chamelium_edid@hdmi-edid-read.html
- bat-mtlp-6: NOTRUN -> [SKIP][114] ([i915#7828]) +8 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_chamelium_edid@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-crc-fast:
- bat-adlm-1: NOTRUN -> [SKIP][115] ([i915#7828]) +8 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][116] ([fdo#109271]) +15 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
- fi-cfl-8109u: NOTRUN -> [SKIP][117] ([fdo#109271]) +18 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8109u/igt@kms_chamelium_frames@hdmi-crc-fast.html
- bat-mtlp-8: NOTRUN -> [SKIP][118] ([i915#7828]) +8 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][119] ([i915#7828])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][120] ([i915#7828]) +8 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- bat-rpls-1: NOTRUN -> [SKIP][121] ([i915#7828]) +7 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- fi-apl-guc: NOTRUN -> [SKIP][122] ([fdo#109271]) +22 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-apl-guc/igt@kms_chamelium_hpd@vga-hpd-fast.html
- bat-jsl-3: NOTRUN -> [SKIP][123] ([i915#7828]) +8 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@kms_chamelium_hpd@vga-hpd-fast.html
- bat-dg2-9: NOTRUN -> [SKIP][124] ([i915#7828]) +8 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: NOTRUN -> [SKIP][125] ([fdo#109271]) +18 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-glk-j4005/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][126] ([i915#4103]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-rkl-11600: NOTRUN -> [SKIP][127] ([i915#4103]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-3: NOTRUN -> [SKIP][128] ([i915#4103]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][129] ([i915#4213]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][130] ([i915#4103]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- bat-atsm-1: NOTRUN -> [SKIP][131] ([i915#6078]) +19 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
- bat-dg2-9: NOTRUN -> [SKIP][132] ([i915#1845] / [i915#5354]) +13 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-rpls-1: NOTRUN -> [SKIP][133] ([i915#1845]) +14 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
- bat-mtlp-6: NOTRUN -> [SKIP][134] ([i915#1845]) +10 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- bat-adlm-1: NOTRUN -> [SKIP][135] ([i915#1845]) +15 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#1845]) +8 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-guc/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][137] ([i915#3637]) +3 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
- bat-dg2-9: NOTRUN -> [SKIP][138] ([i915#4098] / [i915#5354]) +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_flip@basic-flip-vs-modeset:
- bat-rpls-1: NOTRUN -> [SKIP][139] ([i915#3637]) +3 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_flip@basic-plain-flip:
- bat-atsm-1: NOTRUN -> [SKIP][140] ([i915#6166]) +3 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_flip@basic-plain-flip.html
- bat-adlm-1: NOTRUN -> [SKIP][141] ([i915#3637]) +3 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_flip@basic-plain-flip.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][142] ([i915#8299])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-8809g: NOTRUN -> [CRASH][143] ([i915#8299])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][144] ([fdo#109285])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-11600: NOTRUN -> [SKIP][145] ([fdo#109285] / [i915#4098])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][146] ([fdo#109285])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-6: NOTRUN -> [SKIP][147] ([fdo#109285])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-3: NOTRUN -> [SKIP][148] ([fdo#109285])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-9: NOTRUN -> [SKIP][149] ([fdo#109285])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][150] ([fdo#109285])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][151] ([fdo#109285])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
- bat-rpls-1: NOTRUN -> [SKIP][152] ([fdo#109285])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-atsm-1: NOTRUN -> [SKIP][153] ([i915#6093]) +3 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-dg2-9: NOTRUN -> [SKIP][154] ([i915#5274])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][155] ([i915#5274])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-6: NOTRUN -> [SKIP][156] ([i915#5274])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][157] ([i915#1849])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_frontbuffer_tracking@basic.html
- bat-rpls-1: NOTRUN -> [SKIP][158] ([i915#1849])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_frontbuffer_tracking@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][159] ([i915#4342])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12:
- bat-dg2-9: NOTRUN -> [SKIP][160] ([i915#5354]) +2 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-2:
- fi-skl-guc: NOTRUN -> [SKIP][161] ([fdo#109271]) +20 similar issues
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-2.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-atsm-1: NOTRUN -> [SKIP][162] ([i915#1836]) +6 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_pipe_crc_basic@read-crc:
- fi-kbl-x1275: NOTRUN -> [SKIP][163] ([fdo#109271]) +43 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-mtlp-6: NOTRUN -> [SKIP][164] ([i915#1845] / [i915#4078]) +4 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
- bat-rpls-2: NOTRUN -> [SKIP][165] ([i915#1845])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_prop_blob@basic:
- bat-atsm-1: NOTRUN -> [SKIP][166] ([i915#7357])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_prop_blob@basic.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][167] ([fdo#109271]) +62 similar issues
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
- fi-ivb-3770: NOTRUN -> [SKIP][168] ([fdo#109271]) +27 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-ivb-3770/igt@kms_psr@cursor_plane_move.html
- bat-adlm-1: NOTRUN -> [SKIP][169] ([i915#1072]) +3 similar issues
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_psr@cursor_plane_move.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][170] ([fdo#110189]) +3 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@kms_psr@cursor_plane_move.html
- bat-rpls-1: NOTRUN -> [SKIP][171] ([i915#1072]) +3 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_psr@cursor_plane_move.html
- bat-mtlp-6: NOTRUN -> [SKIP][172] ([i915#1072]) +3 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: NOTRUN -> [SKIP][173] ([i915#1072]) +1 similar issue
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rplp-1/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][174] ([i915#1072]) +3 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
- bat-atsm-1: NOTRUN -> [SKIP][175] ([i915#1072]) +3 similar issues
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html
- bat-dg2-9: NOTRUN -> [SKIP][176] ([i915#1072]) +3 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html
- bat-rplp-1: NOTRUN -> [ABORT][177] ([i915#8442] / [i915#8668] / [i915#8712])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][178] ([i915#3555] / [i915#4098])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
- bat-atsm-1: NOTRUN -> [SKIP][179] ([i915#6094])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-3: NOTRUN -> [SKIP][180] ([i915#3555])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-9: NOTRUN -> [SKIP][181] ([i915#3555])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][182] ([i915#8809])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlm-1: NOTRUN -> [SKIP][183] ([i915#3555])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-1: NOTRUN -> [SKIP][184] ([i915#3555])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][185] ([i915#3555])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
- bat-rpls-1: NOTRUN -> [SKIP][186] ([i915#3555])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-6: NOTRUN -> [SKIP][187] ([i915#8809])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-atsm-1: NOTRUN -> [SKIP][188] ([fdo#109295] / [i915#6078])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html
- bat-dg2-9: NOTRUN -> [SKIP][189] ([i915#3708] / [i915#5354])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
- bat-adlm-1: NOTRUN -> [SKIP][190] ([i915#1845] / [i915#3708])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@prime_vgem@basic-fence-flip.html
- bat-rpls-1: NOTRUN -> [SKIP][191] ([fdo#109295] / [i915#1845] / [i915#3708])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@prime_vgem@basic-fence-flip.html
- bat-mtlp-6: NOTRUN -> [SKIP][192] ([i915#1845] / [i915#3708])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-atsm-1: NOTRUN -> [SKIP][193] ([fdo#109295] / [i915#4077]) +1 similar issue
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-6: NOTRUN -> [SKIP][194] ([i915#3708] / [i915#4077]) +1 similar issue
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
- bat-dg2-9: NOTRUN -> [SKIP][195] ([i915#3708] / [i915#4077]) +1 similar issue
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][196] ([i915#3708] / [i915#4077]) +1 similar issue
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][197] ([i915#3708]) +2 similar issues
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][198] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-atsm-1: NOTRUN -> [SKIP][199] ([fdo#109295]) +2 similar issues
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-atsm-1/igt@prime_vgem@basic-write.html
- bat-dg2-9: NOTRUN -> [SKIP][200] ([i915#3291] / [i915#3708]) +2 similar issues
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-dg2-9/igt@prime_vgem@basic-write.html
- bat-adlm-1: NOTRUN -> [SKIP][201] ([i915#3708]) +2 similar issues
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-adlm-1/igt@prime_vgem@basic-write.html
- bat-rpls-1: NOTRUN -> [SKIP][202] ([fdo#109295] / [i915#3708]) +2 similar issues
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-1/igt@prime_vgem@basic-write.html
- bat-mtlp-6: NOTRUN -> [SKIP][203] ([i915#3708]) +2 similar issues
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-mtlp-6/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8700k: [FAIL][204] ([i915#7940]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/fi-cfl-8700k/igt@i915_pm_rpm@module-reload.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/fi-cfl-8700k/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][206] ([i915#4983] / [i915#7913]) -> [PASS][207]
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/bat-rpls-2/igt@i915_selftest@live@requests.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][208] ([i915#8442] / [i915#8668]) -> [PASS][209]
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
[i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
[i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8296]: https://gitlab.freedesktop.org/drm/intel/issues/8296
[i915#8298]: https://gitlab.freedesktop.org/drm/intel/issues/8298
[i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8504]: https://gitlab.freedesktop.org/drm/intel/issues/8504
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843
Build changes
-------------
* Linux: CI_DRM_13380 -> Patchwork_120456v2
CI-20190529: 20190529
CI_DRM_13380: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7383: e9d66ac434bd580af20b475ddbee01f5c042ed61 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120456v2: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
17514812a517 drm/i915/display: Compare the readout dsc pps params
79f6128079f7 drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
e59243479423 drm/i915/vdsc: Add function to write in PPS register
90ed61aa9ddc drm/i915/vdsc: Add function to read any PPS register
8ea2bd7b2554 drm/i915/vdsc: Add a check for dsc split cases
924f25c0a2a8 drm/i915/vdsc: Refactor dsc register field macro
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/index.html
[-- Attachment #2: Type: text/html, Size: 67128 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
@ 2023-07-13 12:29 ` Jani Nikula
2023-07-13 13:03 ` Kandpal, Suraj
0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2023-07-13 12:29 UTC (permalink / raw)
To: Suraj Kandpal, intel-gfx
On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> In intel_vdsc_get_config we only read the primary dsc engine register
> and not take into account if the other dsc engine is in use and if
> both registers have the same value or not this patche fixes that by
> adding a check.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 530f3c08a172..d48b8306bfc3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -939,7 +939,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> enum pipe pipe = crtc->pipe;
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
> + u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
>
> if (!intel_dsc_source_support(crtc_state))
> return;
> @@ -965,11 +965,24 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> /* PPS0 & PPS1 */
> if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> + if (crtc_state->dsc.dsc_split) {
> + pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
> + drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> + }
> +
Superfluous newline.
> } else {
> pps0 = intel_de_read(dev_priv,
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> pps1 = intel_de_read(dev_priv,
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> + if (crtc_state->dsc.dsc_split) {
> + pps_temp0 = intel_de_read(dev_priv,
> + ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> + pps_temp1 = intel_de_read(dev_priv,
> + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
Those are the same two registers as above?
BR,
Jani.
> + drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
> + drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> + }
> }
>
> vdsc_cfg->bits_per_pixel = pps1;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Add DSC PPS readout (rev2)
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (8 preceding siblings ...)
2023-07-13 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-07-13 12:30 ` Patchwork
2023-07-13 13:15 ` [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Jani Nikula
10 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-13 12:30 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
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== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13380_full -> Patchwork_120456v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_120456v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_120456v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 11)
------------------------------
Additional (1): pig-kbl-iris
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_120456v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-panning-vs-hang@a-edp1:
- shard-mtlp: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@kms_flip@flip-vs-panning-vs-hang@a-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@kms_flip@flip-vs-panning-vs-hang@a-edp1.html
New tests
---------
New tests have been introduced between CI_DRM_13380_full and Patchwork_120456v2_full:
### New IGT tests (1) ###
* igt@kms_invalid_mode@int-max-clock@hdmi-a-2-pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_120456v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-rkl: NOTRUN -> [SKIP][3] ([i915#7701])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][4] -> [FAIL][5] ([i915#7742]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@drm_fdinfo@virtual-busy-all.html
* igt@feature_discovery@display-4x:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#1839])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@feature_discovery@display-4x.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#5325])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_create@hog-create@smem0:
- shard-dg2: [PASS][9] -> [FAIL][10] ([i915#5892] / [i915#8758])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-3/igt@gem_create@hog-create@smem0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-8/igt@gem_create@hog-create@smem0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][11] -> [FAIL][12] ([i915#6268])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#8555])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][14] -> [FAIL][15] ([i915#5784])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-11/igt@gem_eio@kms.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none-rrul:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4473] / [i915#4771])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_exec_fair@basic-none-rrul.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: NOTRUN -> [FAIL][17] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#3281]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-apl: [PASS][21] -> [ABORT][22] ([i915#180] / [i915#8213])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-apl6/igt@gem_exec_suspend@basic-s3@smem.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-apl4/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][23] ([i915#7975] / [i915#8213])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gem_exec_suspend@basic-s4-devices@smem.html
- shard-tglu: [PASS][24] -> [ABORT][25] ([i915#7975] / [i915#8213])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-5/igt@gem_exec_suspend@basic-s4-devices@smem.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-mtlp: NOTRUN -> [SKIP][26] ([i915#4860])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_lmem_swapping@parallel-random:
- shard-rkl: NOTRUN -> [SKIP][27] ([i915#4613])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_mmap_gtt@bad-object:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4077])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_mmap_gtt@bad-object.html
* igt@gem_mmap_gtt@basic:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#4077])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@gem_mmap_gtt@basic.html
* igt@gem_partial_pwrite_pread@reads-snoop:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3282])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gem_partial_pwrite_pread@reads-snoop.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][31] ([i915#4270])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4270]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_readwrite@write-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#3282]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#8428]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#4885])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#3297]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen7_exec_parse@basic-allowed:
- shard-mtlp: NOTRUN -> [SKIP][37] ([fdo#109289]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@gen7_exec_parse@basic-allowed.html
* igt@gen7_exec_parse@basic-offset:
- shard-rkl: NOTRUN -> [SKIP][38] ([fdo#109289])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@basic-rejected:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#2856]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#2527])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-mtlp: NOTRUN -> [SKIP][41] ([fdo#109293])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@gem-execbuf@smem0:
- shard-tglu: [PASS][42] -> [FAIL][43] ([i915#7940])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-7/igt@i915_pm_rpm@gem-execbuf@smem0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-2/igt@i915_pm_rpm@gem-execbuf@smem0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [PASS][44] -> [SKIP][45] ([i915#1397])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][46] -> [SKIP][47] ([i915#1397])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-6/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-10/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-dg2: [PASS][48] -> [FAIL][49] ([fdo#103375] / [i915#6121])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-6/igt@i915_pm_rpm@system-suspend-execbuf.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-5/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][50] -> [DMESG-FAIL][51] ([i915#5334])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- shard-mtlp: [PASS][52] -> [DMESG-WARN][53] ([i915#6367])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@i915_selftest@live@slpc.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-8/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu: NOTRUN -> [INCOMPLETE][54] ([i915#7443] / [i915#8102])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4212])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][56] ([i915#8247]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-snb: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#1769])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-snb5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#5286])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#5286])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][60] ([fdo#111614])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][61] ([fdo#111614]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [PASS][62] -> [FAIL][63] ([i915#3743])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][64] ([fdo#110723]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][65] ([fdo#111615]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][66] ([fdo#109271]) +91 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-snb5/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#6095]) +10 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][69] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#5354] / [i915#6095]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][71] ([i915#3886] / [i915#5354] / [i915#6095])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][72] ([i915#3689] / [i915#5354] / [i915#6095])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#5354]) +6 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#3886] / [i915#6095]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4087] / [i915#7213]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#7213])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4087]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-8/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#7828]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-negative:
- shard-mtlp: NOTRUN -> [SKIP][79] ([fdo#111827])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#7828]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#7828]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_color@deep-color:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#3555])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-2/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic-dpms:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#6944])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][84] ([i915#7173])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@kms_content_protection@lic@pipe-a-dp-2.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][85] ([i915#1339])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#3359])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-tglu: NOTRUN -> [SKIP][87] ([i915#3555])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][88] ([i915#3546]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: NOTRUN -> [FAIL][89] ([i915#2346])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#3555] / [i915#3840])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#3840])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][92] ([fdo#111825])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#3637]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][94] -> [FAIL][95] ([i915#2122])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@blocking-wf_vblank@a-edp1:
- shard-mtlp: [PASS][96] -> [DMESG-WARN][97] ([i915#1982])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-3/igt@kms_flip@blocking-wf_vblank@a-edp1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_flip@blocking-wf_vblank@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#2587] / [i915#2672])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#2672]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][100] ([fdo#111825] / [i915#1825]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#5354])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#3458])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#1825]) +13 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][104] ([fdo#109280])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][105] ([fdo#110189])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#3023]) +4 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#8708]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#3555] / [i915#8228])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-2/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#3555] / [i915#8228])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-8/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-suspend:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#8228])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@legacy:
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#6301])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [FAIL][112] ([i915#8292])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-2.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#5176]) +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-dp-2.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][114] ([i915#5176]) +3 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#5176]) +3 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#5235]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#5235]) +11 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#6524])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-mtlp: NOTRUN -> [SKIP][119] ([i915#5289])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][120] ([fdo#111615] / [i915#5289])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#4098])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_vblank@pipe-c-query-forked:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#4070] / [i915#6768]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_vblank@pipe-c-query-forked.html
* igt@kms_vblank@pipe-d-query-idle:
- shard-rkl: NOTRUN -> [SKIP][123] ([i915#4070] / [i915#533] / [i915#6768])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@kms_vblank@pipe-d-query-idle.html
* igt@kms_vrr@flipline:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#8808]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_vrr@flipline.html
* igt@perf_pmu@busy-idle-check-all@vcs0:
- shard-mtlp: [PASS][125] -> [FAIL][126] ([i915#4521])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-7/igt@perf_pmu@busy-idle-check-all@vcs0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-4/igt@perf_pmu@busy-idle-check-all@vcs0.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs1:
- shard-mtlp: [PASS][127] -> [FAIL][128] ([i915#6015])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html
* igt@v3d/v3d_submit_cl@multisync-out-syncs:
- shard-rkl: NOTRUN -> [SKIP][129] ([fdo#109315]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@v3d/v3d_submit_cl@multisync-out-syncs.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#2575]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#7711])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#7711])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: [FAIL][133] ([i915#7742]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-dg2: [ABORT][135] ([i915#7461] / [i915#8211] / [i915#8234]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-10/igt@gem_barrier_race@remote-request@rcs0.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-12/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [FAIL][137] ([i915#5784]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg1-14/igt@gem_eio@unwedge-stress.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg1-17/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][139] ([i915#2846]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][141] ([i915#2842]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][143] ([i915#2842]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@gem_exec_fair@basic-pace@rcs0.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [TIMEOUT][145] ([i915#8628]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-7/igt@gem_exec_whisper@basic-contexts-forked-all.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-4/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-tglu: [INCOMPLETE][147] ([i915#6755] / [i915#7392]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-9/igt@gem_exec_whisper@basic-fds-priority-all.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-3/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [DMESG-WARN][149] ([i915#7061]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-7/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [ABORT][151] ([i915#8489] / [i915#8668]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-dg1}: [SKIP][153] ([i915#1937]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][155] ([i915#1397]) -> [PASS][156] +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-1/igt@i915_pm_rpm@dpms-lpsp.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0:
- shard-tglu: [FAIL][157] ([i915#7940]) -> [PASS][158] +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-3/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-5/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][159] ([i915#5138]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][161] ([i915#72]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-mtlp: [FAIL][163] ([i915#2346]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][165] ([i915#2346]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][167] ([i915#79]) -> [PASS][168] +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][169] ([i915#8292]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-tglu-5/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-tglu-9/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][171] ([i915#7484]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-5/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][173] ([i915#4349]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@perf_pmu@most-busy-check-all@rcs0.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-4/igt@perf_pmu@most-busy-check-all@rcs0.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [FAIL][175] ([i915#6015]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
#### Warnings ####
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [DMESG-WARN][177] ([i915#4936] / [i915#5493]) -> [TIMEOUT][178] ([i915#5493])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][179] ([i915#7118] / [i915#7162]) -> [SKIP][180] ([i915#7118])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-11/igt@kms_content_protection@type1.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-3/igt@kms_content_protection@type1.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][181] ([fdo#109285]) -> [SKIP][182] ([fdo#109285] / [i915#4098])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][183] ([i915#4816]) -> [SKIP][184] ([i915#4070] / [i915#4816])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][185] ([i915#5493]) -> [CRASH][186] ([i915#7331])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-dg2-2/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [ABORT][187] ([i915#8521]) -> [TIMEOUT][188] ([i915#7947])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13380/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/shard-mtlp-2/igt@sysfs_preempt_timeout@timeout@vecs0.html
### Piglit changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- pig-kbl-iris: NOTRUN -> [FAIL][189] ([i915#5603])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/pig-kbl-iris/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4521]: https://gitlab.freedesktop.org/drm/intel/issues/4521
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5603]: https://gitlab.freedesktop.org/drm/intel/issues/5603
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7947]: https://gitlab.freedesktop.org/drm/intel/issues/7947
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758
[i915#8808]: https://gitlab.freedesktop.org/drm/intel/issues/8808
Build changes
-------------
* Linux: CI_DRM_13380 -> Patchwork_120456v2
* Piglit: None -> piglit_4509
CI-20190529: 20190529
CI_DRM_13380: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7383: e9d66ac434bd580af20b475ddbee01f5c042ed61 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120456v2: c8d8bc62e682f5a569b3ded2b80848c47eb5c425 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v2/index.html
[-- Attachment #2: Type: text/html, Size: 60750 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
@ 2023-07-13 12:38 ` Jani Nikula
2023-07-13 12:42 ` Jani Nikula
2023-07-13 12:47 ` Jani Nikula
1 sibling, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2023-07-13 12:38 UTC (permalink / raw)
To: Suraj Kandpal, intel-gfx
On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
> patches.
>
> --v2
> -Changes in read function as PPS enum is removed
> -Initialize pps_val as 0 in pps_read func itself [Jani]
> -Create a function that gets the required register and call that
> in the common read function [Jani]
> -Move the drm_WARN_ON one abstraction layer above [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 276 +++++++++++++++++++---
> 1 file changed, 242 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d48b8306bfc3..48273a3618c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
> return num_vdsc_instances;
> }
>
> +static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
> + int dsc_eng_no, i915_reg_t *dsc_reg)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + bool pipe_dsc;
> +
> + pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> +
> + switch (pps) {
> + case 0:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
What's "dsc_eng_no", and why is it 0 or 2?
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_0;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_0;
> + }
I think the branches are backwards here. Above it's DSC1, DSC0 and here
it's DSCA, DSCC.
I think I'd prefer having
if (dsc_eng_no == 0)
else
ordering in both.
> + break;
> + case 1:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_1;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_1;
> + }
> + break;
> + case 2:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_2;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_2;
> + }
> + break;
> + case 3:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_3;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_3;
> + }
> + break;
> + case 4:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_4;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_4;
> + }
> + break;
> + case 5:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_5;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_5;
> + }
> + break;
> + case 6:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_6;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_6;
> + }
> + break;
> + case 7:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_7;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_7;
> + }
> + break;
> + case 8:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_8;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_8;
> + }
> + break;
> + case 9:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_9;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_9;
> + }
> + break;
> + case 10:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_10;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_10;
> + }
> + break;
> + case 16:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_16;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_16;
> + }
> + break;
> + /*
> + * Since PPS_17 and PPS_18 were introduced from MTL dsc check
> + * need not be done
> + */
> + case 17:
> + if (dsc_eng_no == 2)
> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
> + else
> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
> + break;
> + case 18:
> + if (dsc_eng_no == 2)
> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
> + else
> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
> + break;
> + default:
> + drm_err(&i915->drm, "PPS register does not exist\n");
It's a programming error if we hit here. drm_WARN() or MISSING_CASE() or
something would be better to be loud about it.
> + break;
> + }
> +}
> +
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> }
> }
>
> +static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> + int pps, u32 *pps_val)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> + i915_reg_t dsc_reg;
> + u32 pps_temp;
> +
> + *pps_val = 0;
> +
> + intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
> + *pps_val = intel_de_read(i915, dsc_reg);
> + if (num_vdsc_instances > 1) {
> + intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
> + pps_temp = intel_de_read(i915, dsc_reg);
> + if (*pps_val != pps_temp)
> + return true;
> + }
> + return false;
I'd really like the dsc reg read function to return the register value,
instead of returning it through a pointer variable. Dunno how to make it
work nicely with the verification, though.
Usually functions returning int, ret == 0 means success, and for
functions returning bool, ret == true means success. Here, ret == true
means failure, which is kind of backwards.
> +}
> +
> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
> + int pps, u32 *pps_val)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + bool is_dsc_diff;
> +
> + is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> + drm_WARN_ON(&i915->drm, is_dsc_diff);
> +}
> +
> +static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + u32 pps_temp1, pps_temp2;
> +
> + /* Readout PPS_0 and PPS_1 registers */
> + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> +
> + vdsc_cfg->bits_per_pixel = pps_temp2;
> +
> + if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> + vdsc_cfg->bits_per_pixel >>= 1;
> +
> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +}
> +
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - enum pipe pipe = crtc->pipe;
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
> + u32 dss_ctl1, dss_ctl2;
>
> if (!intel_dsc_source_support(crtc_state))
> return;
> @@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> (dss_ctl1 & JOINER_ENABLE);
>
> - /* FIXME: add more state readout as needed */
> -
> - /* PPS0 & PPS1 */
> - if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> - pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> - if (crtc_state->dsc.dsc_split) {
> - pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> - }
> -
> - } else {
> - pps0 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> - pps1 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> - if (crtc_state->dsc.dsc_split) {
> - pps_temp0 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> - pps_temp1 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> - drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> - }
> - }
> -
> - vdsc_cfg->bits_per_pixel = pps1;
> -
> - if (pps0 & DSC_NATIVE_420_ENABLE)
> - vdsc_cfg->bits_per_pixel >>= 1;
> -
> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> + intel_dsc_get_pps_config(crtc_state);
> out:
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 12:38 ` Jani Nikula
@ 2023-07-13 12:42 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-07-13 12:42 UTC (permalink / raw)
To: Suraj Kandpal, intel-gfx
On Thu, 13 Jul 2023, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> Add function to read any PPS register based on the
>> intel_dsc_pps enum provided. Add a function which will call the
>> new pps read function and place it in crtc state. Only PPS0 and
>> PPS1 are readout the rest of the registers will be read in upcoming
>> patches.
>>
>> --v2
>> -Changes in read function as PPS enum is removed
>> -Initialize pps_val as 0 in pps_read func itself [Jani]
>> -Create a function that gets the required register and call that
>> in the common read function [Jani]
>> -Move the drm_WARN_ON one abstraction layer above [Jani]
>>
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 276 +++++++++++++++++++---
>> 1 file changed, 242 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index d48b8306bfc3..48273a3618c5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>> return num_vdsc_instances;
>> }
>>
>> +static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
>> + int dsc_eng_no, i915_reg_t *dsc_reg)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>> + bool pipe_dsc;
>> +
>> + pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>> +
>> + switch (pps) {
>> + case 0:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>
> What's "dsc_eng_no", and why is it 0 or 2?
>
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_0;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_0;
>> + }
>
> I think the branches are backwards here. Above it's DSC1, DSC0 and here
> it's DSCA, DSCC.
>
> I think I'd prefer having
>
> if (dsc_eng_no == 0)
> else
>
> ordering in both.
Actually, reading the patches further, I think it might be better to
always return both registers here. Make this:
static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state,
int pps, i915_reg_t *dsc_reg0, i915_reg_t *dsc_reg1)
and it both simplifies and optimizes a lot of places later on.
BR,
Jani.
>
>> + break;
>> + case 1:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_1;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_1;
>> + }
>> + break;
>> + case 2:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_2;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_2;
>> + }
>> + break;
>> + case 3:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_3;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_3;
>> + }
>> + break;
>> + case 4:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_4;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_4;
>> + }
>> + break;
>> + case 5:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_5;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_5;
>> + }
>> + break;
>> + case 6:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_6;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_6;
>> + }
>> + break;
>> + case 7:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_7;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_7;
>> + }
>> + break;
>> + case 8:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_8;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_8;
>> + }
>> + break;
>> + case 9:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_9;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_9;
>> + }
>> + break;
>> + case 10:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_10;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_10;
>> + }
>> + break;
>> + case 16:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_16;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_16;
>> + }
>> + break;
>> + /*
>> + * Since PPS_17 and PPS_18 were introduced from MTL dsc check
>> + * need not be done
>> + */
>> + case 17:
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
>> + else
>> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
>> + break;
>> + case 18:
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
>> + else
>> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
>> + break;
>> + default:
>> + drm_err(&i915->drm, "PPS register does not exist\n");
>
> It's a programming error if we hit here. drm_WARN() or MISSING_CASE() or
> something would be better to be loud about it.
>
>> + break;
>> + }
>> +}
>> +
>> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> @@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>> }
>> }
>>
>> +static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
>> + int pps, u32 *pps_val)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> + i915_reg_t dsc_reg;
>> + u32 pps_temp;
>> +
>> + *pps_val = 0;
>> +
>> + intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
>> + *pps_val = intel_de_read(i915, dsc_reg);
>> + if (num_vdsc_instances > 1) {
>> + intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
>> + pps_temp = intel_de_read(i915, dsc_reg);
>> + if (*pps_val != pps_temp)
>> + return true;
>> + }
>> + return false;
>
> I'd really like the dsc reg read function to return the register value,
> instead of returning it through a pointer variable. Dunno how to make it
> work nicely with the verification, though.
>
> Usually functions returning int, ret == 0 means success, and for
> functions returning bool, ret == true means success. Here, ret == true
> means failure, which is kind of backwards.
>
>> +}
>> +
>> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
>> + int pps, u32 *pps_val)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + bool is_dsc_diff;
>> +
>> + is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
>> + drm_WARN_ON(&i915->drm, is_dsc_diff);
>> +}
>> +
>> +static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> + u32 pps_temp1, pps_temp2;
>> +
>> + /* Readout PPS_0 and PPS_1 registers */
>> + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
>> + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
>> +
>> + vdsc_cfg->bits_per_pixel = pps_temp2;
>> +
>> + if (pps_temp1 & DSC_NATIVE_420_ENABLE)
>> + vdsc_cfg->bits_per_pixel >>= 1;
>> +
>> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>> +}
>> +
>> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> - enum pipe pipe = crtc->pipe;
>> enum intel_display_power_domain power_domain;
>> intel_wakeref_t wakeref;
>> - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
>> + u32 dss_ctl1, dss_ctl2;
>>
>> if (!intel_dsc_source_support(crtc_state))
>> return;
>> @@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>> (dss_ctl1 & JOINER_ENABLE);
>>
>> - /* FIXME: add more state readout as needed */
>> -
>> - /* PPS0 & PPS1 */
>> - if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> - pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
>> - if (crtc_state->dsc.dsc_split) {
>> - pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
>> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
>> - }
>> -
>> - } else {
>> - pps0 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>> - pps1 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>> - if (crtc_state->dsc.dsc_split) {
>> - pps_temp0 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>> - pps_temp1 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>> - drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
>> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
>> - }
>> - }
>> -
>> - vdsc_cfg->bits_per_pixel = pps1;
>> -
>> - if (pps0 & DSC_NATIVE_420_ENABLE)
>> - vdsc_cfg->bits_per_pixel >>= 1;
>> -
>> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>> + intel_dsc_get_pps_config(crtc_state);
>> out:
>> intel_display_power_put(dev_priv, power_domain, wakeref);
>> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
2023-07-13 12:38 ` Jani Nikula
@ 2023-07-13 12:47 ` Jani Nikula
2023-07-13 13:06 ` Kandpal, Suraj
2023-07-13 13:10 ` Nautiyal, Ankit K
1 sibling, 2 replies; 19+ messages in thread
From: Jani Nikula @ 2023-07-13 12:47 UTC (permalink / raw)
To: Suraj Kandpal, intel-gfx
On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
> patches.
>
> --v2
> -Changes in read function as PPS enum is removed
> -Initialize pps_val as 0 in pps_read func itself [Jani]
> -Create a function that gets the required register and call that
> in the common read function [Jani]
> -Move the drm_WARN_ON one abstraction layer above [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 276 +++++++++++++++++++---
> 1 file changed, 242 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d48b8306bfc3..48273a3618c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
> return num_vdsc_instances;
> }
>
> +static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
> + int dsc_eng_no, i915_reg_t *dsc_reg)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + bool pipe_dsc;
> +
> + pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> +
> + switch (pps) {
> + case 0:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_0;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_0;
> + }
> + break;
> + case 1:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_1;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_1;
> + }
> + break;
> + case 2:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_2;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_2;
> + }
> + break;
> + case 3:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_3;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_3;
> + }
> + break;
> + case 4:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_4;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_4;
> + }
> + break;
> + case 5:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_5;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_5;
> + }
> + break;
> + case 6:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_6;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_6;
> + }
> + break;
> + case 7:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_7;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_7;
> + }
> + break;
> + case 8:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_8;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_8;
> + }
> + break;
> + case 9:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_9;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_9;
> + }
> + break;
> + case 10:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_10;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_10;
> + }
> + break;
> + case 16:
> + if (pipe_dsc) {
> + if (dsc_eng_no == 2)
> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
> + else
> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
> + } else {
> + if (dsc_eng_no == 2)
> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_16;
> + else
> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_16;
> + }
> + break;
> + /*
> + * Since PPS_17 and PPS_18 were introduced from MTL dsc check
> + * need not be done
> + */
> + case 17:
> + if (dsc_eng_no == 2)
> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
> + else
> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
> + break;
> + case 18:
> + if (dsc_eng_no == 2)
> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
> + else
> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
> + break;
> + default:
> + drm_err(&i915->drm, "PPS register does not exist\n");
> + break;
> + }
> +}
> +
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> }
> }
>
> +static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> + int pps, u32 *pps_val)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
> + i915_reg_t dsc_reg;
> + u32 pps_temp;
> +
> + *pps_val = 0;
> +
> + intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
> + *pps_val = intel_de_read(i915, dsc_reg);
> + if (num_vdsc_instances > 1) {
Btw going from (crtc_state->dsc.dsc_split) to if (num_vdsc_instances >
1) should also be a separate change, instead of baked into this one.
BR,
Jani.
> + intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
> + pps_temp = intel_de_read(i915, dsc_reg);
> + if (*pps_val != pps_temp)
> + return true;
> + }
> + return false;
> +}
> +
> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
> + int pps, u32 *pps_val)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + bool is_dsc_diff;
> +
> + is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> + drm_WARN_ON(&i915->drm, is_dsc_diff);
> +}
> +
> +static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> + u32 pps_temp1, pps_temp2;
> +
> + /* Readout PPS_0 and PPS_1 registers */
> + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> +
> + vdsc_cfg->bits_per_pixel = pps_temp2;
> +
> + if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> + vdsc_cfg->bits_per_pixel >>= 1;
> +
> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +}
> +
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - enum pipe pipe = crtc->pipe;
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
> + u32 dss_ctl1, dss_ctl2;
>
> if (!intel_dsc_source_support(crtc_state))
> return;
> @@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
> (dss_ctl1 & JOINER_ENABLE);
>
> - /* FIXME: add more state readout as needed */
> -
> - /* PPS0 & PPS1 */
> - if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> - pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> - if (crtc_state->dsc.dsc_split) {
> - pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> - }
> -
> - } else {
> - pps0 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> - pps1 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> - if (crtc_state->dsc.dsc_split) {
> - pps_temp0 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> - pps_temp1 = intel_de_read(dev_priv,
> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> - drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
> - }
> - }
> -
> - vdsc_cfg->bits_per_pixel = pps1;
> -
> - if (pps0 & DSC_NATIVE_420_ENABLE)
> - vdsc_cfg->bits_per_pixel >>= 1;
> -
> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> + intel_dsc_get_pps_config(crtc_state);
> out:
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases
2023-07-13 12:29 ` Jani Nikula
@ 2023-07-13 13:03 ` Kandpal, Suraj
0 siblings, 0 replies; 19+ messages in thread
From: Kandpal, Suraj @ 2023-07-13 13:03 UTC (permalink / raw)
To: Jani Nikula, intel-gfx@lists.freedesktop.org
> On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > In intel_vdsc_get_config we only read the primary dsc engine register
> > and not take into account if the other dsc engine is in use and if
> > both registers have the same value or not this patche fixes that by
> > adding a check.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 15 ++++++++++++++-
> > 1 file changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 530f3c08a172..d48b8306bfc3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -939,7 +939,7 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> > enum pipe pipe = crtc->pipe;
> > enum intel_display_power_domain power_domain;
> > intel_wakeref_t wakeref;
> > - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
> > + u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1
> > += 1;
> >
> > if (!intel_dsc_source_support(crtc_state))
> > return;
> > @@ -965,11 +965,24 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> > /* PPS0 & PPS1 */
> > if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > pps1 = intel_de_read(dev_priv,
> DSCA_PICTURE_PARAMETER_SET_1);
> > + if (crtc_state->dsc.dsc_split) {
> > + pps_temp1 = intel_de_read(dev_priv,
> DSCC_PICTURE_PARAMETER_SET_1);
> > + drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > + }
> > +
>
> Superfluous newline.
>
Thanks for the review will fix that
> > } else {
> > pps0 = intel_de_read(dev_priv,
> >
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > pps1 = intel_de_read(dev_priv,
> >
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> > + if (crtc_state->dsc.dsc_split) {
> > + pps_temp0 = intel_de_read(dev_priv,
> > +
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > + pps_temp1 = intel_de_read(dev_priv,
> > +
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>
> Those are the same two registers as above?
>
Yes they are should have been _DSC1_instead
Regards,
Suraj Kandpal
> BR,
> Jani.
>
> > + drm_WARN_ON(&dev_priv->drm, pps0 !=
> pps_temp0);
> > + drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > + }
> > }
> >
> > vdsc_cfg->bits_per_pixel = pps1;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 12:47 ` Jani Nikula
@ 2023-07-13 13:06 ` Kandpal, Suraj
2023-07-13 13:10 ` Nautiyal, Ankit K
1 sibling, 0 replies; 19+ messages in thread
From: Kandpal, Suraj @ 2023-07-13 13:06 UTC (permalink / raw)
To: Jani Nikula, intel-gfx@lists.freedesktop.org
> On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Add function to read any PPS register based on the intel_dsc_pps enum
> > provided. Add a function which will call the new pps read function and
> > place it in crtc state. Only PPS0 and
> > PPS1 are readout the rest of the registers will be read in upcoming
> > patches.
> >
> > --v2
> > -Changes in read function as PPS enum is removed -Initialize pps_val
> > as 0 in pps_read func itself [Jani] -Create a function that gets the
> > required register and call that in the common read function [Jani]
> > -Move the drm_WARN_ON one abstraction layer above [Jani]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 276
> > +++++++++++++++++++---
> > 1 file changed, 242 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index d48b8306bfc3..48273a3618c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const
> struct intel_crtc_state *crtc_state)
> > return num_vdsc_instances;
> > }
> >
> > +static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int
> pps,
> > + int dsc_eng_no, i915_reg_t *dsc_reg) {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + enum pipe pipe = crtc->pipe;
> > + bool pipe_dsc;
> > +
> > + pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> > +
> > + switch (pps) {
> > + case 0:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_0;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_0;
> > + }
> > + break;
> > + case 1:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_1;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_1;
> > + }
> > + break;
> > + case 2:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_2;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_2;
> > + }
> > + break;
> > + case 3:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_3;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_3;
> > + }
> > + break;
> > + case 4:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_4;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_4;
> > + }
> > + break;
> > + case 5:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_5;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_5;
> > + }
> > + break;
> > + case 6:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_6;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_6;
> > + }
> > + break;
> > + case 7:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_7;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_7;
> > + }
> > + break;
> > + case 8:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_8;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_8;
> > + }
> > + break;
> > + case 9:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_9;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_9;
> > + }
> > + break;
> > + case 10:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_10;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_10;
> > + }
> > + break;
> > + case 16:
> > + if (pipe_dsc) {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
> > + else
> > + *dsc_reg =
> ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
> > + } else {
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> DSCA_PICTURE_PARAMETER_SET_16;
> > + else
> > + *dsc_reg =
> DSCC_PICTURE_PARAMETER_SET_16;
> > + }
> > + break;
> > + /*
> > + * Since PPS_17 and PPS_18 were introduced from MTL dsc check
> > + * need not be done
> > + */
> > + case 17:
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
> > + else
> > + *dsc_reg =
> MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
> > + break;
> > + case 18:
> > + if (dsc_eng_no == 2)
> > + *dsc_reg =
> MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
> > + else
> > + *dsc_reg =
> MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
> > + break;
> > + default:
> > + drm_err(&i915->drm, "PPS register does not exist\n");
> > + break;
> > + }
> > +}
> > +
> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> > *crtc_state) {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct
> intel_crtc_state *old_crtc_state)
> > }
> > }
> >
> > +static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> > + int pps, u32 *pps_val)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + int num_vdsc_instances =
> intel_dsc_get_num_vdsc_instances(crtc_state);
> > + i915_reg_t dsc_reg;
> > + u32 pps_temp;
> > +
> > + *pps_val = 0;
> > +
> > + intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
> > + *pps_val = intel_de_read(i915, dsc_reg);
> > + if (num_vdsc_instances > 1) {
>
> Btw going from (crtc_state->dsc.dsc_split) to if (num_vdsc_instances >
> 1) should also be a separate change, instead of baked into this one.
>
Ohkay will create a new patch after this one that goes from using crtc_state->dsc.dsc_split
to num_vdsc_instances > 1
Regards,
Suraj Kandpal
> BR,
> Jani.
>
>
>
> > + intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
> > + pps_temp = intel_de_read(i915, dsc_reg);
> > + if (*pps_val != pps_temp)
> > + return true;
> > + }
> > + return false;
> > +}
> > +
> > +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
> *crtc_state,
> > + int pps, u32 *pps_val)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + bool is_dsc_diff;
> > +
> > + is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> > + drm_WARN_ON(&i915->drm, is_dsc_diff); }
> > +
> > +static void intel_dsc_get_pps_config(struct intel_crtc_state
> > +*crtc_state) {
> > + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > + u32 pps_temp1, pps_temp2;
> > +
> > + /* Readout PPS_0 and PPS_1 registers */
> > + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
> > + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
> > +
> > + vdsc_cfg->bits_per_pixel = pps_temp2;
> > +
> > + if (pps_temp1 & DSC_NATIVE_420_ENABLE)
> > + vdsc_cfg->bits_per_pixel >>= 1;
> > +
> > + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; }
> > +
> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > - enum pipe pipe = crtc->pipe;
> > enum intel_display_power_domain power_domain;
> > intel_wakeref_t wakeref;
> > - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1
> = 1;
> > + u32 dss_ctl1, dss_ctl2;
> >
> > if (!intel_dsc_source_support(crtc_state))
> > return;
> > @@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> > crtc_state->dsc.dsc_split = (dss_ctl2 &
> RIGHT_BRANCH_VDSC_ENABLE) &&
> > (dss_ctl1 & JOINER_ENABLE);
> >
> > - /* FIXME: add more state readout as needed */
> > -
> > - /* PPS0 & PPS1 */
> > - if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> > - pps1 = intel_de_read(dev_priv,
> DSCA_PICTURE_PARAMETER_SET_1);
> > - if (crtc_state->dsc.dsc_split) {
> > - pps_temp1 = intel_de_read(dev_priv,
> DSCC_PICTURE_PARAMETER_SET_1);
> > - drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > - }
> > -
> > - } else {
> > - pps0 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > - pps1 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> > - if (crtc_state->dsc.dsc_split) {
> > - pps_temp0 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> > - pps_temp1 = intel_de_read(dev_priv,
> > -
> ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> > - drm_WARN_ON(&dev_priv->drm, pps0 !=
> pps_temp0);
> > - drm_WARN_ON(&dev_priv->drm, pps1 !=
> pps_temp1);
> > - }
> > - }
> > -
> > - vdsc_cfg->bits_per_pixel = pps1;
> > -
> > - if (pps0 & DSC_NATIVE_420_ENABLE)
> > - vdsc_cfg->bits_per_pixel >>= 1;
> > -
> > - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > + intel_dsc_get_pps_config(crtc_state);
> > out:
> > intel_display_power_put(dev_priv, power_domain, wakeref); }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register
2023-07-13 12:47 ` Jani Nikula
2023-07-13 13:06 ` Kandpal, Suraj
@ 2023-07-13 13:10 ` Nautiyal, Ankit K
1 sibling, 0 replies; 19+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-13 13:10 UTC (permalink / raw)
To: Jani Nikula, Suraj Kandpal, intel-gfx
On 7/13/2023 6:17 PM, Jani Nikula wrote:
> On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> Add function to read any PPS register based on the
>> intel_dsc_pps enum provided. Add a function which will call the
>> new pps read function and place it in crtc state. Only PPS0 and
>> PPS1 are readout the rest of the registers will be read in upcoming
>> patches.
>>
>> --v2
>> -Changes in read function as PPS enum is removed
>> -Initialize pps_val as 0 in pps_read func itself [Jani]
>> -Create a function that gets the required register and call that
>> in the common read function [Jani]
>> -Move the drm_WARN_ON one abstraction layer above [Jani]
>>
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 276 +++++++++++++++++++---
>> 1 file changed, 242 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index d48b8306bfc3..48273a3618c5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -303,6 +303,196 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
>> return num_vdsc_instances;
>> }
>>
>> +static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
>> + int dsc_eng_no, i915_reg_t *dsc_reg)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + enum pipe pipe = crtc->pipe;
>> + bool pipe_dsc;
>> +
>> + pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>> +
>> + switch (pps) {
>> + case 0:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_0;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_0;
>> + }
>> + break;
>> + case 1:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_1;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_1;
>> + }
>> + break;
>> + case 2:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_2;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_2;
>> + }
>> + break;
>> + case 3:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_3;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_3;
>> + }
>> + break;
>> + case 4:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_4;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_4;
>> + }
>> + break;
>> + case 5:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_5;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_5;
>> + }
>> + break;
>> + case 6:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_6;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_6;
>> + }
>> + break;
>> + case 7:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_7;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_7;
>> + }
>> + break;
>> + case 8:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_8;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_8;
>> + }
>> + break;
>> + case 9:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_9;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_9;
>> + }
>> + break;
>> + case 10:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_10;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_10;
>> + }
>> + break;
>> + case 16:
>> + if (pipe_dsc) {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
>> + else
>> + *dsc_reg = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
>> + } else {
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = DSCA_PICTURE_PARAMETER_SET_16;
>> + else
>> + *dsc_reg = DSCC_PICTURE_PARAMETER_SET_16;
>> + }
>> + break;
>> + /*
>> + * Since PPS_17 and PPS_18 were introduced from MTL dsc check
>> + * need not be done
>> + */
>> + case 17:
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
>> + else
>> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
>> + break;
>> + case 18:
>> + if (dsc_eng_no == 2)
>> + *dsc_reg = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
>> + else
>> + *dsc_reg = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
>> + break;
>> + default:
>> + drm_err(&i915->drm, "PPS register does not exist\n");
>> + break;
>> + }
>> +}
>> +
>> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> @@ -930,16 +1120,64 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>> }
>> }
>>
>> +static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
>> + int pps, u32 *pps_val)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>> + i915_reg_t dsc_reg;
>> + u32 pps_temp;
>> +
>> + *pps_val = 0;
>> +
>> + intel_dsc_get_pps_reg(crtc_state, pps, 0, &dsc_reg);
>> + *pps_val = intel_de_read(i915, dsc_reg);
>> + if (num_vdsc_instances > 1) {
> Btw going from (crtc_state->dsc.dsc_split) to if (num_vdsc_instances >
> 1) should also be a separate change, instead of baked into this one.
Also, lets stick to dsc_split. Number of vdsc instances tells total
number of vdsc instances, with bigjoiner it would give 2, even without
dsc split.
Regards,
Ankit
> BR,
> Jani.
>
>
>
>> + intel_dsc_get_pps_reg(crtc_state, pps, 2, &dsc_reg);
>> + pps_temp = intel_de_read(i915, dsc_reg);
>> + if (*pps_val != pps_temp)
>> + return true;
>> + }
>> + return false;
>> +}
>> +
>> +static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
>> + int pps, u32 *pps_val)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + bool is_dsc_diff;
>> +
>> + is_dsc_diff = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
>> + drm_WARN_ON(&i915->drm, is_dsc_diff);
>> +}
>> +
>> +static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> + u32 pps_temp1, pps_temp2;
>> +
>> + /* Readout PPS_0 and PPS_1 registers */
>> + intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
>> + intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
>> +
>> + vdsc_cfg->bits_per_pixel = pps_temp2;
>> +
>> + if (pps_temp1 & DSC_NATIVE_420_ENABLE)
>> + vdsc_cfg->bits_per_pixel >>= 1;
>> +
>> + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>> +}
>> +
>> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> - struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> - enum pipe pipe = crtc->pipe;
>> enum intel_display_power_domain power_domain;
>> intel_wakeref_t wakeref;
>> - u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
>> + u32 dss_ctl1, dss_ctl2;
>>
>> if (!intel_dsc_source_support(crtc_state))
>> return;
>> @@ -960,37 +1198,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
>> (dss_ctl1 & JOINER_ENABLE);
>>
>> - /* FIXME: add more state readout as needed */
>> -
>> - /* PPS0 & PPS1 */
>> - if (!is_pipe_dsc(crtc, cpu_transcoder)) {
>> - pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
>> - if (crtc_state->dsc.dsc_split) {
>> - pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
>> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
>> - }
>> -
>> - } else {
>> - pps0 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>> - pps1 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>> - if (crtc_state->dsc.dsc_split) {
>> - pps_temp0 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
>> - pps_temp1 = intel_de_read(dev_priv,
>> - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
>> - drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
>> - drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
>> - }
>> - }
>> -
>> - vdsc_cfg->bits_per_pixel = pps1;
>> -
>> - if (pps0 & DSC_NATIVE_420_ENABLE)
>> - vdsc_cfg->bits_per_pixel >>= 1;
>> -
>> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>> + intel_dsc_get_pps_config(crtc_state);
>> out:
>> intel_display_power_put(dev_priv, power_domain, wakeref);
>> }
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
` (9 preceding siblings ...)
2023-07-13 12:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-07-13 13:15 ` Jani Nikula
10 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-07-13 13:15 UTC (permalink / raw)
To: Suraj Kandpal, intel-gfx
On Thu, 13 Jul 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Up until now we only verified one or two of the dsc pps
> params like bits_per_component and bits_per_pixel this
> patch series aim to readout almost all PPS param and get
> them compared.
> Along with that some work on making a common function to
> read and write PPS param regiters is also done.
There are some issues that I noted, and I'm sure some things could be
done differently, but overall I think this makes nice improvements, and
it's definitely better than the first version.
The further versions will still require detailed review, but the overall
approach is now
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> --v2
> -Remove duplicated code and create function that fetches register
> and reuse that [Jani]
> -move WARN_ON one abstraction layer up [Jani]
> -Split patch so that refactor and a new functionality is not added
> in the same patch [Jani]
> -Add a new refactor patch so that bit shifting can be done in a
> clean way [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Suraj Kandpal (6):
> drm/i915/vdsc: Refactor dsc register field macro
> drm/i915/vdsc: Add a check for dsc split cases
> drm/i915/vdsc: Add function to read any PPS register
> drm/i915/vdsc: Add function to write in PPS register
> drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
> drm/i915/display: Compare the readout dsc pps params
>
> drivers/gpu/drm/i915/display/intel_display.c | 31 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 622 ++++++++++--------
> .../gpu/drm/i915/display/intel_vdsc_regs.h | 101 ++-
> 3 files changed, 463 insertions(+), 291 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2023-07-13 13:15 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-13 6:29 [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 1/6] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
2023-07-13 12:29 ` Jani Nikula
2023-07-13 13:03 ` Kandpal, Suraj
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
2023-07-13 12:38 ` Jani Nikula
2023-07-13 12:42 ` Jani Nikula
2023-07-13 12:47 ` Jani Nikula
2023-07-13 13:06 ` Kandpal, Suraj
2023-07-13 13:10 ` Nautiyal, Ankit K
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/vdsc: Add function to write in " Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
2023-07-13 6:29 ` [Intel-gfx] [PATCH v2 6/6] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev2) Patchwork
2023-07-13 9:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-13 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-13 12:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-13 13:15 ` [Intel-gfx] [PATCH v2 0/6] Add DSC PPS readout Jani Nikula
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