Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Add media RP0/RPn to per-gt sysfs

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 29/04/2022 20:56, Ashutosh Dixit wrote:
> From: Dale B Stimson <dale.b.stimson@intel.com>
> 
> Retrieve RP0 and RPn freq for media IP from PCODE and display in per-gt
> sysfs. This patch adds the following files to gt/gtN sysfs:
> * media_RP0_freq_mhz
> * media_RPn_freq_mhz
> 
> v2: Fixed commit author (Rodrigo)
> v3: Convert to new uncore interface for pcode functions
> v4: Adapt to intel_pcode.* function rename
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 47 +++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h             |  8 ++++
>   2 files changed, 55 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 2b1cd6a01724..ab91e9cf9deb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -12,6 +12,7 @@
>   #include "i915_sysfs.h"
>   #include "intel_gt.h"
>   #include "intel_gt_regs.h"
> +#include "intel_pcode.h"

Nit - in an alphabetical sandwich.

Regards,

Tvrtko

>   #include "intel_gt_sysfs.h"
>   #include "intel_gt_sysfs_pm.h"
>   #include "intel_rc6.h"
> @@ -669,13 +670,59 @@ static ssize_t media_freq_factor_store(struct device *dev,
>   	return err ?: count;
>   }
>   
> +static ssize_t media_RP0_freq_mhz_show(struct device *dev,
> +				       struct device_attribute *attr,
> +				       char *buff)
> +{
> +	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> +	u32 val;
> +	int err;
> +
> +	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> +			       PCODE_MBOX_FC_SC_READ_FUSED_P0,
> +			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
> +
> +	if (err)
> +		return err;
> +
> +	/* Fused media RP0 read from pcode is in units of 50 MHz */
> +	val *= GT_FREQUENCY_MULTIPLIER;
> +
> +	return sysfs_emit(buff, "%u\n", val);
> +}
> +
> +static ssize_t media_RPn_freq_mhz_show(struct device *dev,
> +				       struct device_attribute *attr,
> +				       char *buff)
> +{
> +	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> +	u32 val;
> +	int err;
> +
> +	err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,
> +			       PCODE_MBOX_FC_SC_READ_FUSED_PN,
> +			       PCODE_MBOX_DOMAIN_MEDIAFF, &val);
> +
> +	if (err)
> +		return err;
> +
> +	/* Fused media RPn read from pcode is in units of 50 MHz */
> +	val *= GT_FREQUENCY_MULTIPLIER;
> +
> +	return sysfs_emit(buff, "%u\n", val);
> +}
> +
>   static DEVICE_ATTR_RW(media_freq_factor);
>   static struct device_attribute dev_attr_media_freq_factor_scale =
>   	__ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
> +static DEVICE_ATTR_RO(media_RP0_freq_mhz);
> +static DEVICE_ATTR_RO(media_RPn_freq_mhz);
>   
>   static const struct attribute *media_perf_power_attrs[] = {
>   	&dev_attr_media_freq_factor.attr,
>   	&dev_attr_media_freq_factor_scale.attr,
> +	&dev_attr_media_RP0_freq_mhz.attr,
> +	&dev_attr_media_RPn_freq_mhz.attr,
>   	NULL
>   };
>   
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5a4689171cc7..90a9922faffc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6758,6 +6758,14 @@
>   #define     DG1_UNCORE_GET_INIT_STATUS		0x0
>   #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
>   #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> +#define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
> +/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
> +#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
> +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
> +/*   XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */
> +#define     PCODE_MBOX_DOMAIN_NONE		0x0
> +#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
>   #define GEN6_PCODE_DATA				_MMIO(0x138128)
>   #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>   #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16