Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
 messages from 2018-11-30 06:08:38 to 2018-12-01 18:56:56 UTC [more...]

[PATCH] i915/dp/fec: Fix static check warning
 2018-12-01 18:56 UTC  (5+ messages)
` ✓ Fi.CI.BAT: success for "
` ✗ Fi.CI.IGT: failure "

[PATCH v3 1/2] drm/i915: Add HAS_DISPLAY() and use it
 2018-12-01 18:32 UTC  (6+ messages)
` [PATCH v3 2/2] drm/i915: Move display device info capabilities to its own struct
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "

[PATCH 1/7] drm/i915: Complete the fences as they are cancelled due to wedging
 2018-12-01 18:32 UTC  (11+ messages)
` [PATCH 2/7] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
` [PATCH 3/7] drm/i915: Allocate a common scratch page
` [PATCH 4/7] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
` [PATCH 5/7] drm/i915/selftests: Reorder request allocation vs vma pinning
` [PATCH 6/7] drm/i915: Pipeline PDP updates for Braswell
` [PATCH 7/7] drm/i915/execlists: Apply a full mb before execution "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "

[CI 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
 2018-12-01 17:15 UTC  (9+ messages)
` [CI 2/2] drm/i915/icl: Define MOCS table for Icelake
` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
` ✓ Fi.CI.IGT: "

[PATCH v2 0/8] Restore workarounds after engine reset and unify their handling
 2018-12-01 13:36 UTC  (23+ messages)
` [PATCH 1/7] drm/i915: Record GT workarounds in a list
` [PATCH 2/7] drm/i915: Introduce per-engine workarounds
` [PATCH 3/7] drm/i915: Verify GT workaround state after GPU init
` [PATCH 4/7] drm/i915/selftests: Add tests for GT and engine workaround verification
` [PATCH 5/7] drm/i915: Move register white-listing to the common workaround framework
` [PATCH 6/7] drm/i915: Fuse per-context workaround handling with the common framework
` [PATCH 7/7] drm/i915: Trim unused workaround list entries
` ✗ Fi.CI.CHECKPATCH: warning for Restore workarounds after engine reset and unify their handling (rev2)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "

[PATCH 1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats
 2018-12-01 12:20 UTC  (6+ messages)
` [PATCH 2/4] drm/i915/dsi: Enable dithering for 6 bpc panels
` [PATCH 3/4] drm/i915/dsi: Adjust crtc_clock for burst_mode_ratio
` [PATCH 4/4] drm/i915/dsi: Call drm_connector_cleanup on vlv_dsi_init error exit path
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats
` ✓ Fi.CI.BAT: success "

[PATCH 1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c
 2018-12-01 12:18 UTC  (6+ messages)
` [PATCH 2/4] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
` [PATCH 3/4] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init
` [PATCH 4/4] drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c
` ✓ Fi.CI.BAT: success "

[PATCH] drm/fbdev: Make skip_vt_switch the default
 2018-12-01 10:55 UTC  (4+ messages)
` ✗ Fi.CI.CHECKPATCH: warning for drm/fbdev: Make skip_vt_switch the default (rev3)
` ✓ Fi.CI.BAT: success "
` ✓ Fi.CI.IGT: "

[PATCH 1/6] drm/i915: Complete the fences as they are cancelled due to wedging
 2018-12-01  9:55 UTC  (12+ messages)
` [PATCH 2/6] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
` [PATCH 3/6] drm/i915: Allocate a common scratch page
` [PATCH 4/6] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
` [PATCH 5/6] drm/i915/selftests: Reorder request allocation vs vma pinning
` [PATCH 6/6] drm/i915: Pipeline PDP updates for Braswell
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.IGT: failure "
` [PATCH] "
` ✗ Fi.CI.BAT: failure for series starting with drm/i915: Complete the fences as they are cancelled due to wedging (rev2)

[PATCH] drm/i915/vgpu: Disallow loading on old vGPU hosts
 2018-12-01  6:31 UTC  (6+ messages)
` ✓ Fi.CI.BAT: success for "
` [PATCH v2] "
` ✓ Fi.CI.BAT: success for drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
` ✓ Fi.CI.IGT: "

[PATCH 1/2] drm/i915/selftests: Extract spinner code
 2018-12-01  3:53 UTC  (15+ messages)
` [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
  ` [PATCH v2 "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)
` ✗ Fi.CI.SPARSE: "
` ✓ Fi.CI.BAT: success "
` ✓ Fi.CI.IGT: "

[PATCH] drm/i915/dp: Fix link compute m_n calc for DSC
 2018-12-01  1:34 UTC  (2+ messages)
` ✓ Fi.CI.BAT: success for "

[PATCH v2 01/11] drm/i915: Disable PSR in Apple panels
 2018-12-01  0:37 UTC  (13+ messages)
` [PATCH v2 02/11] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
` [PATCH v2 03/11] drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block
` [PATCH v2 04/11] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
` [PATCH v2 06/11] drm: Add the PSR SU granularity registers offsets
` [PATCH v2 07/11] drm/i915/psr: Check if resolution is supported by default SU granularity
` ✓ Fi.CI.IGT: success for series starting with [v2,01/11] drm/i915: Disable PSR in Apple panels

[PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
 2018-12-01  0:33 UTC  (6+ messages)
` ✗ Fi.CI.BAT: failure for "
` [PATCH v2] "
` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)

[PATCH v2 1/2] drm/i915: Add HAS_DISPLAY() and use it
 2018-11-30 22:36 UTC  (3+ messages)
` [PATCH v2 2/2] drm/i915: Move display device info capabilities to its own struct

[PATCH 1/3] drm/i915/gvt: mandatory require hypervisor's host_init
 2018-11-30 22:36 UTC  (9+ messages)
` [PATCH 3/3] drm/i915/gvt: Change KVMGT as self load module
  ` [PATCH v2] "
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's host_init
` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's host_init (rev2)
` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's host_init
` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gvt: mandatory require hypervisor's host_init (rev2)
` ✗ Fi.CI.IGT: failure "

[PATCH RFC 0/5] DRM cgroup controller
 2018-11-30 22:22 UTC  (11+ messages)
` [PATCH RFC 2/5] cgroup: Add mechanism to register vendor specific DRM devices
          ` [Intel-gfx] "

[PATCH 1/9] drm/i915: Disable PSR in Apple panels
 2018-11-30 22:02 UTC  (11+ messages)
` [PATCH 4/9] drm/i915/icl: Do not change reserved registers related to PSR2
` [PATCH 8/9] drm/i915/psr: Set the right frames values

[PATCH 0/2] HuC Update for BXT
 2018-11-30 19:54 UTC  (5+ messages)
` [PATCH 1/2] firmware/huc/BXT: Update the HuC version
` [PATCH 2/2] HAX enable HuC for CI
` ✗ Fi.CI.CHECKPATCH: warning for HuC Update for BXT
` ✗ Fi.CI.BAT: failure "

[v3 0/3] Add support for Gen 11 pipe color features
 2018-11-30 19:22 UTC  (8+ messages)
` [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support
` [v3 2/3] drm/i915/icl: Enable ICL Pipe CSC block
` [v3 3/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps

[PATCH] drm/i915/psr: Get pipe id following atomic guidelines
 2018-11-30 19:02 UTC  (11+ messages)
` ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)
` ✓ Fi.CI.BAT: success for drm/i915/psr: Get pipe id following atomic guidelines (rev5)
` ✓ Fi.CI.IGT: "

[PATCH] drm/i915/ddi: Check for unexpectedly disabled transcoders
 2018-11-30 17:14 UTC  (3+ messages)
` ✗ Fi.CI.IGT: failure for "

[PATCH v7] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
 2018-11-30 17:11 UTC  (2+ messages)
` ✓ Fi.CI.IGT: success for drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)

[PATCH] drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
 2018-11-30 16:25 UTC  (4+ messages)
` ✓ Fi.CI.IGT: success for "

[PATCH v2 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
 2018-11-30 16:22 UTC  (10+ messages)
  ` [v2, "

[PATCH] drm: Fix up drm_atomic_state_helper.[hc] extraction
 2018-11-30 15:38 UTC  (3+ messages)
  ` [Intel-gfx] "

[PATCH 0/8] Restore workarounds after engine reset and unify their handling
 2018-11-30 15:21 UTC  (24+ messages)
` [PATCH 1/8] drm/i915: Record GT workarounds in a list
` [PATCH 2/8] drm/i915: Introduce per-engine workarounds
` [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
` [PATCH 4/8] drm/i915: Verify engine "
` [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification
` [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework
` [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework
` [PATCH 8/8] drm/i915: Trim unused workaround list entries
` ✗ Fi.CI.BAT: failure for Restore workarounds after engine reset and unify their handling

[PATCH] drm/i915: Remove whitelist application from ringbuffer backend
 2018-11-30 15:11 UTC  (4+ messages)
` ✓ Fi.CI.BAT: success for drm/i915: Remove whitelist application from ringbuffer backend (rev3)
` ✓ Fi.CI.IGT: "

[PATCH] drm/i915/icl: Remove Wa_1604302699
 2018-11-30 15:10 UTC  (3+ messages)
` ✓ Fi.CI.BAT: success for "

[PATCH 0/3] Support 64 bpp half float formats
 2018-11-30 14:15 UTC  (8+ messages)
` [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property
` [Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats

[PATCH v10 00/15] drm/i915/icl: dsi enabling
 2018-11-30 14:15 UTC  (3+ messages)

[PATCH v11 00/23] drm/i915/icl: dsi enabling
 2018-11-30 14:10 UTC  (9+ messages)
` [PATCH v11 01/23] drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
` [PATCH v11 17/23] drm/i915/icl: add dummy DSI GPIO element execution function
` [PATCH v11 20/23] drm/i915/icl: add pll mapping for DSI
` [PATCH v11 23/23] HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

[CI v13 01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
 2018-11-30 12:52 UTC  (2+ messages)
` ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3)

[PATCH 1/2] drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
 2018-11-30 10:08 UTC  (2+ messages)
` ✗ Fi.CI.IGT: failure for series starting with [1/2] "

[PATCH] drm/lease: Send a distinct uevent
 2018-11-30  9:56 UTC  (3+ messages)

[PATCH 01/16] drm/i915: Properly set PCH as NOP when display is disabled
 2018-11-30  8:29 UTC  (3+ messages)

[PATCH 1/3] drm/i915: Use explicit old crtc state in skl_compute_wm()
 2018-11-30  6:30 UTC  (6+ messages)
` [PATCH 2/3] drm/i915: Remove bogus FIXME from SKL wm computation
` [PATCH 3/3] drm/i915: Remove dead update_wm_pre assignment from SKL wm code


This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox