messages from 2023-09-06 12:43:22 to 2023-09-08 00:57:30 UTC [more...]
[Intel-gfx] [PATCH v2 00/27] Enable Lunar Lake display
2023-09-08 0:57 UTC (47+ messages)
` [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES
` [Intel-gfx] [PATCH v2 02/27] drm/i915/lnl: Add display definitions
` [Intel-gfx] [PATCH v2 03/27] drm/i915/xe2lpd: FBC is now supported on all pipes
` [Intel-gfx] [PATCH v2 04/27] drm/i915: Re-order if/else ladder in intel_detect_pch()
` [Intel-gfx] [PATCH v2 05/27] drm/i915/xe2lpd: Add fake PCH
` [Intel-gfx] [PATCH v2 06/27] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
` [Intel-gfx] [PATCH v2 07/27] drm/i915/display: Consolidate saved port bits in intel_digital_port
` [Intel-gfx] [PATCH v2 08/27] drm/i915/xe2lpd: Move D2D enable/disable
` [Intel-gfx] [PATCH v2 09/27] drm/i915/xe2lpd: Move registers to PICA
` [Intel-gfx] [PATCH v2 10/27] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
` [Intel-gfx] [PATCH v2 11/27] drm/i915/xe2lpd: Register DE_RRMR has been removed
` [Intel-gfx] [PATCH v2 12/27] FIXME: drm/i915/xe2lpd: Add display power well
` [Intel-gfx] [PATCH v2 13/27] drm/i915/xe2lpd: Add DC state support
` [Intel-gfx] [PATCH v2 14/27] drm/i915/display: Remove FBC capability from fused off pipes
` [Intel-gfx] [PATCH v2 15/27] FIXME: drm/i915/xe2lpd: Add support for DP aux channels
` [Intel-gfx] [PATCH v2 16/27] drm/i915/xe2lpd: Handle port AUX interrupts
` [Intel-gfx] [PATCH v2 17/27] drm/i915/xe2lpd: Read pin assignment from IOM
` [Intel-gfx] [PATCH v2 18/27] drm/i915/xe2lpd: Enable odd size and panning for planar yuv
` [Intel-gfx] [PATCH v2 19/27] drm/i915/xe2lpd: Add support for HPD
` [Intel-gfx] [PATCH v2 20/27] drm/i915/xe2lpd: Extend Wa_15010685871
` [Intel-gfx] [PATCH v2 21/27] drm/i915/lnl: Add gmbus/ddc support
` [Intel-gfx] [PATCH v2 22/27] drm/i915/lnl: Add CDCLK table
` [Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL
` [Intel-gfx] [PATCH v2 24/27] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
` [Intel-gfx] [PATCH v2 25/27] drm/i915/lnl: Add support for CDCLK initialization sequence
` [Intel-gfx] [PATCH v2 26/27] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
` [Intel-gfx] [PATCH v2 27/27] drm/i915/xe2lpd: Update mbus on post plane updates
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display (rev3)
[Intel-gfx] [PATCH v8 0/3] Apply Wa_16018031267 / Wa_16018063123
2023-09-08 0:29 UTC (4+ messages)
` [Intel-gfx] [PATCH v8 1/3] drm/i915: Reserve some kernel space per vm
` [Intel-gfx] [PATCH v8 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
` [Intel-gfx] [PATCH v8 3/3] drm/i915: Set copy engine arbitration "
[Intel-gfx] [PATCH v7 0/2] Apply Wa_16018031267 / Wa_16018063123
2023-09-07 23:36 UTC (7+ messages)
` [Intel-gfx] [PATCH v7 1/2] drm/i915: Add WABB blit for "
` [Intel-gfx] [PATCH v7 2/2] drm/i915: Set copy engine arbitration "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply "
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/mtl: Drop Wa_14017240301
2023-09-07 23:31 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Drop Wa_14017240301 (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915: Add Wa_14015150844
2023-09-07 23:15 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add Wa_14015150844 (rev4)
[Intel-gfx] [PATCH] drm/i915: Added Wa_18022495364
2023-09-07 22:27 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [PATCH v3] drm/i915: Run relevant bits of debugfs drop_caches per GT
2023-09-07 21:49 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Run relevant bits of debugfs drop_caches per GT (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v2] drm/i915/huc: silence injected failure in the load via GSC path
2023-09-07 21:13 UTC (2+ messages)
[Intel-gfx] [PATCH 0/4] Separate display workarounds from clock gating
2023-09-07 20:22 UTC (13+ messages)
` [Intel-gfx] [PATCH 1/4] drm/i915: Stop forcing clock gating init for future platforms
` [Intel-gfx] [PATCH 2/4] drm/i915/adlp: Stop calling gen12lp_init_clock_gating()
` [Intel-gfx] [PATCH 3/4] drm/i915/display: Extract display workarounds from clock gating init
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH 4/4] drm/i915/display: Apply workarounds during display init
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Separate display workarounds from clock gating
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Separate display workarounds from clock gating (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Separate display workarounds from clock gating (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [RFC 00/33] Add Support for Plane Color Pipeline
2023-09-07 20:08 UTC (9+ messages)
` [Intel-gfx] [RFC 01/33] drm/doc/rfc: Add RFC document for proposed "
[Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff
2023-09-07 18:49 UTC (19+ messages)
` [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section
` [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention
` [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets
` [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour
` [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates
` [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
` [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range
` [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes
` [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary
[Intel-gfx] [PATCH 0/3] drm/i915: Slightly more atomic multi-pipe commits
2023-09-07 16:50 UTC (6+ messages)
` [Intel-gfx] [PATCH 1/3] drm/i915: Drop redundant !modeset check
` [Intel-gfx] [PATCH 2/3] drm/i915: Split intel_update_crtc() into two parts
` [Intel-gfx] [PATCH 3/3] drm/i915: Do plane/etc. updates more atomically across pipes
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Slightly more atomic multi-pipe commits
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [RFC, drm-misc-next v4 0/9] PCI/VGA: Allowing the user to select the primary video adapter at boot time
2023-09-07 16:33 UTC (26+ messages)
` [Intel-gfx] [RFC, drm-misc-next v4 3/9] drm/radeon: Implement .be_primary() callback
` [Intel-gfx] [Nouveau] [RFC, drm-misc-next v4 0/9] PCI/VGA: Allowing the user to select the primary video adapter at boot time
[Intel-gfx] [PATCH 0/5] Update GGTT with MI_UPDATE_GTT on MTL
2023-09-07 13:48 UTC (14+ messages)
` [Intel-gfx] [PATCH 1/5] drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex
` [Intel-gfx] [PATCH 2/5] drm/i915: Create a kernel context for GGTT updates
` [Intel-gfx] [PATCH 3/5] drm/i915: Implement __for_each_sgt_daddr_next
` [Intel-gfx] [PATCH 4/5] drm/i915: Implement GGTT update method with MI_UPDATE_GTT
` [Intel-gfx] ✗ Fi.CI.BAT: failure for Update GGTT with MI_UPDATE_GTT on MTL
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 0/6] drm/edid: split out drm_eld.[ch], add some SAD helpers
2023-09-07 13:37 UTC (12+ messages)
` [Intel-gfx] [PATCH 1/6] drm/edid: split out drm_eld.h from drm_edid.h
` [Intel-gfx] [PATCH 2/6] drm/eld: replace uint8_t with u8
` [Intel-gfx] [PATCH 3/6] drm/edid: include drm_eld.h only where required
` [Intel-gfx] [PATCH 4/6] drm/edid: use a temp variable for sads to drop one level of dereferences
` [Intel-gfx] [PATCH 5/6] drm/edid: add helpers to get/set struct cea_sad from/to 3-byte sad
` [Intel-gfx] [PATCH 6/6] drm/eld: add helpers to modify the SADs of an ELD
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: split out drm_eld.[ch], add some SAD helpers
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH v2] drm/i915: Run relevant bits of debugfs drop_caches per GT
2023-09-07 13:37 UTC (6+ messages)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for "
[Intel-gfx] [PATCH] drm/i915: Only check eDP HPD when AUX CH is shared
2023-09-07 13:11 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [PATCH 0/2] Drop caches per GT
2023-09-07 9:57 UTC (5+ messages)
` [Intel-gfx] [PATCH 1/2] drm/i915: Split gt cache flushing and gt idling functions
` [Intel-gfx] ✓ Fi.CI.IGT: success for Drop caches per GT (rev2)
[Intel-gfx] [PATCH 0/3] Get optimal audio frequency and channels
2023-09-07 9:35 UTC (6+ messages)
` [Intel-gfx] [PATCH 2/3] drm: Add Wrapper Functions for ELD SAD Extraction
` [Intel-gfx] [PATCH 3/3] drm/i915/display: Configure and initialize HDMI audio capabilities
[Intel-gfx] [PULL] drm-misc-fixes
2023-09-07 7:44 UTC
[Intel-gfx] [PATCH v3 0/5] drm/drm_dbg: add trailing newlines where missing
2023-09-07 6:51 UTC (13+ messages)
` [Intel-gfx] [PATCH v3 1/5] drm/connector: add trailing newlines to drm_dbg msgs
` [Intel-gfx] [PATCH v3 2/5] drm/kmb: "
` [Intel-gfx] [PATCH v3 3/5] drm/msm: "
` [Intel-gfx] [PATCH v3 4/5] drm/vc4: "
` [Intel-gfx] [PATCH v3 5/5] drm/Makefile: use correct ccflags-y syntax
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/drm_dbg: add trailing newlines where missing
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 0/8] drm/i915/dsc: cleanups
2023-09-07 5:51 UTC (16+ messages)
` [Intel-gfx] [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write helpers
` [Intel-gfx] [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value
` [Intel-gfx] [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() "
` [Intel-gfx] [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write()
` [Intel-gfx] [PATCH 6/8] drm/i915/dsc: clean up pps comments
` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content macros
` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1
[Intel-gfx] [PATCH v4 0/3] drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
2023-09-07 5:16 UTC (8+ messages)
` [Intel-gfx] [PATCH v4 1/3] drm/i915/pxp/mtl: Update pxp-firmware response timeout
` [Intel-gfx] [PATCH v4 2/3] drm/i915/pxp/mtl: Update pxp-firmware packet size
` [Intel-gfx] [PATCH v4 3/3] drm/i915/lrc: User PXP contexts requires runalone bit in lrc
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v1 1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events
2023-09-07 5:00 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v1,1/1] "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/mtl: Drop force_probe requirement
2023-09-07 2:05 UTC (4+ messages)
[Intel-gfx] [PATCH v4 0/3] drm/i915/pxp/mtl: Update gsc-heci cmd submission to align with fw/hw spec
2023-09-06 23:47 UTC
[Intel-gfx] [PATCH v6 0/2] Apply Wa_16018031267 / Wa_16018063123
2023-09-06 21:37 UTC (7+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [CI] PR for MTL HuC v8.5.4
2023-09-06 21:04 UTC
[Intel-gfx] [PATCH v5] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
2023-09-06 18:49 UTC (11+ messages)
[Intel-gfx] [PATCH v2 0/6] drm_dbg: add trailing newlines where missing
2023-09-06 18:06 UTC (5+ messages)
` [Intel-gfx] [PATCH v2 3/6] drm_dbg: add trailing newlines to msgs
[Intel-gfx] [PATCH v2] drm/i915/cx0: Check and increase msgbus timeout threshold
2023-09-06 17:45 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cx0: Check and increase msgbus timeout threshold (rev3)
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