[Intel-gfx] [PATCH 0/8] drm/i915/dsc: cleanups

[Intel-gfx] [PATCH 0/8] drm/i915/dsc: cleanups

[Jani Nikula]

Jani Nikula (8):
  drm/i915/dsc: improve clarify of the pps reg read/write helpers
  drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value
  drm/i915/dsc: have intel_dsc_pps_read() return the value
  drm/i915/dsc: rename pps write to intel_dsc_pps_write()
  drm/i915/dsc: drop redundant = 0 assignments
  drm/i915/dsc: clean up pps comments
  drm/i915/dsc: add the PPS number to the register content macros
  drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1

 drivers/gpu/drm/i915/display/intel_vdsc.c     | 362 +++++++++---------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 184 ++++-----
 2 files changed, 272 insertions(+), 274 deletions(-)

-- 
2.39.2

[Intel-gfx] [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write helpers

[Jani Nikula]

Make it clear what's the number of vdsc per pipe, and what's the number
of registers to grab. Have intel_dsc_get_pps_reg() return the registers
it knows even if the requested amount is bigger.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 40 ++++++++++++-----------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b24601d0b2c5..14317bb6d3df 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -372,7 +372,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 }
 
 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
-				  i915_reg_t *dsc_reg, int vdsc_per_pipe)
+				  i915_reg_t *dsc_reg, int dsc_reg_num)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -381,16 +381,12 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
 
 	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
 
-	switch (vdsc_per_pipe) {
-	case 2:
+	if (dsc_reg_num >= 3)
+		MISSING_CASE(dsc_reg_num);
+	if (dsc_reg_num >= 2)
 		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
-		fallthrough;
-	case 1:
+	if (dsc_reg_num >= 1)
 		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
-		break;
-	default:
-		MISSING_CASE(vdsc_per_pipe);
-	}
 }
 
 static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
@@ -399,13 +395,16 @@ static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	i915_reg_t dsc_reg[2];
-	int i, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	int i, vdsc_per_pipe, dsc_reg_num;
+
+	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
 
-	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe);
+	drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
 
-	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
+	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
 
-	for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++)
+	for (i = 0; i < dsc_reg_num; i++)
 		intel_de_write(i915, dsc_reg[i], pps_val);
 }
 
@@ -815,16 +814,19 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	const int vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 	i915_reg_t dsc_reg[2];
-	int i;
+	int i, vdsc_per_pipe, dsc_reg_num;
 
-	*pps_val = 0;
-	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe);
+	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
 
-	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
+	drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
+
+	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
+
+	*pps_val = 0;
 
-	for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) {
+	for (i = 0; i < dsc_reg_num; i++) {
 		u32 pps_temp;
 
 		pps_temp = intel_de_read(i915, dsc_reg[i]);
-- 
2.39.2

[Intel-gfx] [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value

[Jani Nikula]

Register read functions usually return the value instead of passing via
pointer parameters. The calling code becomes easier to read.

Make the name conform to existing style better while at it.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 36 ++++++++++++-----------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 14317bb6d3df..abb2c4370231 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -840,15 +840,17 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
 	return true;
 }
 
-static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
-					      int pps, u32 *pps_val)
+static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	u32 val;
 	int ret;
 
-	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+	ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
 	drm_WARN_ON(&i915->drm, !ret);
+
+	return val;
 }
 
 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
@@ -860,7 +862,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	u32 pps_temp;
 
 	/* PPS_0 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
 
 	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
 	vdsc_cfg->line_buf_depth =
@@ -873,7 +875,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
 
 	/* PPS_1 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
 
 	vdsc_cfg->bits_per_pixel = pps_temp;
 
@@ -883,31 +885,31 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
 
 	/* PPS_2 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
 
 	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
 	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
 
 	/* PPS_3 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
 
 	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
 	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
 
 	/* PPS_4 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
 
 	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
 	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
 
 	/* PPS_5 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
 
 	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
 	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
 
 	/* PPS_6 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
 
 	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
 	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
@@ -915,41 +917,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
 
 	/* PPS_7 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
 
 	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
 	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
 
 	/* PPS_8 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
 
 	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
 	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
 
 	/* PPS_9 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
 
 	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
 
 	/* PPS_10 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
 
 	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
 	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
 
 	/* PPS_16 */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
+	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
 
 	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
 
 	if (DISPLAY_VER(i915) >= 14) {
 		/* PPS_17 */
-		intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
+		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
 
 		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
 
 		/* PPS_18 */
-		intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
+		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
 
 		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
 		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
-- 
2.39.2

[Intel-gfx] [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() return the value

[Jani Nikula]

Register read functions usually return the value instead of passing via
pointer parameters. Return the multiple register verification results
via a pointer parameter, which can also be NULL to skip the extra
checks.

Make the name conform to existing style better while at it.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 32 ++++++++++++++---------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index abb2c4370231..b0be6615a865 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -809,13 +809,14 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 	}
 }
 
-static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
-				   int pps, u32 *pps_val)
+static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
+			      bool *check_equal)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	i915_reg_t dsc_reg[2];
 	int i, vdsc_per_pipe, dsc_reg_num;
+	u32 val = 0;
 
 	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
@@ -824,20 +825,25 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
 
 	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
 
-	*pps_val = 0;
+	if (check_equal)
+		*check_equal = true;
 
 	for (i = 0; i < dsc_reg_num; i++) {
-		u32 pps_temp;
+		u32 tmp;
 
-		pps_temp = intel_de_read(i915, dsc_reg[i]);
+		tmp = intel_de_read(i915, dsc_reg[i]);
 
-		if (i == 0)
-			*pps_val = pps_temp;
-		else if (pps_temp != *pps_val)
-			return false;
+		if (i == 0) {
+			val = tmp;
+		} else if (check_equal && tmp != val) {
+			*check_equal = false;
+			break;
+		} else if (!check_equal) {
+			break;
+		}
 	}
 
-	return true;
+	return val;
 }
 
 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
@@ -845,10 +851,10 @@ static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, in
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	u32 val;
-	int ret;
+	bool all_equal;
 
-	ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
-	drm_WARN_ON(&i915->drm, !ret);
+	val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
+	drm_WARN_ON(&i915->drm, !all_equal);
 
 	return val;
 }
-- 
2.39.2

[Intel-gfx] [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write()

[Jani Nikula]

Make the function name conform to existing style better.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b0be6615a865..4086dbb25ca5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -389,8 +389,8 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
 		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
 }
 
-static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
-				    int pps, u32 pps_val)
+static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
+				int pps, u32 pps_val)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -443,41 +443,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->vbr_enable)
 		pps_val |= DSC_VBR_ENABLE;
 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
+	intel_dsc_pps_write(crtc_state, 0, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_1 registers */
 	pps_val = 0;
 	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
+	intel_dsc_pps_write(crtc_state, 1, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_2 registers */
 	pps_val = 0;
 	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 2, pps_val);
+	intel_dsc_pps_write(crtc_state, 2, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_3 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 3, pps_val);
+	intel_dsc_pps_write(crtc_state, 3, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_4 registers */
 	pps_val = 0;
 	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 4, pps_val);
+	intel_dsc_pps_write(crtc_state, 4, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_5 registers */
 	pps_val = 0;
 	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 5, pps_val);
+	intel_dsc_pps_write(crtc_state, 5, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_6 registers */
 	pps_val = 0;
@@ -486,28 +486,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 6, pps_val);
+	intel_dsc_pps_write(crtc_state, 6, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_7 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 7, pps_val);
+	intel_dsc_pps_write(crtc_state, 7, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_8 registers */
 	pps_val = 0;
 	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 8, pps_val);
+	intel_dsc_pps_write(crtc_state, 8, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
 	pps_val = 0;
 	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 9, pps_val);
+	intel_dsc_pps_write(crtc_state, 9, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_10 registers */
 	pps_val = 0;
@@ -516,7 +516,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 10, pps_val);
+	intel_dsc_pps_write(crtc_state, 10, pps_val);
 
 	/* Populate Picture parameter set 16 */
 	pps_val = 0;
@@ -526,21 +526,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 					vdsc_cfg->slice_height);
 	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
-	intel_dsc_write_pps_reg(crtc_state, 16, pps_val);
+	intel_dsc_pps_write(crtc_state, 16, pps_val);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		/* Populate PICTURE_PARAMETER_SET_17 registers */
 		pps_val = 0;
 		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
-		intel_dsc_write_pps_reg(crtc_state, 17, pps_val);
+		intel_dsc_pps_write(crtc_state, 17, pps_val);
 
 		/* Populate PICTURE_PARAMETER_SET_18 registers */
 		pps_val = 0;
 		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
 			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
-		intel_dsc_write_pps_reg(crtc_state, 18, pps_val);
+		intel_dsc_pps_write(crtc_state, 18, pps_val);
 	}
 
 	/* Populate the RC_BUF_THRESH registers */
-- 
2.39.2

[Intel-gfx] [PATCH 5/8] drm/i915/dsc: drop redundant = 0 assignments

[Jani Nikula]

Directly assign the values instead of first assigning 0 and then |= the
values.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 43 ++++++++---------------
 1 file changed, 15 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 4086dbb25ca5..73bfa4d6633d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -415,7 +415,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
-	u32 pps_val = 0;
+	u32 pps_val;
 	u32 rc_buf_thresh_dword[4];
 	u32 rc_range_params_dword[8];
 	int i = 0;
@@ -446,42 +446,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	intel_dsc_pps_write(crtc_state, 0, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_1 registers */
-	pps_val = 0;
-	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 1, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_2 registers */
-	pps_val = 0;
-	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
+	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 2, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_3 registers */
-	pps_val = 0;
-	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
+	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 3, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_4 registers */
-	pps_val = 0;
-	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
+	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 4, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_5 registers */
-	pps_val = 0;
-	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
+	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 5, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_6 registers */
-	pps_val = 0;
-	pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
+	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
@@ -489,29 +483,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	intel_dsc_pps_write(crtc_state, 6, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_7 registers */
-	pps_val = 0;
-	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
+	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 7, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_8 registers */
-	pps_val = 0;
-	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
+	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 8, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
-	pps_val = 0;
-	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
+	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 9, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_10 registers */
-	pps_val = 0;
-	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
+	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
@@ -519,8 +509,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	intel_dsc_pps_write(crtc_state, 10, pps_val);
 
 	/* Populate Picture parameter set 16 */
-	pps_val = 0;
-	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
+	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 				   vdsc_cfg->slice_width) |
 		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
@@ -530,15 +519,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		/* Populate PICTURE_PARAMETER_SET_17 registers */
-		pps_val = 0;
-		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
 		intel_dsc_pps_write(crtc_state, 17, pps_val);
 
 		/* Populate PICTURE_PARAMETER_SET_18 registers */
-		pps_val = 0;
-		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
-			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
 		intel_dsc_pps_write(crtc_state, 18, pps_val);
 	}
-- 
2.39.2

[Intel-gfx] [PATCH 6/8] drm/i915/dsc: clean up pps comments

[Jani Nikula]

Unify comments to be the simple "PPS n" instead of all sorts of
variants.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 56 +++++++++----------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 29 +++++-----
 2 files changed, 42 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 73bfa4d6633d..4855514d7b09 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -422,7 +422,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
 	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
-	/* Populate PICTURE_PARAMETER_SET_0 registers */
+	/* PPS 0 */
 	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
@@ -445,36 +445,36 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 0, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_1 registers */
+	/* PPS 1 */
 	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 1, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_2 registers */
+	/* PPS 2 */
 	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 2, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_3 registers */
+	/* PPS 3 */
 	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 3, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_4 registers */
+	/* PPS 4 */
 	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 4, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_5 registers */
+	/* PPS 5 */
 	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 5, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_6 registers */
+	/* PPS 6 */
 	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
@@ -482,25 +482,25 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 6, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_7 registers */
+	/* PPS 7 */
 	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 7, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_8 registers */
+	/* PPS 8 */
 	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 8, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_9 registers */
+	/* PPS 9 */
 	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 9, pps_val);
 
-	/* Populate PICTURE_PARAMETER_SET_10 registers */
+	/* PPS 10 */
 	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
@@ -508,7 +508,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 10, pps_val);
 
-	/* Populate Picture parameter set 16 */
+	/* PPS 16 */
 	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 				   vdsc_cfg->slice_width) |
@@ -518,12 +518,12 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	intel_dsc_pps_write(crtc_state, 16, pps_val);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
-		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		/* PPS 17 */
 		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
 		intel_dsc_pps_write(crtc_state, 17, pps_val);
 
-		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		/* PPS 18 */
 		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
 			DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
@@ -854,7 +854,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
 	u32 pps_temp;
 
-	/* PPS_0 */
+	/* PPS 0 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
 
 	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
@@ -867,7 +867,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
 	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
 
-	/* PPS_1 */
+	/* PPS 1 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
 
 	vdsc_cfg->bits_per_pixel = pps_temp;
@@ -877,31 +877,31 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
 
-	/* PPS_2 */
+	/* PPS 2 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
 
 	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
 	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
 
-	/* PPS_3 */
+	/* PPS 3 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
 
 	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
 	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
 
-	/* PPS_4 */
+	/* PPS 4 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
 
 	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
 	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
 
-	/* PPS_5 */
+	/* PPS 5 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
 
 	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
 	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
 
-	/* PPS_6 */
+	/* PPS 6 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
 
 	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
@@ -909,41 +909,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
 	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
 
-	/* PPS_7 */
+	/* PPS 7 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
 
 	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
 	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
 
-	/* PPS_8 */
+	/* PPS 8 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
 
 	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
 	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
 
-	/* PPS_9 */
+	/* PPS 9 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
 
 	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
 
-	/* PPS_10 */
+	/* PPS 10 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
 
 	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
 	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
 
-	/* PPS_16 */
+	/* PPS 16 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
 
 	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
 
 	if (DISPLAY_VER(i915) >= 14) {
-		/* PPS_17 */
+		/* PPS 17 */
 		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
 
 		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
 
-		/* PPS_18 */
+		/* PPS 18 */
 		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
 
 		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 5cbcbd9db7b1..58d282dcfc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -72,7 +72,7 @@
 #define  ICL_DSC0_PPS(pipe, pps)		_MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
 #define  ICL_DSC1_PPS(pipe, pps)		_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
 
-/* PPS0 */
+/* PPS 0 */
 #define  DSC_NATIVE_422_ENABLE		BIT(23)
 #define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
@@ -87,22 +87,22 @@
 #define  DSC_VER_MIN_SHIFT		4
 #define  DSC_VER_MAJ			(0x1 << 0)
 
-/* PPS1 */
+/* PPS 1 */
 #define  DSC_BPP(bpp)				((bpp) << 0)
 
-/* PPS2 */
+/* PPS 2 */
 #define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
 #define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
 #define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
 #define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
 
-/* PPS3 */
+/* PPS 3 */
 #define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)
 #define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
 #define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
 #define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
 
-/* PPS4 */
+/* PPS 4 */
 #define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)
 #define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
@@ -110,13 +110,13 @@
 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
 							       xmit_delay)
 
-/* PPS5 */
+/* PPS 5 */
 #define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)
 #define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
 #define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
 #define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
 
-/* PPS6 */
+/* PPS 6 */
 #define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
 #define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
 #define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
@@ -128,13 +128,13 @@
 #define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
 							       value)
 
-/* PPS7 */
+/* PPS 7 */
 #define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
 #define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
 #define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
 							       bpg_offset)
-/* PPS8 */
+/* PPS 8 */
 #define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
 #define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
 #define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
@@ -142,7 +142,7 @@
 #define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
 							       final_offset)
 
-/* PPS9 */
+/* PPS 9 */
 #define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
 #define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
@@ -150,7 +150,7 @@
 #define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
 							       rc_model_size)
 
-/* PPS10 */
+/* PPS 10 */
 #define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)
 #define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)
 #define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)
@@ -162,7 +162,7 @@
 #define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
 #define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
 
-/* PPS16 */
+/* PPS 16 */
 #define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)
 #define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)
 #define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)
@@ -173,12 +173,11 @@
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
 								       slice_chunk_size)
 
-/* MTL Display Stream Compression registers */
-/* PPS17 */
+/* PPS 17 (MTL+) */
 #define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
 #define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
 
-/* PPS18 */
+/* PPS 18 (MTL+) */
 #define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
 #define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
 #define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
-- 
2.39.2

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content macros

[Jani Nikula]

Improve clarity by specifying the PPS number in the register content
macros. It's easier to notice if macros are being used for the wrong
register.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

Probably easiest to review by applying and using 'git show --word-diff'
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 146 ++++++++---------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 152 +++++++++---------
 2 files changed, 149 insertions(+), 149 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 4855514d7b09..126aff804e33 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -423,109 +423,109 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	/* PPS 0 */
-	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
-		DSC_VER_MIN_SHIFT |
-		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
-		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+		DSC_PPS0_VER_MIN_SHIFT |
+		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
+		vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
 	if (vdsc_cfg->dsc_version_minor == 2) {
-		pps_val |= DSC_ALT_ICH_SEL;
+		pps_val |= DSC_PPS0_ALT_ICH_SEL;
 		if (vdsc_cfg->native_420)
-			pps_val |= DSC_NATIVE_420_ENABLE;
+			pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
 		if (vdsc_cfg->native_422)
-			pps_val |= DSC_NATIVE_422_ENABLE;
+			pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
 	}
 	if (vdsc_cfg->block_pred_enable)
-		pps_val |= DSC_BLOCK_PREDICTION;
+		pps_val |= DSC_PPS0_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
-		pps_val |= DSC_COLOR_SPACE_CONVERSION;
+		pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
 	if (vdsc_cfg->simple_422)
-		pps_val |= DSC_422_ENABLE;
+		pps_val |= DSC_PPS0_422_ENABLE;
 	if (vdsc_cfg->vbr_enable)
-		pps_val |= DSC_VBR_ENABLE;
+		pps_val |= DSC_PPS0_VBR_ENABLE;
 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 0, pps_val);
 
 	/* PPS 1 */
-	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
+	pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 1, pps_val);
 
 	/* PPS 2 */
-	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
-		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
+	pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
+		DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 2, pps_val);
 
 	/* PPS 3 */
-	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
-		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
+	pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
+		DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 3, pps_val);
 
 	/* PPS 4 */
-	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
-		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
+	pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
+		DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 4, pps_val);
 
 	/* PPS 5 */
-	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
-		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
+	pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
+		DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 5, pps_val);
 
 	/* PPS 6 */
-	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
-		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
-		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
-		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
+	pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
+		DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
+		DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
+		DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 6, pps_val);
 
 	/* PPS 7 */
-	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
-		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
+	pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
+		DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 7, pps_val);
 
 	/* PPS 8 */
-	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
-		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
+	pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
+		DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 8, pps_val);
 
 	/* PPS 9 */
-	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
-		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
+	pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
+		DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 9, pps_val);
 
 	/* PPS 10 */
-	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
-		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
-		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
-		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
+	pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
+		DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
+		DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
+		DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 10, pps_val);
 
 	/* PPS 16 */
-	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
-		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
-				   vdsc_cfg->slice_width) |
-		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
-					vdsc_cfg->slice_height);
+	pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
+		DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
+					 vdsc_cfg->slice_width) |
+		DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
+					      vdsc_cfg->slice_height);
 	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
 	intel_dsc_pps_write(crtc_state, 16, pps_val);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		/* PPS 17 */
-		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
 		intel_dsc_pps_write(crtc_state, 17, pps_val);
 
 		/* PPS 18 */
-		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
-			DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
 		intel_dsc_pps_write(crtc_state, 18, pps_val);
 	}
@@ -857,15 +857,15 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	/* PPS 0 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
 
-	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
+	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT;
 	vdsc_cfg->line_buf_depth =
-		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;
-	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
-	vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
-	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
-	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
-	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
-	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
+		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
+	vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
+	vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
+	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
+	vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
+	vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
+	vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
 
 	/* PPS 1 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
@@ -880,74 +880,74 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	/* PPS 2 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
 
-	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
-	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
+	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) / num_vdsc_instances;
+	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);
 
 	/* PPS 3 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
 
-	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
-	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
+	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
+	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);
 
 	/* PPS 4 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
 
-	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
-	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
+	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
+	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
 
 	/* PPS 5 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
 
-	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
-	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
+	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
+	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
 
 	/* PPS 6 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
 
-	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
-	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
-	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
-	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
+	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
+	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
+	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
 
 	/* PPS 7 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
 
-	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
-	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
 
 	/* PPS 8 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
 
-	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
-	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
+	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
+	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);
 
 	/* PPS 9 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
 
-	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
+	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);
 
 	/* PPS 10 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
 
-	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
-	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
+	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
+	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
 
 	/* PPS 16 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
 
-	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
+	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
 
 	if (DISPLAY_VER(i915) >= 14) {
 		/* PPS 17 */
 		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
 
-		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
+		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
 
 		/* PPS 18 */
 		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
 
-		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
-		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
+		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
+		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 58d282dcfc6f..92782de2b309 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -73,115 +73,115 @@
 #define  ICL_DSC1_PPS(pipe, pps)		_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
 
 /* PPS 0 */
-#define  DSC_NATIVE_422_ENABLE		BIT(23)
-#define  DSC_NATIVE_420_ENABLE		BIT(22)
-#define  DSC_ALT_ICH_SEL		(1 << 20)
-#define  DSC_VBR_ENABLE			(1 << 19)
-#define  DSC_422_ENABLE			(1 << 18)
-#define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
-#define  DSC_BLOCK_PREDICTION		(1 << 16)
-#define  DSC_LINE_BUF_DEPTH_SHIFT	12
-#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)
-#define  DSC_BPC_SHIFT			8
-#define  DSC_BPC_MASK			REG_GENMASK(11, 8)
-#define  DSC_VER_MIN_SHIFT		4
-#define  DSC_VER_MAJ			(0x1 << 0)
+#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)
+#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)
+#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)
+#define   DSC_PPS0_VBR_ENABLE			(1 << 19)
+#define   DSC_PPS0_422_ENABLE			(1 << 18)
+#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)
+#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)
+#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12
+#define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15, 12)
+#define   DSC_PPS0_BPC_SHIFT			8
+#define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)
+#define   DSC_PPS0_VER_MIN_SHIFT		4
+#define   DSC_PPS0_VER_MAJ			(0x1 << 0)
 
 /* PPS 1 */
-#define  DSC_BPP(bpp)				((bpp) << 0)
+#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)
 
 /* PPS 2 */
-#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
-#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
-#define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
-#define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
+#define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
+#define   DSC_PPS2_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS2_PIC_WIDTH(pic_width)		REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
+#define   DSC_PPS2_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
 
 /* PPS 3 */
-#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)
-#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
-#define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
-#define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
+#define   DSC_PPS3_SLICE_WIDTH_MASK		REG_GENMASK(31, 16)
+#define   DSC_PPS3_SLICE_HEIGHT_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS3_SLICE_WIDTH(slice_width)	REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
+#define   DSC_PPS3_SLICE_HEIGHT(slice_height)	REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
 
 /* PPS 4 */
-#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)
-#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
-#define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
+#define   DSC_PPS4_INITIAL_DEC_DELAY_MASK	REG_GENMASK(31, 16)
+#define   DSC_PPS4_INITIAL_XMIT_DELAY_MASK	REG_GENMASK(9, 0)
+#define   DSC_PPS4_INITIAL_DEC_DELAY(dec_delay)	REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
 							       dec_delay)
-#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
-							       xmit_delay)
+#define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)	REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
+								       xmit_delay)
 
 /* PPS 5 */
-#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)
-#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
-#define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
-#define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
+#define   DSC_PPS5_SCALE_DEC_INT_MASK		REG_GENMASK(27, 16)
+#define   DSC_PPS5_SCALE_INC_INT_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS5_SCALE_DEC_INT(scale_dec)	REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
+#define   DSC_PPS5_SCALE_INC_INT(scale_inc)	REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
 
 /* PPS 6 */
-#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
-#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
-#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
-#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)
-#define  DSC_FLATNESS_MAX_QP(max_qp)		REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
-#define  DSC_FLATNESS_MIN_QP(min_qp)		REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
-#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
-							       offset)
-#define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
+#define   DSC_PPS6_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
+#define   DSC_PPS6_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
+#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK	REG_GENMASK(12, 8)
+#define   DSC_PPS6_INITIAL_SCALE_VALUE_MASK	REG_GENMASK(5, 0)
+#define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
+#define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
+#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
+								       offset)
+#define   DSC_PPS6_INITIAL_SCALE_VALUE(value)	REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
 							       value)
 
 /* PPS 7 */
-#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
-#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
-#define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
-#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
+#define   DSC_PPS7_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
+#define   DSC_PPS7_SLICE_BPG_OFFSET_MASK	REG_GENMASK(15, 0)
+#define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
+#define   DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
 							       bpg_offset)
 /* PPS 8 */
-#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
-#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
-#define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
-							       initial_offset)
-#define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
+#define   DSC_PPS8_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
+#define   DSC_PPS8_FINAL_OFFSET_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS8_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
+								       initial_offset)
+#define   DSC_PPS8_FINAL_OFFSET(final_offset)	REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
 							       final_offset)
 
 /* PPS 9 */
-#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
-#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
-#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
+#define   DSC_PPS9_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
+#define   DSC_PPS9_RC_MODEL_SIZE_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
 							       rc_edge_fact)
-#define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
+#define   DSC_PPS9_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
 							       rc_model_size)
 
 /* PPS 10 */
-#define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)
-#define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)
-#define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)
-#define  DSC_RC_QUANT_INC_LIMIT0_MASK			REG_GENMASK(4, 0)
-#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \
+#define   DSC_PPS10_RC_TGT_OFF_LOW_MASK		REG_GENMASK(23, 20)
+#define   DSC_PPS10_RC_TGT_OFF_HIGH_MASK	REG_GENMASK(19, 16)
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK	REG_GENMASK(12, 8)
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK	REG_GENMASK(4, 0)
+#define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
 								       rc_tgt_off_low)
-#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \
+#define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
 								       rc_tgt_off_high)
-#define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
-#define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
 
 /* PPS 16 */
-#define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)
-#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)
-#define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)
-#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \
-								       slice_row_per_frame)
-#define  DSC_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
-								       slice_per_line)
-#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
-								       slice_chunk_size)
+#define   DSC_PPS16_SLICE_ROW_PR_FRME_MASK	REG_GENMASK(31, 20)
+#define   DSC_PPS16_SLICE_PER_LINE_MASK		REG_GENMASK(18, 16)
+#define   DSC_PPS16_SLICE_CHUNK_SIZE_MASK	REG_GENMASK(15, 0)
+#define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
+									       slice_row_per_frame)
+#define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
+									       slice_per_line)
+#define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
+									       slice_chunk_size)
 
 /* PPS 17 (MTL+) */
-#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
-#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
+#define   DSC_PPS17_SL_BPG_OFFSET_MASK		REG_GENMASK(31, 27)
+#define   DSC_PPS17_SL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
 
 /* PPS 18 (MTL+) */
-#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
-#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
-#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
-#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
+#define   DSC_PPS18_NSL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
+#define   DSC_PPS18_SL_OFFSET_ADJ_MASK		REG_GENMASK(15, 0)
+#define   DSC_PPS18_NSL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
+#define   DSC_PPS18_SL_OFFSET_ADJ(offset)	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
 
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
-- 
2.39.2

[Intel-gfx] [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1

[Jani Nikula]

Use the register helper macros for PPS0 and PPS1 register contents.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 15 +++++------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 27 ++++++++++---------
 2 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 126aff804e33..5c00f7ccad7f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -423,10 +423,10 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
 
 	/* PPS 0 */
-	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
-		DSC_PPS0_VER_MIN_SHIFT |
-		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
-		vdsc_cfg->line_buf_depth << DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
+	pps_val = DSC_PPS0_VER_MAJOR(1) |
+		DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
+		DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
+		DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
 	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_PPS0_ALT_ICH_SEL;
 		if (vdsc_cfg->native_420)
@@ -857,9 +857,8 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	/* PPS 0 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
 
-	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK) >> DSC_PPS0_BPC_SHIFT;
-	vdsc_cfg->line_buf_depth =
-		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
+	vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
+	vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
 	vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
 	vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
 	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
@@ -870,7 +869,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	/* PPS 1 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
 
-	vdsc_cfg->bits_per_pixel = pps_temp;
+	vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
 
 	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 92782de2b309..64f440fdc22b 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -73,22 +73,25 @@
 #define  ICL_DSC1_PPS(pipe, pps)		_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
 
 /* PPS 0 */
-#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)
-#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)
-#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)
-#define   DSC_PPS0_VBR_ENABLE			(1 << 19)
-#define   DSC_PPS0_422_ENABLE			(1 << 18)
-#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)
-#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)
-#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12
+#define   DSC_PPS0_NATIVE_422_ENABLE		REG_BIT(23)
+#define   DSC_PPS0_NATIVE_420_ENABLE		REG_BIT(22)
+#define   DSC_PPS0_ALT_ICH_SEL			REG_BIT(20)
+#define   DSC_PPS0_VBR_ENABLE			REG_BIT(19)
+#define   DSC_PPS0_422_ENABLE			REG_BIT(18)
+#define   DSC_PPS0_COLOR_SPACE_CONVERSION	REG_BIT(17)
+#define   DSC_PPS0_BLOCK_PREDICTION		REG_BIT(16)
 #define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15, 12)
-#define   DSC_PPS0_BPC_SHIFT			8
+#define   DSC_PPS0_LINE_BUF_DEPTH(depth)	REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
 #define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)
-#define   DSC_PPS0_VER_MIN_SHIFT		4
-#define   DSC_PPS0_VER_MAJ			(0x1 << 0)
+#define   DSC_PPS0_BPC(bpc)			REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
+#define   DSC_PPS0_VER_MINOR_MASK		REG_GENMASK(7, 4)
+#define   DSC_PPS0_VER_MINOR(minor)		REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
+#define   DSC_PPS0_VER_MAJOR_MASK		REG_GENMASK(3, 0)
+#define   DSC_PPS0_VER_MAJOR(major)		REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
 
 /* PPS 1 */
-#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)
+#define   DSC_PPS1_BPP_MASK			REG_GENMASK(9, 0)
+#define   DSC_PPS1_BPP(bpp)			REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
 
 /* PPS 2 */
 #define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
-- 
2.39.2

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsc: cleanups

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: cleanups
URL   : https://patchwork.freedesktop.org/series/123291/
State : warning

== Summary ==

Error: dim checkpatch failed
485ced3f5bf8 drm/i915/dsc: improve clarify of the pps reg read/write helpers
21be8697dfba drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value
97b57a727048 drm/i915/dsc: have intel_dsc_pps_read() return the value
76972ba1a5e1 drm/i915/dsc: rename pps write to intel_dsc_pps_write()
8fbce99af540 drm/i915/dsc: drop redundant = 0 assignments
2f5aa6719445 drm/i915/dsc: clean up pps comments
f0a412705ae1 drm/i915/dsc: add the PPS number to the register content macros
-:236: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#236: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:908:
+	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);

-:267: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:932:
+	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);

-:268: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#268: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:933:
+	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);

-:281: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#281: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:944:
+		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);

-:289: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#289: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:950:
+		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);

-:349: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#349: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:102:
+#define   DSC_PPS3_SLICE_WIDTH(slice_width)	REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)

-:350: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#350: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:103:
+#define   DSC_PPS3_SLICE_HEIGHT(slice_height)	REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)

-:362: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#362: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:110:
+#define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)	REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \

-:372: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#372: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:116:
+#define   DSC_PPS5_SCALE_DEC_INT(scale_dec)	REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)

-:373: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#373: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:117:
+#define   DSC_PPS5_SCALE_INC_INT(scale_inc)	REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)

-:389: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#389: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:124:
+#define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)

-:390: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#390: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:125:
+#define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)

-:391: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#391: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:126:
+#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \

-:403: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#403: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:134:
+#define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)

-:414: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#414: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:140:
+#define   DSC_PPS8_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \

-:441: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#441: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:158:
+#define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \

-:444: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#444: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:160:
+#define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \

-:448: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#448: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:162:
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)

-:449: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#449: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:163:
+#define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)

-:464: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#464: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:169:
+#define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \

-:466: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#466: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:171:
+#define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \

-:468: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#468: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:173:
+#define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \

-:484: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#484: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:183:
+#define   DSC_PPS18_NSL_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)

total: 0 errors, 23 warnings, 0 checks, 462 lines checked
7a424cc5c4fa drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 12084 bytes --]

== Series Details ==

Series: drm/i915/dsc: cleanups
URL   : https://patchwork.freedesktop.org/series/123291/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13599 -> Patchwork_123291v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/index.html

Participating hosts (38 -> 38)
------------------------------

  Additional (1): bat-dg2-8 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_123291v1 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - fi-hsw-4770:        [PASS][1] -> [FAIL][2] ([i915#8293])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-hsw-4770/boot.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/fi-hsw-4770/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap@basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - bat-dg2-8:          NOTRUN -> [SKIP][6] ([i915#5354] / [i915#7561])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-8:          NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-dg2-8:          NOTRUN -> [SKIP][8] ([i915#6645])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][9] ([i915#5190])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-8:          NOTRUN -> [SKIP][11] ([i915#4212]) +7 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg2-8:          NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-8:          NOTRUN -> [SKIP][14] ([i915#5274])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5:
    - bat-adlp-11:        [PASS][15] -> [DMESG-WARN][16] ([i915#4309])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-adlp-9:         NOTRUN -> [SKIP][17] ([i915#3546]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
    - bat-dg2-11:         NOTRUN -> [SKIP][18] ([i915#1845]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
    - bat-adlp-11:        [PASS][19] -> [ABORT][20] ([i915#8668])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [PASS][21] -> [ABORT][22] ([i915#8442] / [i915#8668])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  * igt@kms_psr@cursor_plane_move:
    - bat-dg2-8:          NOTRUN -> [SKIP][23] ([i915#1072]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_psr@cursor_plane_move.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg2-8:          NOTRUN -> [SKIP][24] ([i915#3555])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-8:          NOTRUN -> [SKIP][25] ([i915#3708])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-8:          NOTRUN -> [SKIP][26] ([i915#3708] / [i915#4077]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-8:          NOTRUN -> [SKIP][27] ([i915#3291] / [i915#3708]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-8/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - {bat-dg2-13}:       [DMESG-WARN][28] ([i915#7952]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-13/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - {bat-dg2-13}:       [DMESG-WARN][30] ([Intel XE#485]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6:
    - bat-adlp-11:        [FAIL][32] ([i915#6121]) -> [PASS][33] +4 other tests pass
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5:
    - bat-adlp-11:        [DMESG-WARN][34] ([i915#6868]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-bsw-nick:        [FAIL][36] -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
    - bat-adlp-11:        [ABORT][38] ([i915#8668]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4309]: https://gitlab.freedesktop.org/drm/intel/issues/4309
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668


Build changes
-------------

  * Linux: CI_DRM_13599 -> Patchwork_123291v1

  CI-20190529: 20190529
  CI_DRM_13599: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7468: 7468
  Patchwork_123291v1: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

7723adaf7efe drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1
c5f0a5c6637f drm/i915/dsc: add the PPS number to the register content macros
96e5f3065b4f drm/i915/dsc: clean up pps comments
8452dc36b6c0 drm/i915/dsc: drop redundant = 0 assignments
3c6e601beb18 drm/i915/dsc: rename pps write to intel_dsc_pps_write()
ee5c3f8d6fd7 drm/i915/dsc: have intel_dsc_pps_read() return the value
7a1f8440d751 drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value
7543e03fc272 drm/i915/dsc: improve clarify of the pps reg read/write helpers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/index.html

[-- Attachment #2: Type: text/html, Size: 13864 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsc: cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 44514 bytes --]

== Series Details ==

Series: drm/i915/dsc: cleanups
URL   : https://patchwork.freedesktop.org/series/123291/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13599_full -> Patchwork_123291v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_123291v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][1] ([i915#8411]) +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [PASS][2] -> [INCOMPLETE][3] ([i915#6311])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-11/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-snb:          NOTRUN -> [DMESG-WARN][4] ([i915#8841]) +5 other tests dmesg-warn
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb6/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb6/igt@gem_ctx_persistence@engines-mixed.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#8555]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#280])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@hibernate:
    - shard-dg2:          [PASS][8] -> [ABORT][9] ([i915#7975] / [i915#8213])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-11/igt@gem_eio@hibernate.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-6/igt@gem_eio@hibernate.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          NOTRUN -> [FAIL][10] ([i915#8898])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb7/igt@gem_eio@reset-stress.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          [PASS][11] -> [FAIL][12] ([i915#5784]) +1 other test fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-14/igt@gem_eio@unwedge-stress.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-15/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#4812]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_capture@capture-invisible@lmem0:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#6334]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@gem_exec_capture@capture-invisible@lmem0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-rkl:          [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fence@syncobj-backward-timeline-chain-engines:
    - shard-snb:          NOTRUN -> [SKIP][17] ([fdo#109271]) +297 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb4/igt@gem_exec_fence@syncobj-backward-timeline-chain-engines.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#3539] / [i915#4852]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_gttfill@multigpu-basic:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#7697])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_exec_gttfill@multigpu-basic.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg2:          NOTRUN -> [SKIP][20] ([i915#3281]) +8 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#4537] / [i915#4812])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg2:          NOTRUN -> [ABORT][22] ([i915#7975] / [i915#8213])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4860])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_mmap_wc@bad-object:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#4083]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_mmap_wc@bad-object.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#3282]) +4 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#4270]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_pxp@display-protected-crc.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4079])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#3297]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-dg2:          NOTRUN -> [SKIP][29] ([i915#3297] / [i915#4880])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-dg2:          NOTRUN -> [FAIL][30] ([i915#3318])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_userptr_blits@vma-merge.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][31] ([i915#7061] / [i915#8617])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglu:         [PASS][32] -> [FAIL][33] ([i915#3989] / [i915#454])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-tglu-7/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#1937])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-dg1:          [PASS][35] -> [SKIP][36] ([i915#1397]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-19/igt@i915_pm_rpm@dpms-lpsp.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-14/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rpm@fences-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#4077]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@i915_pm_rpm@fences-dpms.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][38] -> [SKIP][39] ([i915#1397])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@i915_pm_rps@reset:
    - shard-tglu:         [PASS][40] -> [INCOMPLETE][41] ([i915#8320])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-tglu-10/igt@i915_pm_rps@reset.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-tglu-9/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-park@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#8925])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@i915_pm_rps@thresholds-park@gt0.html

  * igt@i915_suspend@sysfs-reader:
    - shard-dg2:          NOTRUN -> [FAIL][43] ([fdo#103375])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@i915_suspend@sysfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-mtlp:         [PASS][44] -> [FAIL][45] ([i915#2521])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#8502]) +3 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][47] ([i915#8502]) +7 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-15/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         [PASS][48] -> [FAIL][49] ([i915#3743]) +1 other test fail
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([fdo#111614]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#5190]) +9 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#4538] / [i915#5190])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#2705])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#3689] / [i915#5354]) +16 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#3689] / [i915#3886] / [i915#5354]) +5 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][56] ([i915#3886] / [i915#6095])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#6095])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#4087] / [i915#7213]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][59] ([i915#7828]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_color@deep-color:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3555])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][61] ([i915#7173])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][62] ([i915#3299])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#7118])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#3359])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-128x128@pipe-a-edp-1:
    - shard-mtlp:         [PASS][65] -> [DMESG-WARN][66] ([i915#1982])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-1/igt@kms_cursor_crc@cursor-sliding-128x128@pipe-a-edp-1.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-128x128@pipe-a-edp-1.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#3555]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#111767] / [i915#5354])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4103] / [i915#4213])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([fdo#109274] / [i915#5354]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [PASS][71] -> [FAIL][72] ([i915#2346])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#4213])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@single-move@all-pipes:
    - shard-mtlp:         [PASS][74] -> [DMESG-WARN][75] ([i915#2017]) +1 other test dmesg-warn
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-7/igt@kms_cursor_legacy@single-move@all-pipes.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-4/igt@kms_cursor_legacy@single-move@all-pipes.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#3804])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#8812])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([fdo#109274] / [fdo#111767]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-snb:          NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111767]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([fdo#109274]) +4 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#2672]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#5460])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#3458]) +12 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][84] ([i915#8708]) +11 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#5354]) +29 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#1825]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#3555] / [i915#8228]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#4816])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-1:
    - shard-apl:          NOTRUN -> [INCOMPLETE][89] ([i915#180])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-dg2:          [PASS][90] -> [FAIL][91] ([fdo#103375])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][92] ([i915#8292])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#5176]) +7 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][94] ([i915#5176]) +19 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#5176]) +9 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#5235]) +11 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-10/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][97] ([i915#5235]) +7 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-19/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#5235]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#6524] / [i915#6805])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#658])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#1072]) +6 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#4235])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_selftest@drm_format_helper:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#8661])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@kms_selftest@drm_format_helper.html

  * igt@kms_selftest@drm_plane:
    - shard-snb:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#8661])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb6/igt@kms_selftest@drm_plane.html

  * igt@kms_setmode@basic@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [FAIL][105] ([i915#5465]) +1 other test fail
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-snb4/igt@kms_setmode@basic@pipe-a-vga-1.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([i915#2437])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@kms_writeback@writeback-fb-id.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([fdo#109289]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@perf@per-context-mode-unprivileged.html

  * igt@perf_pmu@frequency@gt0:
    - shard-dg2:          NOTRUN -> [FAIL][108] ([i915#6806])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@perf_pmu@frequency@gt0.html

  * igt@prime_vgem@basic-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#3708] / [i915#4077])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#3708])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@prime_vgem@fence-read-hang.html

  * igt@v3d/v3d_submit_csd@job-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#2575]) +6 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@v3d/v3d_submit_csd@job-perfmon.html

  * igt@vc4/vc4_tiling@set-get:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#7711]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-11/igt@vc4/vc4_tiling@set-get.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-dg2:          [FAIL][113] ([fdo#103375]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-11/igt@gem_eio@in-flight-suspend.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-1/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][115] ([i915#2842]) -> [PASS][116] +1 other test pass
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][117] ([i915#2842]) -> [PASS][118] +2 other tests pass
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-tglu:         [FAIL][119] ([i915#2842]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fence@parallel@bcs0:
    - shard-mtlp:         [DMESG-FAIL][121] ([i915#8962] / [i915#9121]) -> [PASS][122] +1 other test pass
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-4/igt@gem_exec_fence@parallel@bcs0.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-3/igt@gem_exec_fence@parallel@bcs0.html

  * igt@gem_exec_fence@parallel@vcs0:
    - shard-mtlp:         [DMESG-FAIL][123] ([i915#9121]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-4/igt@gem_exec_fence@parallel@vcs0.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-3/igt@gem_exec_fence@parallel@vcs0.html

  * igt@gem_exec_fence@parallel@vecs0:
    - shard-mtlp:         [FAIL][125] ([i915#8957]) -> [PASS][126] +2 other tests pass
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-4/igt@gem_exec_fence@parallel@vecs0.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-3/igt@gem_exec_fence@parallel@vecs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [INCOMPLETE][127] ([i915#6311]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-5/igt@gem_exec_suspend@basic-s0@smem.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-5/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-dg2:          [INCOMPLETE][129] ([i915#7793]) -> [PASS][130]
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-5/igt@gem_exec_suspend@basic-s3@smem.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-rkl:          [SKIP][131] ([i915#1937]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
    - shard-dg1:          [SKIP][133] ([i915#1937]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-16/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-dg1:          [FAIL][135] ([i915#3591]) -> [PASS][136] +1 other test pass
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-dg1:          [SKIP][137] ([i915#1397]) -> [PASS][138] +2 other tests pass
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][139] ([i915#1397]) -> [PASS][140] +1 other test pass
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-mtlp:         [FAIL][141] ([i915#3743]) -> [PASS][142]
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         [DMESG-FAIL][143] ([i915#2017] / [i915#5954]) -> [PASS][144]
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          [FAIL][145] ([i915#6880]) -> [PASS][146] +2 other tests pass
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  
#### Warnings ####

  * igt@gem_ctx_param@invalid-size-get:
    - shard-mtlp:         [DMESG-WARN][147] -> [DMESG-WARN][148] ([i915#2017])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-mtlp-1/igt@gem_ctx_param@invalid-size-get.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-mtlp-6/igt@gem_ctx_param@invalid-size-get.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-tglu:         [WARN][149] ([i915#2681]) -> [FAIL][150] ([i915#2681] / [i915#3591]) +1 other test fail
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [FAIL][151] ([fdo#103375]) -> [INCOMPLETE][152] ([i915#4817])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][153] ([i915#3955]) -> [SKIP][154] ([fdo#110189] / [i915#3955])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-7/igt@kms_fbcon_fbt@psr.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-2/igt@kms_fbcon_fbt@psr.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][155] ([fdo#109285]) -> [SKIP][156] ([fdo#109285] / [i915#4098])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][157] ([i915#4816]) -> [SKIP][158] ([i915#4070] / [i915#4816])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][159] ([i915#1072] / [i915#4078]) -> [SKIP][160] ([i915#1072]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/shard-dg1-12/igt@kms_psr@sprite_plane_onoff.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/shard-dg1-19/igt@kms_psr@sprite_plane_onoff.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7793]: https://gitlab.freedesktop.org/drm/intel/issues/7793
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8320]: https://gitlab.freedesktop.org/drm/intel/issues/8320
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#8957]: https://gitlab.freedesktop.org/drm/intel/issues/8957
  [i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
  [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121


Build changes
-------------

  * Linux: CI_DRM_13599 -> Patchwork_123291v1

  CI-20190529: 20190529
  CI_DRM_13599: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7468: 7468
  Patchwork_123291v1: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123291v1/index.html

[-- Attachment #2: Type: text/html, Size: 51721 bytes --]

Re: [Intel-gfx] [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write helpers

[Kandpal, Suraj]

> Subject: [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write
> helpers

Should be clarity here in the commit header

With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> Make it clear what's the number of vdsc per pipe, and what's the number of
> registers to grab. Have intel_dsc_get_pps_reg() return the registers it knows
> even if the requested amount is bigger.
> 
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 40 ++++++++++++-----------
>  1 file changed, 21 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b24601d0b2c5..14317bb6d3df 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -372,7 +372,7 @@ int intel_dsc_get_num_vdsc_instances(const struct
> intel_crtc_state *crtc_state)  }
> 
>  static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
> pps,
> -				  i915_reg_t *dsc_reg, int vdsc_per_pipe)
> +				  i915_reg_t *dsc_reg, int dsc_reg_num)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -
> 381,16 +381,12 @@ static void intel_dsc_get_pps_reg(const struct
> intel_crtc_state *crtc_state, int
> 
>  	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
> 
> -	switch (vdsc_per_pipe) {
> -	case 2:
> +	if (dsc_reg_num >= 3)
> +		MISSING_CASE(dsc_reg_num);
> +	if (dsc_reg_num >= 2)
>  		dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) :
> DSCC_PPS(pps);
> -		fallthrough;
> -	case 1:
> +	if (dsc_reg_num >= 1)
>  		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) :
> DSCA_PPS(pps);
> -		break;
> -	default:
> -		MISSING_CASE(vdsc_per_pipe);
> -	}
>  }
> 
>  static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
> @@ -399,13 +395,16 @@ static void intel_dsc_write_pps_reg(const struct
> intel_crtc_state *crtc_state,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	i915_reg_t dsc_reg[2];
> -	int i, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> +	int i, vdsc_per_pipe, dsc_reg_num;
> +
> +	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> +	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> 
> -	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) <
> vdsc_per_pipe);
> +	drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> 
> -	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
> +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> 
> -	for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++)
> +	for (i = 0; i < dsc_reg_num; i++)
>  		intel_de_write(i915, dsc_reg[i], pps_val);  }
> 
> @@ -815,16 +814,19 @@ static bool intel_dsc_read_pps_reg(struct
> intel_crtc_state *crtc_state,  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	const int vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>  	i915_reg_t dsc_reg[2];
> -	int i;
> +	int i, vdsc_per_pipe, dsc_reg_num;
> 
> -	*pps_val = 0;
> -	drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) <
> vdsc_per_pipe);
> +	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
> +	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
> 
> -	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
> +	drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
> +
> +	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> +
> +	*pps_val = 0;
> 
> -	for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) {
> +	for (i = 0; i < dsc_reg_num; i++) {
>  		u32 pps_temp;
> 
>  		pps_temp = intel_de_read(i915, dsc_reg[i]);
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify() return the value

[Kandpal, Suraj]

> Subject: [PATCH 2/8] drm/i915/dsc: have intel_dsc_pps_read_and_verify()
> return the value
> 
> Register read functions usually return the value instead of passing via pointer
> parameters. The calling code becomes easier to read.
> 
> Make the name conform to existing style better while at it.
> 
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGMT.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 36 ++++++++++++-----------
>  1 file changed, 19 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 14317bb6d3df..abb2c4370231 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -840,15 +840,17 @@ static bool intel_dsc_read_pps_reg(struct
> intel_crtc_state *crtc_state,
>  	return true;
>  }
> 
> -static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
> *crtc_state,
> -					      int pps, u32 *pps_val)
> +static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state
> +*crtc_state, int pps)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	u32 val;
>  	int ret;
> 
> -	ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
> +	ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
>  	drm_WARN_ON(&i915->drm, !ret);
> +
> +	return val;
>  }
> 
>  static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) @@ -
> 860,7 +862,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	u32 pps_temp;
> 
>  	/* PPS_0 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
> 
>  	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >>
> DSC_BPC_SHIFT;
>  	vdsc_cfg->line_buf_depth =
> @@ -873,7 +875,7 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
> 
>  	/* PPS_1 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
> 
>  	vdsc_cfg->bits_per_pixel = pps_temp;
> 
> @@ -883,31 +885,31 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> 
>  	/* PPS_2 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
> 
>  	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
>  	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK,
> pps_temp);
> 
>  	/* PPS_3 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
> 
>  	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK,
> pps_temp);
>  	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK,
> pps_temp);
> 
>  	/* PPS_4 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
> 
>  	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
>  	vdsc_cfg->initial_xmit_delay =
> REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
> 
>  	/* PPS_5 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
> 
>  	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
>  	vdsc_cfg->scale_increment_interval =
> REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
> 
>  	/* PPS_6 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
> 
>  	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
>  	vdsc_cfg->first_line_bpg_offset =
> REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); @@ -
> 915,41 +917,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	vdsc_cfg->flatness_max_qp =
> REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
> 
>  	/* PPS_7 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
> 
>  	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
>  	vdsc_cfg->slice_bpg_offset =
> REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
> 
>  	/* PPS_8 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
> 
>  	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK,
> pps_temp);
>  	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK,
> pps_temp);
> 
>  	/* PPS_9 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
> 
>  	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
> 
>  	/* PPS_10 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
> 
>  	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
>  	vdsc_cfg->rc_quant_incr_limit1 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> 
>  	/* PPS_16 */
> -	intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
> +	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
> 
>  	vdsc_cfg->slice_chunk_size =
> REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
> 
>  	if (DISPLAY_VER(i915) >= 14) {
>  		/* PPS_17 */
> -		intel_dsc_read_and_verify_pps_reg(crtc_state, 17,
> &pps_temp);
> +		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
> 
>  		vdsc_cfg->second_line_bpg_offset =
> REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
> 
>  		/* PPS_18 */
> -		intel_dsc_read_and_verify_pps_reg(crtc_state, 18,
> &pps_temp);
> +		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
> 
>  		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
>  		vdsc_cfg->second_line_offset_adj =
> REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() return the value

[Kandpal, Suraj]

> Subject: [PATCH 3/8] drm/i915/dsc: have intel_dsc_pps_read() return the value
> 
> Register read functions usually return the value instead of passing via pointer
> parameters. Return the multiple register verification results via a pointer
> parameter, which can also be NULL to skip the extra checks.
> 
> Make the name conform to existing style better while at it.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 32 ++++++++++++++---------
>  1 file changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index abb2c4370231..b0be6615a865 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -809,13 +809,14 @@ void intel_dsc_disable(const struct intel_crtc_state
> *old_crtc_state)
>  	}
>  }
> 
> -static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
> -				   int pps, u32 *pps_val)
> +static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
> +			      bool *check_equal)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	i915_reg_t dsc_reg[2];
>  	int i, vdsc_per_pipe, dsc_reg_num;
> +	u32 val = 0;
> 
>  	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>  	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); @@ -
> 824,20 +825,25 @@ static bool intel_dsc_read_pps_reg(struct intel_crtc_state
> *crtc_state,
> 
>  	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
> 
> -	*pps_val = 0;
> +	if (check_equal)
> +		*check_equal = true;
> 
>  	for (i = 0; i < dsc_reg_num; i++) {
> -		u32 pps_temp;
> +		u32 tmp;
> 
> -		pps_temp = intel_de_read(i915, dsc_reg[i]);
> +		tmp = intel_de_read(i915, dsc_reg[i]);
> 
> -		if (i == 0)
> -			*pps_val = pps_temp;
> -		else if (pps_temp != *pps_val)
> -			return false;
> +		if (i == 0) {
> +			val = tmp;
> +		} else if (check_equal && tmp != val) {
> +			*check_equal = false;
> +			break;
> +		} else if (!check_equal) {
> +			break;
> +		}
>  	}
> 
> -	return true;
> +	return val;
>  }
> 
>  static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state,
> int pps) @@ -845,10 +851,10 @@ static u32
> intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, in
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	u32 val;
> -	int ret;
> +	bool all_equal;
> 
> -	ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
> -	drm_WARN_ON(&i915->drm, !ret);
> +	val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
> +	drm_WARN_ON(&i915->drm, !all_equal);
> 
>  	return val;
>  }
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write()

[Kandpal, Suraj]

> Subject: [PATCH 4/8] drm/i915/dsc: rename pps write to intel_dsc_pps_write()
> 
> Make the function name conform to existing style better.
> 

LGTM. 

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b0be6615a865..4086dbb25ca5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -389,8 +389,8 @@ static void intel_dsc_get_pps_reg(const struct
> intel_crtc_state *crtc_state, int
>  		dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) :
> DSCA_PPS(pps);  }
> 
> -static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
> -				    int pps, u32 pps_val)
> +static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
> +				int pps, u32 pps_val)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -443,41
> +443,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state
> *crtc_state)
>  	if (vdsc_cfg->vbr_enable)
>  		pps_val |= DSC_VBR_ENABLE;
>  	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
> +	intel_dsc_pps_write(crtc_state, 0, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_1 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
>  	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
> +	intel_dsc_pps_write(crtc_state, 1, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_2 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
>  		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
>  	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 2, pps_val);
> +	intel_dsc_pps_write(crtc_state, 2, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_3 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
>  		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
>  	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 3, pps_val);
> +	intel_dsc_pps_write(crtc_state, 3, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_4 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
>  		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>  	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 4, pps_val);
> +	intel_dsc_pps_write(crtc_state, 4, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_5 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
>  		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
>  	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 5, pps_val);
> +	intel_dsc_pps_write(crtc_state, 5, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_6 registers */
>  	pps_val = 0;
> @@ -486,28 +486,28 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
>  		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
>  	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 6, pps_val);
> +	intel_dsc_pps_write(crtc_state, 6, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_7 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
>  		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 7, pps_val);
> +	intel_dsc_pps_write(crtc_state, 7, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_8 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
>  		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 8, pps_val);
> +	intel_dsc_pps_write(crtc_state, 8, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_9 registers */
>  	pps_val = 0;
>  	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
>  		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 9, pps_val);
> +	intel_dsc_pps_write(crtc_state, 9, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_10 registers */
>  	pps_val = 0;
> @@ -516,7 +516,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> 
> 	DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 10, pps_val);
> +	intel_dsc_pps_write(crtc_state, 10, pps_val);
> 
>  	/* Populate Picture parameter set 16 */
>  	pps_val = 0;
> @@ -526,21 +526,21 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
>  					vdsc_cfg->slice_height);
>  	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
> -	intel_dsc_write_pps_reg(crtc_state, 16, pps_val);
> +	intel_dsc_pps_write(crtc_state, 16, pps_val);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		/* Populate PICTURE_PARAMETER_SET_17 registers */
>  		pps_val = 0;
>  		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
>  		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
> -		intel_dsc_write_pps_reg(crtc_state, 17, pps_val);
> +		intel_dsc_pps_write(crtc_state, 17, pps_val);
> 
>  		/* Populate PICTURE_PARAMETER_SET_18 registers */
>  		pps_val = 0;
>  		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
>  			   DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
>  		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> -		intel_dsc_write_pps_reg(crtc_state, 18, pps_val);
> +		intel_dsc_pps_write(crtc_state, 18, pps_val);
>  	}
> 
>  	/* Populate the RC_BUF_THRESH registers */
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 6/8] drm/i915/dsc: clean up pps comments

[Kandpal, Suraj]

> Subject: [PATCH 6/8] drm/i915/dsc: clean up pps comments
> 
> Unify comments to be the simple "PPS n" instead of all sorts of variants.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 56 +++++++++----------
>  .../gpu/drm/i915/display/intel_vdsc_regs.h    | 29 +++++-----
>  2 files changed, 42 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 73bfa4d6633d..4855514d7b09 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -422,7 +422,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	int num_vdsc_instances =
> intel_dsc_get_num_vdsc_instances(crtc_state);
>  	int vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> 
> -	/* Populate PICTURE_PARAMETER_SET_0 registers */
> +	/* PPS 0 */
>  	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
>  		DSC_VER_MIN_SHIFT |
>  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | @@ -
> 445,36 +445,36 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 0, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_1 registers */
> +	/* PPS 1 */
>  	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
>  	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 1, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_2 registers */
> +	/* PPS 2 */
>  	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
>  		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
>  	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 2, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_3 registers */
> +	/* PPS 3 */
>  	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
>  		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
>  	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 3, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_4 registers */
> +	/* PPS 4 */
>  	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
>  		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>  	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 4, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_5 registers */
> +	/* PPS 5 */
>  	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
>  		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
>  	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 5, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_6 registers */
> +	/* PPS 6 */
>  	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
>  		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset)
> |
>  		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | @@ -
> 482,25 +482,25 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 6, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_7 registers */
> +	/* PPS 7 */
>  	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
>  		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 7, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_8 registers */
> +	/* PPS 8 */
>  	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
>  		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 8, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_9 registers */
> +	/* PPS 9 */
>  	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
>  		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 9, pps_val);
> 
> -	/* Populate PICTURE_PARAMETER_SET_10 registers */
> +	/* PPS 10 */
>  	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
>  		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1)
> |
>  		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> | @@ -508,7 +508,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 10, pps_val);
> 
> -	/* Populate Picture parameter set 16 */
> +	/* PPS 16 */
>  	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
>  		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
>  				   vdsc_cfg->slice_width) |
> @@ -518,12 +518,12 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	intel_dsc_pps_write(crtc_state, 16, pps_val);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> -		/* Populate PICTURE_PARAMETER_SET_17 registers */
> +		/* PPS 17 */
>  		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
>  		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 17, pps_val);
> 
> -		/* Populate PICTURE_PARAMETER_SET_18 registers */
> +		/* PPS 18 */
>  		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
>  			DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
>  		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> @@ -854,7 +854,7 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	int num_vdsc_instances =
> intel_dsc_get_num_vdsc_instances(crtc_state);
>  	u32 pps_temp;
> 
> -	/* PPS_0 */
> +	/* PPS 0 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
> 
>  	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >>
> DSC_BPC_SHIFT; @@ -867,7 +867,7 @@ static void
> intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
>  	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
>  	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
> 
> -	/* PPS_1 */
> +	/* PPS 1 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
> 
>  	vdsc_cfg->bits_per_pixel = pps_temp;
> @@ -877,31 +877,31 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
> 
>  	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> 
> -	/* PPS_2 */
> +	/* PPS 2 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
> 
>  	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
>  	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK,
> pps_temp);
> 
> -	/* PPS_3 */
> +	/* PPS 3 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
> 
>  	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK,
> pps_temp);
>  	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK,
> pps_temp);
> 
> -	/* PPS_4 */
> +	/* PPS 4 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
> 
>  	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
>  	vdsc_cfg->initial_xmit_delay =
> REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
> 
> -	/* PPS_5 */
> +	/* PPS 5 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
> 
>  	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
>  	vdsc_cfg->scale_increment_interval =
> REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
> 
> -	/* PPS_6 */
> +	/* PPS 6 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
> 
>  	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp); @@ -909,41
> +909,41 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	vdsc_cfg->flatness_min_qp =
> REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
>  	vdsc_cfg->flatness_max_qp =
> REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
> 
> -	/* PPS_7 */
> +	/* PPS 7 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
> 
>  	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
>  	vdsc_cfg->slice_bpg_offset =
> REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
> 
> -	/* PPS_8 */
> +	/* PPS 8 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
> 
>  	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK,
> pps_temp);
>  	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK,
> pps_temp);
> 
> -	/* PPS_9 */
> +	/* PPS 9 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
> 
>  	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
> 
> -	/* PPS_10 */
> +	/* PPS 10 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
> 
>  	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
>  	vdsc_cfg->rc_quant_incr_limit1 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> 
> -	/* PPS_16 */
> +	/* PPS 16 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
> 
>  	vdsc_cfg->slice_chunk_size =
> REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
> 
>  	if (DISPLAY_VER(i915) >= 14) {
> -		/* PPS_17 */
> +		/* PPS 17 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
> 
>  		vdsc_cfg->second_line_bpg_offset =
> REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
> 
> -		/* PPS_18 */
> +		/* PPS 18 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
> 
>  		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp); diff --git
> a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 5cbcbd9db7b1..58d282dcfc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -72,7 +72,7 @@
>  #define  ICL_DSC0_PPS(pipe, pps)
> 	_MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
>  #define  ICL_DSC1_PPS(pipe, pps)
> 	_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> 
> -/* PPS0 */
> +/* PPS 0 */
>  #define  DSC_NATIVE_422_ENABLE		BIT(23)
>  #define  DSC_NATIVE_420_ENABLE		BIT(22)
>  #define  DSC_ALT_ICH_SEL		(1 << 20)
> @@ -87,22 +87,22 @@
>  #define  DSC_VER_MIN_SHIFT		4
>  #define  DSC_VER_MAJ			(0x1 << 0)
> 
> -/* PPS1 */
> +/* PPS 1 */
>  #define  DSC_BPP(bpp)				((bpp) << 0)
> 
> -/* PPS2 */
> +/* PPS 2 */
>  #define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
>  #define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
>  #define  DSC_PIC_WIDTH(pic_width)
> 	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
>  #define  DSC_PIC_HEIGHT(pic_height)
> 	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
> 
> -/* PPS3 */
> +/* PPS 3 */
>  #define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31,
> 16)
>  #define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
>  #define  DSC_SLICE_WIDTH(slice_width)
> 	REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
>  #define  DSC_SLICE_HEIGHT(slice_height)
> 	REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
> 
> -/* PPS4 */
> +/* PPS 4 */
>  #define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31,
> 16)
>  #define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
>  #define  DSC_INITIAL_DEC_DELAY(dec_delay)
> REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
> @@ -110,13 +110,13 @@
>  #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)
> REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
>  							       xmit_delay)
> 
> -/* PPS5 */
> +/* PPS 5 */
>  #define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27,
> 16)
>  #define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
>  #define  DSC_SCALE_DEC_INT(scale_dec)
> 	REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
>  #define  DSC_SCALE_INC_INT(scale_inc)
> 	REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
> 
> -/* PPS6 */
> +/* PPS 6 */
>  #define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28,
> 24)
>  #define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20,
> 16)
>  #define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
> @@ -128,13 +128,13 @@
>  #define  DSC_INITIAL_SCALE_VALUE(value)
> 	REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
>  							       value)
> 
> -/* PPS7 */
> +/* PPS 7 */
>  #define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
>  #define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
>  #define  DSC_NFL_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
>  #define  DSC_SLICE_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
>  							       bpg_offset)
> -/* PPS8 */
> +/* PPS 8 */
>  #define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
>  #define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
>  #define  DSC_INITIAL_OFFSET(initial_offset)
> 	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
> @@ -142,7 +142,7 @@
>  #define  DSC_FINAL_OFFSET(final_offset)
> 	REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
>  							       final_offset)
> 
> -/* PPS9 */
> +/* PPS 9 */
>  #define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
>  #define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
>  #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)
> 	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
> @@ -150,7 +150,7 @@
>  #define  DSC_RC_MODEL_SIZE(rc_model_size)
> 	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
>  							       rc_model_size)
> 
> -/* PPS10 */
> +/* PPS 10 */
>  #define  DSC_RC_TGT_OFF_LOW_MASK
> 	REG_GENMASK(23, 20)
>  #define  DSC_RC_TGT_OFF_HIGH_MASK
> 	REG_GENMASK(19, 16)
>  #define  DSC_RC_QUANT_INC_LIMIT1_MASK
> 	REG_GENMASK(12, 8)
> @@ -162,7 +162,7 @@
>  #define  DSC_RC_QUANT_INC_LIMIT1(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
>  #define  DSC_RC_QUANT_INC_LIMIT0(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
> 
> -/* PPS16 */
> +/* PPS 16 */
>  #define  DSC_SLICE_ROW_PR_FRME_MASK
> 	REG_GENMASK(31, 20)
>  #define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18,
> 16)
>  #define  DSC_SLICE_CHUNK_SIZE_MASK
> 	REG_GENMASK(15, 0)
> @@ -173,12 +173,11 @@
>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
> 	REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
> 
> slice_chunk_size)
> 
> -/* MTL Display Stream Compression registers */
> -/* PPS17 */
> +/* PPS 17 (MTL+) */
>  #define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 27)
>  #define DSC_SL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
> 
> -/* PPS18 */
> +/* PPS 18 (MTL+) */
>  #define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 16)
>  #define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
>  #define DSC_NSL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content macros

[Kandpal, Suraj]

> Subject: [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content
> macros
> 
> Improve clarity by specifying the PPS number in the register content macros. It's
> easier to notice if macros are being used for the wrong register.

LGTM.

Reviewed-by : Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> 
> ---
> 
> Probably easiest to review by applying and using 'git show --word-diff'
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 146 ++++++++---------
>  .../gpu/drm/i915/display/intel_vdsc_regs.h    | 152 +++++++++---------
>  2 files changed, 149 insertions(+), 149 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 4855514d7b09..126aff804e33 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -423,109 +423,109 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	int vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> 
>  	/* PPS 0 */
> -	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> -		DSC_VER_MIN_SHIFT |
> -		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> -		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> +	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> +		DSC_PPS0_VER_MIN_SHIFT |
> +		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
> +		vdsc_cfg->line_buf_depth <<
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
>  	if (vdsc_cfg->dsc_version_minor == 2) {
> -		pps_val |= DSC_ALT_ICH_SEL;
> +		pps_val |= DSC_PPS0_ALT_ICH_SEL;
>  		if (vdsc_cfg->native_420)
> -			pps_val |= DSC_NATIVE_420_ENABLE;
> +			pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
>  		if (vdsc_cfg->native_422)
> -			pps_val |= DSC_NATIVE_422_ENABLE;
> +			pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
>  	}
>  	if (vdsc_cfg->block_pred_enable)
> -		pps_val |= DSC_BLOCK_PREDICTION;
> +		pps_val |= DSC_PPS0_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> -		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> +		pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
>  	if (vdsc_cfg->simple_422)
> -		pps_val |= DSC_422_ENABLE;
> +		pps_val |= DSC_PPS0_422_ENABLE;
>  	if (vdsc_cfg->vbr_enable)
> -		pps_val |= DSC_VBR_ENABLE;
> +		pps_val |= DSC_PPS0_VBR_ENABLE;
>  	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 0, pps_val);
> 
>  	/* PPS 1 */
> -	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
> +	pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
>  	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 1, pps_val);
> 
>  	/* PPS 2 */
> -	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> -		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> +	pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
> +		DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width /
> num_vdsc_instances);
>  	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 2, pps_val);
> 
>  	/* PPS 3 */
> -	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> -		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> +	pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> +		DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
>  	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 3, pps_val);
> 
>  	/* PPS 4 */
> -	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> -		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> +	pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg-
> >initial_xmit_delay) |
> +		DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>  	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 4, pps_val);
> 
>  	/* PPS 5 */
> -	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> -		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> +	pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg-
> >scale_increment_interval) |
> +		DSC_PPS5_SCALE_DEC_INT(vdsc_cfg-
> >scale_decrement_interval);
>  	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 5, pps_val);
> 
>  	/* PPS 6 */
> -	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> -		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset)
> |
> -		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> -		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> +	pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg-
> >initial_scale_value) |
> +		DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg-
> >first_line_bpg_offset) |
> +		DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> +		DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
>  	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 6, pps_val);
> 
>  	/* PPS 7 */
> -	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> -		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> +	pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> +		DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 7, pps_val);
> 
>  	/* PPS 8 */
> -	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> -		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> +	pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
> +		DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 8, pps_val);
> 
>  	/* PPS 9 */
> -	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> -		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> +	pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> +
> 	DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 9, pps_val);
> 
>  	/* PPS 10 */
> -	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
> -		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1)
> |
> -		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> -
> 	DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> +	pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
> +		DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg-
> >rc_quant_incr_limit1) |
> +
> 	DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> +
> 	DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 10, pps_val);
> 
>  	/* PPS 16 */
> -	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> -		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
> -				   vdsc_cfg->slice_width) |
> -		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> -					vdsc_cfg->slice_height);
> +	pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size)
> |
> +		DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
> +					 vdsc_cfg->slice_width) |
> +		DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> +					      vdsc_cfg->slice_height);
>  	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 16, pps_val);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		/* PPS 17 */
> -		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
>  		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 17, pps_val);
> 
>  		/* PPS 18 */
> -		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> -			DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
> +		pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg-
> >nsl_bpg_offset) |
> +			DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
>  		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 18, pps_val);
>  	}
> @@ -857,15 +857,15 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	/* PPS 0 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
> 
> -	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >>
> DSC_BPC_SHIFT;
> +	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK)
> >>
> +DSC_PPS0_BPC_SHIFT;
>  	vdsc_cfg->line_buf_depth =
> -		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >>
> DSC_LINE_BUF_DEPTH_SHIFT;
> -	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
> -	vdsc_cfg->convert_rgb = pps_temp &
> DSC_COLOR_SPACE_CONVERSION;
> -	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
> -	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
> -	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
> -	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
> +		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >>
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> +	vdsc_cfg->block_pred_enable = pps_temp &
> DSC_PPS0_BLOCK_PREDICTION;
> +	vdsc_cfg->convert_rgb = pps_temp &
> DSC_PPS0_COLOR_SPACE_CONVERSION;
> +	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
> +	vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
> +	vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
> +	vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
> 
>  	/* PPS 1 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); @@ -880,74
> +880,74 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	/* PPS 2 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
> 
> -	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
> -	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK,
> pps_temp);
> +	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
> +	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK,
> +pps_temp);
> 
>  	/* PPS 3 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
> 
> -	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK,
> pps_temp);
> -	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK,
> pps_temp);
> +	vdsc_cfg->slice_width =
> REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
> +	vdsc_cfg->slice_height =
> REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK,
> +pps_temp);
> 
>  	/* PPS 4 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
> 
> -	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
> -	vdsc_cfg->initial_xmit_delay =
> REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
> +	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
> +	vdsc_cfg->initial_xmit_delay =
> +REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
> 
>  	/* PPS 5 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
> 
> -	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
> -	vdsc_cfg->scale_increment_interval =
> REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
> +	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
> +	vdsc_cfg->scale_increment_interval =
> +REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
> 
>  	/* PPS 6 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
> 
> -	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
> -	vdsc_cfg->first_line_bpg_offset =
> REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
> -	vdsc_cfg->flatness_min_qp =
> REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
> -	vdsc_cfg->flatness_max_qp =
> REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
> +	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
> +	vdsc_cfg->first_line_bpg_offset =
> REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->flatness_min_qp =
> REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
> +	vdsc_cfg->flatness_max_qp =
> +REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
> 
>  	/* PPS 7 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
> 
> -	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
> -	vdsc_cfg->slice_bpg_offset =
> REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->slice_bpg_offset =
> +REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
> 
>  	/* PPS 8 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
> 
> -	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK,
> pps_temp);
> -	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK,
> pps_temp);
> +	vdsc_cfg->initial_offset =
> REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->final_offset =
> REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK,
> +pps_temp);
> 
>  	/* PPS 9 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
> 
> -	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
> +	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK,
> +pps_temp);
> 
>  	/* PPS 10 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
> 
> -	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
> -	vdsc_cfg->rc_quant_incr_limit1 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> +	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
> +	vdsc_cfg->rc_quant_incr_limit1 =
> +REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> 
>  	/* PPS 16 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
> 
> -	vdsc_cfg->slice_chunk_size =
> REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
> +	vdsc_cfg->slice_chunk_size =
> +REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
> 
>  	if (DISPLAY_VER(i915) >= 14) {
>  		/* PPS 17 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
> 
> -		vdsc_cfg->second_line_bpg_offset =
> REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
> +		vdsc_cfg->second_line_bpg_offset =
> +REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
> 
>  		/* PPS 18 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
> 
> -		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
> -		vdsc_cfg->second_line_offset_adj =
> REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
> +		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
> +		vdsc_cfg->second_line_offset_adj =
> +REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 58d282dcfc6f..92782de2b309 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -73,115 +73,115 @@
>  #define  ICL_DSC1_PPS(pipe, pps)
> 	_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> 
>  /* PPS 0 */
> -#define  DSC_NATIVE_422_ENABLE		BIT(23)
> -#define  DSC_NATIVE_420_ENABLE		BIT(22)
> -#define  DSC_ALT_ICH_SEL		(1 << 20)
> -#define  DSC_VBR_ENABLE			(1 << 19)
> -#define  DSC_422_ENABLE			(1 << 18)
> -#define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
> -#define  DSC_BLOCK_PREDICTION		(1 << 16)
> -#define  DSC_LINE_BUF_DEPTH_SHIFT	12
> -#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)
> -#define  DSC_BPC_SHIFT			8
> -#define  DSC_BPC_MASK			REG_GENMASK(11, 8)
> -#define  DSC_VER_MIN_SHIFT		4
> -#define  DSC_VER_MAJ			(0x1 << 0)
> +#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)
> +#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)
> +#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)
> +#define   DSC_PPS0_VBR_ENABLE			(1 << 19)
> +#define   DSC_PPS0_422_ENABLE			(1 << 18)
> +#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)
> +#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)
> +#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12
> +#define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15,
> 12)
> +#define   DSC_PPS0_BPC_SHIFT			8
> +#define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)
> +#define   DSC_PPS0_VER_MIN_SHIFT		4
> +#define   DSC_PPS0_VER_MAJ			(0x1 << 0)
> 
>  /* PPS 1 */
> -#define  DSC_BPP(bpp)				((bpp) << 0)
> +#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)
> 
>  /* PPS 2 */
> -#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
> -#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> -#define  DSC_PIC_WIDTH(pic_width)
> 	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
> -#define  DSC_PIC_HEIGHT(pic_height)
> 	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
> +#define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
> +#define   DSC_PPS2_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS2_PIC_WIDTH(pic_width)
> 	REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
> +#define   DSC_PPS2_PIC_HEIGHT(pic_height)
> 	REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
> 
>  /* PPS 3 */
> -#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31,
> 16)
> -#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
> -#define  DSC_SLICE_WIDTH(slice_width)
> 	REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
> -#define  DSC_SLICE_HEIGHT(slice_height)
> 	REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
> +#define   DSC_PPS3_SLICE_WIDTH_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS3_SLICE_HEIGHT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS3_SLICE_WIDTH(slice_width)
> 	REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
> +#define   DSC_PPS3_SLICE_HEIGHT(slice_height)
> 	REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
> 
>  /* PPS 4 */
> -#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31,
> 16)
> -#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
> -#define  DSC_INITIAL_DEC_DELAY(dec_delay)
> REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
> +#define   DSC_PPS4_INITIAL_DEC_DELAY_MASK	REG_GENMASK(31,
> 16)
> +#define   DSC_PPS4_INITIAL_XMIT_DELAY_MASK	REG_GENMASK(9, 0)
> +#define   DSC_PPS4_INITIAL_DEC_DELAY(dec_delay)
> 	REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
>  							       dec_delay)
> -#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)
> REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
> -							       xmit_delay)
> +#define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)
> 	REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
> +
> xmit_delay)
> 
>  /* PPS 5 */
> -#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27,
> 16)
> -#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
> -#define  DSC_SCALE_DEC_INT(scale_dec)
> 	REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
> -#define  DSC_SCALE_INC_INT(scale_inc)
> 	REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
> +#define   DSC_PPS5_SCALE_DEC_INT_MASK		REG_GENMASK(27,
> 16)
> +#define   DSC_PPS5_SCALE_INC_INT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS5_SCALE_DEC_INT(scale_dec)
> 	REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
> +#define   DSC_PPS5_SCALE_INC_INT(scale_inc)
> 	REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
> 
>  /* PPS 6 */
> -#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28,
> 24)
> -#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20,
> 16)
> -#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
> -#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)
> -#define  DSC_FLATNESS_MAX_QP(max_qp)
> 	REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
> -#define  DSC_FLATNESS_MIN_QP(min_qp)
> 	REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
> -#define  DSC_FIRST_LINE_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
> -							       offset)
> -#define  DSC_INITIAL_SCALE_VALUE(value)
> 	REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
> +#define   DSC_PPS6_FLATNESS_MAX_QP_MASK
> 	REG_GENMASK(28, 24)
> +#define   DSC_PPS6_FLATNESS_MIN_QP_MASK		REG_GENMASK(20,
> 16)
> +#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK	REG_GENMASK(12, 8)
> +#define   DSC_PPS6_INITIAL_SCALE_VALUE_MASK	REG_GENMASK(5, 0)
> +#define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)
> 	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
> +#define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)
> 	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
> +#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
> +								       offset)
> +#define   DSC_PPS6_INITIAL_SCALE_VALUE(value)
> 	REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
>  							       value)
> 
>  /* PPS 7 */
> -#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
> -#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
> -#define  DSC_NFL_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
> -#define  DSC_SLICE_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
> +#define   DSC_PPS7_NFL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS7_SLICE_BPG_OFFSET_MASK	REG_GENMASK(15, 0)
> +#define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
> +#define   DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
>  							       bpg_offset)
>  /* PPS 8 */
> -#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
> -#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
> -#define  DSC_INITIAL_OFFSET(initial_offset)
> 	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
> -							       initial_offset)
> -#define  DSC_FINAL_OFFSET(final_offset)
> 	REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
> +#define   DSC_PPS8_INITIAL_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS8_FINAL_OFFSET_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS8_INITIAL_OFFSET(initial_offset)
> 	REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
> +
> initial_offset)
> +#define   DSC_PPS8_FINAL_OFFSET(final_offset)
> 	REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
>  							       final_offset)
> 
>  /* PPS 9 */
> -#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19,
> 16)
> -#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
> -#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)
> 	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
> +#define   DSC_PPS9_RC_EDGE_FACTOR_MASK		REG_GENMASK(19,
> 16)
> +#define   DSC_PPS9_RC_MODEL_SIZE_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact)
> 	REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
>  							       rc_edge_fact)
> -#define  DSC_RC_MODEL_SIZE(rc_model_size)
> 	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
> +#define   DSC_PPS9_RC_MODEL_SIZE(rc_model_size)
> 	REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
>  							       rc_model_size)
> 
>  /* PPS 10 */
> -#define  DSC_RC_TGT_OFF_LOW_MASK
> 	REG_GENMASK(23, 20)
> -#define  DSC_RC_TGT_OFF_HIGH_MASK
> 	REG_GENMASK(19, 16)
> -#define  DSC_RC_QUANT_INC_LIMIT1_MASK
> 	REG_GENMASK(12, 8)
> -#define  DSC_RC_QUANT_INC_LIMIT0_MASK
> 	REG_GENMASK(4, 0)
> -#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)
> 	REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \
> +#define   DSC_PPS10_RC_TGT_OFF_LOW_MASK
> 	REG_GENMASK(23, 20)
> +#define   DSC_PPS10_RC_TGT_OFF_HIGH_MASK	REG_GENMASK(19,
> 16)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK	REG_GENMASK(12, 8)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK	REG_GENMASK(4, 0)
> +#define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)
> 	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
> 
> rc_tgt_off_low)
> -#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)
> 	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \
> +#define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high)
> 	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
> 
> rc_tgt_off_high)
> -#define  DSC_RC_QUANT_INC_LIMIT1(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
> -#define  DSC_RC_QUANT_INC_LIMIT0(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)
> 	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)
> 	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
> 
>  /* PPS 16 */
> -#define  DSC_SLICE_ROW_PR_FRME_MASK
> 	REG_GENMASK(31, 20)
> -#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18,
> 16)
> -#define  DSC_SLICE_CHUNK_SIZE_MASK
> 	REG_GENMASK(15, 0)
> -#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)
> 	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \
> -
> slice_row_per_frame)
> -#define  DSC_SLICE_PER_LINE(slice_per_line)
> 	REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
> -
> slice_per_line)
> -#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
> 	REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
> -
> slice_chunk_size)
> +#define   DSC_PPS16_SLICE_ROW_PR_FRME_MASK	REG_GENMASK(31,
> 20)
> +#define   DSC_PPS16_SLICE_PER_LINE_MASK		REG_GENMASK(18,
> 16)
> +#define   DSC_PPS16_SLICE_CHUNK_SIZE_MASK	REG_GENMASK(15, 0)
> +#define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
> +
> slice_row_per_frame)
> +#define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
> +
> slice_per_line)
> +#define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
> +
> slice_chunk_size)
> 
>  /* PPS 17 (MTL+) */
> -#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 27)
> -#define DSC_SL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
> +#define   DSC_PPS17_SL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 27)
> +#define   DSC_PPS17_SL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
> 
>  /* PPS 18 (MTL+) */
> -#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 16)
> -#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
> -#define DSC_NSL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
> -#define DSC_SL_OFFSET_ADJ(offset)
> 	REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
> +#define   DSC_PPS18_NSL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS18_SL_OFFSET_ADJ_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS18_NSL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
> +#define   DSC_PPS18_SL_OFFSET_ADJ(offset)
> 	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
> 
>  /* Icelake Rate Control Buffer Threshold Registers */
>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1

[Kandpal, Suraj]

> Subject: [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends
> for PPS0 and PPS1
> 
> Use the register helper macros for PPS0 and PPS1 register contents.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 15 +++++------
>  .../gpu/drm/i915/display/intel_vdsc_regs.h    | 27 ++++++++++---------
>  2 files changed, 22 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 126aff804e33..5c00f7ccad7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -423,10 +423,10 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	int vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> 
>  	/* PPS 0 */
> -	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> -		DSC_PPS0_VER_MIN_SHIFT |
> -		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
> -		vdsc_cfg->line_buf_depth <<
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> +	pps_val = DSC_PPS0_VER_MAJOR(1) |
> +		DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
> +		DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
> +		DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
>  	if (vdsc_cfg->dsc_version_minor == 2) {
>  		pps_val |= DSC_PPS0_ALT_ICH_SEL;
>  		if (vdsc_cfg->native_420)
> @@ -857,9 +857,8 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	/* PPS 0 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
> 
> -	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK)
> >> DSC_PPS0_BPC_SHIFT;
> -	vdsc_cfg->line_buf_depth =
> -		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >>
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> +	vdsc_cfg->bits_per_component =
> REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
> +	vdsc_cfg->line_buf_depth =
> REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK,
> +pps_temp);
>  	vdsc_cfg->block_pred_enable = pps_temp &
> DSC_PPS0_BLOCK_PREDICTION;
>  	vdsc_cfg->convert_rgb = pps_temp &
> DSC_PPS0_COLOR_SPACE_CONVERSION;
>  	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; @@ -
> 870,7 +869,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	/* PPS 1 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
> 
> -	vdsc_cfg->bits_per_pixel = pps_temp;
> +	vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK,
> pps_temp);
> 
>  	if (vdsc_cfg->native_420)
>  		vdsc_cfg->bits_per_pixel >>= 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 92782de2b309..64f440fdc22b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -73,22 +73,25 @@
>  #define  ICL_DSC1_PPS(pipe, pps)
> 	_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> 
>  /* PPS 0 */
> -#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)
> -#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)
> -#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)
> -#define   DSC_PPS0_VBR_ENABLE			(1 << 19)
> -#define   DSC_PPS0_422_ENABLE			(1 << 18)
> -#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)
> -#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)
> -#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12
> +#define   DSC_PPS0_NATIVE_422_ENABLE		REG_BIT(23)
> +#define   DSC_PPS0_NATIVE_420_ENABLE		REG_BIT(22)
> +#define   DSC_PPS0_ALT_ICH_SEL			REG_BIT(20)
> +#define   DSC_PPS0_VBR_ENABLE			REG_BIT(19)
> +#define   DSC_PPS0_422_ENABLE			REG_BIT(18)
> +#define   DSC_PPS0_COLOR_SPACE_CONVERSION	REG_BIT(17)
> +#define   DSC_PPS0_BLOCK_PREDICTION		REG_BIT(16)
>  #define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15,
> 12)
> -#define   DSC_PPS0_BPC_SHIFT			8
> +#define   DSC_PPS0_LINE_BUF_DEPTH(depth)
> 	REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
>  #define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)
> -#define   DSC_PPS0_VER_MIN_SHIFT		4
> -#define   DSC_PPS0_VER_MAJ			(0x1 << 0)
> +#define   DSC_PPS0_BPC(bpc)
> 	REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
> +#define   DSC_PPS0_VER_MINOR_MASK		REG_GENMASK(7, 4)
> +#define   DSC_PPS0_VER_MINOR(minor)
> 	REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
> +#define   DSC_PPS0_VER_MAJOR_MASK		REG_GENMASK(3, 0)
> +#define   DSC_PPS0_VER_MAJOR(major)
> 	REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
> 
>  /* PPS 1 */
> -#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)
> +#define   DSC_PPS1_BPP_MASK			REG_GENMASK(9, 0)
> +#define   DSC_PPS1_BPP(bpp)
> 	REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
> 
>  /* PPS 2 */
>  #define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content macros

[Kandpal, Suraj]

> Subject: [PATCH 7/8] drm/i915/dsc: add the PPS number to the register content
> macros
> 
> Improve clarity by specifying the PPS number in the register content macros. It's
> easier to notice if macros are being used for the wrong register.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> 
> ---
> 
> Probably easiest to review by applying and using 'git show --word-diff'
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 146 ++++++++---------
>  .../gpu/drm/i915/display/intel_vdsc_regs.h    | 152 +++++++++---------
>  2 files changed, 149 insertions(+), 149 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 4855514d7b09..126aff804e33 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -423,109 +423,109 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	int vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
> 
>  	/* PPS 0 */
> -	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> -		DSC_VER_MIN_SHIFT |
> -		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> -		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> +	pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> +		DSC_PPS0_VER_MIN_SHIFT |
> +		vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
> +		vdsc_cfg->line_buf_depth <<
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
>  	if (vdsc_cfg->dsc_version_minor == 2) {
> -		pps_val |= DSC_ALT_ICH_SEL;
> +		pps_val |= DSC_PPS0_ALT_ICH_SEL;
>  		if (vdsc_cfg->native_420)
> -			pps_val |= DSC_NATIVE_420_ENABLE;
> +			pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
>  		if (vdsc_cfg->native_422)
> -			pps_val |= DSC_NATIVE_422_ENABLE;
> +			pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
>  	}
>  	if (vdsc_cfg->block_pred_enable)
> -		pps_val |= DSC_BLOCK_PREDICTION;
> +		pps_val |= DSC_PPS0_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> -		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> +		pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
>  	if (vdsc_cfg->simple_422)
> -		pps_val |= DSC_422_ENABLE;
> +		pps_val |= DSC_PPS0_422_ENABLE;
>  	if (vdsc_cfg->vbr_enable)
> -		pps_val |= DSC_VBR_ENABLE;
> +		pps_val |= DSC_PPS0_VBR_ENABLE;
>  	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 0, pps_val);
> 
>  	/* PPS 1 */
> -	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
> +	pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
>  	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 1, pps_val);
> 
>  	/* PPS 2 */
> -	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> -		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
> +	pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
> +		DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width /
> num_vdsc_instances);
>  	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 2, pps_val);
> 
>  	/* PPS 3 */
> -	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> -		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
> +	pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> +		DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
>  	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 3, pps_val);
> 
>  	/* PPS 4 */
> -	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> -		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
> +	pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg-
> >initial_xmit_delay) |
> +		DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>  	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 4, pps_val);
> 
>  	/* PPS 5 */
> -	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> -		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
> +	pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg-
> >scale_increment_interval) |
> +		DSC_PPS5_SCALE_DEC_INT(vdsc_cfg-
> >scale_decrement_interval);
>  	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 5, pps_val);
> 
>  	/* PPS 6 */
> -	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> -		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset)
> |
> -		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> -		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> +	pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg-
> >initial_scale_value) |
> +		DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg-
> >first_line_bpg_offset) |
> +		DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
> +		DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
>  	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 6, pps_val);
> 
>  	/* PPS 7 */
> -	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> -		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
> +	pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> +		DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 7, pps_val);
> 
>  	/* PPS 8 */
> -	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> -		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
> +	pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
> +		DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 8, pps_val);
> 
>  	/* PPS 9 */
> -	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> -		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> +	pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> +
> 	DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 9, pps_val);
> 
>  	/* PPS 10 */
> -	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
> -		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1)
> |
> -		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> -
> 	DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> +	pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
> +		DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg-
> >rc_quant_incr_limit1) |
> +
> 	DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> +
> 	DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 10, pps_val);
> 
>  	/* PPS 16 */
> -	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> -		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
> -				   vdsc_cfg->slice_width) |
> -		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> -					vdsc_cfg->slice_height);
> +	pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size)
> |
> +		DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
> +					 vdsc_cfg->slice_width) |
> +		DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
> +					      vdsc_cfg->slice_height);
>  	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 16, pps_val);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		/* PPS 17 */
> -		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
>  		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 17, pps_val);
> 
>  		/* PPS 18 */
> -		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> -			DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
> +		pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg-
> >nsl_bpg_offset) |
> +			DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
>  		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 18, pps_val);
>  	}
> @@ -857,15 +857,15 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	/* PPS 0 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
> 
> -	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >>
> DSC_BPC_SHIFT;
> +	vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK)
> >>
> +DSC_PPS0_BPC_SHIFT;
>  	vdsc_cfg->line_buf_depth =
> -		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >>
> DSC_LINE_BUF_DEPTH_SHIFT;
> -	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
> -	vdsc_cfg->convert_rgb = pps_temp &
> DSC_COLOR_SPACE_CONVERSION;
> -	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
> -	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
> -	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
> -	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
> +		(pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >>
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> +	vdsc_cfg->block_pred_enable = pps_temp &
> DSC_PPS0_BLOCK_PREDICTION;
> +	vdsc_cfg->convert_rgb = pps_temp &
> DSC_PPS0_COLOR_SPACE_CONVERSION;
> +	vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
> +	vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
> +	vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
> +	vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
> 
>  	/* PPS 1 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); @@ -880,74
> +880,74 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
>  	/* PPS 2 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
> 
> -	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
> -	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK,
> pps_temp);
> +	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK,
> pps_temp) / num_vdsc_instances;
> +	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK,
> +pps_temp);
> 
>  	/* PPS 3 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
> 
> -	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK,
> pps_temp);
> -	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK,
> pps_temp);
> +	vdsc_cfg->slice_width =
> REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
> +	vdsc_cfg->slice_height =
> REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK,
> +pps_temp);
> 
>  	/* PPS 4 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
> 
> -	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
> -	vdsc_cfg->initial_xmit_delay =
> REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
> +	vdsc_cfg->initial_dec_delay =
> REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
> +	vdsc_cfg->initial_xmit_delay =
> +REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
> 
>  	/* PPS 5 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
> 
> -	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
> -	vdsc_cfg->scale_increment_interval =
> REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
> +	vdsc_cfg->scale_decrement_interval =
> REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
> +	vdsc_cfg->scale_increment_interval =
> +REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
> 
>  	/* PPS 6 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
> 
> -	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
> -	vdsc_cfg->first_line_bpg_offset =
> REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
> -	vdsc_cfg->flatness_min_qp =
> REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
> -	vdsc_cfg->flatness_max_qp =
> REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
> +	vdsc_cfg->initial_scale_value =
> REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
> +	vdsc_cfg->first_line_bpg_offset =
> REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->flatness_min_qp =
> REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
> +	vdsc_cfg->flatness_max_qp =
> +REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
> 
>  	/* PPS 7 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
> 
> -	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
> -	vdsc_cfg->slice_bpg_offset =
> REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->nfl_bpg_offset =
> REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->slice_bpg_offset =
> +REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
> 
>  	/* PPS 8 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
> 
> -	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK,
> pps_temp);
> -	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK,
> pps_temp);
> +	vdsc_cfg->initial_offset =
> REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
> +	vdsc_cfg->final_offset =
> REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK,
> +pps_temp);
> 
>  	/* PPS 9 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
> 
> -	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
> +	vdsc_cfg->rc_model_size =
> REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK,
> +pps_temp);
> 
>  	/* PPS 10 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
> 
> -	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
> -	vdsc_cfg->rc_quant_incr_limit1 =
> REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> +	vdsc_cfg->rc_quant_incr_limit0 =
> REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
> +	vdsc_cfg->rc_quant_incr_limit1 =
> +REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
> 
>  	/* PPS 16 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
> 
> -	vdsc_cfg->slice_chunk_size =
> REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
> +	vdsc_cfg->slice_chunk_size =
> +REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
> 
>  	if (DISPLAY_VER(i915) >= 14) {
>  		/* PPS 17 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
> 
> -		vdsc_cfg->second_line_bpg_offset =
> REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
> +		vdsc_cfg->second_line_bpg_offset =
> +REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
> 
>  		/* PPS 18 */
>  		pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
> 
> -		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
> -		vdsc_cfg->second_line_offset_adj =
> REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
> +		vdsc_cfg->nsl_bpg_offset =
> REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
> +		vdsc_cfg->second_line_offset_adj =
> +REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 58d282dcfc6f..92782de2b309 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -73,115 +73,115 @@
>  #define  ICL_DSC1_PPS(pipe, pps)
> 	_MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
> 
>  /* PPS 0 */
> -#define  DSC_NATIVE_422_ENABLE		BIT(23)
> -#define  DSC_NATIVE_420_ENABLE		BIT(22)
> -#define  DSC_ALT_ICH_SEL		(1 << 20)
> -#define  DSC_VBR_ENABLE			(1 << 19)
> -#define  DSC_422_ENABLE			(1 << 18)
> -#define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
> -#define  DSC_BLOCK_PREDICTION		(1 << 16)
> -#define  DSC_LINE_BUF_DEPTH_SHIFT	12
> -#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)
> -#define  DSC_BPC_SHIFT			8
> -#define  DSC_BPC_MASK			REG_GENMASK(11, 8)
> -#define  DSC_VER_MIN_SHIFT		4
> -#define  DSC_VER_MAJ			(0x1 << 0)
> +#define   DSC_PPS0_NATIVE_422_ENABLE		BIT(23)
> +#define   DSC_PPS0_NATIVE_420_ENABLE		BIT(22)
> +#define   DSC_PPS0_ALT_ICH_SEL			(1 << 20)
> +#define   DSC_PPS0_VBR_ENABLE			(1 << 19)
> +#define   DSC_PPS0_422_ENABLE			(1 << 18)
> +#define   DSC_PPS0_COLOR_SPACE_CONVERSION	(1 << 17)
> +#define   DSC_PPS0_BLOCK_PREDICTION		(1 << 16)
> +#define   DSC_PPS0_LINE_BUF_DEPTH_SHIFT		12
> +#define   DSC_PPS0_LINE_BUF_DEPTH_MASK		REG_GENMASK(15,
> 12)
> +#define   DSC_PPS0_BPC_SHIFT			8
> +#define   DSC_PPS0_BPC_MASK			REG_GENMASK(11, 8)
> +#define   DSC_PPS0_VER_MIN_SHIFT		4
> +#define   DSC_PPS0_VER_MAJ			(0x1 << 0)
> 
>  /* PPS 1 */
> -#define  DSC_BPP(bpp)				((bpp) << 0)
> +#define   DSC_PPS1_BPP(bpp)			((bpp) << 0)
> 
>  /* PPS 2 */
> -#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
> -#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> -#define  DSC_PIC_WIDTH(pic_width)
> 	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
> -#define  DSC_PIC_HEIGHT(pic_height)
> 	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
> +#define   DSC_PPS2_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
> +#define   DSC_PPS2_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS2_PIC_WIDTH(pic_width)
> 	REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
> +#define   DSC_PPS2_PIC_HEIGHT(pic_height)
> 	REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
> 
>  /* PPS 3 */
> -#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31,
> 16)
> -#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
> -#define  DSC_SLICE_WIDTH(slice_width)
> 	REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
> -#define  DSC_SLICE_HEIGHT(slice_height)
> 	REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
> +#define   DSC_PPS3_SLICE_WIDTH_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS3_SLICE_HEIGHT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS3_SLICE_WIDTH(slice_width)
> 	REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
> +#define   DSC_PPS3_SLICE_HEIGHT(slice_height)
> 	REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
> 
>  /* PPS 4 */
> -#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31,
> 16)
> -#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
> -#define  DSC_INITIAL_DEC_DELAY(dec_delay)
> REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
> +#define   DSC_PPS4_INITIAL_DEC_DELAY_MASK	REG_GENMASK(31,
> 16)
> +#define   DSC_PPS4_INITIAL_XMIT_DELAY_MASK	REG_GENMASK(9, 0)
> +#define   DSC_PPS4_INITIAL_DEC_DELAY(dec_delay)
> 	REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
>  							       dec_delay)
> -#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)
> REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
> -							       xmit_delay)
> +#define   DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay)
> 	REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
> +
> xmit_delay)
> 
>  /* PPS 5 */
> -#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27,
> 16)
> -#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
> -#define  DSC_SCALE_DEC_INT(scale_dec)
> 	REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
> -#define  DSC_SCALE_INC_INT(scale_inc)
> 	REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
> +#define   DSC_PPS5_SCALE_DEC_INT_MASK		REG_GENMASK(27,
> 16)
> +#define   DSC_PPS5_SCALE_INC_INT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS5_SCALE_DEC_INT(scale_dec)
> 	REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
> +#define   DSC_PPS5_SCALE_INC_INT(scale_inc)
> 	REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
> 
>  /* PPS 6 */
> -#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28,
> 24)
> -#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20,
> 16)
> -#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
> -#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)
> -#define  DSC_FLATNESS_MAX_QP(max_qp)
> 	REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
> -#define  DSC_FLATNESS_MIN_QP(min_qp)
> 	REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
> -#define  DSC_FIRST_LINE_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
> -							       offset)
> -#define  DSC_INITIAL_SCALE_VALUE(value)
> 	REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
> +#define   DSC_PPS6_FLATNESS_MAX_QP_MASK
> 	REG_GENMASK(28, 24)
> +#define   DSC_PPS6_FLATNESS_MIN_QP_MASK		REG_GENMASK(20,
> 16)
> +#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK	REG_GENMASK(12, 8)
> +#define   DSC_PPS6_INITIAL_SCALE_VALUE_MASK	REG_GENMASK(5, 0)
> +#define   DSC_PPS6_FLATNESS_MAX_QP(max_qp)
> 	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
> +#define   DSC_PPS6_FLATNESS_MIN_QP(min_qp)
> 	REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
> +#define   DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
> +								       offset)
> +#define   DSC_PPS6_INITIAL_SCALE_VALUE(value)
> 	REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
>  							       value)
> 
>  /* PPS 7 */
> -#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
> -#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
> -#define  DSC_NFL_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
> -#define  DSC_SLICE_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
> +#define   DSC_PPS7_NFL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS7_SLICE_BPG_OFFSET_MASK	REG_GENMASK(15, 0)
> +#define   DSC_PPS7_NFL_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
> +#define   DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset)
> 	REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
>  							       bpg_offset)
>  /* PPS 8 */
> -#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
> -#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
> -#define  DSC_INITIAL_OFFSET(initial_offset)
> 	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
> -							       initial_offset)
> -#define  DSC_FINAL_OFFSET(final_offset)
> 	REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
> +#define   DSC_PPS8_INITIAL_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS8_FINAL_OFFSET_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS8_INITIAL_OFFSET(initial_offset)
> 	REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
> +
> initial_offset)
> +#define   DSC_PPS8_FINAL_OFFSET(final_offset)
> 	REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
>  							       final_offset)
> 
>  /* PPS 9 */
> -#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19,
> 16)
> -#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
> -#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)
> 	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
> +#define   DSC_PPS9_RC_EDGE_FACTOR_MASK		REG_GENMASK(19,
> 16)
> +#define   DSC_PPS9_RC_MODEL_SIZE_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact)
> 	REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
>  							       rc_edge_fact)
> -#define  DSC_RC_MODEL_SIZE(rc_model_size)
> 	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
> +#define   DSC_PPS9_RC_MODEL_SIZE(rc_model_size)
> 	REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
>  							       rc_model_size)
> 
>  /* PPS 10 */
> -#define  DSC_RC_TGT_OFF_LOW_MASK
> 	REG_GENMASK(23, 20)
> -#define  DSC_RC_TGT_OFF_HIGH_MASK
> 	REG_GENMASK(19, 16)
> -#define  DSC_RC_QUANT_INC_LIMIT1_MASK
> 	REG_GENMASK(12, 8)
> -#define  DSC_RC_QUANT_INC_LIMIT0_MASK
> 	REG_GENMASK(4, 0)
> -#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)
> 	REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \
> +#define   DSC_PPS10_RC_TGT_OFF_LOW_MASK
> 	REG_GENMASK(23, 20)
> +#define   DSC_PPS10_RC_TGT_OFF_HIGH_MASK	REG_GENMASK(19,
> 16)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK	REG_GENMASK(12, 8)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK	REG_GENMASK(4, 0)
> +#define   DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low)
> 	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
> 
> rc_tgt_off_low)
> -#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)
> 	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \
> +#define   DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high)
> 	REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
> 
> rc_tgt_off_high)
> -#define  DSC_RC_QUANT_INC_LIMIT1(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
> -#define  DSC_RC_QUANT_INC_LIMIT0(lim)
> 	REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT1(lim)
> 	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
> +#define   DSC_PPS10_RC_QUANT_INC_LIMIT0(lim)
> 	REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
> 
>  /* PPS 16 */
> -#define  DSC_SLICE_ROW_PR_FRME_MASK
> 	REG_GENMASK(31, 20)
> -#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18,
> 16)
> -#define  DSC_SLICE_CHUNK_SIZE_MASK
> 	REG_GENMASK(15, 0)
> -#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)
> 	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \
> -
> slice_row_per_frame)
> -#define  DSC_SLICE_PER_LINE(slice_per_line)
> 	REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
> -
> slice_per_line)
> -#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
> 	REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
> -
> slice_chunk_size)
> +#define   DSC_PPS16_SLICE_ROW_PR_FRME_MASK	REG_GENMASK(31,
> 20)
> +#define   DSC_PPS16_SLICE_PER_LINE_MASK		REG_GENMASK(18,
> 16)
> +#define   DSC_PPS16_SLICE_CHUNK_SIZE_MASK	REG_GENMASK(15, 0)
> +#define   DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
> +
> slice_row_per_frame)
> +#define   DSC_PPS16_SLICE_PER_LINE(slice_per_line)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
> +
> slice_per_line)
> +#define   DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size)
> 	REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
> +
> slice_chunk_size)
> 
>  /* PPS 17 (MTL+) */
> -#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 27)
> -#define DSC_SL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
> +#define   DSC_PPS17_SL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 27)
> +#define   DSC_PPS17_SL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
> 
>  /* PPS 18 (MTL+) */
> -#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31,
> 16)
> -#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
> -#define DSC_NSL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
> -#define DSC_SL_OFFSET_ADJ(offset)
> 	REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
> +#define   DSC_PPS18_NSL_BPG_OFFSET_MASK		REG_GENMASK(31,
> 16)
> +#define   DSC_PPS18_SL_OFFSET_ADJ_MASK		REG_GENMASK(15, 0)
> +#define   DSC_PPS18_NSL_BPG_OFFSET(offset)
> 	REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
> +#define   DSC_PPS18_SL_OFFSET_ADJ(offset)
> 	REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
> 
>  /* Icelake Rate Control Buffer Threshold Registers */
>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 5/8] drm/i915/dsc: drop redundant = 0 assignments

[Kandpal, Suraj]

> Subject: [PATCH 5/8] drm/i915/dsc: drop redundant = 0 assignments
> 
> Directly assign the values instead of first assigning 0 and then |= the values.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 43 ++++++++---------------
>  1 file changed, 15 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 4086dbb25ca5..73bfa4d6633d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -415,7 +415,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	enum pipe pipe = crtc->pipe;
> -	u32 pps_val = 0;
> +	u32 pps_val;
>  	u32 rc_buf_thresh_dword[4];
>  	u32 rc_range_params_dword[8];
>  	int i = 0;
> @@ -446,42 +446,36 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	intel_dsc_pps_write(crtc_state, 0, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_1 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
> +	pps_val = DSC_BPP(vdsc_cfg->bits_per_pixel);
>  	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 1, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_2 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
> +	pps_val = DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
>  		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
>  	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 2, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_3 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
> +	pps_val = DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
>  		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
>  	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 3, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_4 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
> +	pps_val = DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
>  		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
>  	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 4, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_5 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
> +	pps_val = DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
>  		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
>  	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 5, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_6 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
> +	pps_val = DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
>  		DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset)
> |
>  		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
>  		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
> @@ -489,29 +483,25 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	intel_dsc_pps_write(crtc_state, 6, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_7 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
> +	pps_val = DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
>  		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 7, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_8 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
> +	pps_val = DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
>  		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
>  	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 8, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_9 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> +	pps_val = DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
>  		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
>  	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
>  	intel_dsc_pps_write(crtc_state, 9, pps_val);
> 
>  	/* Populate PICTURE_PARAMETER_SET_10 registers */
> -	pps_val = 0;
> -	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
> +	pps_val = DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg-
> >rc_quant_incr_limit0) |
>  		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1)
> |
>  		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST)
> |
> 
> 	DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
> @@ -519,8 +509,7 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  	intel_dsc_pps_write(crtc_state, 10, pps_val);
> 
>  	/* Populate Picture parameter set 16 */
> -	pps_val = 0;
> -	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
> +	pps_val = DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
>  		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width /
> num_vdsc_instances) /
>  				   vdsc_cfg->slice_width) |
>  		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / @@ -
> 530,15 +519,13 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		/* Populate PICTURE_PARAMETER_SET_17 registers */
> -		pps_val = 0;
> -		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		pps_val = DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
>  		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 17, pps_val);
> 
>  		/* Populate PICTURE_PARAMETER_SET_18 registers */
> -		pps_val = 0;
> -		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> -			   DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
> +		pps_val = DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> +			DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
>  		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
>  		intel_dsc_pps_write(crtc_state, 18, pps_val);
>  	}
> --
> 2.39.2

Re: [Intel-gfx] [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write helpers

[Jani Nikula]

On Thu, 07 Sep 2023, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: [PATCH 1/8] drm/i915/dsc: improve clarify of the pps reg read/write
>> helpers
>
> Should be clarity here in the commit header

Thanks, fixed.

>
> With that fixed
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks for the reviews, pushed the lot to drm-intel-next.

BR,
Jani.


>>
>> Make it clear what's the number of vdsc per pipe, and what's the number of
>> registers to grab. Have intel_dsc_get_pps_reg() return the registers it knows
>> even if the requested amount is bigger.
>>
>> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_vdsc.c | 40 ++++++++++++-----------
>>  1 file changed, 21 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index b24601d0b2c5..14317bb6d3df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -372,7 +372,7 @@ int intel_dsc_get_num_vdsc_instances(const struct
>> intel_crtc_state *crtc_state)  }
>>
>>  static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int
>> pps,
>> -                               i915_reg_t *dsc_reg, int vdsc_per_pipe)
>> +                               i915_reg_t *dsc_reg, int dsc_reg_num)
>>  {
>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -
>> 381,16 +381,12 @@ static void intel_dsc_get_pps_reg(const struct
>> intel_crtc_state *crtc_state, int
>>
>>       pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>>
>> -     switch (vdsc_per_pipe) {
>> -     case 2:
>> +     if (dsc_reg_num >= 3)
>> +             MISSING_CASE(dsc_reg_num);
>> +     if (dsc_reg_num >= 2)
>>               dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) :
>> DSCC_PPS(pps);
>> -             fallthrough;
>> -     case 1:
>> +     if (dsc_reg_num >= 1)
>>               dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) :
>> DSCA_PPS(pps);
>> -             break;
>> -     default:
>> -             MISSING_CASE(vdsc_per_pipe);
>> -     }
>>  }
>>
>>  static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
>> @@ -399,13 +395,16 @@ static void intel_dsc_write_pps_reg(const struct
>> intel_crtc_state *crtc_state,
>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>       i915_reg_t dsc_reg[2];
>> -     int i, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>> +     int i, vdsc_per_pipe, dsc_reg_num;
>> +
>> +     vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>> +     dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>>
>> -     drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) <
>> vdsc_per_pipe);
>> +     drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
>>
>> -     intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
>> +     intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>>
>> -     for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++)
>> +     for (i = 0; i < dsc_reg_num; i++)
>>               intel_de_write(i915, dsc_reg[i], pps_val);  }
>>
>> @@ -815,16 +814,19 @@ static bool intel_dsc_read_pps_reg(struct
>> intel_crtc_state *crtc_state,  {
>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> -     const int vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>>       i915_reg_t dsc_reg[2];
>> -     int i;
>> +     int i, vdsc_per_pipe, dsc_reg_num;
>>
>> -     *pps_val = 0;
>> -     drm_WARN_ON_ONCE(&i915->drm, ARRAY_SIZE(dsc_reg) <
>> vdsc_per_pipe);
>> +     vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
>> +     dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
>>
>> -     intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
>> +     drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe);
>> +
>> +     intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
>> +
>> +     *pps_val = 0;
>>
>> -     for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) {
>> +     for (i = 0; i < dsc_reg_num; i++) {
>>               u32 pps_temp;
>>
>>               pps_temp = intel_de_read(i915, dsc_reg[i]);
>> --
>> 2.39.2
>

-- 
Jani Nikula, Intel Open Source Graphics Center