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* [Intel-gfx] [PATCH stable-5.4] drm/i915: Correctly set SFC capability for video engines
@ 2020-11-17  0:03 Daniele Ceraolo Spurio
  2020-11-17  0:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Correctly set SFC capability for video engines (rev2) Patchwork
  2020-11-17 10:19 ` [Intel-gfx] [PATCH stable-5.4] drm/i915: Correctly set SFC capability for video engines Greg KH
  0 siblings, 2 replies; 3+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-11-17  0:03 UTC (permalink / raw)
  To: stable; +Cc: intel-gfx, Chris Wilson

From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>

Commit 5ce6861d36ed5207aff9e5eead4c7cc38a986586 upstream.

This backport targets stable version 5.4, since the original patch fails
to apply there, due to a variable having moved from one struct to another.
The only change required for the patch to apply to 5.4 is to use the
correct structure:

 -	(engine->gt->info.vdbox_sfc_access &
++	(RUNTIME_INFO(i915)->vdbox_sfc_access &

Original commit message below.

SFC capability of video engines is not set correctly because i915
is testing for incorrect bits.

Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: <stable@vger.kernel.org> # v5.3+
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201106011842.36203-1-daniele.ceraolospurio@intel.com
(cherry picked from commit ad18fa0f5f052046cad96fee762b5c64f42dd86a)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4ce8626b140e..8073758d1036 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -354,7 +354,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 		 * instances.
 		 */
 		if ((INTEL_GEN(i915) >= 11 &&
-		     RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) ||
+		     (RUNTIME_INFO(i915)->vdbox_sfc_access &
+		      BIT(engine->instance))) ||
 		    (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
-- 
2.29.2

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2020-11-17  0:03 [Intel-gfx] [PATCH stable-5.4] drm/i915: Correctly set SFC capability for video engines Daniele Ceraolo Spurio
2020-11-17  0:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Correctly set SFC capability for video engines (rev2) Patchwork
2020-11-17 10:19 ` [Intel-gfx] [PATCH stable-5.4] drm/i915: Correctly set SFC capability for video engines Greg KH

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