[Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches

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* [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches
@ 2023-02-22  7:34 Radhakrishna Sripada
  2023-02-22  7:34 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation Radhakrishna Sripada
                   ` (11 more replies)
  0 siblings, 12 replies; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:34 UTC (permalink / raw)
  To: intel-gfx

This series adds patches needed for Meteorlake platform.

There are 2 GT related patches 1 to handle interrupts for both
render and media gt, 1 patches to generate per gt debug files.

There are 4 patches for CCS support, 1 for the phy to hold its values
during dc9 entry/exit, 1 fbdev related fix, 1 patch that fixes implementation
of a workaround.

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Andi Shyti (1):
  drm/i915/gt: generate per tile debugfs files

Clint Taylor (1):
  drm/i915/mtl: Add MTL for remapping CCS FBs

José Roberto de Souza (1):
  drm/i915/display/mtl: Program latch to phy reset

Juha-Pekka Heikkilä (2):
  drm/i915/mtl: define MTL related ccs modifiers
  drm/i915/mtl: Add handling for MTL ccs modifiers

Pallavi Mishra (1):
  drm/i915/mtl: Drop FLAT CCS check

Radhakrishna Sripada (2):
  drm/i915/mtl: Fix Wa_14015855405 implementation
  drm/i915/mtl: make IRQ reset and postinstall multi-gt aware

Tejas Upadhyay (1):
  drm/i915/fbdev: lock the fbdev obj before vma pin

 .../drm/i915/display/intel_display_power.c    |  8 +++
 drivers/gpu/drm/i915/display/intel_dmc.c      | 35 +++++++++++--
 drivers/gpu/drm/i915/display/intel_fb.c       | 51 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_fbdev.c    | 24 ++++++---
 .../drm/i915/display/skl_universal_plane.c    | 22 +++++++-
 drivers/gpu/drm/i915/gt/intel_gt_debugfs.c    |  4 +-
 drivers/gpu/drm/i915/gt/intel_migrate.c       |  4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c    |  5 +-
 drivers/gpu/drm/i915/i915_irq.c               | 28 ++++++----
 drivers/gpu/drm/i915/i915_reg.h               | 12 +++--
 include/uapi/drm/drm_fourcc.h                 | 43 ++++++++++++++++
 12 files changed, 204 insertions(+), 34 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
@ 2023-02-22  7:34 ` Radhakrishna Sripada
  2023-02-22 18:53   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
                   ` (10 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:34 UTC (permalink / raw)
  To: intel-gfx

The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.

Implement the workaround with the correct register.

Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 35 ++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h          | 10 +++++--
 2 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index f70ada2357dc..0e478ede66e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
 	}
 }
 
-static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
 {
 	enum pipe pipe;
 
-	if (DISPLAY_VER(i915) < 13)
-		return;
-
 	/*
-	 * Wa_16015201720:adl-p,dg2, mtl
+	 * Wa_16015201720:adl-p,dg2
 	 * The WA requires clock gating to be disabled all the time
 	 * for pipe A and B.
 	 * For pipe C and D clock gating needs to be disabled only
@@ -413,6 +410,34 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
 				     PIPEDMC_GATING_DIS, 0);
 }
 
+static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+{
+	/*
+	 * Wa_14015855405
+	 * The WA requires clock gating to be disabled all the time
+	 * for pipe A and B.
+	 * For pipe C and D clock gating needs to be disabled only
+	 * during initializing the firmware.
+	 * TODO/FIXME: WA deviates wrt. enable/disable for Pipes C, D. Needs recheck.
+	 * For now carry-forward the implementation for dg2.
+	 */
+	if (enable)
+		intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
+			     MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B |
+			     MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D);
+	else
+		intel_de_rmw(i915, GEN9_CLKGATE_DIS_0,
+			     MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D, 0);
+}
+
+static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+{
+	if (DISPLAY_VER(i915) >= 14)
+		return mtl_pipedmc_clock_gating_wa(i915, enable);
+	else if (DISPLAY_VER(i915) == 13)
+		return adlp_pipedmc_clock_gating_wa(i915, enable);
+}
+
 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
 {
 	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1efa655fb68..7c9ac5b43831 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,9 +1794,13 @@
  * GEN9 clock gating regs
  */
 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
-#define   DARBF_GATING_DIS		(1 << 27)
-#define   PWM2_GATING_DIS		(1 << 14)
-#define   PWM1_GATING_DIS		(1 << 13)
+#define   DARBF_GATING_DIS		REG_BIT(27)
+#define   MTL_PIPEDMC_GATING_DIS_A	REG_BIT(15)
+#define   MTL_PIPEDMC_GATING_DIS_B	REG_BIT(14)
+#define   PWM2_GATING_DIS		REG_BIT(14)
+#define   MTL_PIPEDMC_GATING_DIS_C	REG_BIT(13)
+#define   PWM1_GATING_DIS		REG_BIT(13)
+#define   MTL_PIPEDMC_GATING_DIS_D	REG_BIT(12)
 
 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
 #define   TGL_VRH_GATING_DIS		REG_BIT(31)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation
  2023-02-22  7:34 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation Radhakrishna Sripada
@ 2023-02-22 18:53   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 18:53 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:34:59PM -0800, Radhakrishna Sripada wrote:
> The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> extended the workaround Wa_16015201720 to MTL. However the registers
> that the original WA implemented moved for MTL.
> 
> Implement the workaround with the correct register.

The title is still incorrect.  14015855405 is not a workaround lineage
number; you want Wa_16015201720 as you have in the commit message.

> 
> Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 35 ++++++++++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h          | 10 +++++--
>  2 files changed, 37 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f70ada2357dc..0e478ede66e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
>  	}
>  }
>  
> -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
>  {
>  	enum pipe pipe;
>  
> -	if (DISPLAY_VER(i915) < 13)
> -		return;
> -
>  	/*
> -	 * Wa_16015201720:adl-p,dg2, mtl
> +	 * Wa_16015201720:adl-p,dg2
>  	 * The WA requires clock gating to be disabled all the time
>  	 * for pipe A and B.
>  	 * For pipe C and D clock gating needs to be disabled only
> @@ -413,6 +410,34 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
>  				     PIPEDMC_GATING_DIS, 0);
>  }
>  
> +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> +	/*
> +	 * Wa_14015855405

This number is incorrect as well.

> +	 * The WA requires clock gating to be disabled all the time
> +	 * for pipe A and B.
> +	 * For pipe C and D clock gating needs to be disabled only
> +	 * during initializing the firmware.
> +	 * TODO/FIXME: WA deviates wrt. enable/disable for Pipes C, D. Needs recheck.
> +	 * For now carry-forward the implementation for dg2.

Why are we deviating from the documented workaround?  As far as I can
see, there's nothing asking us to do this (on any platform).  And why
would we handle enable/disable in a different manner?  For that matter,
there's nothing specifically asking us to re-enable clock-gating during
suspend/unload either.  We should probably clarify the expectations with
the hardware people before landing this patch.


Matt

> +	 */
> +	if (enable)
> +		intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> +			     MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B |
> +			     MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D);
> +	else
> +		intel_de_rmw(i915, GEN9_CLKGATE_DIS_0,
> +			     MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D, 0);
> +}
> +
> +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> +	if (DISPLAY_VER(i915) >= 14)
> +		return mtl_pipedmc_clock_gating_wa(i915, enable);
> +	else if (DISPLAY_VER(i915) == 13)
> +		return adlp_pipedmc_clock_gating_wa(i915, enable);
> +}
> +
>  void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
>  {
>  	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1efa655fb68..7c9ac5b43831 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,9 +1794,13 @@
>   * GEN9 clock gating regs
>   */
>  #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
> -#define   DARBF_GATING_DIS		(1 << 27)
> -#define   PWM2_GATING_DIS		(1 << 14)
> -#define   PWM1_GATING_DIS		(1 << 13)
> +#define   DARBF_GATING_DIS		REG_BIT(27)
> +#define   MTL_PIPEDMC_GATING_DIS_A	REG_BIT(15)
> +#define   MTL_PIPEDMC_GATING_DIS_B	REG_BIT(14)
> +#define   PWM2_GATING_DIS		REG_BIT(14)
> +#define   MTL_PIPEDMC_GATING_DIS_C	REG_BIT(13)
> +#define   PWM1_GATING_DIS		REG_BIT(13)
> +#define   MTL_PIPEDMC_GATING_DIS_D	REG_BIT(12)
>  
>  #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
>  #define   TGL_VRH_GATING_DIS		REG_BIT(31)
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
  2023-02-22  7:34 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:00   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
                   ` (9 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

In the view of multi-gt we want independent per gt debug files.

In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
tiles, the debugfs would be structured as follows:

/sys/kernel/debug/dri
                  └── 0
                      ├── gt0
                      │   ├── drpc
                      │   ├── engines
                      │   ├── forcewake
                      │   ├── frequency
                      │   └── rps_boost
                      ├── gt1
                      │   ├── drpc
                      │   ├── engines
                      │   ├── forcewake
                      │   ├── frequency
                      │   └── rps_boost
                      ├── gt2
                      │   ├── drpc
                      │   ├── engines
                      │   ├── forcewake
                      │   ├── frequency
                      │   └── rps_boost
                      └─- gt3
                      :   ├── drpc
                      :   ├── engines
                      :   ├── forcewake
                          ├── frequency
                          └── rps_boost

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h     | 2 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 5fc2df01aa0d..4dc23b8d3aa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
 void intel_gt_debugfs_register(struct intel_gt *gt)
 {
 	struct dentry *root;
+	char gtname[4];
 
 	if (!gt->i915->drm.primary->debugfs_root)
 		return;
 
-	root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
+	snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
+	root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
 	if (IS_ERR(root))
 		return;
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bb4dfe707a7d..e46aac1a41e6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -42,6 +42,8 @@ struct intel_guc {
 	/** @capture: the error-state-capture module's data and objects */
 	struct intel_guc_state_capture *capture;
 
+	struct dentry *dbgfs_node;
+
 	/** @sched_engine: Global engine used to submit requests to GuC */
 	struct i915_sched_engine *sched_engine;
 	/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 818e9e0e66a8..6eefbe6e3519 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
 	 */
 	n_subbufs = 8;
 
+	if (!guc->dbgfs_node)
+		return -ENOENT;
+
 	guc_log_relay_chan = relay_open("guc_log",
-					dev_priv->drm.primary->debugfs_root,
+					guc->dbgfs_node,
 					subbuf_size, n_subbufs,
 					&relay_callbacks, dev_priv);
 	if (!guc_log_relay_chan) {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
@ 2023-02-22 19:00   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:00 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:00PM -0800, Radhakrishna Sripada wrote:
> From: Andi Shyti <andi.shyti@intel.com>
> 
> In the view of multi-gt we want independent per gt debug files.
> 
> In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
> tiles, the debugfs would be structured as follows:
> 
> /sys/kernel/debug/dri
>                   └── 0
>                       ├── gt0
>                       │   ├── drpc
>                       │   ├── engines
>                       │   ├── forcewake
>                       │   ├── frequency
>                       │   └── rps_boost
>                       ├── gt1
>                       │   ├── drpc
>                       │   ├── engines
>                       │   ├── forcewake
>                       │   ├── frequency
>                       │   └── rps_boost
>                       ├── gt2
>                       │   ├── drpc
>                       │   ├── engines
>                       │   ├── forcewake
>                       │   ├── frequency
>                       │   └── rps_boost
>                       └─- gt3
>                       :   ├── drpc
>                       :   ├── engines
>                       :   ├── forcewake
>                           ├── frequency
>                           └── rps_boost
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc.h     | 2 ++
>  drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++-
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 5fc2df01aa0d..4dc23b8d3aa2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
>  void intel_gt_debugfs_register(struct intel_gt *gt)
>  {
>  	struct dentry *root;
> +	char gtname[4];
>  
>  	if (!gt->i915->drm.primary->debugfs_root)
>  		return;
>  
> -	root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> +	snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> +	root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
>  	if (IS_ERR(root))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bb4dfe707a7d..e46aac1a41e6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -42,6 +42,8 @@ struct intel_guc {
>  	/** @capture: the error-state-capture module's data and objects */
>  	struct intel_guc_state_capture *capture;
>  
> +	struct dentry *dbgfs_node;
> +
>  	/** @sched_engine: Global engine used to submit requests to GuC */
>  	struct i915_sched_engine *sched_engine;
>  	/**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 818e9e0e66a8..6eefbe6e3519 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
>  	 */
>  	n_subbufs = 8;
>  
> +	if (!guc->dbgfs_node)
> +		return -ENOENT;

Is this patch incomplete?  It doesn't look like dbgfs_node ever gets
assigned, so this is always going to bail out early?


Matt

> +
>  	guc_log_relay_chan = relay_open("guc_log",
> -					dev_priv->drm.primary->debugfs_root,
> +					guc->dbgfs_node,
>  					subbuf_size, n_subbufs,
>  					&relay_callbacks, dev_priv);
>  	if (!guc_log_relay_chan) {
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
  2023-02-22  7:34 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation Radhakrishna Sripada
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 15:19   ` Lucas De Marchi
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
                   ` (8 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

Irq reset and post install are to be made multi-gt aware for the
interrupts to work for the media tile on Meteorlake. Iterate through
all the gts to process irq reset for each gt.

Based on original version by Paulo and Tvrtko
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b024a3a7ca19..be1212a5f4c5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2761,14 +2761,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_gt *gt = to_gt(dev_priv);
 	struct intel_uncore *uncore = gt->uncore;
+	unsigned int i;
 
 	dg1_master_intr_disable(dev_priv->uncore.regs);
 
-	gen11_gt_irq_reset(gt);
-	gen11_display_irq_reset(dev_priv);
+	for_each_gt(gt, dev_priv, i) {
+		gen11_gt_irq_reset(gt);
 
-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+		uncore = gt->uncore;
+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+	}
+
+	gen11_display_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3422,13 +3427,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	struct intel_gt *gt = to_gt(dev_priv);
-	struct intel_uncore *uncore = gt->uncore;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+	struct intel_gt *gt;
+	unsigned int i;
 
-	gen11_gt_irq_postinstall(gt);
+	for_each_gt(gt, dev_priv, i) {
+		gen11_gt_irq_postinstall(gt);
 
-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+			      gu_misc_masked);
+	}
 
 	if (HAS_DISPLAY(dev_priv)) {
 		icp_irq_postinstall(dev_priv);
@@ -3437,8 +3445,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
 				   GEN11_DISPLAY_IRQ_ENABLE);
 	}
 
-	dg1_master_intr_enable(uncore->regs);
-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+	dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
+	intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
 }
 
 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
@ 2023-02-22 15:19   ` Lucas De Marchi
  0 siblings, 0 replies; 21+ messages in thread
From: Lucas De Marchi @ 2023-02-22 15:19 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:01PM -0800, Radhakrishna Sripada wrote:
>Irq reset and post install are to be made multi-gt aware for the
>interrupts to work for the media tile on Meteorlake. Iterate through
>all the gts to process irq reset for each gt.
>
>Based on original version by Paulo and Tvrtko

add a blank line here so the sentence above is not part of the commit
trailers.

>Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++----------
> 1 file changed, 18 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b024a3a7ca19..be1212a5f4c5 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2761,14 +2761,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> {
> 	struct intel_gt *gt = to_gt(dev_priv);
> 	struct intel_uncore *uncore = gt->uncore;

probably better to remove these 2, so it's explicit what we are doing on
a gt level and what we are doing on a device/root-gt level.

struct intel_gt *gt;

>+	unsigned int i;
>
> 	dg1_master_intr_disable(dev_priv->uncore.regs);
>
>-	gen11_gt_irq_reset(gt);
>-	gen11_display_irq_reset(dev_priv);
>+	for_each_gt(gt, dev_priv, i) {
>+		gen11_gt_irq_reset(gt);

ok

>
>-	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
>-	GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>+		uncore = gt->uncore;

remove this line

>+		GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
>+		GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>+	}

s/uncore/gt->uncore/

>+
>+	gen11_display_irq_reset(dev_priv);
> }
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>@@ -3422,13 +3427,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>
> static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct intel_gt *gt = to_gt(dev_priv);
>-	struct intel_uncore *uncore = gt->uncore;
> 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>+	struct intel_gt *gt;
>+	unsigned int i;
>
>-	gen11_gt_irq_postinstall(gt);
>+	for_each_gt(gt, dev_priv, i) {
>+		gen11_gt_irq_postinstall(gt);
>
>-	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
>+		GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
>+			      gu_misc_masked);
>+	}

yep, the postinstall matches the logic I mentioned above.


with the changes above,

	
	Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

>
> 	if (HAS_DISPLAY(dev_priv)) {
> 		icp_irq_postinstall(dev_priv);
>@@ -3437,8 +3445,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> 				   GEN11_DISPLAY_IRQ_ENABLE);
> 	}
>
>-	dg1_master_intr_enable(uncore->regs);
>-	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
>+	dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
>+	intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
> }
>
> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
>-- 
>2.34.1
>

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (2 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:07   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
                   ` (7 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Tejas Upadhyay <tejas.upadhyay@intel.com>

lock the fbdev obj before calling into
i915_vma_pin_iomap(). This helps to solve below :

<7>[   93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
<4>[   93.581844] ------------[ cut here ]------------
<4>[   93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915]

Fixes: b473df22760f9 ("backport "drm/i915: Add ww context to intel_dpt_pin, v2.")
Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbdev.c | 24 ++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 3659350061a7..2766d7ef0128 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
 	bool prealloc = false;
 	void __iomem *vaddr;
 	struct drm_i915_gem_object *obj;
+	struct i915_gem_ww_ctx ww;
 	int ret;
 
 	mutex_lock(&ifbdev->hpd_lock);
@@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper,
 		info->fix.smem_len = vma->size;
 	}
 
-	vaddr = i915_vma_pin_iomap(vma);
-	if (IS_ERR(vaddr)) {
-		drm_err(&dev_priv->drm,
-			"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
-		ret = PTR_ERR(vaddr);
-		goto out_unpin;
+	for_i915_gem_ww(&ww, ret, false) {
+		ret = i915_gem_object_lock(vma->obj, &ww);
+
+		if (ret)
+			continue;
+
+		vaddr = i915_vma_pin_iomap(vma);
+		if (IS_ERR(vaddr)) {
+			drm_err(&dev_priv->drm,
+					"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
+			ret = PTR_ERR(vaddr);
+			continue;
+		}
 	}
+
+	if (ret)
+		goto out_unpin;
+
 	info->screen_base = vaddr;
 	info->screen_size = vma->size;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
@ 2023-02-22 19:07   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:07 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:02PM -0800, Radhakrishna Sripada wrote:
> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
> 
> lock the fbdev obj before calling into
> i915_vma_pin_iomap(). This helps to solve below :
> 
> <7>[   93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
> <4>[   93.581844] ------------[ cut here ]------------
> <4>[   93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915]
> 
> Fixes: b473df22760f9 ("backport "drm/i915: Add ww context to intel_dpt_pin, v2.")

This Fixes line isn't correct.  I think you wanted:

Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

BTW, your git-sendemail configuration seems to be incorrect; even though
there are Cc's in the body of several of your patches, they're not being
picked up to send copies to the necessary people.


Matt

> Cc: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbdev.c | 24 ++++++++++++++++------
>  1 file changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 3659350061a7..2766d7ef0128 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
>  	bool prealloc = false;
>  	void __iomem *vaddr;
>  	struct drm_i915_gem_object *obj;
> +	struct i915_gem_ww_ctx ww;
>  	int ret;
>  
>  	mutex_lock(&ifbdev->hpd_lock);
> @@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper,
>  		info->fix.smem_len = vma->size;
>  	}
>  
> -	vaddr = i915_vma_pin_iomap(vma);
> -	if (IS_ERR(vaddr)) {
> -		drm_err(&dev_priv->drm,
> -			"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
> -		ret = PTR_ERR(vaddr);
> -		goto out_unpin;
> +	for_i915_gem_ww(&ww, ret, false) {
> +		ret = i915_gem_object_lock(vma->obj, &ww);
> +
> +		if (ret)
> +			continue;
> +
> +		vaddr = i915_vma_pin_iomap(vma);
> +		if (IS_ERR(vaddr)) {
> +			drm_err(&dev_priv->drm,
> +					"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
> +			ret = PTR_ERR(vaddr);
> +			continue;
> +		}
>  	}
> +
> +	if (ret)
> +		goto out_unpin;
> +
>  	info->screen_base = vaddr;
>  	info->screen_size = vma->size;
>  
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (3 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:13   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check Radhakrishna Sripada
                   ` (6 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: José Roberto de Souza <jose.souza@intel.com>

Latch reset of phys during DC9 and when driver is unloaded to avoid
phy reset.

Specification ask us to program it closer to the step that enables
DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
latch during driver load.

BSpec: 49197
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h                    | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 743b919bb2cf..50098c77e3be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	intel_power_well_enable(dev_priv, well);
 	mutex_unlock(&power_domains->lock);
 
+	if (DISPLAY_VER(dev_priv) == 14)
+		intel_de_rmw(dev_priv, DC_STATE_EN,
+			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
+
 	/* 4. Enable CDCLK. */
 	intel_cdclk_init_hw(dev_priv);
 
@@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 	/* 3. Disable CD clock */
 	intel_cdclk_uninit_hw(dev_priv);
 
+	if (DISPLAY_VER(dev_priv) == 14)
+		intel_de_rmw(dev_priv, DC_STATE_EN, 0,
+			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
+
 	/*
 	 * 4. Disable Power Well 1 (PG1).
 	 *    The AUX IO power wells are toggled on demand, so they are already
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c9ac5b43831..fa1905cc5a99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7360,6 +7360,8 @@ enum skl_power_gate {
 #define  DC_STATE_DISABLE		0
 #define  DC_STATE_EN_DC3CO		REG_BIT(30)
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
+#define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
+#define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
@ 2023-02-22 19:13   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:13 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:03PM -0800, Radhakrishna Sripada wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> Latch reset of phys during DC9 and when driver is unloaded to avoid
> phy reset.
> 
> Specification ask us to program it closer to the step that enables
> DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
> latch during driver load.
> 
> BSpec: 49197
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 ++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 743b919bb2cf..50098c77e3be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	intel_power_well_enable(dev_priv, well);
>  	mutex_unlock(&power_domains->lock);
>  
> +	if (DISPLAY_VER(dev_priv) == 14)
> +		intel_de_rmw(dev_priv, DC_STATE_EN,
> +			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
> +
>  	/* 4. Enable CDCLK. */
>  	intel_cdclk_init_hw(dev_priv);
>  
> @@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
>  	/* 3. Disable CD clock */
>  	intel_cdclk_uninit_hw(dev_priv);
>  
> +	if (DISPLAY_VER(dev_priv) == 14)
> +		intel_de_rmw(dev_priv, DC_STATE_EN, 0,
> +			     HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
> +
>  	/*
>  	 * 4. Disable Power Well 1 (PG1).
>  	 *    The AUX IO power wells are toggled on demand, so they are already
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c9ac5b43831..fa1905cc5a99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7360,6 +7360,8 @@ enum skl_power_gate {
>  #define  DC_STATE_DISABLE		0
>  #define  DC_STATE_EN_DC3CO		REG_BIT(30)
>  #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
> +#define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
> +#define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>  #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>  #define  DC_STATE_EN_DC9		(1 << 3)
>  #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (4 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:16   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs Radhakrishna Sripada
                   ` (5 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Pallavi Mishra <pallavi.mishra@intel.com>

Remove FLAT CCS check from XY_FAST_COLOR_BLT usage, thus
enabling MTL to use it.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 3f638f198796..e0998879a0e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -920,7 +920,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
 
 	GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
 
-	if (HAS_FLAT_CCS(i915) && ver >= 12)
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 		ring_sz = XY_FAST_COLOR_BLT_DW;
 	else if (ver >= 8)
 		ring_sz = 8;
@@ -931,7 +931,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	if (HAS_FLAT_CCS(i915) && ver >= 12) {
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 		*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
 			(XY_FAST_COLOR_BLT_DW - 2);
 		*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check Radhakrishna Sripada
@ 2023-02-22 19:16   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:16 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:04PM -0800, Radhakrishna Sripada wrote:
> From: Pallavi Mishra <pallavi.mishra@intel.com>
> 
> Remove FLAT CCS check from XY_FAST_COLOR_BLT usage, thus
> enabling MTL to use it.

The title "Drop FLAT CCS check" seems incomplete; it makes it sound like
we're dropping the checks everywhere any treating MTL as a FlatCCS
platform (which would be incorrect) when in reality we're just switching
one specific operation to a version check instead of feature check
because it was never really tied to FlatCCS in the first place.  It
might be good to elaborate on the reasoning in the commit message too.


Matt

> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_migrate.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 3f638f198796..e0998879a0e1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -920,7 +920,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
>  
>  	GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
>  
> -	if (HAS_FLAT_CCS(i915) && ver >= 12)
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>  		ring_sz = XY_FAST_COLOR_BLT_DW;
>  	else if (ver >= 8)
>  		ring_sz = 8;
> @@ -931,7 +931,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
>  
> -	if (HAS_FLAT_CCS(i915) && ver >= 12) {
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>  		*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
>  			(XY_FAST_COLOR_BLT_DW - 2);
>  		*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (5 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:26   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers Radhakrishna Sripada
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Clint Taylor <clinton.a.taylor@intel.com>

    Add support for remapping CCS FBs on MTL to remove the restriction
    of the power-of-two sized stride and the 2MB surface offset alignment
    for these FBs.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 799bdc81a6a9..fc4cb829e8af 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1189,7 +1189,8 @@ bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
 {
 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
 
-	return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
+	return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
+	       fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
 }
 
 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
@@ -1325,9 +1326,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
 			  unsigned int tile_width,
 			  unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
 {
+	struct drm_i915_private *i915 = to_i915(fb->base.dev);
 	unsigned int stride_tiles;
 
-	if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
+	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 		stride_tiles = src_stride_tiles;
 	else
 		stride_tiles = dst_stride_tiles;
@@ -1521,7 +1523,8 @@ static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_vi
 	memset(view, 0, sizeof(*view));
 	view->gtt.type = view_type;
 
-	if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
+	if (view_type == I915_GTT_VIEW_REMAPPED &&
+	    (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
 		view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
 }
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs Radhakrishna Sripada
@ 2023-02-22 19:26   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:26 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:05PM -0800, Radhakrishna Sripada wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
>     Add support for remapping CCS FBs on MTL to remove the restriction
>     of the power-of-two sized stride and the 2MB surface offset alignment
>     for these FBs.

There's strange/unwanted indentation here...

The "Add MTL for..." part of the title also seems confusing to me.  It
might be worth rewording?

> 
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fb.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 799bdc81a6a9..fc4cb829e8af 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -1189,7 +1189,8 @@ bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
>  {
>  	struct drm_i915_private *i915 = to_i915(fb->base.dev);
>  
> -	return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
> +	return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&

We're updating this condition in a few places (and may need to update it
again in the future); it might be worth creating a feature flag for
this, since I'm not sure if it's definitely going to carry forward to
all future platforms.


Matt

> +	       fb->base.modifier != DRM_FORMAT_MOD_LINEAR;
>  }
>  
>  static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
> @@ -1325,9 +1326,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
>  			  unsigned int tile_width,
>  			  unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
>  {
> +	struct drm_i915_private *i915 = to_i915(fb->base.dev);
>  	unsigned int stride_tiles;
>  
> -	if (IS_ALDERLAKE_P(to_i915(fb->base.dev)))
> +	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
>  		stride_tiles = src_stride_tiles;
>  	else
>  		stride_tiles = dst_stride_tiles;
> @@ -1521,7 +1523,8 @@ static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_vi
>  	memset(view, 0, sizeof(*view));
>  	view->gtt.type = view_type;
>  
> -	if (view_type == I915_GTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
> +	if (view_type == I915_GTT_VIEW_REMAPPED &&
> +	    (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
>  		view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
>  }
>  
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (6 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22 19:29   ` Matt Roper
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/mtl: Add handling for MTL " Radhakrishna Sripada
                   ` (3 subsequent siblings)
  11 siblings, 1 reply; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Add Tile4 type ccs modifiers with aux buffer needed for MTL

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 43 +++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index de703c6be969..cbe214adf1e4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -657,6 +657,49 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
 
+/*
+ * Intel color control surfaces (CCS) for display ver 14 render compression.
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
+
+/*
+ * Intel color control surfaces (CCS) for display ver 14 media compression
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for display ver 14 render
+ * compression.
+ *
+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers Radhakrishna Sripada
@ 2023-02-22 19:29   ` Matt Roper
  0 siblings, 0 replies; 21+ messages in thread
From: Matt Roper @ 2023-02-22 19:29 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

On Tue, Feb 21, 2023 at 11:35:06PM -0800, Radhakrishna Sripada wrote:
> From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> 
> Add Tile4 type ccs modifiers with aux buffer needed for MTL
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

This is defining new uapi, so you need Cc's for all the relevant
usermode drivers (and acks from them).  In fact it's probably best to
break this out to its own series for visibility rather than mixing it
into the middle of a MTL enablement series.


Matt

> ---
>  include/uapi/drm/drm_fourcc.h | 43 +++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index de703c6be969..cbe214adf1e4 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -657,6 +657,49 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
>  
> +/*
> + * Intel color control surfaces (CCS) for display ver 14 render compression.
> + *
> + * The main surface is tile4 and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * tile4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
> +
> +/*
> + * Intel color control surfaces (CCS) for display ver 14 media compression
> + *
> + * The main surface is tile4 and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
> + * planes 2 and 3 for the respective CCS.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
> +
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for display ver 14 render
> + * compression.
> + *
> + * The main surface is tile4 and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] [PATCH v2 9/9] drm/i915/mtl: Add handling for MTL ccs modifiers
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (7 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers Radhakrishna Sripada
@ 2023-02-22  7:35 ` Radhakrishna Sripada
  2023-02-22  8:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Misc Meteorlake patches (rev2) Patchwork
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 21+ messages in thread
From: Radhakrishna Sripada @ 2023-02-22  7:35 UTC (permalink / raw)
  To: intel-gfx

From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>

Add Tile4 ccs modifiers w/ auxbuffer handling

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c       | 42 ++++++++++++++++++-
 .../drm/i915/display/skl_universal_plane.c    | 22 +++++++++-
 2 files changed, 61 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index fc4cb829e8af..4db245f4c70b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -157,6 +157,32 @@ struct intel_modifier_desc {
 
 static const struct intel_modifier_desc intel_modifiers[] = {
 	{
+		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
+		.display_ver = { 14, 14 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+
+		.ccs.packed_aux_planes = BIT(1),
+		.ccs.planar_aux_planes = BIT(2) | BIT(3),
+
+		FORMAT_OVERRIDE(gen12_ccs_formats),
+	}, {
+		.modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
+		.display_ver = { 14, 14 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
+
+		.ccs.packed_aux_planes = BIT(1),
+
+		FORMAT_OVERRIDE(gen12_ccs_formats),
+	}, {
+		.modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,
+		.display_ver = { 14, 14 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
+
+		.ccs.cc_planes = BIT(2),
+		.ccs.packed_aux_planes = BIT(1),
+
+		FORMAT_OVERRIDE(gen12_ccs_cc_formats),
+	}, {
 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
 		.display_ver = { 13, 13 },
 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
@@ -370,6 +396,14 @@ static bool plane_has_modifier(struct drm_i915_private *i915,
 	if (!plane_caps_contain_all(plane_caps, md->plane_caps))
 		return false;
 
+	/*
+	 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms
+	 * where supported.
+	 */
+	if (intel_fb_is_ccs_modifier(md->modifier) &&
+	   HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
+		return false;
+
 	return true;
 }
 
@@ -489,7 +523,7 @@ static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, in
 {
 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 
-	return check_modifier_display_ver_range(md, 12, 13) &&
+	return check_modifier_display_ver_range(md, 12, 14) &&
 	       ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
 }
 
@@ -605,6 +639,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 			return 128;
 		fallthrough;
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
@@ -790,6 +827,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 		return 16 * 1024;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ce55b8f09301..af4a1baa46d1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -790,6 +790,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 			PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+		return PLANE_CTL_TILED_4 |
+			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+			PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
+		return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2161,6 +2169,11 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
+	/* Wa_14017240301 */
+	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		return false;
+
 	/* Wa_22011186057 */
 	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
@@ -2442,12 +2455,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			if (DISPLAY_VER(dev_priv) >= 12)
+			if (DISPLAY_VER(dev_priv) >= 14)
+				fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
+			else if (DISPLAY_VER(dev_priv) >= 12)
 				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
 			else
 				fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
 		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+			if (DISPLAY_VER(dev_priv) >= 14)
+				fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
+			else
+				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Misc Meteorlake patches (rev2)
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (8 preceding siblings ...)
  2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/mtl: Add handling for MTL " Radhakrishna Sripada
@ 2023-02-22  8:04 ` Patchwork
  2023-02-22 15:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2023-02-22 16:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-02-22  8:04 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

== Series Details ==

Series: Misc Meteorlake patches (rev2)
URL   : https://patchwork.freedesktop.org/series/112700/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Misc Meteorlake patches (rev2)
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (9 preceding siblings ...)
  2023-02-22  8:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Misc Meteorlake patches (rev2) Patchwork
@ 2023-02-22 15:06 ` Patchwork
  2023-02-22 16:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-02-22 15:06 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 13913 bytes --]

== Series Details ==

Series: Misc Meteorlake patches (rev2)
URL   : https://patchwork.freedesktop.org/series/112700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12768 -> Patchwork_112700v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/index.html

Participating hosts (38 -> 37)
------------------------------

  Additional (1): bat-atsm-1 
  Missing    (2): bat-dg1-6 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_112700v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@eof:
    - bat-atsm-1:         NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@fbdev@eof.html

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][2] -> [FAIL][3] ([i915#7229])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_lmem_swapping@basic:
    - fi-apl-guc:         NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [PASS][8] -> [DMESG-FAIL][9] ([i915#5334] / [i915#7872])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
    - fi-skl-6600u:       [PASS][10] -> [DMESG-FAIL][11] ([i915#5334])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html
    - fi-apl-guc:         NOTRUN -> [DMESG-FAIL][12] ([i915#5334])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
    - bat-adln-1:         [PASS][13] -> [INCOMPLETE][14] ([i915#4983] / [i915#7609])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-adln-1/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [PASS][15] -> [DMESG-WARN][16] ([i915#7699])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [PASS][17] -> [ABORT][18] ([i915#7982])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-2/igt@i915_selftest@live@requests.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-rpls-2/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-1:         [PASS][19] -> [ABORT][20] ([i915#4983] / [i915#7981])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-1/igt@i915_selftest@live@reset.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-rpls-1/igt@i915_selftest@live@reset.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-atsm-1:         NOTRUN -> [SKIP][21] ([i915#6645])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][22] ([i915#6077]) +36 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-apl-guc:         NOTRUN -> [SKIP][23] ([fdo#109271])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-apl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor:
    - bat-atsm-1:         NOTRUN -> [SKIP][24] ([i915#6078]) +14 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor.html

  * igt@kms_flip@basic-plain-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][25] ([i915#6166]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_flip@basic-plain-flip.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-atsm-1:         NOTRUN -> [SKIP][26] ([i915#6093]) +3 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@hang-read-crc:
    - bat-atsm-1:         NOTRUN -> [SKIP][27] ([i915#1836]) +6 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][28] ([i915#7357])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-atsm-1:         NOTRUN -> [SKIP][29] ([i915#1072]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][30] ([i915#6094])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][31] ([fdo#109295] / [i915#6078])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-atsm-1:         NOTRUN -> [SKIP][32] ([fdo#109295] / [i915#4077]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][33] ([fdo#109295]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-apl-guc:         [ABORT][34] -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-7:          [SKIP][36] ([i915#6621]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg1-7/igt@i915_pm_rps@basic-api.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg1-7/igt@i915_pm_rps@basic-api.html
    - bat-rpls-2:         [SKIP][38] ([i915#6621]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-2/igt@i915_pm_rps@basic-api.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-rpls-2/igt@i915_pm_rps@basic-api.html
    - bat-adlp-9:         [SKIP][40] ([i915#6621]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-adlp-9/igt@i915_pm_rps@basic-api.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-adlp-9/igt@i915_pm_rps@basic-api.html
    - bat-adlp-6:         [SKIP][42] ([i915#6621]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-adlp-6/igt@i915_pm_rps@basic-api.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-adlp-6/igt@i915_pm_rps@basic-api.html
    - bat-rplp-1:         [SKIP][44] ([i915#6621]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rplp-1/igt@i915_pm_rps@basic-api.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-rplp-1/igt@i915_pm_rps@basic-api.html
    - bat-dg1-5:          [SKIP][46] ([i915#6621]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg1-5/igt@i915_pm_rps@basic-api.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg1-5/igt@i915_pm_rps@basic-api.html
    - bat-dg2-9:          [SKIP][48] ([i915#6621]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg2-9/igt@i915_pm_rps@basic-api.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg2-9/igt@i915_pm_rps@basic-api.html
    - bat-dg2-11:         [SKIP][50] ([i915#6621]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg2-11/igt@i915_pm_rps@basic-api.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg2-11/igt@i915_pm_rps@basic-api.html
    - bat-adln-1:         [SKIP][52] ([i915#6621]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-adln-1/igt@i915_pm_rps@basic-api.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-adln-1/igt@i915_pm_rps@basic-api.html
    - bat-dg2-8:          [SKIP][54] ([i915#6621]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-dg2-8/igt@i915_pm_rps@basic-api.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-dg2-8/igt@i915_pm_rps@basic-api.html
    - bat-adlm-1:         [SKIP][56] ([i915#6621]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-adlm-1/igt@i915_pm_rps@basic-api.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-adlm-1/igt@i915_pm_rps@basic-api.html
    - bat-rpls-1:         [SKIP][58] ([i915#6621]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-1/igt@i915_pm_rps@basic-api.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/bat-rpls-1/igt@i915_pm_rps@basic-api.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
  [i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
  [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
  [i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
  [i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982


Build changes
-------------

  * Linux: CI_DRM_12768 -> Patchwork_112700v2

  CI-20190529: 20190529
  CI_DRM_12768: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7168: 165df656261863684067cd53f95c3a301e67fa24 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112700v2: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

1ac5aefe18b9 drm/i915/mtl: Add handling for MTL ccs modifiers
6d41b19f30d5 drm/i915/mtl: define MTL related ccs modifiers
c9400b1fe9f1 drm/i915/mtl: Add MTL for remapping CCS FBs
74c112d12c8b drm/i915/mtl: Drop FLAT CCS check
1e01b09bce9d drm/i915/display/mtl: Program latch to phy reset
09243ecd1582 drm/i915/fbdev: lock the fbdev obj before vma pin
6ecbd2a6e8d0 drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
15f4d9bbf837 drm/i915/gt: generate per tile debugfs files
aa2122e3e211 drm/i915/mtl: Fix Wa_14015855405 implementation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/index.html

[-- Attachment #2: Type: text/html, Size: 16655 bytes --]

^ permalink raw reply	[flat|nested] 21+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Misc Meteorlake patches (rev2)
  2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
                   ` (10 preceding siblings ...)
  2023-02-22 15:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-02-22 16:26 ` Patchwork
  11 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-02-22 16:26 UTC (permalink / raw)
  To: Radhakrishna Sripada; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 38656 bytes --]

== Series Details ==

Series: Misc Meteorlake patches (rev2)
URL   : https://patchwork.freedesktop.org/series/112700/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12768_full -> Patchwork_112700v2_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/index.html

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_112700v2_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rps@basic-api:
    - {shard-dg1}:        [SKIP][1] ([i915#6621]) -> [FAIL][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-dg1-18/igt@i915_pm_rps@basic-api.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-dg1-16/igt@i915_pm_rps@basic-api.html

  * {igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-edp-1}:
    - {shard-rkl}:        NOTRUN -> [SKIP][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-edp-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_112700v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@nullptr:
    - shard-tglu-9:       NOTRUN -> [SKIP][4] ([i915#2582])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@fbdev@nullptr.html

  * igt@feature_discovery@chamelium:
    - shard-tglu-9:       NOTRUN -> [SKIP][5] ([fdo#111827]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@feature_discovery@chamelium.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-tglu-9:       NOTRUN -> [SKIP][6] ([i915#5325])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglu-9:       NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu-9:       NOTRUN -> [SKIP][10] ([i915#7582])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-tglu-10:      NOTRUN -> [SKIP][11] ([i915#4613]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_media_vme:
    - shard-tglu-9:       NOTRUN -> [SKIP][12] ([i915#284])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_media_vme.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-tglu-9:       NOTRUN -> [SKIP][13] ([i915#4270]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-on:
    - shard-tglu-10:      NOTRUN -> [SKIP][14] ([i915#4270]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@gem_pxp@reject-modify-context-protection-on.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-tglu-9:       NOTRUN -> [SKIP][15] ([fdo#109312])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_userptr_blits@access-control:
    - shard-tglu-10:      NOTRUN -> [SKIP][16] ([i915#3297]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu-9:       NOTRUN -> [SKIP][17] ([i915#3323])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu-9:       NOTRUN -> [SKIP][18] ([i915#3297])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-tglu-10:      NOTRUN -> [SKIP][19] ([fdo#109289]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglu-10:      NOTRUN -> [SKIP][20] ([i915#2527] / [i915#2856]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-9:       NOTRUN -> [SKIP][21] ([i915#2527] / [i915#2856]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@gen9_exec_parse@bb-large.html

  * igt@i915_hwmon@hwmon-read:
    - shard-tglu-9:       NOTRUN -> [SKIP][22] ([i915#7707])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@i915_hwmon@hwmon-read.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-tglu-10:      NOTRUN -> [SKIP][23] ([fdo#111644] / [i915#1397])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_pm_rpm@pc8-residency:
    - shard-tglu-9:       NOTRUN -> [SKIP][24] ([fdo#109506]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@i915_pm_rpm@pc8-residency.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-tglu-10:      NOTRUN -> [INCOMPLETE][25] ([i915#7443])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-tglu-10:      NOTRUN -> [SKIP][26] ([i915#5286])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglu-10:      NOTRUN -> [SKIP][27] ([fdo#111614]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-tglu-10:      NOTRUN -> [SKIP][28] ([fdo#111615]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglu-9:       NOTRUN -> [SKIP][29] ([fdo#111615] / [i915#1845] / [i915#7651]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][30] ([i915#6095]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][32] ([i915#3689] / [i915#6095]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
    - shard-tglu-9:       NOTRUN -> [SKIP][33] ([i915#1845] / [i915#7651]) +53 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglu-10:      NOTRUN -> [SKIP][34] ([i915#3689] / [i915#3886]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium_color@gamma:
    - shard-tglu-10:      NOTRUN -> [SKIP][35] ([fdo#111827])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-tglu-9:       NOTRUN -> [SKIP][36] ([i915#7828]) +4 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-tglu-10:      NOTRUN -> [SKIP][37] ([i915#7828]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_color@ctm-0-75:
    - shard-tglu-9:       NOTRUN -> [SKIP][38] ([i915#3546])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_color@ctm-0-75.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-tglu-9:       NOTRUN -> [SKIP][39] ([i915#1845]) +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu-10:      NOTRUN -> [SKIP][40] ([fdo#109279] / [i915#3359])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-tglu-10:      NOTRUN -> [SKIP][41] ([i915#3555])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-tglu-10:      NOTRUN -> [SKIP][42] ([fdo#109274]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-apl:          [PASS][43] -> [FAIL][44] ([i915#2346])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu-10:      NOTRUN -> [SKIP][45] ([i915#3528])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglu-10:      NOTRUN -> [FAIL][46] ([i915#4767])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-tglu-9:       NOTRUN -> [SKIP][47] ([fdo#109274] / [i915#3637])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-tglu-10:      NOTRUN -> [SKIP][48] ([fdo#109274] / [i915#3637])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][49] -> [FAIL][50] ([i915#79]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@nonexisting-fb:
    - shard-tglu-9:       NOTRUN -> [SKIP][51] ([i915#3637]) +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_flip@nonexisting-fb.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-tglu-10:      NOTRUN -> [SKIP][52] ([i915#2587] / [i915#2672]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271]) +25 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
    - shard-tglu-9:       NOTRUN -> [SKIP][54] ([i915#1849]) +35 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu:
    - shard-tglu-10:      NOTRUN -> [SKIP][55] ([fdo#109280]) +11 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-tglu-10:      NOTRUN -> [SKIP][56] ([fdo#110189]) +6 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-tglu-9:       NOTRUN -> [SKIP][57] ([i915#7128] / [i915#7294])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-1:
    - shard-tglu-10:      NOTRUN -> [SKIP][58] ([i915#5176]) +3 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling:
    - shard-tglu-9:       NOTRUN -> [SKIP][59] ([i915#3555]) +7 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-tglu-9:       NOTRUN -> [SKIP][60] ([i915#6953] / [i915#8152]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][61] ([fdo#109271]) +7 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-snb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-tglu-10:      NOTRUN -> [SKIP][62] ([i915#658])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr@psr2_basic:
    - shard-tglu-9:       NOTRUN -> [SKIP][63] ([fdo#110189]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_psr@psr2_basic.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-tglu-9:       NOTRUN -> [SKIP][64] ([i915#5461])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_setmode@basic@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [FAIL][65] ([i915#5465]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-snb2/igt@kms_setmode@basic@pipe-a-vga-1.html

  * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b:
    - shard-tglu-9:       NOTRUN -> [SKIP][66] ([fdo#109274]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html

  * igt@perf@polling-small-buf:
    - shard-tglu-9:       NOTRUN -> [FAIL][67] ([i915#1722])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@perf@polling-small-buf.html

  * igt@prime_vgem@coherency-gtt:
    - shard-tglu-9:       NOTRUN -> [SKIP][68] ([fdo#109295] / [fdo#111656])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@prime_vgem@coherency-gtt.html

  * igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
    - shard-tglu-9:       NOTRUN -> [SKIP][69] ([fdo#109315] / [i915#2575]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html

  * igt@v3d/v3d_perfmon@get-values-invalid-pointer:
    - shard-tglu-10:      NOTRUN -> [SKIP][70] ([fdo#109315] / [i915#2575])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html

  * igt@vc4/vc4_create_bo@create-bo-0:
    - shard-tglu-10:      NOTRUN -> [SKIP][71] ([i915#2575]) +3 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-10/igt@vc4/vc4_create_bo@create-bo-0.html

  * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
    - shard-tglu-9:       NOTRUN -> [SKIP][72] ([i915#2575]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-9/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html

  
#### Possible fixes ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - {shard-rkl}:        [SKIP][73] ([i915#3281]) -> [PASS][74] +4 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@fbdev@info:
    - {shard-rkl}:        [SKIP][75] ([i915#2582]) -> [PASS][76] +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-3/igt@fbdev@info.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@fbdev@info.html

  * {igt@gem_barrier_race@remote-request@rcs0}:
    - {shard-dg1}:        [DMESG-WARN][77] -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-dg1-18/igt@gem_barrier_race@remote-request@rcs0.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-dg1-16/igt@gem_barrier_race@remote-request@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][79] ([i915#6268]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-deadline:
    - {shard-rkl}:        [FAIL][81] ([i915#2846]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][83] ([i915#2842]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - {shard-rkl}:        [FAIL][85] ([i915#2842]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - {shard-rkl}:        [FAIL][87] ([fdo#103375]) -> [PASS][88] +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_pread@bench:
    - {shard-rkl}:        [SKIP][89] ([i915#3282]) -> [PASS][90] +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@gem_pread@bench.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@gem_pread@bench.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - {shard-rkl}:        [SKIP][91] ([i915#2527]) -> [PASS][92] +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-6/igt@gen9_exec_parse@batch-invalid-length.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - {shard-rkl}:        [SKIP][93] ([i915#1397]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-3/igt@i915_pm_rpm@dpms-lpsp.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rpm@system-suspend-devices:
    - {shard-rkl}:        [FAIL][95] ([i915#7052]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-3/igt@i915_pm_rpm@system-suspend-devices.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@i915_pm_rpm@system-suspend-devices.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - {shard-rkl}:        [SKIP][97] ([fdo#109308]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@i915_pm_rpm@system-suspend-modeset.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-apl:          [DMESG-FAIL][99] ([i915#5334]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_suspend@sysfs-reader:
    - {shard-tglu}:       [ABORT][101] ([i915#5122]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-tglu-1/igt@i915_suspend@sysfs-reader.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-tglu-3/igt@i915_suspend@sysfs-reader.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - {shard-rkl}:        [SKIP][103] ([i915#1845] / [i915#4098]) -> [PASS][104] +24 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-3/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [FAIL][105] ([i915#4767]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [ABORT][107] -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - {shard-rkl}:        [SKIP][109] ([i915#1849] / [i915#4098]) -> [PASS][110] +15 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_psr@sprite_plane_onoff:
    - {shard-rkl}:        [SKIP][111] ([i915#1072]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@kms_psr@sprite_plane_onoff.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@perf@mi-rpc:
    - {shard-rkl}:        [SKIP][113] ([i915#2434]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-1/igt@perf@mi-rpc.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@perf@mi-rpc.html

  * igt@prime_vgem@basic-read:
    - {shard-rkl}:        [SKIP][115] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-4/igt@prime_vgem@basic-read.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@coherency-gtt:
    - {shard-rkl}:        [SKIP][117] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/shard-rkl-6/igt@prime_vgem@coherency-gtt.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/shard-rkl-5/igt@prime_vgem@coherency-gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6333]: https://gitlab.freedesktop.org/drm/intel/issues/6333
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152


Build changes
-------------

  * Linux: CI_DRM_12768 -> Patchwork_112700v2

  CI-20190529: 20190529
  CI_DRM_12768: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7168: 165df656261863684067cd53f95c3a301e67fa24 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112700v2: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v2/index.html

[-- Attachment #2: Type: text/html, Size: 38422 bytes --]

^ permalink raw reply	[flat|nested] 21+ messages in thread

end of thread, other threads:[~2023-02-22 19:30 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-22  7:34 [Intel-gfx] [PATCH v2 0/9] Misc Meteorlake patches Radhakrishna Sripada
2023-02-22  7:34 ` [Intel-gfx] [PATCH v2 1/9] drm/i915/mtl: Fix Wa_14015855405 implementation Radhakrishna Sripada
2023-02-22 18:53   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
2023-02-22 19:00   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
2023-02-22 15:19   ` Lucas De Marchi
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
2023-02-22 19:07   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
2023-02-22 19:13   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/mtl: Drop FLAT CCS check Radhakrishna Sripada
2023-02-22 19:16   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Add MTL for remapping CCS FBs Radhakrishna Sripada
2023-02-22 19:26   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/mtl: define MTL related ccs modifiers Radhakrishna Sripada
2023-02-22 19:29   ` Matt Roper
2023-02-22  7:35 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/mtl: Add handling for MTL " Radhakrishna Sripada
2023-02-22  8:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Misc Meteorlake patches (rev2) Patchwork
2023-02-22 15:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-22 16:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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