[Intel-gfx] [PATCH v3 0/4] drm/i915/mtl: Add OAG 32 bit format support for MTL

[Intel-gfx] [PATCH v3 0/4] drm/i915/mtl: Add OAG 32 bit format support for MTL

[Umesh Nerlige Ramappa]

Enable OA for MTL by adding 32-bit OA format support and relevant fixes.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Test-with: 20221129010522.994524-1-umesh.nerlige.ramappa@intel.com

Umesh Nerlige Ramappa (4):
  drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
  drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
  drm/i915/mtl: Update OA mux whitelist for MTL
  drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

 drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 ---
 drivers/gpu/drm/i915/i915_perf.c         | 49 ++++++++++++++++++------
 2 files changed, 38 insertions(+), 17 deletions(-)

-- 
2.38.1

[Intel-gfx] [PATCH v3 1/4] drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

[Umesh Nerlige Ramappa]

On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
caused a hang that was attributed to saving and restoring the GPR
registers used for noa_wait.

Add an additional page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 ------
 drivers/gpu/drm/i915/i915_perf.c         | 25 ++++++++++++++++--------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0b6da2aa9718..f08c2556aa25 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -304,12 +304,6 @@ enum intel_gt_scratch_field {
 
 	/* 8 bytes */
 	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
-
-	/* 6 * 8 bytes */
-	INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
-
-	/* 4 bytes */
-	INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
 };
 
 #endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d22f30dd4fba..a8b34460d36f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1846,8 +1846,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
 	for (d = 0; d < dword_count; d++) {
 		*cs++ = cmd;
 		*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
-		*cs++ = intel_gt_scratch_offset(stream->engine->gt,
-						offset) + 4 * d;
+		*cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
 		*cs++ = 0;
 	}
 
@@ -1880,7 +1879,13 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 					  MI_PREDICATE_RESULT_2_ENGINE(base) :
 					  MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
-	bo = i915_gem_object_create_internal(i915, 4096);
+	/*
+	 * gt->scratch was being used to save/restore the GPR registers, but on
+	 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
+	 * causes an engine hang. Instead allocate an additional page here to
+	 * save/restore GPR registers
+	 */
+	bo = i915_gem_object_create_internal(i915, 8192);
 	if (IS_ERR(bo)) {
 		drm_err(&i915->drm,
 			"Failed to allocate NOA wait batchbuffer\n");
@@ -1914,14 +1919,19 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 		goto err_unpin;
 	}
 
+	stream->noa_wait = vma;
+
+#define GPR_SAVE_OFFSET 4096
+#define PREDICATE_SAVE_OFFSET 4160
+
 	/* Save registers. */
 	for (i = 0; i < N_CS_GPR; i++)
 		cs = save_restore_register(
 			stream, cs, true /* save */, CS_GPR(i),
-			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+			GPR_SAVE_OFFSET + 8 * i, 2);
 	cs = save_restore_register(
 		stream, cs, true /* save */, mi_predicate_result,
-		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+		PREDICATE_SAVE_OFFSET, 1);
 
 	/* First timestamp snapshot location. */
 	ts0 = cs;
@@ -2037,10 +2047,10 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 	for (i = 0; i < N_CS_GPR; i++)
 		cs = save_restore_register(
 			stream, cs, false /* restore */, CS_GPR(i),
-			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+			GPR_SAVE_OFFSET + 8 * i, 2);
 	cs = save_restore_register(
 		stream, cs, false /* restore */, mi_predicate_result,
-		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+		PREDICATE_SAVE_OFFSET, 1);
 
 	/* And return to the ring. */
 	*cs++ = MI_BATCH_BUFFER_END;
@@ -2050,7 +2060,6 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
 	i915_gem_object_flush_map(bo);
 	__i915_gem_object_release_map(bo);
 
-	stream->noa_wait = vma;
 	goto out_ww;
 
 err_unpin:
-- 
2.38.1

[Intel-gfx] [PATCH v3 2/4] drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch

[Umesh Nerlige Ramappa]

Similar to ACM, OA timestamp that is part of the OA report is shifted
when compared to the CS timestamp. Add MTL to the WA.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a8b34460d36f..1a8618a787d6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3140,8 +3140,11 @@ get_sseu_config(struct intel_sseu *out_sseu,
  */
 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 {
-	/* Wa_18013179988:dg2 */
-	if (IS_DG2(i915)) {
+	/*
+	 * Wa_18013179988:dg2
+	 * Wa_14015846243:mtl
+	 */
+	if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
 		intel_wakeref_t wakeref;
 		u32 reg, shift;
 
-- 
2.38.1

[Intel-gfx] [PATCH v3 3/4] drm/i915/mtl: Update OA mux whitelist for MTL

[Umesh Nerlige Ramappa]

0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
a separate mux table to verify oa configs passed by user.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a8618a787d6..41f6c0923ba5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4322,6 +4322,17 @@ static const struct i915_range gen12_oa_mux_regs[] = {
 	{}
 };
 
+/*
+ * Ref: 14010536224:
+ * 0x20cc is repurposed on MTL, so use a separate array for MTL.
+ */
+static const struct i915_range mtl_oa_mux_regs[] = {
+	{ .start = 0x0d00, .end = 0x0d04 },	/* RPM_CONFIG[0-1] */
+	{ .start = 0x0d0c, .end = 0x0d2c },	/* NOA_CONFIG[0-8] */
+	{ .start = 0x9840, .end = 0x9840 },	/* GDT_CHICKEN_BITS */
+	{ .start = 0x9884, .end = 0x9888 },	/* NOA_WRITE */
+};
+
 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 {
 	return reg_in_range_table(addr, gen7_oa_b_counters);
@@ -4365,7 +4376,10 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
-	return reg_in_range_table(addr, gen12_oa_mux_regs);
+	if (IS_METEORLAKE(perf->i915))
+		return reg_in_range_table(addr, mtl_oa_mux_regs);
+	else
+		return reg_in_range_table(addr, gen12_oa_mux_regs);
 }
 
 static u32 mask_reg_value(u32 reg, u32 val)
-- 
2.38.1

[Intel-gfx] [PATCH v3 4/4] drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

[Umesh Nerlige Ramappa]

Without an entry in oa_init_supported_formats, OA will not be functional
in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20228

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 41f6c0923ba5..824a34ec0b83 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4776,6 +4776,7 @@ static void oa_init_supported_formats(struct i915_perf *perf)
 		break;
 
 	case INTEL_DG2:
+	case INTEL_METEORLAKE:
 		oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
 		oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
 		break;
-- 
2.38.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev3)
URL   : https://patchwork.freedesktop.org/series/111512/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3647 bytes --]

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev3)
URL   : https://patchwork.freedesktop.org/series/111512/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12491 -> Patchwork_111512v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_111512v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111512v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v3/index.html

Participating hosts (41 -> 6)
------------------------------

  ERROR: It appears as if the changes made in Patchwork_111512v3 prevented too many machines from booting.

  Missing    (35): fi-kbl-soraka fi-rkl-11600 fi-rkl-guc bat-adls-5 bat-dg1-5 fi-bdw-gvtdvm fi-icl-u2 bat-adlp-6 fi-pnv-d510 fi-skl-6600u fi-snb-2600 fi-bsw-n3050 fi-adl-ddr5 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-hsw-4770 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-elk-e7500 bat-dg2-11 fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u bat-kbl-2 bat-adlp-9 fi-skl-guc fi-glk-j4005 fi-ehl-2 fi-jsl-1 fi-cfl-guc bat-adlp-4 fi-kbl-8809g fi-bsw-kefka 

Known issues
------------

  Here are the changes found in Patchwork_111512v3 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@fbdev@read:
    - {bat-rpls-2}:       [SKIP][1] ([i915#2582]) -> [PASS][2] +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/bat-rpls-2/igt@fbdev@read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v3/bat-rpls-2/igt@fbdev@read.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-rpls-2}:       [DMESG-WARN][3] ([i915#6434]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/bat-rpls-2/igt@gem_exec_suspend@basic-s0@smem.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v3/bat-rpls-2/igt@gem_exec_suspend@basic-s0@smem.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7355]: https://gitlab.freedesktop.org/drm/intel/issues/7355
  [i915#7467]: https://gitlab.freedesktop.org/drm/intel/issues/7467


Build changes
-------------

  * IGT: IGT_7090 -> IGTPW_8166
  * Linux: CI_DRM_12491 -> Patchwork_111512v3

  CI-20190529: 20190529
  CI_DRM_12491: d322881f7e33af24901ee8ccaec3beef82f21203 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8166: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8166/index.html
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111512v3: d322881f7e33af24901ee8ccaec3beef82f21203 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

1f74a227d48b drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL
5544dfa5fc93 drm/i915/mtl: Update OA mux whitelist for MTL
3d0f93c4e73a drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
48b5e7bc23de drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v3/index.html

[-- Attachment #2: Type: text/html, Size: 4074 bytes --]

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)
URL   : https://patchwork.freedesktop.org/series/111512/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3006 bytes --]

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)
URL   : https://patchwork.freedesktop.org/series/111512/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12491 -> Patchwork_111512v4
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_111512v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111512v4, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html

Participating hosts (41 -> 5)
------------------------------

  ERROR: It appears as if the changes made in Patchwork_111512v4 prevented too many machines from booting.

  Missing    (36): fi-kbl-soraka fi-rkl-11600 fi-rkl-guc bat-adls-5 bat-dg1-5 fi-bdw-gvtdvm fi-icl-u2 bat-adlp-6 fi-pnv-d510 bat-rpls-2 fi-skl-6600u fi-snb-2600 fi-bsw-n3050 fi-adl-ddr5 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-hsw-4770 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-elk-e7500 bat-dg2-11 fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u bat-kbl-2 bat-adlp-9 fi-skl-guc fi-glk-j4005 fi-ehl-2 fi-jsl-1 fi-cfl-guc bat-adlp-4 fi-kbl-8809g fi-bsw-kefka 

Known issues
------------

  Here are the changes found in Patchwork_111512v4 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@gt_pm:
    - {bat-adln-1}:       [DMESG-FAIL][1] ([i915#4258]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/bat-adln-1/igt@i915_selftest@live@gt_pm.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/bat-adln-1/igt@i915_selftest@live@gt_pm.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258


Build changes
-------------

  * IGT: IGT_7090 -> IGTPW_8166
  * Linux: CI_DRM_12491 -> Patchwork_111512v4

  CI-20190529: 20190529
  CI_DRM_12491: d322881f7e33af24901ee8ccaec3beef82f21203 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8166: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8166/index.html
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111512v4: d322881f7e33af24901ee8ccaec3beef82f21203 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

9785f3767702 drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL
43cf178c5377 drm/i915/mtl: Update OA mux whitelist for MTL
ec5896546520 drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
1beb85683fa3 drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html

[-- Attachment #2: Type: text/html, Size: 3667 bytes --]

Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

[Upadhyay, Tejas]

Thanks for patch, looks like identifying MTL was needed here.
Acked-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Umesh Nerlige Ramappa
> Sent: Saturday, December 10, 2022 8:31 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 4/4] drm/i915/mtl: Add OA support by enabling
> 32 bit OAG formats for MTL
> 
> Without an entry in oa_init_supported_formats, OA will not be functional in
> MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
> 
> Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-
> /merge_requests/20228
> 
> Signed-off-by: Umesh Nerlige Ramappa
> <umesh.nerlige.ramappa@intel.com>
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 41f6c0923ba5..824a34ec0b83 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4776,6 +4776,7 @@ static void oa_init_supported_formats(struct
> i915_perf *perf)
>  		break;
> 
>  	case INTEL_DG2:
> +	case INTEL_METEORLAKE:
>  		oa_format_add(perf,
> I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
>  		oa_format_add(perf,
> I915_OA_FORMAT_A24u40_A14u32_B8_C8);
>  		break;
> --
> 2.38.1

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)

[Umesh Nerlige Ramappa]

On Sat, Dec 10, 2022 at 05:09:40PM +0000, Patchwork wrote:
>   Patch Details
>
>Series:  drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)
>URL:     [1]https://patchwork.freedesktop.org/series/111512/
>State:   failure
>Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html
>
>          CI Bug Log - changes from CI_DRM_12491 -> Patchwork_111512v4
>
>Summary
>
>   FAILURE
>
>   Serious unknown changes coming with Patchwork_111512v4 absolutely need to
>   be
>   verified manually.
>
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_111512v4, please notify your bug team to allow
>   them
>   to document this new failure mode, which will reduce false positives in
>   CI.
>
>   External URL:
>   https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html
>
>Participating hosts (41 -> 5)
>
>   ERROR: It appears as if the changes made in Patchwork_111512v4 prevented
>   too many machines from booting.
>
>   Missing (36): fi-kbl-soraka fi-rkl-11600 fi-rkl-guc bat-adls-5 bat-dg1-5
>   fi-bdw-gvtdvm fi-icl-u2 bat-adlp-6 fi-pnv-d510 bat-rpls-2 fi-skl-6600u
>   fi-snb-2600 fi-bsw-n3050 fi-adl-ddr5 bat-dg2-8 bat-adlm-1 bat-dg2-9
>   fi-hsw-4770 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-elk-e7500 bat-dg2-11
>   fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u bat-kbl-2 bat-adlp-9 fi-skl-guc
>   fi-glk-j4005 fi-ehl-2 fi-jsl-1 fi-cfl-guc bat-adlp-4 fi-kbl-8809g
>   fi-bsw-kefka

This looks like a false alarm. I loaded this on an ADLP and KBL and I 
don't see any issues.  This does not happen on rev2. Diff between rev2 
and rev3 is a change in commit message. rev4 is just a rerun.

I will post a rebased version to see if this resolves.

Regards,
Umesh

>
>Known issues