* [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
@ 2023-01-02 18:33 Imre Deak
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Imre Deak @ 2023-01-02 18:33 UTC (permalink / raw)
To: intel-gfx
Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
enabled.
This is required at least by the latest ADLP v2.18 firmware, which adds
a new handler enabled by default and running whenever the pipe is
enabled at the vertical referesh rate.
Bspec: 50344, 67620
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++
drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 ++++
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +++++++++
.../drm/i915/display/intel_modeset_setup.c | 4 +++-
5 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e75b9b2a0e015..ddbf22d5667a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
+ intel_dmc_enable_pipe(dev_priv, crtc->pipe);
+
if (!new_crtc_state->bigjoiner_pipes) {
intel_encoders_pre_pll_enable(state, crtc);
@@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
/*
* FIXME collapse everything to one hook.
@@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
}
+
+ intel_dmc_disable_pipe(i915, crtc->pipe);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 905b5dcdca14f..fe8a8941dbf3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define DMC_V3_MAX_MMIO_COUNT 20
#define DMC_V1_MMIO_START_RANGE 0x80000
+#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
+
struct intel_css_header {
/* 0x09 for DMC */
u32 module_type;
@@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
PIPEDMC_GATING_DIS, 0);
}
+void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+{
+ if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
+ return;
+
+ if (DISPLAY_VER(i915) >= 14)
+ intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
+ else
+ intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
+}
+
+void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+{
+ if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
+ return;
+
+ if (DISPLAY_VER(i915) >= 14)
+ intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
+ else
+ intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
+}
+
/**
* intel_dmc_load_program() - write the firmware from memory to register.
* @dev_priv: i915 drm device.
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 67e03315ef999..c65a5769879fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -13,6 +13,8 @@
struct drm_i915_error_state_buf;
struct drm_i915_private;
+enum pipe;
+
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
@@ -48,6 +50,8 @@ struct intel_dmc {
void intel_dmc_ucode_init(struct drm_i915_private *i915);
void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_disable_program(struct drm_i915_private *i915);
+void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
+void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 5e5e41644ddfd..aac4f5465c6a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -11,6 +11,17 @@
#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
+#define _PIPEDMC_CONTROL_A 0x45250
+#define _PIPEDMC_CONTROL_B 0x45254
+#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
+ _PIPEDMC_CONTROL_A, \
+ _PIPEDMC_CONTROL_B)
+#define PIPEDMC_ENABLE REG_BIT(0)
+
+#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
+#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
+
+
#define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
#define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 96395bfbd41df..52cdbd4fc2fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -698,8 +698,10 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
drm_crtc_vblank_reset(&crtc->base);
- if (crtc_state->hw.active)
+ if (crtc_state->hw.active) {
+ intel_dmc_enable_pipe(i915, crtc->pipe);
intel_crtc_vblank_on(crtc_state);
+ }
}
intel_fbc_sanitize(i915);
--
2.37.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
@ 2023-01-02 18:50 ` Patchwork
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-02 18:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL : https://patchwork.freedesktop.org/series/112355/
State : warning
== Summary ==
Error: dim checkpatch failed
af0cece2d473 drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
-:130: CHECK:LINE_SPACING: Please don't use multiple blank lines
#130: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:24:
+
+
total: 0 errors, 0 warnings, 1 checks, 103 lines checked
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-01-02 18:50 ` Patchwork
2023-01-02 19:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-02 18:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL : https://patchwork.freedesktop.org/series/112355/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-01-02 19:09 ` Patchwork
2023-01-02 20:18 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-03 16:01 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-02 19:09 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3734 bytes --]
== Series Details ==
Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL : https://patchwork.freedesktop.org/series/112355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12537 -> Patchwork_112355v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html
Participating hosts (44 -> 42)
------------------------------
Missing (2): fi-bsw-kefka fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112355v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-dg2-oem1}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-dg2-oem1/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-dg2-oem1/igt@i915_selftest@live@migrate.html
Known issues
------------
Here are the changes found in Patchwork_112355v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][3] -> [DMESG-FAIL][4] ([i915#7699])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-adlp-4/igt@i915_selftest@live@migrate.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-adlp-4/igt@i915_selftest@live@migrate.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}: [DMESG-WARN][5] ([i915#6687]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][7] ([i915#6367]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-rpls-1/igt@i915_selftest@live@slpc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7351]: https://gitlab.freedesktop.org/drm/intel/issues/7351
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
Build changes
-------------
* Linux: CI_DRM_12537 -> Patchwork_112355v1
CI-20190529: 20190529
CI_DRM_12537: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112355v1: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0b72b5f56045 drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html
[-- Attachment #2: Type: text/html, Size: 4026 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
` (2 preceding siblings ...)
2023-01-02 19:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-02 20:18 ` Patchwork
2023-01-03 16:01 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-01-02 20:18 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 23464 bytes --]
== Series Details ==
Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL : https://patchwork.freedesktop.org/series/112355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12537_full -> Patchwork_112355v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html
Participating hosts (14 -> 10)
------------------------------
Missing (4): shard-rkl0 pig-kbl-iris pig-glk-j5005 pig-skl-6260u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112355v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- {shard-dg1}: [PASS][3] -> [WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-19/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_plane@pixel-format@pipe-b-planes:
- {shard-rkl}: [PASS][5] -> [SKIP][6] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-6/igt@kms_plane@pixel-format@pipe-b-planes.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-1/igt@kms_plane@pixel-format@pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- {shard-rkl}: NOTRUN -> [SKIP][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb:
- {shard-tglu-9}: NOTRUN -> [SKIP][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-9/igt@kms_plane_alpha_blend@alpha-transparent-fb.html
Known issues
------------
Here are the changes found in Patchwork_112355v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2842]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][11] ([i915#2658])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@gem_pwrite@basic-exhaustion.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3886]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +71 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-hpd:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +6 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2346])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@sysfs_clients@sema-50:
- shard-glk: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2994]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@fbdev@unaligned-write:
- {shard-rkl}: [SKIP][19] ([i915#2582]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-1/igt@fbdev@unaligned-write.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@fbdev@unaligned-write.html
- {shard-tglu}: [SKIP][21] ([i915#2582]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-tglu-6/igt@fbdev@unaligned-write.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-7/igt@fbdev@unaligned-write.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][23] ([i915#6268]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@reset-stress:
- {shard-dg1}: [FAIL][25] ([i915#5784]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-14/igt@gem_eio@reset-stress.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-15/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}: [FAIL][27] ([i915#2842]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- {shard-rkl}: [SKIP][29] ([i915#3281]) -> [PASS][30] +9 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-rkl}: [SKIP][31] ([i915#1850]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-4/igt@gem_mmap_wc@set-cache-level.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_pwrite_snooped:
- {shard-rkl}: [SKIP][33] ([i915#3282]) -> [PASS][34] +4 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-3/igt@gem_pwrite_snooped.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@gem_pwrite_snooped.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][35] ([i915#5566] / [i915#716]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-glk4/igt@gen9_exec_parse@allowed-single.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-chained:
- {shard-rkl}: [SKIP][37] ([i915#2527]) -> [PASS][38] +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-3/igt@gen9_exec_parse@bb-chained.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- {shard-rkl}: [SKIP][39] ([i915#4098]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-5/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_dc@dc5-psr:
- {shard-rkl}: [SKIP][41] ([i915#658]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-4/igt@i915_pm_dc@dc5-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][43] ([i915#1397]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-16/igt@i915_pm_rpm@dpms-lpsp.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-14/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@pm-tiling:
- {shard-rkl}: [SKIP][45] ([fdo#109308]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-4/igt@i915_pm_rpm@pm-tiling.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html
* igt@i915_selftest@live@gt_pm:
- {shard-rkl}: [DMESG-FAIL][47] ([i915#4258]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-6/igt@i915_selftest@live@gt_pm.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-4/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][49] ([i915#1845] / [i915#4098]) -> [PASS][50] +24 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_fence_pin_leak:
- {shard-tglu}: [SKIP][51] ([fdo#109274] / [i915#1845]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-tglu-6/igt@kms_fence_pin_leak.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-7/igt@kms_fence_pin_leak.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a4:
- {shard-dg1}: [FAIL][53] ([i915#79]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-12/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a4.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-18/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a4.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: [SKIP][55] ([i915#1849] / [i915#4098]) -> [PASS][56] +13 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
- {shard-tglu}: [SKIP][57] ([i915#1849]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][59] ([i915#1072]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-5/igt@kms_psr@cursor_render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_rotation_crc@primary-rotation-180:
- {shard-tglu}: [SKIP][61] ([i915#7651]) -> [PASS][62] +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-tglu-6/igt@kms_rotation_crc@primary-rotation-180.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-7/igt@kms_rotation_crc@primary-rotation-180.html
* igt@perf@gen12-mi-rpc:
- {shard-rkl}: [SKIP][63] ([fdo#109289]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-5/igt@perf@gen12-mi-rpc.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-6/igt@perf@gen12-mi-rpc.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][65] ([i915#1722]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@perf@polling-small-buf.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-5/igt@perf@polling-small-buf.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}: [FAIL][67] ([i915#4349]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-14/igt@perf_pmu@idle@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-15/igt@perf_pmu@idle@rcs0.html
* igt@syncobj_wait@wait-delayed-signal:
- {shard-dg1}: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-14/igt@syncobj_wait@wait-delayed-signal.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-12/igt@syncobj_wait@wait-delayed-signal.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12537 -> Patchwork_112355v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12537: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112355v1: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html
[-- Attachment #2: Type: text/html, Size: 19363 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
` (3 preceding siblings ...)
2023-01-02 20:18 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-03 16:01 ` Rodrigo Vivi
2023-01-03 17:03 ` Imre Deak
2023-01-20 20:53 ` Gustavo Sousa
4 siblings, 2 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2023-01-03 16:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Jan 02, 2023 at 08:33:24PM +0200, Imre Deak wrote:
> Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
> enabled.
>
> This is required at least by the latest ADLP v2.18 firmware, which adds
> a new handler enabled by default and running whenever the pipe is
> enabled at the vertical referesh rate.
>
> Bspec: 50344, 67620
mlt hw looks a good register clean-up! why multiple registers for single bits! :)
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++
> drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h | 4 ++++
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +++++++++
> .../drm/i915/display/intel_modeset_setup.c | 4 +++-
> 5 files changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e75b9b2a0e015..ddbf22d5667a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> return;
>
> + intel_dmc_enable_pipe(dev_priv, crtc->pipe);
> +
> if (!new_crtc_state->bigjoiner_pipes) {
> intel_encoders_pre_pll_enable(state, crtc);
>
> @@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> {
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> /*
> * FIXME collapse everything to one hook.
> @@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> intel_encoders_disable(state, crtc);
> intel_encoders_post_disable(state, crtc);
> }
> +
> + intel_dmc_disable_pipe(i915, crtc->pipe);
> }
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 905b5dcdca14f..fe8a8941dbf3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
> #define DMC_V3_MAX_MMIO_COUNT 20
> #define DMC_V1_MMIO_START_RANGE 0x80000
>
> +#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
> +
> struct intel_css_header {
> /* 0x09 for DMC */
> u32 module_type;
> @@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> PIPEDMC_GATING_DIS, 0);
> }
>
> +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> +{
> + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> + return;
> +
> + if (DISPLAY_VER(i915) >= 14)
> + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> + else
> + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> +}
> +
> +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> +{
> + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> + return;
> +
> + if (DISPLAY_VER(i915) >= 14)
> + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> + else
> + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> +}
> +
> /**
> * intel_dmc_load_program() - write the firmware from memory to register.
> * @dev_priv: i915 drm device.
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 67e03315ef999..c65a5769879fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -13,6 +13,8 @@
> struct drm_i915_error_state_buf;
> struct drm_i915_private;
>
> +enum pipe;
> +
> enum {
> DMC_FW_MAIN = 0,
> DMC_FW_PIPEA,
> @@ -48,6 +50,8 @@ struct intel_dmc {
> void intel_dmc_ucode_init(struct drm_i915_private *i915);
> void intel_dmc_load_program(struct drm_i915_private *i915);
> void intel_dmc_disable_program(struct drm_i915_private *i915);
> +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 5e5e41644ddfd..aac4f5465c6a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -11,6 +11,17 @@
> #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
> #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
>
> +#define _PIPEDMC_CONTROL_A 0x45250
> +#define _PIPEDMC_CONTROL_B 0x45254
> +#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
> + _PIPEDMC_CONTROL_A, \
> + _PIPEDMC_CONTROL_B)
> +#define PIPEDMC_ENABLE REG_BIT(0)
> +
> +#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
> +#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
> +
> +
> #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
> #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
>
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 96395bfbd41df..52cdbd4fc2fa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -698,8 +698,10 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
>
> drm_crtc_vblank_reset(&crtc->base);
>
> - if (crtc_state->hw.active)
> + if (crtc_state->hw.active) {
> + intel_dmc_enable_pipe(i915, crtc->pipe);
> intel_crtc_vblank_on(crtc_state);
> + }
> }
>
> intel_fbc_sanitize(i915);
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-03 16:01 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
@ 2023-01-03 17:03 ` Imre Deak
2023-01-20 20:53 ` Gustavo Sousa
1 sibling, 0 replies; 9+ messages in thread
From: Imre Deak @ 2023-01-03 17:03 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jan 03, 2023 at 11:01:55AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 02, 2023 at 08:33:24PM +0200, Imre Deak wrote:
> > Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
> > enabled.
> >
> > This is required at least by the latest ADLP v2.18 firmware, which adds
> > a new handler enabled by default and running whenever the pipe is
> > enabled at the vertical referesh rate.
> >
> > Bspec: 50344, 67620
>
> mlt hw looks a good register clean-up! why multiple registers for single bits! :)
That change was probably due to power gating, where those registers were
backed by pipe power wells. On MTL this changed so the single register
doesn't depend on those power wells.
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks.
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 5 ++++
> > drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dmc.h | 4 ++++
> > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +++++++++
> > .../drm/i915/display/intel_modeset_setup.c | 4 +++-
> > 5 files changed, 47 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index e75b9b2a0e015..ddbf22d5667a6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > return;
> >
> > + intel_dmc_enable_pipe(dev_priv, crtc->pipe);
> > +
> > if (!new_crtc_state->bigjoiner_pipes) {
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > @@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > {
> > const struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >
> > /*
> > * FIXME collapse everything to one hook.
> > @@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > intel_encoders_disable(state, crtc);
> > intel_encoders_post_disable(state, crtc);
> > }
> > +
> > + intel_dmc_disable_pipe(i915, crtc->pipe);
> > }
> >
> > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 905b5dcdca14f..fe8a8941dbf3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
> > #define DMC_V3_MAX_MMIO_COUNT 20
> > #define DMC_V1_MMIO_START_RANGE 0x80000
> >
> > +#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
> > +
> > struct intel_css_header {
> > /* 0x09 for DMC */
> > u32 module_type;
> > @@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> > PIPEDMC_GATING_DIS, 0);
> > }
> >
> > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > +{
> > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) >= 14)
> > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> > + else
> > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> > +}
> > +
> > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > +{
> > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) >= 14)
> > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> > + else
> > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> > +}
> > +
> > /**
> > * intel_dmc_load_program() - write the firmware from memory to register.
> > * @dev_priv: i915 drm device.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> > index 67e03315ef999..c65a5769879fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > @@ -13,6 +13,8 @@
> > struct drm_i915_error_state_buf;
> > struct drm_i915_private;
> >
> > +enum pipe;
> > +
> > enum {
> > DMC_FW_MAIN = 0,
> > DMC_FW_PIPEA,
> > @@ -48,6 +50,8 @@ struct intel_dmc {
> > void intel_dmc_ucode_init(struct drm_i915_private *i915);
> > void intel_dmc_load_program(struct drm_i915_private *i915);
> > void intel_dmc_disable_program(struct drm_i915_private *i915);
> > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> > void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> > void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > index 5e5e41644ddfd..aac4f5465c6a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > @@ -11,6 +11,17 @@
> > #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
> > #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
> >
> > +#define _PIPEDMC_CONTROL_A 0x45250
> > +#define _PIPEDMC_CONTROL_B 0x45254
> > +#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
> > + _PIPEDMC_CONTROL_A, \
> > + _PIPEDMC_CONTROL_B)
> > +#define PIPEDMC_ENABLE REG_BIT(0)
> > +
> > +#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
> > +#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
> > +
> > +
> > #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
> > #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 96395bfbd41df..52cdbd4fc2fa0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -698,8 +698,10 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
> >
> > drm_crtc_vblank_reset(&crtc->base);
> >
> > - if (crtc_state->hw.active)
> > + if (crtc_state->hw.active) {
> > + intel_dmc_enable_pipe(i915, crtc->pipe);
> > intel_crtc_vblank_on(crtc_state);
> > + }
> > }
> >
> > intel_fbc_sanitize(i915);
> > --
> > 2.37.1
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-03 16:01 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2023-01-03 17:03 ` Imre Deak
@ 2023-01-20 20:53 ` Gustavo Sousa
2023-01-20 21:43 ` Imre Deak
1 sibling, 1 reply; 9+ messages in thread
From: Gustavo Sousa @ 2023-01-20 20:53 UTC (permalink / raw)
To: Rodrigo Vivi, Imre Deak; +Cc: intel-gfx
On Tue, Jan 03, 2023 at 11:01:55AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 02, 2023 at 08:33:24PM +0200, Imre Deak wrote:
> > Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
> > enabled.
> >
> > This is required at least by the latest ADLP v2.18 firmware, which adds
> > a new handler enabled by default and running whenever the pipe is
> > enabled at the vertical referesh rate.
> >
> > Bspec: 50344, 67620
>
> mlt hw looks a good register clean-up! why multiple registers for single bits! :)
>
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
I ran some tests with the fast-feedback IGT testlist and can confirm
that this patch fixes tests that, without it, would fail or timeout when
using ADLP DMC v2.18.
If the above justifies a Tested-by tag, then:
Tested-by: Gustavo Sousa <gustavo.sousa@intel.com>
We need this merged before using the new ADLP DMC realease (v2.18).
--
Gustavo Sousa
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 5 ++++
> > drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dmc.h | 4 ++++
> > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +++++++++
> > .../drm/i915/display/intel_modeset_setup.c | 4 +++-
> > 5 files changed, 47 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index e75b9b2a0e015..ddbf22d5667a6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > return;
> >
> > + intel_dmc_enable_pipe(dev_priv, crtc->pipe);
> > +
> > if (!new_crtc_state->bigjoiner_pipes) {
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > @@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > {
> > const struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> >
> > /*
> > * FIXME collapse everything to one hook.
> > @@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > intel_encoders_disable(state, crtc);
> > intel_encoders_post_disable(state, crtc);
> > }
> > +
> > + intel_dmc_disable_pipe(i915, crtc->pipe);
> > }
> >
> > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 905b5dcdca14f..fe8a8941dbf3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
> > #define DMC_V3_MAX_MMIO_COUNT 20
> > #define DMC_V1_MMIO_START_RANGE 0x80000
> >
> > +#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
> > +
> > struct intel_css_header {
> > /* 0x09 for DMC */
> > u32 module_type;
> > @@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> > PIPEDMC_GATING_DIS, 0);
> > }
> >
> > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > +{
> > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) >= 14)
> > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> > + else
> > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> > +}
> > +
> > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > +{
> > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) >= 14)
> > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> > + else
> > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> > +}
> > +
> > /**
> > * intel_dmc_load_program() - write the firmware from memory to register.
> > * @dev_priv: i915 drm device.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> > index 67e03315ef999..c65a5769879fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > @@ -13,6 +13,8 @@
> > struct drm_i915_error_state_buf;
> > struct drm_i915_private;
> >
> > +enum pipe;
> > +
> > enum {
> > DMC_FW_MAIN = 0,
> > DMC_FW_PIPEA,
> > @@ -48,6 +50,8 @@ struct intel_dmc {
> > void intel_dmc_ucode_init(struct drm_i915_private *i915);
> > void intel_dmc_load_program(struct drm_i915_private *i915);
> > void intel_dmc_disable_program(struct drm_i915_private *i915);
> > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> > void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> > void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > index 5e5e41644ddfd..aac4f5465c6a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > @@ -11,6 +11,17 @@
> > #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
> > #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
> >
> > +#define _PIPEDMC_CONTROL_A 0x45250
> > +#define _PIPEDMC_CONTROL_B 0x45254
> > +#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
> > + _PIPEDMC_CONTROL_A, \
> > + _PIPEDMC_CONTROL_B)
> > +#define PIPEDMC_ENABLE REG_BIT(0)
> > +
> > +#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
> > +#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
> > +
> > +
> > #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
> > #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 96395bfbd41df..52cdbd4fc2fa0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -698,8 +698,10 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
> >
> > drm_crtc_vblank_reset(&crtc->base);
> >
> > - if (crtc_state->hw.active)
> > + if (crtc_state->hw.active) {
> > + intel_dmc_enable_pipe(i915, crtc->pipe);
> > intel_crtc_vblank_on(crtc_state);
> > + }
> > }
> >
> > intel_fbc_sanitize(i915);
> > --
> > 2.37.1
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
2023-01-20 20:53 ` Gustavo Sousa
@ 2023-01-20 21:43 ` Imre Deak
0 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2023-01-20 21:43 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Jan 20, 2023 at 05:53:50PM -0300, Gustavo Sousa wrote:
> On Tue, Jan 03, 2023 at 11:01:55AM -0500, Rodrigo Vivi wrote:
> > On Mon, Jan 02, 2023 at 08:33:24PM +0200, Imre Deak wrote:
> > > Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
> > > enabled.
> > >
> > > This is required at least by the latest ADLP v2.18 firmware, which adds
> > > a new handler enabled by default and running whenever the pipe is
> > > enabled at the vertical referesh rate.
> > >
> > > Bspec: 50344, 67620
> >
> > mlt hw looks a good register clean-up! why multiple registers for single bits! :)
> >
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> I ran some tests with the fast-feedback IGT testlist and can confirm
> that this patch fixes tests that, without it, would fail or timeout when
> using ADLP DMC v2.18.
>
> If the above justifies a Tested-by tag, then:
>
> Tested-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
> We need this merged before using the new ADLP DMC realease (v2.18).
Ok, I pushed the patch to drm-intel-next, thanks for the testing and
review.
>
> --
> Gustavo Sousa
>
> >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 5 ++++
> > > drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_dmc.h | 4 ++++
> > > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +++++++++
> > > .../drm/i915/display/intel_modeset_setup.c | 4 +++-
> > > 5 files changed, 47 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e75b9b2a0e015..ddbf22d5667a6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > return;
> > >
> > > + intel_dmc_enable_pipe(dev_priv, crtc->pipe);
> > > +
> > > if (!new_crtc_state->bigjoiner_pipes) {
> > > intel_encoders_pre_pll_enable(state, crtc);
> > >
> > > @@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > > {
> > > const struct intel_crtc_state *old_crtc_state =
> > > intel_atomic_get_old_crtc_state(state, crtc);
> > > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > >
> > > /*
> > > * FIXME collapse everything to one hook.
> > > @@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> > > intel_encoders_disable(state, crtc);
> > > intel_encoders_post_disable(state, crtc);
> > > }
> > > +
> > > + intel_dmc_disable_pipe(i915, crtc->pipe);
> > > }
> > >
> > > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > index 905b5dcdca14f..fe8a8941dbf3a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > @@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
> > > #define DMC_V3_MAX_MMIO_COUNT 20
> > > #define DMC_V1_MMIO_START_RANGE 0x80000
> > >
> > > +#define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A))
> > > +
> > > struct intel_css_header {
> > > /* 0x09 for DMC */
> > > u32 module_type;
> > > @@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> > > PIPEDMC_GATING_DIS, 0);
> > > }
> > >
> > > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > > +{
> > > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > > + return;
> > > +
> > > + if (DISPLAY_VER(i915) >= 14)
> > > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
> > > + else
> > > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
> > > +}
> > > +
> > > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > > +{
> > > + if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
> > > + return;
> > > +
> > > + if (DISPLAY_VER(i915) >= 14)
> > > + intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
> > > + else
> > > + intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
> > > +}
> > > +
> > > /**
> > > * intel_dmc_load_program() - write the firmware from memory to register.
> > > * @dev_priv: i915 drm device.
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> > > index 67e03315ef999..c65a5769879fc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > > @@ -13,6 +13,8 @@
> > > struct drm_i915_error_state_buf;
> > > struct drm_i915_private;
> > >
> > > +enum pipe;
> > > +
> > > enum {
> > > DMC_FW_MAIN = 0,
> > > DMC_FW_PIPEA,
> > > @@ -48,6 +50,8 @@ struct intel_dmc {
> > > void intel_dmc_ucode_init(struct drm_i915_private *i915);
> > > void intel_dmc_load_program(struct drm_i915_private *i915);
> > > void intel_dmc_disable_program(struct drm_i915_private *i915);
> > > +void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > > +void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
> > > void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> > > void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> > > void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > index 5e5e41644ddfd..aac4f5465c6a2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > @@ -11,6 +11,17 @@
> > > #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
> > > #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
> > >
> > > +#define _PIPEDMC_CONTROL_A 0x45250
> > > +#define _PIPEDMC_CONTROL_B 0x45254
> > > +#define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \
> > > + _PIPEDMC_CONTROL_A, \
> > > + _PIPEDMC_CONTROL_B)
> > > +#define PIPEDMC_ENABLE REG_BIT(0)
> > > +
> > > +#define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
> > > +#define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
> > > +
> > > +
> > > #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
> > > #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > index 96395bfbd41df..52cdbd4fc2fa0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > > @@ -698,8 +698,10 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
> > >
> > > drm_crtc_vblank_reset(&crtc->base);
> > >
> > > - if (crtc_state->hw.active)
> > > + if (crtc_state->hw.active) {
> > > + intel_dmc_enable_pipe(i915, crtc->pipe);
> > > intel_crtc_vblank_on(crtc_state);
> > > + }
> > > }
> > >
> > > intel_fbc_sanitize(i915);
> > > --
> > > 2.37.1
> > >
^ permalink raw reply [flat|nested] 9+ messages in thread
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2023-01-02 18:33 [Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled Imre Deak
2023-01-02 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
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2023-01-03 16:01 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2023-01-03 17:03 ` Imre Deak
2023-01-20 20:53 ` Gustavo Sousa
2023-01-20 21:43 ` Imre Deak
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