* [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds
@ 2022-12-15 23:30 Matt Atwood
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Matt Atwood @ 2022-12-15 23:30 UTC (permalink / raw)
To: intel-gfx; +Cc: lucas.demarchi
From: Matt Roper <matthew.d.roper@intel.com>
This patch introduces initial gt workarounds for the MTL platform.
v2: drop redundant/stale comments specifying wa platforms affected
(Lucas). Drop Wa_22011802037 for MTL.
Bspec: 66622
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 11 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +++++++++++++-----
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/intel_device_info.c | 6 +
9 files changed, 128 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 99c4b866addd..e3f30bdf7e61 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
/*
- * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 49a8f10d76c7..c14476c777cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
- * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 41a237509dcf..4127830c33ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
- fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
- intel_uncore_read(gt->uncore, XEHP_FUSE4));
+ /* Wa_14016747170 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
+ intel_uncore_read(gt->uncore,
+ MTL_GT_ACTIVITY_FACTOR));
+ else
+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
+ intel_uncore_read(gt->uncore, XEHP_FUSE4));
/*
* Despite the register field being named "exclude mask" the
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8eb807b56f9..470d6feb456a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -414,6 +414,7 @@
#define TBIMR_FAST_CLIP REG_BIT(5)
#define VFLSKPD MCR_REG(0x62a8)
+#define VF_PREFETCH_TLB_DIS REG_BIT(5)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
@@ -1535,6 +1536,10 @@
#define MTL_MEDIA_MC6 _MMIO(0x138048)
+/* Wa_14016747170:mtl-p[a0], mtl-m[a0] */
+#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
+#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)
+
#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bf84efb3f15f..fc166e25f606 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -786,6 +786,32 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
}
+static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ /* Wa_14014947963:mtl */
+ wa_masked_field_set(wal, VF_PREEMPTION,
+ PREEMPTION_VERTEX_COUNT, 0x4000);
+
+ /* Wa_16013271637:mtl */
+ wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
+ MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
+
+ /* Wa_18019627453:mtl */
+ wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
+
+ /* Wa_18018764978:mtl */
+ wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+ }
+
+ /* Wa_18019271663:mtl */
+ wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
+}
+
static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
@@ -872,7 +898,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
- if (IS_PONTEVECCHIO(i915))
+ if (IS_METEORLAKE(i915))
+ mtl_ctx_workarounds_init(engine, wal);
+ else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
else if (IS_DG2(i915))
dg2_ctx_workarounds_init(engine, wal);
@@ -1628,7 +1656,10 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
static void
xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
- /* FIXME: Actual workarounds will be added in future patch(es) */
+ /* Wa_14014830051:mtl */
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
+ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
/*
* Unlike older platforms, we no longer setup implicit steering here;
@@ -2168,7 +2199,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, engine->gt, "whitelist", engine->name);
- if (IS_PONTEVECCHIO(i915))
+ if (IS_METEORLAKE(i915))
+ ; /* noop; none at this time */
+ else if (IS_PONTEVECCHIO(i915))
pvc_whitelist_build(engine);
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
@@ -2278,6 +2311,34 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ /* Wa_22014600077:mtl */
+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
+ ENABLE_EU_COUNT_FOR_TDL_FLUSH);
+ }
+
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2,mtl */
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
+
+ /* Wa_22013037850:dg2,mtl */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
+ DISABLE_128B_EVICTION_COMMAND_UDW);
+ }
+
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
+ IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+ /* Wa_22012856258:dg2,mtl */
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+ GEN12_DISABLE_READ_SUPPRESSION);
+ }
+
if (IS_DG2(i915)) {
/* Wa_1509235366:dg2 */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
@@ -2289,13 +2350,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
}
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
- IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
- /* Wa_1509727124:dg2 */
- wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
- SC_DISABLE_POWER_OPTIMIZATION_EBB);
- }
-
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
@@ -2327,14 +2381,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
- /* Wa_22013037850:dg2 */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
- DISABLE_128B_EVICTION_COMMAND_UDW);
-
- /* Wa_22012856258:dg2 */
- wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
- GEN12_DISABLE_READ_SUPPRESSION);
-
/*
* Wa_22010960976:dg2
* Wa_14013347512:dg2
@@ -2944,6 +2990,27 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
add_render_compute_tuning_settings(i915, wal);
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ IS_PONTEVECCHIO(i915) ||
+ IS_DG2(i915)) {
+ /* Wa_18018781329:dg2,pvc,mtl */
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+
+ /* Wa_22014226127:dg2,pvc,mtl */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+ }
+
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ IS_DG2(i915)) {
+ /* Wa_18017747507:dg2,mtl */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
+ }
+
if (IS_PONTEVECCHIO(i915)) {
/* Wa_16016694945 */
wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
@@ -2985,17 +3052,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
/* Wa_14015227452:dg2,pvc */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
- /* Wa_22014226127:dg2,pvc */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
-
/* Wa_16015675438:dg2,pvc */
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
-
- /* Wa_18018781329:dg2,pvc */
- wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2(i915)) {
@@ -3004,9 +3062,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
* Wa_22015475538:dg2
*/
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
-
- /* Wa_18017747507:dg2 */
- wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c0b5aa6fde26..aed2973e5f8d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -274,8 +274,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
flags |= GUC_WA_GAM_CREDITS;
- /* Wa_14014475959:dg2 */
- if (IS_DG2(gt->i915))
+ /* Wa_14014475959:dg2,mtl */
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+ IS_DG2(gt->i915))
flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
/*
@@ -289,7 +290,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
flags |= GUC_WA_DUAL_QUEUE;
/* Wa_22011802037: graphics version 11/12 */
- if (IS_GRAPHICS_VER(gt->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(gt->i915) >= 11 &&
+ GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 53f7f599cde3..f2d917132693 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1621,7 +1621,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
- * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+ * Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
intel_engine_wait_for_pending_mi_fw(engine);
@@ -4202,8 +4202,10 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_TIMESLICES;
/* Wa_14014475959:dg2 */
- if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS)
- engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+ if (engine->class == COMPUTE_CLASS)
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_DG2(engine->i915))
+ engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
/*
* TODO: GuC supports timeslicing and semaphores as well, but they're
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12..f742328c4d95 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -735,6 +735,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_METEORLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+ (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
+ IS_GRAPHICS_STEP(__i915, since, until))
+
/*
* DG2 hardware steppings are a bit unusual. The hardware design was forked to
* create three variants (G10, G11, and G12) which each have distinct
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 849baf6c3b3c..7add88dde79e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -343,6 +343,12 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
&runtime->graphics.ip);
+ /* Wa_22012778468:mtl */
+ if (runtime->graphics.ip.ver == 0x0 &&
+ INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
+ RUNTIME_INFO(i915)->graphics.ip.ver = 12;
+ RUNTIME_INFO(i915)->graphics.ip.rel = 70;
+ }
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
&runtime->display.ip);
ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
--
2.38.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add initial gt workarounds
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
@ 2022-12-15 23:46 ` Patchwork
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-12-15 23:46 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add initial gt workarounds
URL : https://patchwork.freedesktop.org/series/111994/
State : warning
== Summary ==
Error: dim checkpatch failed
782c85c8339a drm/i915/mtl: Add initial gt workarounds
-:351: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#351: FILE: drivers/gpu/drm/i915/i915_drv.h:738:
+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+ (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
+ IS_GRAPHICS_STEP(__i915, since, until))
total: 0 errors, 0 warnings, 1 checks, 302 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add initial gt workarounds
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-12-15 23:46 ` Patchwork
2022-12-16 0:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-12-15 23:46 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add initial gt workarounds
URL : https://patchwork.freedesktop.org/series/111994/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add initial gt workarounds
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-12-16 0:09 ` Patchwork
2022-12-16 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-04 0:18 ` [Intel-gfx] [PATCH v2] " Matt Roper
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-12-16 0:09 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3988 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add initial gt workarounds
URL : https://patchwork.freedesktop.org/series/111994/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12511 -> Patchwork_111994v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): bat-atsm-1
Known issues
------------
Here are the changes found in Patchwork_111994v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@workarounds:
- bat-adlp-4: [PASS][3] -> [INCOMPLETE][4] ([i915#4983])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/bat-adlp-4/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/bat-adlp-4/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/fi-pnv-d510/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}: [DMESG-WARN][6] ([i915#6687]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adln-1}: [INCOMPLETE][8] ([i915#4983] / [i915#7609]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [INCOMPLETE][10] ([i915#4983] / [i915#6257]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/bat-rpls-2/igt@i915_selftest@live@requests.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/bat-rpls-2/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
Build changes
-------------
* Linux: CI_DRM_12511 -> Patchwork_111994v1
CI-20190529: 20190529
CI_DRM_12511: 2f1afd3898412b8487d420921f34fb5340e15e5b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7095: 0d821bca4e1086c96bb8928a0d24e707396e9373 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111994v1: 2f1afd3898412b8487d420921f34fb5340e15e5b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
52546a64da53 drm/i915/mtl: Add initial gt workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/index.html
[-- Attachment #2: Type: text/html, Size: 4673 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Add initial gt workarounds
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
` (2 preceding siblings ...)
2022-12-16 0:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-12-16 15:36 ` Patchwork
2023-01-04 0:18 ` [Intel-gfx] [PATCH v2] " Matt Roper
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-12-16 15:36 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 45615 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add initial gt workarounds
URL : https://patchwork.freedesktop.org/series/111994/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12511_full -> Patchwork_111994v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 13)
------------------------------
Missing (1): shard-tglu-9
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_111994v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_hwmon@hwmon-read}:
- {shard-tglu}: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglu-1/igt@i915_hwmon@hwmon-read.html
Known issues
------------
Here are the changes found in Patchwork_111994v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#4386]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl6/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl2/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl2/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl3/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl8/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl8/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl8/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl8/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-apl2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl8/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl8/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl8/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl8/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl2/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl2/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109314])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][53] ([i915#2842])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-sync@rcs0:
- shard-tglb: [PASS][58] -> [SKIP][59] ([i915#2848])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-tglb6/igt@gem_exec_fair@basic-sync@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb6/igt@gem_exec_fair@basic-sync@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2190])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@smem-oom:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#4613])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][63] ([i915#2658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@gem_pwrite@basic-exhaustion.html
- shard-iclb: NOTRUN -> [WARN][64] ([i915#2658])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#768])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@access-control:
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#3297]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#3297])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen7_exec_parse@chained-batch:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109289])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@bb-start-out:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#2856])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@secure-batches:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#2527] / [i915#2856])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#5286]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#110723])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3689])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#6095])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109278] / [i915#3886]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109278]) +7 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109284] / [fdo#111827])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109284] / [fdo#111827]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_color_chamelium@ctm-limited-range.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109279] / [i915#3359])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#3555]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271]) +60 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#3555])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#1769] / [i915#3555])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_fbcon_fbt@fbc:
- shard-glk: NOTRUN -> [FAIL][89] ([i915#4767])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@kms_fbcon_fbt@fbc.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109274]) +4 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#2672]) +5 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#2587] / [i915#2672]) +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][93] ([i915#2672] / [i915#3555]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109280] / [fdo#111825])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109280]) +6 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +43 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#5438])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2:
- shard-glk: NOTRUN -> [FAIL][98] ([i915#4573]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2.html
* igt@kms_plane_alpha_blend@constant-alpha-max@pipe-b-dp-1:
- shard-apl: NOTRUN -> [FAIL][99] ([i915#4573]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-apl3/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-b-dp-1.html
* igt@kms_plane_lowres@tiling-4:
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#5288])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_plane_lowres@tiling-4.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-edp-1:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#5176]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [PASS][102] -> [SKIP][103] ([i915#5235]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#2920])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109642] / [fdo#111068] / [i915#658])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][106] -> [SKIP][107] ([fdo#109441]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [PASS][108] -> [SKIP][109] ([i915#5519])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-tglb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#111615] / [i915#5289])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2437])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@kms_writeback@writeback-fb-id.html
* igt@sysfs_clients@fair-7:
- shard-glk: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk1/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-25:
- shard-tglb: NOTRUN -> [SKIP][113] ([i915#2994])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-25:
- shard-iclb: NOTRUN -> [SKIP][114] ([i915#2994])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@sysfs_clients@split-25.html
* igt@v3d/v3d_mmap@mmap-bad-handle:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109315])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@v3d/v3d_mmap@mmap-bad-handle.html
#### Possible fixes ####
* igt@api_intel_allocator@alloc-simple:
- {shard-rkl}: [SKIP][116] ([fdo#109315]) -> [PASS][117] +11 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@api_intel_allocator@alloc-simple.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@api_intel_allocator@alloc-simple.html
* igt@core_setmaster@master-drop-set-shared-fd:
- {shard-rkl}: [SKIP][118] -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@core_setmaster@master-drop-set-shared-fd.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@core_setmaster@master-drop-set-shared-fd.html
* igt@device_reset@unbind-reset-rebind:
- {shard-rkl}: [FAIL][120] ([i915#4778]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@device_reset@unbind-reset-rebind.html
* igt@drm_read@empty-block:
- {shard-rkl}: [SKIP][122] ([i915#4098]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-3/igt@drm_read@empty-block.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@drm_read@empty-block.html
* igt@fbdev@unaligned-write:
- {shard-rkl}: [SKIP][124] ([i915#2582]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-4/igt@fbdev@unaligned-write.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@fbdev@unaligned-write.html
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][126] ([i915#658]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb7/igt@feature_discovery@psr2.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@feature_discovery@psr2.html
- {shard-rkl}: [SKIP][128] ([i915#658]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-4/igt@feature_discovery@psr2.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][130] ([i915#4525]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb7/igt@gem_exec_balancer@parallel-balancer.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [FAIL][132] ([i915#2842]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-glk4/igt@gem_exec_fair@basic-pace@vcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk8/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: [FAIL][134] ([i915#2842]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-tglb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-gtt:
- {shard-rkl}: [SKIP][136] ([i915#3281]) -> [PASS][137] +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-1/igt@gem_exec_reloc@basic-gtt.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_schedule@semaphore-power:
- {shard-rkl}: [SKIP][138] ([i915#7276]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-3/igt@gem_exec_schedule@semaphore-power.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-rkl}: [SKIP][140] ([i915#1850]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-4/igt@gem_mmap_wc@set-cache-level.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_pread@uncached:
- {shard-rkl}: [SKIP][142] ([i915#3282]) -> [PASS][143] +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-1/igt@gem_pread@uncached.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-5/igt@gem_pread@uncached.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][144] ([i915#5566] / [i915#716]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-glk6/igt@gen9_exec_parse@allowed-single.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][146] ([i915#3361]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][148] ([i915#3989] / [i915#454]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][150] ([i915#1397]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-dg1-16/igt@i915_pm_rpm@dpms-lpsp.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-dg1-14/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][152] ([i915#1397]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@system-suspend-devices:
- {shard-rkl}: [SKIP][154] ([i915#5174]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@i915_pm_rpm@system-suspend-devices.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@i915_pm_rpm@system-suspend-devices.html
* igt@kms_atomic@plane-immutable-zpos:
- {shard-rkl}: [SKIP][156] ([i915#1845] / [i915#4098]) -> [PASS][157] +26 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-3/igt@kms_atomic@plane-immutable-zpos.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@kms_atomic@plane-immutable-zpos.html
* igt@kms_cursor_edge_walk@right-edge@pipe-b-edp-1-128x128:
- shard-tglb: [INCOMPLETE][158] -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-tglb6/igt@kms_cursor_edge_walk@right-edge@pipe-b-edp-1-128x128.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-tglb2/igt@kms_cursor_edge_walk@right-edge@pipe-b-edp-1-128x128.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][160] ([i915#2346]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: [SKIP][162] ([i915#1849] / [i915#4098]) -> [PASS][163] +17 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [SKIP][164] ([i915#5176]) -> [PASS][165] +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][166] ([i915#5235]) -> [PASS][167] +2 similar issues
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@primary_mmap_gtt:
- {shard-rkl}: [SKIP][168] ([i915#1072]) -> [PASS][169] +1 similar issue
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-3/igt@kms_psr@primary_mmap_gtt.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-6/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][170] ([fdo#109441]) -> [PASS][171] +3 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [SKIP][172] ([i915#5519]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf_pmu@gt-awake:
- {shard-rkl}: [SKIP][174] ([i915#5608]) -> [PASS][175] +2 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@perf_pmu@gt-awake.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@perf_pmu@gt-awake.html
* igt@syncobj_wait@wait-delayed-signal:
- {shard-rkl}: [SKIP][176] ([i915#2575]) -> [PASS][177] +10 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-rkl-5/igt@syncobj_wait@wait-delayed-signal.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-rkl-2/igt@syncobj_wait@wait-delayed-signal.html
#### Warnings ####
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][178] ([i915#658]) -> [SKIP][179] ([i915#2920])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][180] ([i915#2920]) -> [SKIP][181] ([fdo#111068] / [i915#658]) +1 similar issue
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][182] ([i915#2920]) -> [SKIP][183] ([i915#658])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12511/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5438]: https://gitlab.freedesktop.org/drm/intel/issues/5438
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6914]: https://gitlab.freedesktop.org/drm/intel/issues/6914
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7663]: https://gitlab.freedesktop.org/drm/intel/issues/7663
[i915#7678]: https://gitlab.freedesktop.org/drm/intel/issues/7678
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#7688]: https://gitlab.freedesktop.org/drm/intel/issues/7688
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
Build changes
-------------
* Linux: CI_DRM_12511 -> Patchwork_111994v1
CI-20190529: 20190529
CI_DRM_12511: 2f1afd3898412b8487d420921f34fb5340e15e5b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7095: 0d821bca4e1086c96bb8928a0d24e707396e9373 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111994v1: 2f1afd3898412b8487d420921f34fb5340e15e5b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111994v1/index.html
[-- Attachment #2: Type: text/html, Size: 46593 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
` (3 preceding siblings ...)
2022-12-16 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-04 0:18 ` Matt Roper
2023-01-05 23:39 ` Matt Atwood
4 siblings, 1 reply; 7+ messages in thread
From: Matt Roper @ 2023-01-04 0:18 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx, lucas.demarchi
On Thu, Dec 15, 2022 at 03:30:55PM -0800, Matt Atwood wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> This patch introduces initial gt workarounds for the MTL platform.
>
> v2: drop redundant/stale comments specifying wa platforms affected
This is being discussed on the other thread, but it also doesn't look
like this actually happened completely in v2 here. You removed a few
but most of the workarounds still have them?
> (Lucas). Drop Wa_22011802037 for MTL.
This statement doesn't seem right...Wa_22011802037 is still (correctly)
present for the affected variant/steppings of MTL.
Matt
>
> Bspec: 66622
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
> .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 11 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +++++++++++++-----
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/intel_device_info.c | 6 +
> 9 files changed, 128 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 99c4b866addd..e3f30bdf7e61 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
>
> /*
> - * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> + * Wa_22011802037 : Prior to doing a reset, ensure CS is
> * stopped, set ring stop bit and prefetch disable bit to halt CS
> */
> - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + (GRAPHICS_VER(engine->i915) >= 11 &&
> + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 49a8f10d76c7..c14476c777cc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> intel_engine_stop_cs(engine);
>
> /*
> - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * Wa_22011802037: In addition to stopping the cs, we need
> * to wait for any pending mi force wakeups
> */
> - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + (GRAPHICS_VER(engine->i915) >= 11 &&
> + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> intel_engine_wait_for_pending_mi_fw(engine);
>
> engine->execlists.reset_ccid = active_ccid(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 41a237509dcf..4127830c33ca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> - fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> - intel_uncore_read(gt->uncore, XEHP_FUSE4));
> + /* Wa_14016747170 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> + intel_uncore_read(gt->uncore,
> + MTL_GT_ACTIVITY_FACTOR));
> + else
> + fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> + intel_uncore_read(gt->uncore, XEHP_FUSE4));
>
> /*
> * Despite the register field being named "exclude mask" the
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f8eb807b56f9..470d6feb456a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -414,6 +414,7 @@
> #define TBIMR_FAST_CLIP REG_BIT(5)
>
> #define VFLSKPD MCR_REG(0x62a8)
> +#define VF_PREFETCH_TLB_DIS REG_BIT(5)
> #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
>
> @@ -1535,6 +1536,10 @@
>
> #define MTL_MEDIA_MC6 _MMIO(0x138048)
>
> +/* Wa_14016747170:mtl-p[a0], mtl-m[a0] */
> +#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
> +#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)
> +
> #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index bf84efb3f15f..fc166e25f606 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -786,6 +786,32 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> }
>
> +static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> + struct drm_i915_private *i915 = engine->i915;
> +
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + /* Wa_14014947963:mtl */
> + wa_masked_field_set(wal, VF_PREEMPTION,
> + PREEMPTION_VERTEX_COUNT, 0x4000);
> +
> + /* Wa_16013271637:mtl */
> + wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> + MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> +
> + /* Wa_18019627453:mtl */
> + wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
> +
> + /* Wa_18018764978:mtl */
> + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> + }
> +
> + /* Wa_18019271663:mtl */
> + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> +}
> +
> static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> @@ -872,7 +898,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> if (engine->class != RENDER_CLASS)
> goto done;
>
> - if (IS_PONTEVECCHIO(i915))
> + if (IS_METEORLAKE(i915))
> + mtl_ctx_workarounds_init(engine, wal);
> + else if (IS_PONTEVECCHIO(i915))
> ; /* noop; none at this time */
> else if (IS_DG2(i915))
> dg2_ctx_workarounds_init(engine, wal);
> @@ -1628,7 +1656,10 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> static void
> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - /* FIXME: Actual workarounds will be added in future patch(es) */
> + /* Wa_14014830051:mtl */
> + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
> + wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>
> /*
> * Unlike older platforms, we no longer setup implicit steering here;
> @@ -2168,7 +2199,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> wa_init_start(w, engine->gt, "whitelist", engine->name);
>
> - if (IS_PONTEVECCHIO(i915))
> + if (IS_METEORLAKE(i915))
> + ; /* noop; none at this time */
> + else if (IS_PONTEVECCHIO(i915))
> pvc_whitelist_build(engine);
> else if (IS_DG2(i915))
> dg2_whitelist_build(engine);
> @@ -2278,6 +2311,34 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + /* Wa_22014600077:mtl */
> + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> + ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> + }
> +
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> + /* Wa_1509727124:dg2,mtl */
> + wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> + SC_DISABLE_POWER_OPTIMIZATION_EBB);
> +
> + /* Wa_22013037850:dg2,mtl */
> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> + DISABLE_128B_EVICTION_COMMAND_UDW);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> + IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> + /* Wa_22012856258:dg2,mtl */
> + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> + GEN12_DISABLE_READ_SUPPRESSION);
> + }
> +
> if (IS_DG2(i915)) {
> /* Wa_1509235366:dg2 */
> wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
> @@ -2289,13 +2350,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> }
>
> - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> - IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> - /* Wa_1509727124:dg2 */
> - wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> - SC_DISABLE_POWER_OPTIMIZATION_EBB);
> - }
> -
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14012419201:dg2 */
> @@ -2327,14 +2381,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> - /* Wa_22013037850:dg2 */
> - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> - DISABLE_128B_EVICTION_COMMAND_UDW);
> -
> - /* Wa_22012856258:dg2 */
> - wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> - GEN12_DISABLE_READ_SUPPRESSION);
> -
> /*
> * Wa_22010960976:dg2
> * Wa_14013347512:dg2
> @@ -2944,6 +2990,27 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + IS_PONTEVECCHIO(i915) ||
> + IS_DG2(i915)) {
> + /* Wa_18018781329:dg2,pvc,mtl */
> + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> +
> + /* Wa_22014226127:dg2,pvc,mtl */
> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> + }
> +
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + IS_DG2(i915)) {
> + /* Wa_18017747507:dg2,mtl */
> + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> + }
> +
> if (IS_PONTEVECCHIO(i915)) {
> /* Wa_16016694945 */
> wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> @@ -2985,17 +3052,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> /* Wa_14015227452:dg2,pvc */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
>
> - /* Wa_22014226127:dg2,pvc */
> - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> -
> /* Wa_16015675438:dg2,pvc */
> wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
> -
> - /* Wa_18018781329:dg2,pvc */
> - wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> }
>
> if (IS_DG2(i915)) {
> @@ -3004,9 +3062,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> * Wa_22015475538:dg2
> */
> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> -
> - /* Wa_18017747507:dg2 */
> - wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index c0b5aa6fde26..aed2973e5f8d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -274,8 +274,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
> flags |= GUC_WA_GAM_CREDITS;
>
> - /* Wa_14014475959:dg2 */
> - if (IS_DG2(gt->i915))
> + /* Wa_14014475959:dg2,mtl */
> + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> + IS_DG2(gt->i915))
> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>
> /*
> @@ -289,7 +290,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> flags |= GUC_WA_DUAL_QUEUE;
>
> /* Wa_22011802037: graphics version 11/12 */
> - if (IS_GRAPHICS_VER(gt->i915, 11, 12))
> + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> + (GRAPHICS_VER(gt->i915) >= 11 &&
> + GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> flags |= GUC_WA_PRE_PARSER;
>
> /* Wa_16011777198:dg2 */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 53f7f599cde3..f2d917132693 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1621,7 +1621,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> intel_engine_stop_cs(engine);
>
> /*
> - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * Wa_22011802037: In addition to stopping the cs, we need
> * to wait for any pending mi force wakeups
> */
> intel_engine_wait_for_pending_mi_fw(engine);
> @@ -4202,8 +4202,10 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> engine->flags |= I915_ENGINE_HAS_TIMESLICES;
>
> /* Wa_14014475959:dg2 */
> - if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS)
> - engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> + if (engine->class == COMPUTE_CLASS)
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + IS_DG2(engine->i915))
> + engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>
> /*
> * TODO: GuC supports timeslicing and semaphores as well, but they're
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48fd82722f12..f742328c4d95 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -735,6 +735,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_METEORLAKE(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
>
> +#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> + (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> + IS_GRAPHICS_STEP(__i915, since, until))
> +
> /*
> * DG2 hardware steppings are a bit unusual. The hardware design was forked to
> * create three variants (G10, G11, and G12) which each have distinct
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 849baf6c3b3c..7add88dde79e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -343,6 +343,12 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
>
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
> &runtime->graphics.ip);
> + /* Wa_22012778468:mtl */
> + if (runtime->graphics.ip.ver == 0x0 &&
> + INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
> + RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> + RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> + }
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> &runtime->display.ip);
> ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> --
> 2.38.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds
2023-01-04 0:18 ` [Intel-gfx] [PATCH v2] " Matt Roper
@ 2023-01-05 23:39 ` Matt Atwood
0 siblings, 0 replies; 7+ messages in thread
From: Matt Atwood @ 2023-01-05 23:39 UTC (permalink / raw)
To: Matt Roper, intel-gfx, lucas.demarchi; +Cc: intel-gfx, lucas.demarchi
On Tue, Jan 03, 2023 at 04:18:27PM -0800, Matt Roper wrote:
> On Thu, Dec 15, 2022 at 03:30:55PM -0800, Matt Atwood wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> >
> > This patch introduces initial gt workarounds for the MTL platform.
> >
> > v2: drop redundant/stale comments specifying wa platforms affected
>
> This is being discussed on the other thread, but it also doesn't look
> like this actually happened completely in v2 here. You removed a few
> but most of the workarounds still have them?
Ack.
>
> > (Lucas). Drop Wa_22011802037 for MTL.
>
> This statement doesn't seem right...Wa_22011802037 is still (correctly)
> present for the affected variant/steppings of MTL.
You're right.
>
>
> Matt
>
> >
> > Bspec: 66622
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 11 +-
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +++++++++++++-----
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
> > drivers/gpu/drm/i915/i915_drv.h | 4 +
> > drivers/gpu/drm/i915/intel_device_info.c | 6 +
> > 9 files changed, 128 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 99c4b866addd..e3f30bdf7e61 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> > intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
> >
> > /*
> > - * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> > + * Wa_22011802037 : Prior to doing a reset, ensure CS is
> > * stopped, set ring stop bit and prefetch disable bit to halt CS
> > */
> > - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> > intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> > _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 49a8f10d76c7..c14476c777cc 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> > intel_engine_stop_cs(engine);
> >
> > /*
> > - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> > + * Wa_22011802037: In addition to stopping the cs, we need
> > * to wait for any pending mi force wakeups
> > */
> > - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> > intel_engine_wait_for_pending_mi_fw(engine);
> >
> > engine->execlists.reset_ccid = active_ccid(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 41a237509dcf..4127830c33ca 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> > if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
> > gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > - fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> > - intel_uncore_read(gt->uncore, XEHP_FUSE4));
> > + /* Wa_14016747170 */
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> > + intel_uncore_read(gt->uncore,
> > + MTL_GT_ACTIVITY_FACTOR));
> > + else
> > + fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> > + intel_uncore_read(gt->uncore, XEHP_FUSE4));
> >
> > /*
> > * Despite the register field being named "exclude mask" the
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index f8eb807b56f9..470d6feb456a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -414,6 +414,7 @@
> > #define TBIMR_FAST_CLIP REG_BIT(5)
> >
> > #define VFLSKPD MCR_REG(0x62a8)
> > +#define VF_PREFETCH_TLB_DIS REG_BIT(5)
> > #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> > #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
> >
> > @@ -1535,6 +1536,10 @@
> >
> > #define MTL_MEDIA_MC6 _MMIO(0x138048)
> >
> > +/* Wa_14016747170:mtl-p[a0], mtl-m[a0] */
> > +#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
> > +#define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3)
> > +
> > #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> > #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index bf84efb3f15f..fc166e25f606 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -786,6 +786,32 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> > }
> >
> > +static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > + struct i915_wa_list *wal)
> > +{
> > + struct drm_i915_private *i915 = engine->i915;
> > +
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > + /* Wa_14014947963:mtl */
> > + wa_masked_field_set(wal, VF_PREEMPTION,
> > + PREEMPTION_VERTEX_COUNT, 0x4000);
> > +
> > + /* Wa_16013271637:mtl */
> > + wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> > + MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> > +
> > + /* Wa_18019627453:mtl */
> > + wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
> > +
> > + /* Wa_18018764978:mtl */
> > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> > + }
> > +
> > + /* Wa_18019271663:mtl */
> > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> > +}
> > +
> > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > @@ -872,7 +898,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > if (engine->class != RENDER_CLASS)
> > goto done;
> >
> > - if (IS_PONTEVECCHIO(i915))
> > + if (IS_METEORLAKE(i915))
> > + mtl_ctx_workarounds_init(engine, wal);
> > + else if (IS_PONTEVECCHIO(i915))
> > ; /* noop; none at this time */
> > else if (IS_DG2(i915))
> > dg2_ctx_workarounds_init(engine, wal);
> > @@ -1628,7 +1656,10 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > static void
> > xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > - /* FIXME: Actual workarounds will be added in future patch(es) */
> > + /* Wa_14014830051:mtl */
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0))
> > + wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> >
> > /*
> > * Unlike older platforms, we no longer setup implicit steering here;
> > @@ -2168,7 +2199,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> >
> > wa_init_start(w, engine->gt, "whitelist", engine->name);
> >
> > - if (IS_PONTEVECCHIO(i915))
> > + if (IS_METEORLAKE(i915))
> > + ; /* noop; none at this time */
> > + else if (IS_PONTEVECCHIO(i915))
> > pvc_whitelist_build(engine);
> > else if (IS_DG2(i915))
> > dg2_whitelist_build(engine);
> > @@ -2278,6 +2311,34 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > + /* Wa_22014600077:mtl */
> > + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > + ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> > + }
> > +
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > + /* Wa_1509727124:dg2,mtl */
> > + wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > + SC_DISABLE_POWER_OPTIMIZATION_EBB);
> > +
> > + /* Wa_22013037850:dg2,mtl */
> > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> > + DISABLE_128B_EVICTION_COMMAND_UDW);
> > + }
> > +
> > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > + IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > + IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > + /* Wa_22012856258:dg2,mtl */
> > + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > + GEN12_DISABLE_READ_SUPPRESSION);
> > + }
> > +
> > if (IS_DG2(i915)) {
> > /* Wa_1509235366:dg2 */
> > wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
> > @@ -2289,13 +2350,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> > }
> >
> > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > - IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > - /* Wa_1509727124:dg2 */
> > - wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > - SC_DISABLE_POWER_OPTIMIZATION_EBB);
> > - }
> > -
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
> > IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> > /* Wa_14012419201:dg2 */
> > @@ -2327,14 +2381,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > - /* Wa_22013037850:dg2 */
> > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> > - DISABLE_128B_EVICTION_COMMAND_UDW);
> > -
> > - /* Wa_22012856258:dg2 */
> > - wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > - GEN12_DISABLE_READ_SUPPRESSION);
> > -
> > /*
> > * Wa_22010960976:dg2
> > * Wa_14013347512:dg2
> > @@ -2944,6 +2990,27 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >
> > add_render_compute_tuning_settings(i915, wal);
> >
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + IS_PONTEVECCHIO(i915) ||
> > + IS_DG2(i915)) {
> > + /* Wa_18018781329:dg2,pvc,mtl */
> > + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> > + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> > + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> > + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> > +
> > + /* Wa_22014226127:dg2,pvc,mtl */
> > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> > + }
> > +
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + IS_DG2(i915)) {
> > + /* Wa_18017747507:dg2,mtl */
> > + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > + }
> > +
> > if (IS_PONTEVECCHIO(i915)) {
> > /* Wa_16016694945 */
> > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> > @@ -2985,17 +3052,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > /* Wa_14015227452:dg2,pvc */
> > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
> >
> > - /* Wa_22014226127:dg2,pvc */
> > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> > -
> > /* Wa_16015675438:dg2,pvc */
> > wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
> > -
> > - /* Wa_18018781329:dg2,pvc */
> > - wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> > - wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> > - wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> > - wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> > }
> >
> > if (IS_DG2(i915)) {
> > @@ -3004,9 +3062,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > * Wa_22015475538:dg2
> > */
> > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> > -
> > - /* Wa_18017747507:dg2 */
> > - wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > }
> >
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index c0b5aa6fde26..aed2973e5f8d 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -274,8 +274,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
> > flags |= GUC_WA_GAM_CREDITS;
> >
> > - /* Wa_14014475959:dg2 */
> > - if (IS_DG2(gt->i915))
> > + /* Wa_14014475959:dg2,mtl */
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > + IS_DG2(gt->i915))
> > flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> >
> > /*
> > @@ -289,7 +290,9 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > flags |= GUC_WA_DUAL_QUEUE;
> >
> > /* Wa_22011802037: graphics version 11/12 */
> > - if (IS_GRAPHICS_VER(gt->i915, 11, 12))
> > + if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(gt->i915) >= 11 &&
> > + GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
> > flags |= GUC_WA_PRE_PARSER;
> >
> > /* Wa_16011777198:dg2 */
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 53f7f599cde3..f2d917132693 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1621,7 +1621,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> > intel_engine_stop_cs(engine);
> >
> > /*
> > - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> > + * Wa_22011802037: In addition to stopping the cs, we need
> > * to wait for any pending mi force wakeups
> > */
> > intel_engine_wait_for_pending_mi_fw(engine);
> > @@ -4202,8 +4202,10 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > engine->flags |= I915_ENGINE_HAS_TIMESLICES;
> >
> > /* Wa_14014475959:dg2 */
> > - if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS)
> > - engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > + if (engine->class == COMPUTE_CLASS)
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + IS_DG2(engine->i915))
> > + engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> >
> > /*
> > * TODO: GuC supports timeslicing and semaphores as well, but they're
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 48fd82722f12..f742328c4d95 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -735,6 +735,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > (IS_METEORLAKE(__i915) && \
> > IS_DISPLAY_STEP(__i915, since, until))
> >
> > +#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > + (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> > + IS_GRAPHICS_STEP(__i915, since, until))
> > +
> > /*
> > * DG2 hardware steppings are a bit unusual. The hardware design was forked to
> > * create three variants (G10, G11, and G12) which each have distinct
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 849baf6c3b3c..7add88dde79e 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -343,6 +343,12 @@ static void intel_ipver_early_init(struct drm_i915_private *i915)
> >
> > ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
> > &runtime->graphics.ip);
> > + /* Wa_22012778468:mtl */
> > + if (runtime->graphics.ip.ver == 0x0 &&
> > + INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
> > + RUNTIME_INFO(i915)->graphics.ip.ver = 12;
> > + RUNTIME_INFO(i915)->graphics.ip.rel = 70;
> > + }
> > ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
> > &runtime->display.ip);
> > ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
> > --
> > 2.38.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-01-05 23:39 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-12-15 23:30 [Intel-gfx] [PATCH v2] drm/i915/mtl: Add initial gt workarounds Matt Atwood
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-12-15 23:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-12-16 0:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-16 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-04 0:18 ` [Intel-gfx] [PATCH v2] " Matt Roper
2023-01-05 23:39 ` Matt Atwood
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox