From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Implement UHBR bandwidth check
Date: Fri, 13 Jan 2023 16:43:54 +0200 [thread overview]
Message-ID: <Y8FuKtLJuio28wwb@intel.com> (raw)
In-Reply-To: <20230113130628.19772-1-stanislav.lisovskiy@intel.com>
On Fri, Jan 13, 2023 at 03:06:28PM +0200, Stanislav Lisovskiy wrote:
> According to spec, we should check if output_bpp * pixel_rate is less
> than DDI clock * 72, if UHBR is used.
>
> HSDES: 1406899791
> BSPEC: 49259
>
> v2: - Removed wrong comment(Rodrigo Vivi)
> - Added HSDES to the commit msg(Rodrigo Vivi)
> - Moved UHBR check to the MST specific code
>
> v3: - Changed commit subject(Rodrigo Vivi)
> - Fixed the error message if check fails(Rodrigo Vivi)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8b0e4defa3f1..36e368995bef 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -339,10 +339,20 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
> conn_state, &limits,
> pipe_config->dp_m_n.tu, false);
> - }
> + if (ret < 0)
> + return ret;
>
> - if (ret)
> - return ret;
> + if (intel_dp_is_uhbr(pipe_config)) {
> + int output_bpp = pipe_config->dsc.compressed_bpp;
> +
> + if (output_bpp * adjusted_mode->crtc_clock >=
> + pipe_config->port_clock * 72) {
> + drm_dbg_kms(&dev_priv->drm, "UHBR check failed(required bw %d available %d)\n",
> + output_bpp * adjusted_mode->crtc_clock, pipe_config->port_clock * 72);
> + return -EINVAL;
Doesn't this just mean the user can never enable this particular
mode? Would seem more sensible to account for the extra
limitation when we determine port_clock and/or compressed_bpp.
> + }
> + }
> + }
>
> ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
> if (ret)
> --
> 2.37.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-01-13 14:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 13:06 [Intel-gfx] [PATCH] drm/i915: Implement UHBR bandwidth check Stanislav Lisovskiy
2023-01-13 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-01-13 14:43 ` Ville Syrjälä [this message]
2023-01-16 7:51 ` [Intel-gfx] [PATCH] " Lisovskiy, Stanislav
2023-01-13 22:43 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-02-27 11:20 [Intel-gfx] [PATCH] " Stanislav Lisovskiy
2023-03-09 12:54 ` Ville Syrjälä
2023-03-24 13:51 Stanislav Lisovskiy
2023-04-04 10:56 ` Govindapillai, Vinod
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