* [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
@ 2023-01-13 1:19 Gustavo Sousa
2023-01-13 3:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Gustavo Sousa @ 2023-01-13 1:19 UTC (permalink / raw)
To: intel-gfx
That register doesn't belong to a specific engine, so the proper
placement for workarounds programming it should be
general_render_compute_wa_init().
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++---------
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6dacd0dc5c2c..bd40b8c93d24 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2325,10 +2325,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
/* Wa_1509727124 */
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
SC_DISABLE_POWER_OPTIMIZATION_EBB);
-
- /* Wa_22013037850 */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
- DISABLE_128B_EVICTION_COMMAND_UDW);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
@@ -2357,21 +2353,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
}
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
- IS_DG2_G11(i915)) {
- /*
- * Wa_22012826095:dg2
- * Wa_22013059131:dg2
- */
- wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
- MAXREQS_PER_BANK,
- REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
-
- /* Wa_22013059131:dg2 */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
- FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
- }
-
/* Wa_1308578152:dg2_g10 when first gslice is fused off */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
needs_wa_1308578152(engine)) {
@@ -2396,16 +2377,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
*/
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
-
- /*
- * Wa_14010918519:dg2_g10
- *
- * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
- * so ignoring verification.
- */
- wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
- FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
- 0, false);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
@@ -2990,6 +2961,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
add_render_compute_tuning_settings(i915, wal);
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_22013037850 */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
+ DISABLE_128B_EVICTION_COMMAND_UDW);
+ }
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_PONTEVECCHIO(i915) ||
@@ -3011,6 +2991,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
+ IS_DG2_G11(i915)) {
+ /*
+ * Wa_22012826095:dg2
+ * Wa_22013059131:dg2
+ */
+ wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
+ MAXREQS_PER_BANK,
+ REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
+
+ /* Wa_22013059131:dg2 */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
+ FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
+ }
+
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
+ /*
+ * Wa_14010918519:dg2_g10
+ *
+ * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
+ * so ignoring verification.
+ */
+ wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
+ FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
+ 0, false);
+ }
+
if (IS_PONTEVECCHIO(i915)) {
/* Wa_16016694945 */
wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
--
2.39.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
2023-01-13 1:19 [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa
@ 2023-01-13 3:14 ` Patchwork
2023-01-13 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-17 18:06 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-01-13 3:14 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5294 bytes --]
== Series Details ==
Series: drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
URL : https://patchwork.freedesktop.org/series/112764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12578 -> Patchwork_112764v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/index.html
Participating hosts (42 -> 42)
------------------------------
Additional (1): fi-kbl-soraka
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112764v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
Known issues
------------
Here are the changes found in Patchwork_112764v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +15 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][6] ([i915#7156])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#5334])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [INCOMPLETE][9] ([i915#4983] / [i915#6257]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/bat-rpls-2/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- {bat-adlp-9}: [DMESG-FAIL][11] ([i915#6367]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/bat-adlp-9/igt@i915_selftest@live@slpc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/bat-adlp-9/igt@i915_selftest@live@slpc.html
- {bat-adln-1}: [DMESG-FAIL][13] ([i915#6997]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/bat-adln-1/igt@i915_selftest@live@slpc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/bat-adln-1/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12578 -> Patchwork_112764v1
CI-20190529: 20190529
CI_DRM_12578: c0ba6b6312e9139ce4b89da2904b329c13b5e94d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7119: 1e6d24e6dfa42b22f950f7d5e436b8f9acf8747f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112764v1: c0ba6b6312e9139ce4b89da2904b329c13b5e94d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1e40fc8f9383 drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/index.html
[-- Attachment #2: Type: text/html, Size: 6149 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
2023-01-13 1:19 [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa
2023-01-13 3:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2023-01-13 13:20 ` Patchwork
2023-01-17 18:06 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-01-13 13:20 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16723 bytes --]
== Series Details ==
Series: drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
URL : https://patchwork.freedesktop.org/series/112764/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12578_full -> Patchwork_112764v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/index.html
Participating hosts (13 -> 10)
------------------------------
Additional (1): shard-tglu-9
Missing (4): shard-rkl0 pig-kbl-iris pig-glk-j5005 pig-skl-6260u
Known issues
------------
Here are the changes found in Patchwork_112764v1_full that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}: [FAIL][1] ([i915#7742]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_create@hog-create@smem0:
- {shard-rkl}: [FAIL][3] ([i915#7679]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@gem_create@hog-create@smem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@gem_create@hog-create@smem0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][5] ([i915#2842]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_reloc@basic-gtt:
- {shard-rkl}: [SKIP][7] ([i915#3281]) -> [PASS][8] +10 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-4/igt@gem_exec_reloc@basic-gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_schedule@semaphore-power:
- {shard-rkl}: [SKIP][9] ([i915#7276]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@gem_exec_schedule@semaphore-power.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- {shard-rkl}: [SKIP][11] ([i915#3282]) -> [PASS][12] +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-uncached.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gen9_exec_parse@basic-rejected:
- {shard-rkl}: [SKIP][13] ([i915#2527]) -> [PASS][14] +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-4/igt@gen9_exec_parse@basic-rejected.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@gen9_exec_parse@basic-rejected.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][15] ([i915#1845] / [i915#4098]) -> [PASS][16] +9 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][17] ([i915#2346]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
- shard-glk: [FAIL][19] ([i915#79]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-rkl}: [SKIP][21] ([i915#1849] / [i915#4098]) -> [PASS][22] +7 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][23] ([i915#1849]) -> [PASS][24] +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][25] ([i915#1072]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-3/igt@kms_psr@cursor_render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- {shard-rkl}: [SKIP][27] ([i915#2436]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-1/igt@perf@gen8-unprivileged-single-ctx-counters.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][29] ([i915#1722]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-1/igt@perf@polling-small-buf.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@perf@polling-small-buf.html
* igt@prime_vgem@basic-fence-read:
- {shard-rkl}: [SKIP][31] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12578/shard-rkl-4/igt@prime_vgem@basic-fence-read.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7863]: https://gitlab.freedesktop.org/drm/intel/issues/7863
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12578 -> Patchwork_112764v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12578: c0ba6b6312e9139ce4b89da2904b329c13b5e94d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7119: 1e6d24e6dfa42b22f950f7d5e436b8f9acf8747f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112764v1: c0ba6b6312e9139ce4b89da2904b329c13b5e94d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112764v1/index.html
[-- Attachment #2: Type: text/html, Size: 9854 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
2023-01-13 1:19 [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa
2023-01-13 3:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-01-13 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-17 18:06 ` Rodrigo Vivi
2023-01-18 17:51 ` Gustavo Sousa
2 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2023-01-17 18:06 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Thu, Jan 12, 2023 at 10:19:47PM -0300, Gustavo Sousa wrote:
> That register doesn't belong to a specific engine, so the proper
> placement for workarounds programming it should be
> general_render_compute_wa_init().
Looking to the surrounds it seems like we have more registers
that are not per engine specific being touched there.
So, a few questions came to my mind:
- do we need to a bigger clean up and move other cases as well?
- do we need to review one by one and see if the bug is really
for all the engines or affect one specific engine hence the
function was initially placed here?
- do we have any clean documentation on how to split things
around and when or where to place things here or there?
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++---------
> 1 file changed, 36 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6dacd0dc5c2c..bd40b8c93d24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2325,10 +2325,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> /* Wa_1509727124 */
> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> SC_DISABLE_POWER_OPTIMIZATION_EBB);
> -
> - /* Wa_22013037850 */
> - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> - DISABLE_128B_EVICTION_COMMAND_UDW);
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> @@ -2357,21 +2353,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
> }
>
> - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
> - IS_DG2_G11(i915)) {
> - /*
> - * Wa_22012826095:dg2
> - * Wa_22013059131:dg2
> - */
> - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
> - MAXREQS_PER_BANK,
> - REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
> -
> - /* Wa_22013059131:dg2 */
> - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> - FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
> - }
> -
> /* Wa_1308578152:dg2_g10 when first gslice is fused off */
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
> needs_wa_1308578152(engine)) {
> @@ -2396,16 +2377,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> */
> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
> MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
> -
> - /*
> - * Wa_14010918519:dg2_g10
> - *
> - * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
> - * so ignoring verification.
> - */
> - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
> - FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
> - 0, false);
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> @@ -2990,6 +2961,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> + /* Wa_22013037850 */
> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> + DISABLE_128B_EVICTION_COMMAND_UDW);
> + }
> +
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_PONTEVECCHIO(i915) ||
> @@ -3011,6 +2991,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> }
>
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
> + IS_DG2_G11(i915)) {
> + /*
> + * Wa_22012826095:dg2
> + * Wa_22013059131:dg2
> + */
> + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
> + MAXREQS_PER_BANK,
> + REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
> +
> + /* Wa_22013059131:dg2 */
> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> + FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> + /*
> + * Wa_14010918519:dg2_g10
> + *
> + * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
> + * so ignoring verification.
> + */
> + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
> + FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
> + 0, false);
> + }
> +
> if (IS_PONTEVECCHIO(i915)) {
> /* Wa_16016694945 */
> wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> --
> 2.39.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function
2023-01-17 18:06 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
@ 2023-01-18 17:51 ` Gustavo Sousa
0 siblings, 0 replies; 5+ messages in thread
From: Gustavo Sousa @ 2023-01-18 17:51 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jan 17, 2023 at 01:06:17PM -0500, Rodrigo Vivi wrote:
> On Thu, Jan 12, 2023 at 10:19:47PM -0300, Gustavo Sousa wrote:
> > That register doesn't belong to a specific engine, so the proper
> > placement for workarounds programming it should be
> > general_render_compute_wa_init().
>
>
> Looking to the surrounds it seems like we have more registers
> that are not per engine specific being touched there.
>
> So, a few questions came to my mind:
> - do we need to a bigger clean up and move other cases as well?
I think so. I just happens that I was already working on a workaround
for that register and realized the inconsistency.
> - do we need to review one by one and see if the bug is really
> for all the engines or affect one specific engine hence the
> function was initially placed here?
As far as I know, the general_render_compute_wa_init() is actually
applied for a single engine and is for registers that are not tied to a
specific engine but share the common render/compute reset domain. I'm
including Matt Roper here, in case I'm missing something.
> - do we have any clean documentation on how to split things
> around and when or where to place things here or there?
I have sent a v2 with an additional patch extending our existing
documentation to make it clear where workarounds should be implemented
according to their classification:
https://patchwork.freedesktop.org/series/113036/
--
Gustavo Sousa
>
> >
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 ++++++++++++---------
> > 1 file changed, 36 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 6dacd0dc5c2c..bd40b8c93d24 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2325,10 +2325,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > /* Wa_1509727124 */
> > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > SC_DISABLE_POWER_OPTIMIZATION_EBB);
> > -
> > - /* Wa_22013037850 */
> > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> > - DISABLE_128B_EVICTION_COMMAND_UDW);
> > }
> >
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > @@ -2357,21 +2353,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
> > }
> >
> > - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
> > - IS_DG2_G11(i915)) {
> > - /*
> > - * Wa_22012826095:dg2
> > - * Wa_22013059131:dg2
> > - */
> > - wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
> > - MAXREQS_PER_BANK,
> > - REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
> > -
> > - /* Wa_22013059131:dg2 */
> > - wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> > - FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
> > - }
> > -
> > /* Wa_1308578152:dg2_g10 when first gslice is fused off */
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
> > needs_wa_1308578152(engine)) {
> > @@ -2396,16 +2377,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > */
> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
> > MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
> > -
> > - /*
> > - * Wa_14010918519:dg2_g10
> > - *
> > - * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
> > - * so ignoring verification.
> > - */
> > - wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
> > - FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
> > - 0, false);
> > }
> >
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> > @@ -2990,6 +2961,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >
> > add_render_compute_tuning_settings(i915, wal);
> >
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > + /* Wa_22013037850 */
> > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> > + DISABLE_128B_EVICTION_COMMAND_UDW);
> > + }
> > +
> > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > IS_PONTEVECCHIO(i915) ||
> > @@ -3011,6 +2991,33 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > }
> >
> > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
> > + IS_DG2_G11(i915)) {
> > + /*
> > + * Wa_22012826095:dg2
> > + * Wa_22013059131:dg2
> > + */
> > + wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
> > + MAXREQS_PER_BANK,
> > + REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
> > +
> > + /* Wa_22013059131:dg2 */
> > + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> > + FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
> > + }
> > +
> > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> > + /*
> > + * Wa_14010918519:dg2_g10
> > + *
> > + * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
> > + * so ignoring verification.
> > + */
> > + wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
> > + FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
> > + 0, false);
> > + }
> > +
> > if (IS_PONTEVECCHIO(i915)) {
> > /* Wa_16016694945 */
> > wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> > --
> > 2.39.0
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-01-18 17:51 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2023-01-13 1:19 [Intel-gfx] [PATCH] drm/i915/gt: Move LSC_CHICKEN_BIT* workarounds to correct function Gustavo Sousa
2023-01-13 3:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-01-13 13:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-17 18:06 ` [Intel-gfx] [PATCH] " Rodrigo Vivi
2023-01-18 17:51 ` Gustavo Sousa
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