From: Daniel Vetter <daniel@ffwll.ch>
To: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Daniel Vetter" <daniel.vetter@ffwll.ch>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
"Kenneth Graunke" <kenneth@whitecape.org>
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/uapi: reject caching ioctls for discrete
Date: Fri, 2 Jul 2021 21:16:26 +0200 [thread overview]
Message-ID: <YN9mCrx53/a5y/8n@phenom.ffwll.local> (raw)
In-Reply-To: <20210701143650.1094468-2-matthew.auld@intel.com>
On Thu, Jul 01, 2021 at 03:36:49PM +0100, Matthew Auld wrote:
> It's a noop on DG1, and in the future when need to support other devices
> which let us control the coherency, then it should be an immutable
> creation time property for the BO.
>
> Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ramalingam C <ramalingam.c@intel.com>
For this and the next can you pls add kerneldoc for the uapi structs and
then add a note there that on dgfx they're disallowed? Same for the next
one.
At least I'd like if we can document uapi here as we go, so that we have
something to point people to when they as "what has changed? what should I
do in my userspace driver?".
Also please make sure these two have acks from mesa devs before you land
them.
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 7d1400b13429..43004bef55cb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -268,6 +268,9 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
> struct drm_i915_gem_object *obj;
> int err = 0;
>
> + if (IS_DGFX(to_i915(dev)))
> + return -ENODEV;
> +
> rcu_read_lock();
> obj = i915_gem_object_lookup_rcu(file, args->handle);
> if (!obj) {
> @@ -303,6 +306,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
> enum i915_cache_level level;
> int ret = 0;
>
> + if (IS_DGFX(i915))
> + return -ENODEV;
> +
> switch (args->caching) {
> case I915_CACHING_NONE:
> level = I915_CACHE_NONE;
> --
> 2.26.3
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2021-07-02 19:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 14:36 [Intel-gfx] [PATCH 1/3] drm/i915: use consistent CPU mappings for pin_map users Matthew Auld
2021-07-01 14:36 ` [Intel-gfx] [PATCH 2/3] drm/i915/uapi: reject caching ioctls for discrete Matthew Auld
2021-07-02 19:16 ` Daniel Vetter [this message]
2021-07-01 14:36 ` [Intel-gfx] [PATCH 3/3] drm/i915/uapi: reject set_domain " Matthew Auld
2021-07-01 15:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: use consistent CPU mappings for pin_map users Patchwork
2021-07-01 15:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-01 15:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-01 18:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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