public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts
Date: Tue, 2 Nov 2021 22:08:54 +0100	[thread overview]
Message-ID: <YYGo5tfOevjL2UaV@intel.intel> (raw)
In-Reply-To: <8c2ec510-4e86-97f1-f0a9-872a2168455d@linux.intel.com>

Hi Tvrtko,

> > > > [...]
> > > > 
> > > > >    static int
> > > > >    intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
> > > > 
> > > > we don't actually need 'id', it's gt->info.id. It's introduced in
> > > > patch 3 with the value '0' but it's not needed.
> > > 
> > > I have a suspicion code got munged up over endless rebases and refactors.
> > > 
> > > This patch is the one which introduces the id member to gt->info. But it is not setting it, even though I suspect the intent was for intel_gt_tile_setup to do that.
> > > 
> > > Instead gt->info.id is only set to a valid value in last patch of this series inside intel_gt_probe_all:
> > > 
> > > +		gt->i915 = i915;
> > > +		gt->name = gtdef->name;
> > > +		gt->type = gtdef->type;
> > > +		gt->info.engine_mask = gtdef->engine_mask;
> > > +		gt->info.id = i;
> > > +
> > > +		drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id);
> > > +		ret = intel_gt_tile_setup(gt, i, phys_addr + gtdef->mapping_base);
> > > 
> > > And intel_gt_tile_setup then calls __intel_gt_init_early which assigns gt->i915 yet again.
> > > 
> > > So I'd say there is probably space to bring this all into a more streamlined flow, even more than what you suggest below.
> > 
> > yes, I noticed them!
> > 
> > Patch 3, 5 and 10 are very much connected with each other: 3
> > prepares for one tile, 5 prepares for multitile and 10 does the
> > multitile. While in between other patches are doing other things.
> > 
> > On top of some cleanups we could also rearrange the patches with
> > some squashing and reordering to have them a bit more linear and
> > also easier to review.
> 
> Yes. Maybe make intel_gt_tile_setup accept more arguments so it can be truly
> used to setup a gt?
> 
>   intel_gt_tile_setup(gt, id, name, type, engine_mask)
> 
> The usual thing where patch which adds something extends the prototype to
> include more stuff. If that applies here.
> 
> I know it is originally my patch but I don't have the time to rework it,
> much less the whole series, so usual dispensation to take over authorship if
> changes are large applies.

as no one is stepping forward, if you and Matt are OK, I can try
to venture in some refactoring of these three patches (3, 5 and
10).

Andi

  reply	other threads:[~2021-11-02 21:09 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-29  3:28 [Intel-gfx] [PATCH v3 00/10] i915: Initial multi-tile support Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 01/10] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 02/10] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper
2021-11-11  5:12   ` Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 03/10] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper
2021-11-01 22:58   ` Andi Shyti
2021-11-01 23:21   ` Andi Shyti
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 04/10] drm/i915: Store backpointer to GT in uncore Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts Matt Roper
2021-11-01 23:11   ` Andi Shyti
2021-11-02  9:36     ` Tvrtko Ursulin
2021-11-02 11:26       ` Andi Shyti
2021-11-02 13:58         ` Tvrtko Ursulin
2021-11-02 21:08           ` Andi Shyti [this message]
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 06/10] drm/i915: Initial support for per-tile uncore Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper
2021-11-01 23:33   ` Andi Shyti
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 09/10] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper
2021-11-01 23:35   ` Andi Shyti
2021-10-29  3:28 ` [Intel-gfx] [PATCH v3 10/10] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper
2021-10-29  3:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev3) Patchwork
2021-10-29  4:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-29 10:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
     [not found] <20211110232018.GA33197@dbstims-dev.fm.intel.com>
2021-11-10 23:30 ` [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts Andi Shyti
  -- strict thread matches above, loose matches on Subject: below --
2021-11-10 23:33 Stimson, Dale B

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YYGo5tfOevjL2UaV@intel.intel \
    --to=andi.shyti@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=tvrtko.ursulin@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox