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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	DRI Devel <dri-devel@lists.freedesktop.org>,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Matthew Auld <matthew.auld@intel.com>
Subject: Re: [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: Adding new sysfs frequency attributes
Date: Mon, 14 Mar 2022 02:38:04 +0200	[thread overview]
Message-ID: <Yi6ObL00OJ8gB+V8@intel.intel> (raw)
In-Reply-To: <28e2363a-38aa-9d68-ac59-b78c9168a814@intel.com>

Hi Michal,

[...]

> > +static ssize_t punit_req_freq_mhz_show(struct device *dev,
> > +				       struct device_attribute *attr,
> > +				       char *buff)
> > +{
> > +	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> > +	struct intel_rps *rps = &gt->rps;
> > +	u32 preq = intel_rps_read_punit_req_frequency(rps);
> > +
> > +	return scnprintf(buff, PAGE_SIZE, "%d\n", preq);
> 
> %u since preq is u32
> 
> and use sysfs_emit (also in below show functions)

sure! I'll change them.

[...]

> >  static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
> >  				const struct attribute * const *attrs)
> >  {
> > @@ -493,4 +628,11 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
> >  	if (ret)
> >  		drm_warn(&gt->i915->drm,
> >  			 "failed to create gt%u RPS sysfs files", gt->info.id);
> > +
> > +	ret = sysfs_create_files(kobj, freq_attrs);
> > +	if (ret)
> > +		drm_warn(&gt->i915->drm,
> > +			 "failed to create gt%u throttle sysfs files",
> > +			 gt->info.id);
> 
> nit: would be nice to see %pe why it failed

[...]

I will add it to the other cases as well.

> > +static u32 __rps_read_mmio(struct intel_gt *gt, i915_reg_t reg32)
> 
> this doesn't look like "rps" helper, rather like "gt" so it should have
> different prefix and maybe even be exported by the gt or uncore ?
> 
> unless you wanted:
> 
> static u32 __rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)
> {
> 	struct intel_gt *gt = rps_to_gt(rps);
> 
> > +{
> > +	intel_wakeref_t wakeref;
> > +	u32 val;
> > +
> > +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > +		val = intel_uncore_read(gt->uncore, reg32);
> > +
> > +	return val;
> > +}

Yes, you are right!

@Sujaritha: shall I move "__rps_read_mmio()" in intel_gt.c and
call it intel_gt_read_mmio()?

[...]

> > +u32 intel_rps_read_throttle_reason_vr_thermalert(struct intel_rps *rps)
> > +{
> > +	struct intel_gt *gt = rps_to_gt(rps);
> > +	u32 thermalert = __rps_read_mmio(gt, GT0_PERF_LIMIT_REASONS) & VR_THERMALERT_MASK;
> > +
> > +	return thermalert;
> > +}
> 
> shouldn't we return bool by all of these functions as used/expected in
> show() counterparts ?

Suja?

[...]

> > +#define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381A8)
> > +#define   GT0_PERF_LIMIT_REASONS_MASK	0x00000de3
> 
> this mask is different that other (FIELD_PREP/GET wont work) so maybe we
> should name it in special way ?

As far as I understood this is still a mask and used as such.
This mask is actually telling that there is some throttling going
on.

It looks weird because there are some unwanted bits in between
the interesting bits.

> > +#define   PROCHOT_MASK			BIT(1)
> > +#define   THERMAL_LIMIT_MASK		BIT(2)
> > +#define   RATL_MASK			BIT(6)
> > +#define   VR_THERMALERT_MASK		BIT(7)
> > +#define   VR_TDC_MASK			BIT(8)
> > +#define   POWER_LIMIT_4_MASK		BIT(9)
> > +#define   POWER_LIMIT_1_MASK		BIT(11)
> > +#define   POWER_LIMIT_2_MASK		BIT(12)
> 
> REG_BIT ?

yes!

Thanks, Michal!
Andi

  reply	other threads:[~2022-03-14  0:38 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-17 14:41 [Intel-gfx] [PATCH v5 0/7] Introduce multitile support Andi Shyti
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0 Andi Shyti
2022-02-28 19:53   ` Michal Wajdeczko
2022-03-01 15:19   ` Andrzej Hajda
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 2/7] drm/i915: Prepare for multiple GTs Andi Shyti
2022-03-01 15:15   ` Andrzej Hajda
2022-03-06 19:20     ` Andi Shyti
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/gt: add gt_is_root() helper Andi Shyti
2022-02-28 20:02   ` Michal Wajdeczko
2022-03-01 15:25     ` Andrzej Hajda
2022-03-06 19:23       ` Andi Shyti
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/gt: create per-tile sysfs interface Andi Shyti
2022-03-02 16:57   ` Andrzej Hajda
2022-03-06 23:04     ` Andi Shyti
2022-03-07 20:25       ` Andrzej Hajda
2022-03-13 19:45         ` Andi Shyti
2022-03-13 21:30           ` Andi Shyti
2022-03-14 12:08           ` Andrzej Hajda
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/gt: Create per-tile RC6 " Andi Shyti
2022-02-17 15:34   ` Tvrtko Ursulin
2022-02-17 15:53     ` Andi Shyti
2022-02-18  9:12       ` Tvrtko Ursulin
2022-02-18  9:21         ` Andi Shyti
2022-02-18 10:46       ` Joonas Lahtinen
2022-02-21 17:12         ` Tvrtko Ursulin
2022-02-22  8:57           ` Andi Shyti
2022-11-07  0:08             ` Dixit, Ashutosh
2022-02-17 20:49   ` kernel test robot
2022-02-17 23:53   ` kernel test robot
2022-03-03 10:19   ` Andrzej Hajda
2022-03-13 22:15     ` Andi Shyti
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces Andi Shyti
2022-02-17 19:47   ` kernel test robot
2022-03-03 10:55   ` Andrzej Hajda
2022-03-13 23:09     ` Andi Shyti
2022-02-17 14:41 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/gt: Adding new sysfs frequency attributes Andi Shyti
2022-02-17 15:45   ` Andi Shyti
2022-02-17 17:06     ` Sundaresan, Sujaritha
2022-02-28 20:37   ` Michal Wajdeczko
2022-03-14  0:38     ` Andi Shyti [this message]
2022-03-14  1:32       ` Sundaresan, Sujaritha
2022-03-03 11:17   ` Andrzej Hajda
2022-02-17 23:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce multitile support Patchwork
2022-02-17 23:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-17 23:40 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-02-17 23:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork

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