From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
Date: Wed, 9 Mar 2022 21:08:12 +0200 [thread overview]
Message-ID: <Yij7HFOvBiVg+kqD@intel.com> (raw)
In-Reply-To: <20220309185959.GA9439@intel.com>
On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote:
> On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Don't just mask off all the PSF GV points when SAGV gets disabled.
> > This should in fact cause the Pcode to reject the request since
> > at least one PSF point must remain enabled at all times.
>
> Good point, however I think this is not the full fix:
>
> BSpec says:
>
> "At least one GV point of each type must always remain unmasked."
>
> and
>
> "The GV point of each type providing the highest bandwidth
> for display must always remain unmasked."
>
> So I guess we should then also choose thr PSF GV point with
> the highest bandwidth as well.
The spec says PSF GV is fast enough to now stall the display data
fetch so we don't need to restrict the PSF points here.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2022-03-09 19:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 16:49 [Intel-gfx] [PATCH v2 0/8] drm/i915: SAGV block time fixes Ville Syrjala
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Treat SAGV block time 0 as SAGV disabled Ville Syrjala
2022-03-09 19:29 ` Lisovskiy, Stanislav
2022-03-09 20:35 ` Ville Syrjälä
2022-03-16 17:55 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Rework SAGV block time probing Ville Syrjala
2022-03-16 17:55 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Probe whether SAGV works on pre-icl Ville Syrjala
2022-03-16 17:57 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Reject excessive SAGV block time Ville Syrjala
2022-03-16 17:58 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Rename pre-icl SAGV enable/disable functions Ville Syrjala
2022-03-16 17:57 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible Ville Syrjala
2022-03-09 18:59 ` Lisovskiy, Stanislav
2022-03-09 19:08 ` Ville Syrjälä [this message]
2022-03-09 19:34 ` Lisovskiy, Stanislav
2022-03-09 20:21 ` Ville Syrjälä
2022-03-16 18:01 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Unconfuses QGV vs. PSF point masks Ville Syrjala
2022-03-16 17:56 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Rename QGV request/response bits Ville Syrjala
2022-03-16 17:57 ` Lisovskiy, Stanislav
2022-03-09 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: SAGV block time fixes (rev2) Patchwork
2022-03-09 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 5:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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