Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA

[Matt Roper <matthew.d.roper@intel.com>]

On Thu, Sep 29, 2022 at 10:09:01PM -0700, Lucas De Marchi wrote:
> ce->wa_bb_page is allocated only for graphics version 12. However
> __gen125_emit_bb_start() is used for any graphics version >= 12.50. For
> the currently supported platforms this is not an issue, but for future
> ones there's a mismatch causing the jump to
> `wa_offset + DG2_PREDICATE_RESULT_BB` to be invalid since wa_offset is
> not correct.
> 
> As in other places in the driver, check for graphics version "greater or
> equal" to future-proof the support for new platforms.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c |  2 ++
>  drivers/gpu/drm/i915/gt/intel_lrc.c      | 19 +++++++++----------
>  2 files changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 31a2fbd8c4a8..e000eaf8abed 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -405,6 +405,8 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
>  	u32 wa_offset = lrc_indirect_bb(ce);
>  	u32 *cs;
>  
> +	GEM_BUG_ON(!ce->wa_bb_page);
> +
>  	cs = intel_ring_begin(rq, 12);
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e84ef3859934..3515882a91fb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -825,19 +825,18 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>  static u32
>  lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
>  {
> -	switch (GRAPHICS_VER(engine->i915)) {
> -	default:
> -		MISSING_CASE(GRAPHICS_VER(engine->i915));
> -		fallthrough;
> -	case 12:
> +	if (GRAPHICS_VER(engine->i915) >= 12)
>  		return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> -	case 11:
> +	else if (GRAPHICS_VER(engine->i915) >= 11)
>  		return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> -	case 9:
> +	else if (GRAPHICS_VER(engine->i915) >= 9)
>  		return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> -	case 8:
> +	else if (GRAPHICS_VER(engine->i915) >= 8)
>  		return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> -	}
> +
> +	GEM_BUG_ON(GRAPHICS_VER(engine->i915) < 8);
> +
> +	return 0;
>  }
>  
>  static void
> @@ -1092,7 +1091,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>  	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>  		context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>  
> -	if (GRAPHICS_VER(engine->i915) == 12) {
> +	if (GRAPHICS_VER(engine->i915) >= 12) {
>  		ce->wa_bb_page = context_size / PAGE_SIZE;
>  		context_size += PAGE_SIZE;
>  	}
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation