* [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init
@ 2022-09-30 5:09 Lucas De Marchi
2022-09-30 5:09 ` [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA Lucas De Marchi
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Lucas De Marchi @ 2022-09-30 5:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Lucas De Marchi, Matthew Auld, Chris Wilson
Some small improvements to future-proof the initialization around the
register state context.
Lucas De Marchi (3):
drm/i915: Fix __gen125_emit_bb_start() without WA
drm/i915/gt: Document function to decode register state context
drm/i915/gt: Fix platform prefix
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 26 +++++------
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 12 +++---
.../drm/i915/gt/intel_execlists_submission.c | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ++++++++++++++-----
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
5 files changed, 56 insertions(+), 31 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
@ 2022-09-30 5:09 ` Lucas De Marchi
2022-09-30 17:49 ` Matt Roper
2022-09-30 5:09 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context Lucas De Marchi
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2022-09-30 5:09 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: Lucas De Marchi, Matthew Auld, Chris Wilson, Chris Wilson
ce->wa_bb_page is allocated only for graphics version 12. However
__gen125_emit_bb_start() is used for any graphics version >= 12.50. For
the currently supported platforms this is not an issue, but for future
ones there's a mismatch causing the jump to
`wa_offset + DG2_PREDICATE_RESULT_BB` to be invalid since wa_offset is
not correct.
As in other places in the driver, check for graphics version "greater or
equal" to future-proof the support for new platforms.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 31a2fbd8c4a8..e000eaf8abed 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -405,6 +405,8 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
u32 wa_offset = lrc_indirect_bb(ce);
u32 *cs;
+ GEM_BUG_ON(!ce->wa_bb_page);
+
cs = intel_ring_begin(rq, 12);
if (IS_ERR(cs))
return PTR_ERR(cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e84ef3859934..3515882a91fb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -825,19 +825,18 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
static u32
lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
{
- switch (GRAPHICS_VER(engine->i915)) {
- default:
- MISSING_CASE(GRAPHICS_VER(engine->i915));
- fallthrough;
- case 12:
+ if (GRAPHICS_VER(engine->i915) >= 12)
return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
- case 11:
+ else if (GRAPHICS_VER(engine->i915) >= 11)
return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
- case 9:
+ else if (GRAPHICS_VER(engine->i915) >= 9)
return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
- case 8:
+ else if (GRAPHICS_VER(engine->i915) >= 8)
return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
- }
+
+ GEM_BUG_ON(GRAPHICS_VER(engine->i915) < 8);
+
+ return 0;
}
static void
@@ -1092,7 +1091,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
context_size += I915_GTT_PAGE_SIZE; /* for redzone */
- if (GRAPHICS_VER(engine->i915) == 12) {
+ if (GRAPHICS_VER(engine->i915) >= 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
context_size += PAGE_SIZE;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
2022-09-30 5:09 ` [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA Lucas De Marchi
@ 2022-09-30 5:09 ` Lucas De Marchi
2022-09-30 17:55 ` Matt Roper
2022-09-30 5:09 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix Lucas De Marchi
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2022-09-30 5:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Lucas De Marchi, Matthew Auld, Chris Wilson
It's no obviously clear how the encode/decode of the per platform tables
is done. Document it so while adding tables for new platforms people can
be confident they right things is being done.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3515882a91fb..7771a19008c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -20,6 +20,30 @@
#include "intel_ring.h"
#include "shmem_utils.h"
+/*
+ * The per-platform tables are u8-encoded in @data. Decode @data and set the
+ * addresses' offset and commands in @regs. The following encoding is used
+ * for each byte. There are 2 steps: decoding commands and decoding addresses.
+ *
+ * Commands:
+ * [7]: create NOPs - number of NOPs are set in lower bits
+ * [6]: When creating MI_LOAD_REGISTER_IMM command, allow to set
+ * MI_LRI_FORCE_POSTED
+ * [5:0]: Number of NOPs or registers to set values to in case of
+ * MI_LOAD_REGISTER_IMM
+ *
+ * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"
+ * number of registers. They are set by using the REG/REG16 macros: the former
+ * is used for offsets smaller than 0x200 while the latter is for values bigger
+ * than that. Those macros already set all the bits documented below correctly:
+ *
+ * [7]: When a register offset needs more than 6 bits, use additional bytes, to
+ * follow, for the lower bits
+ * [6:0]: Register offset, without considering the engine base.
+ *
+ * This function only tweaks the commands and register offsets. Values are not
+ * filled out.
+ */
static void set_offsets(u32 *regs,
const u8 *data,
const struct intel_engine_cs *engine,
--
2.37.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
2022-09-30 5:09 ` [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA Lucas De Marchi
2022-09-30 5:09 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context Lucas De Marchi
@ 2022-09-30 5:09 ` Lucas De Marchi
2022-09-30 17:56 ` Matt Roper
2022-09-30 6:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve register state context init Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2022-09-30 5:09 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Lucas De Marchi, Matthew Auld, Chris Wilson
Different handling for XeHP and later platforms should be using the
xehp prefix, not gen125. Rename them.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 24 +++++++++----------
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 12 +++++-----
.../drm/i915/gt/intel_execlists_submission.c | 4 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e000eaf8abed..e1c76e5bfa82 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -396,10 +396,10 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq)
return 0;
}
-static int __gen125_emit_bb_start(struct i915_request *rq,
- u64 offset, u32 len,
- const unsigned int flags,
- u32 arb)
+static int __xehp_emit_bb_start(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags,
+ u32 arb)
{
struct intel_context *ce = rq->context;
u32 wa_offset = lrc_indirect_bb(ce);
@@ -437,18 +437,18 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
return 0;
}
-int gen125_emit_bb_start_noarb(struct i915_request *rq,
- u64 offset, u32 len,
- const unsigned int flags)
+int xehp_emit_bb_start_noarb(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags)
{
- return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
+ return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
}
-int gen125_emit_bb_start(struct i915_request *rq,
- u64 offset, u32 len,
- const unsigned int flags)
+int xehp_emit_bb_start(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags)
{
- return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
+ return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
}
int gen8_emit_bb_start_noarb(struct i915_request *rq,
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
index e4d24c811dd6..655e5c00ddc2 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
@@ -32,12 +32,12 @@ int gen8_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
const unsigned int flags);
-int gen125_emit_bb_start_noarb(struct i915_request *rq,
- u64 offset, u32 len,
- const unsigned int flags);
-int gen125_emit_bb_start(struct i915_request *rq,
- u64 offset, u32 len,
- const unsigned int flags);
+int xehp_emit_bb_start_noarb(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags);
+int xehp_emit_bb_start(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags);
u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index c718e6dc40b5..0187bc72310d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3471,9 +3471,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
if (intel_engine_has_preemption(engine))
- engine->emit_bb_start = gen125_emit_bb_start;
+ engine->emit_bb_start = xehp_emit_bb_start;
else
- engine->emit_bb_start = gen125_emit_bb_start_noarb;
+ engine->emit_bb_start = xehp_emit_bb_start_noarb;
} else {
if (intel_engine_has_preemption(engine))
engine->emit_bb_start = gen8_emit_bb_start;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0ef295a94060..d81f68fef9a8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4094,7 +4094,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_bb_start = gen8_emit_bb_start;
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- engine->emit_bb_start = gen125_emit_bb_start;
+ engine->emit_bb_start = xehp_emit_bb_start;
}
static void rcs_submission_override(struct intel_engine_cs *engine)
--
2.37.3
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve register state context init
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
` (2 preceding siblings ...)
2022-09-30 5:09 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix Lucas De Marchi
@ 2022-09-30 6:13 ` Patchwork
2022-09-30 18:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve register state context init (rev2) Patchwork
2022-10-01 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-30 6:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3865 bytes --]
== Series Details ==
Series: drm/i915: Improve register state context init
URL : https://patchwork.freedesktop.org/series/109284/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12202 -> Patchwork_109284v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109284v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109284v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/index.html
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-rkl-11600 fi-hsw-4200u fi-tgl-u2 fi-ctg-p8600 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109284v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12202/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_109284v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12202/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@lmem0:
- {bat-dg2-11}: [DMESG-WARN][5] ([i915#6816]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12202/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][7] ([i915#4983]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12202/bat-rpls-1/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/bat-rpls-1/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
Build changes
-------------
* Linux: CI_DRM_12202 -> Patchwork_109284v1
CI-20190529: 20190529
CI_DRM_12202: 0b9f0501c9541cf79fdfb43a7760360a81453d88 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109284v1: 0b9f0501c9541cf79fdfb43a7760360a81453d88 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
93b56b01f580 drm/i915/gt: Fix platform prefix
a3a4bfec1d19 drm/i915/gt: Document function to decode register state context
b996c7997bbb drm/i915: Fix __gen125_emit_bb_start() without WA
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v1/index.html
[-- Attachment #2: Type: text/html, Size: 4384 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA
2022-09-30 5:09 ` [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA Lucas De Marchi
@ 2022-09-30 17:49 ` Matt Roper
0 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2022-09-30 17:49 UTC (permalink / raw)
To: Lucas De Marchi
Cc: intel-gfx, Chris Wilson, Matthew Auld, dri-devel, Chris Wilson
On Thu, Sep 29, 2022 at 10:09:01PM -0700, Lucas De Marchi wrote:
> ce->wa_bb_page is allocated only for graphics version 12. However
> __gen125_emit_bb_start() is used for any graphics version >= 12.50. For
> the currently supported platforms this is not an issue, but for future
> ones there's a mismatch causing the jump to
> `wa_offset + DG2_PREDICATE_RESULT_BB` to be invalid since wa_offset is
> not correct.
>
> As in other places in the driver, check for graphics version "greater or
> equal" to future-proof the support for new platforms.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++++++++----------
> 2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 31a2fbd8c4a8..e000eaf8abed 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -405,6 +405,8 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
> u32 wa_offset = lrc_indirect_bb(ce);
> u32 *cs;
>
> + GEM_BUG_ON(!ce->wa_bb_page);
> +
> cs = intel_ring_begin(rq, 12);
> if (IS_ERR(cs))
> return PTR_ERR(cs);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e84ef3859934..3515882a91fb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -825,19 +825,18 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> static u32
> lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
> {
> - switch (GRAPHICS_VER(engine->i915)) {
> - default:
> - MISSING_CASE(GRAPHICS_VER(engine->i915));
> - fallthrough;
> - case 12:
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> - case 11:
> + else if (GRAPHICS_VER(engine->i915) >= 11)
> return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> - case 9:
> + else if (GRAPHICS_VER(engine->i915) >= 9)
> return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> - case 8:
> + else if (GRAPHICS_VER(engine->i915) >= 8)
> return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> - }
> +
> + GEM_BUG_ON(GRAPHICS_VER(engine->i915) < 8);
> +
> + return 0;
> }
>
> static void
> @@ -1092,7 +1091,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>
> - if (GRAPHICS_VER(engine->i915) == 12) {
> + if (GRAPHICS_VER(engine->i915) >= 12) {
> ce->wa_bb_page = context_size / PAGE_SIZE;
> context_size += PAGE_SIZE;
> }
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context
2022-09-30 5:09 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context Lucas De Marchi
@ 2022-09-30 17:55 ` Matt Roper
0 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2022-09-30 17:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Chris Wilson, Matthew Auld, dri-devel
On Thu, Sep 29, 2022 at 10:09:02PM -0700, Lucas De Marchi wrote:
> It's no obviously clear how the encode/decode of the per platform tables
This should probably say "...not obvious..." or "...not clear..."
Otherwise,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> is done. Document it so while adding tables for new platforms people can
> be confident they right things is being done.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 3515882a91fb..7771a19008c6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -20,6 +20,30 @@
> #include "intel_ring.h"
> #include "shmem_utils.h"
>
> +/*
> + * The per-platform tables are u8-encoded in @data. Decode @data and set the
> + * addresses' offset and commands in @regs. The following encoding is used
> + * for each byte. There are 2 steps: decoding commands and decoding addresses.
> + *
> + * Commands:
> + * [7]: create NOPs - number of NOPs are set in lower bits
> + * [6]: When creating MI_LOAD_REGISTER_IMM command, allow to set
> + * MI_LRI_FORCE_POSTED
> + * [5:0]: Number of NOPs or registers to set values to in case of
> + * MI_LOAD_REGISTER_IMM
> + *
> + * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"
> + * number of registers. They are set by using the REG/REG16 macros: the former
> + * is used for offsets smaller than 0x200 while the latter is for values bigger
> + * than that. Those macros already set all the bits documented below correctly:
> + *
> + * [7]: When a register offset needs more than 6 bits, use additional bytes, to
> + * follow, for the lower bits
> + * [6:0]: Register offset, without considering the engine base.
> + *
> + * This function only tweaks the commands and register offsets. Values are not
> + * filled out.
> + */
> static void set_offsets(u32 *regs,
> const u8 *data,
> const struct intel_engine_cs *engine,
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix
2022-09-30 5:09 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix Lucas De Marchi
@ 2022-09-30 17:56 ` Matt Roper
0 siblings, 0 replies; 10+ messages in thread
From: Matt Roper @ 2022-09-30 17:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Chris Wilson, Matthew Auld, dri-devel
On Thu, Sep 29, 2022 at 10:09:03PM -0700, Lucas De Marchi wrote:
> Different handling for XeHP and later platforms should be using the
> xehp prefix, not gen125. Rename them.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 24 +++++++++----------
> drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 12 +++++-----
> .../drm/i915/gt/intel_execlists_submission.c | 4 ++--
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> 4 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e000eaf8abed..e1c76e5bfa82 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -396,10 +396,10 @@ int gen8_emit_init_breadcrumb(struct i915_request *rq)
> return 0;
> }
>
> -static int __gen125_emit_bb_start(struct i915_request *rq,
> - u64 offset, u32 len,
> - const unsigned int flags,
> - u32 arb)
> +static int __xehp_emit_bb_start(struct i915_request *rq,
> + u64 offset, u32 len,
> + const unsigned int flags,
> + u32 arb)
> {
> struct intel_context *ce = rq->context;
> u32 wa_offset = lrc_indirect_bb(ce);
> @@ -437,18 +437,18 @@ static int __gen125_emit_bb_start(struct i915_request *rq,
> return 0;
> }
>
> -int gen125_emit_bb_start_noarb(struct i915_request *rq,
> - u64 offset, u32 len,
> - const unsigned int flags)
> +int xehp_emit_bb_start_noarb(struct i915_request *rq,
> + u64 offset, u32 len,
> + const unsigned int flags)
> {
> - return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
> + return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
> }
>
> -int gen125_emit_bb_start(struct i915_request *rq,
> - u64 offset, u32 len,
> - const unsigned int flags)
> +int xehp_emit_bb_start(struct i915_request *rq,
> + u64 offset, u32 len,
> + const unsigned int flags)
> {
> - return __gen125_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
> + return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
> }
>
> int gen8_emit_bb_start_noarb(struct i915_request *rq,
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> index e4d24c811dd6..655e5c00ddc2 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
> @@ -32,12 +32,12 @@ int gen8_emit_bb_start(struct i915_request *rq,
> u64 offset, u32 len,
> const unsigned int flags);
>
> -int gen125_emit_bb_start_noarb(struct i915_request *rq,
> - u64 offset, u32 len,
> - const unsigned int flags);
> -int gen125_emit_bb_start(struct i915_request *rq,
> - u64 offset, u32 len,
> - const unsigned int flags);
> +int xehp_emit_bb_start_noarb(struct i915_request *rq,
> + u64 offset, u32 len,
> + const unsigned int flags);
> +int xehp_emit_bb_start(struct i915_request *rq,
> + u64 offset, u32 len,
> + const unsigned int flags);
>
> u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
> u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index c718e6dc40b5..0187bc72310d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3471,9 +3471,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>
> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
> if (intel_engine_has_preemption(engine))
> - engine->emit_bb_start = gen125_emit_bb_start;
> + engine->emit_bb_start = xehp_emit_bb_start;
> else
> - engine->emit_bb_start = gen125_emit_bb_start_noarb;
> + engine->emit_bb_start = xehp_emit_bb_start_noarb;
> } else {
> if (intel_engine_has_preemption(engine))
> engine->emit_bb_start = gen8_emit_bb_start;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0ef295a94060..d81f68fef9a8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4094,7 +4094,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>
> engine->emit_bb_start = gen8_emit_bb_start;
> if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> - engine->emit_bb_start = gen125_emit_bb_start;
> + engine->emit_bb_start = xehp_emit_bb_start;
> }
>
> static void rcs_submission_override(struct intel_engine_cs *engine)
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve register state context init (rev2)
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
` (3 preceding siblings ...)
2022-09-30 6:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve register state context init Patchwork
@ 2022-09-30 18:51 ` Patchwork
2022-10-01 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-30 18:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7027 bytes --]
== Series Details ==
Series: drm/i915: Improve register state context init (rev2)
URL : https://patchwork.freedesktop.org/series/109284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12203 -> Patchwork_109284v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/index.html
Participating hosts (48 -> 47)
------------------------------
Additional (1): fi-hsw-4770
Missing (2): fi-ctg-p8600 fi-hsw-4200u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109284v2:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@slpc:
- {bat-rpls-2}: [DMESG-FAIL][1] ([i915#6367]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-rpls-2/igt@i915_selftest@live@slpc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in Patchwork_109284v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770: NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1072]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([fdo#109295] / [i915#3301])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#4312])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][9] ([i915#2582]) -> [PASS][10] +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-rpls-2/igt@fbdev@read.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-rpls-2/igt@fbdev@read.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][11] ([i915#2867]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}: [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][15] ([i915#5537]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-rpls-2/igt@i915_module_load@reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-rpls-2/igt@i915_module_load@reload.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][17] ([i915#6106]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][19] ([i915#6257]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/bat-rpls-1/igt@i915_selftest@live@requests.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-bsw-kefka: [FAIL][21] ([i915#2122]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/fi-bsw-kefka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
Build changes
-------------
* Linux: CI_DRM_12203 -> Patchwork_109284v2
CI-20190529: 20190529
CI_DRM_12203: 40460fc26c763f07130fdafc72c39ba4110ad19b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109284v2: 40460fc26c763f07130fdafc72c39ba4110ad19b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
71a1f5db5199 drm/i915/gt: Fix platform prefix
b8ccad75af01 drm/i915/gt: Document function to decode register state context
b89b56ea34d3 drm/i915: Fix __gen125_emit_bb_start() without WA
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/index.html
[-- Attachment #2: Type: text/html, Size: 8195 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Improve register state context init (rev2)
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
` (4 preceding siblings ...)
2022-09-30 18:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve register state context init (rev2) Patchwork
@ 2022-10-01 16:00 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-10-01 16:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 25047 bytes --]
== Series Details ==
Series: drm/i915: Improve register state context init (rev2)
URL : https://patchwork.freedesktop.org/series/109284/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12203_full -> Patchwork_109284v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109284v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109284v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109284v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_scaling_modes@scaling-mode-center@edp-1-pipe-d:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-tglb7/igt@kms_scaling_modes@scaling-mode-center@edp-1-pipe-d.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-tglb8/igt@kms_scaling_modes@scaling-mode-center@edp-1-pipe-d.html
Known issues
------------
Here are the changes found in Patchwork_109284v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-apl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [FAIL][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4386])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl8/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl8/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl7/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl8/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl8/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][55] -> [SKIP][56] ([i915#4525])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][57] ([i915#2842])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk8/igt@gem_exec_fair@basic-none@vcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-iclb: [PASS][62] -> [DMESG-WARN][63] ([i915#2867])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb8/igt@i915_suspend@basic-s3-without-i915.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-iclb: [PASS][64] -> [FAIL][65] ([i915#2521])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271]) +45 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3886])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3886])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-crc-single:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@dp-hpd-enable-disable-mode:
- shard-glk: NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@kms_chamelium@dp-hpd-enable-disable-mode.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][71] ([i915#1319])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][72] -> [FAIL][73] ([i915#2122])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#2672]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#3555])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [PASS][76] -> [SKIP][77] ([i915#5314])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271]) +59 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#2920])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-tglb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][82] -> [SKIP][83] ([fdo#109441]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][84] -> [DMESG-WARN][85] ([i915#180]) +4 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][87] ([i915#4525]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][89] ([i915#2842]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][91] ([i915#2190]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-tglb8/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][93] ([i915#3989] / [i915#454]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-apl: [FAIL][95] ([i915#2346]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
- shard-iclb: [FAIL][97] ([i915#2346]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [DMESG-WARN][99] ([i915#180]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_plane_multiple@tiling-y@pipe-d-edp-1:
- shard-tglb: [INCOMPLETE][101] ([i915#7006]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-tglb8/igt@kms_plane_multiple@tiling-y@pipe-d-edp-1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-tglb7/igt@kms_plane_multiple@tiling-y@pipe-d-edp-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][103] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][105] ([fdo#109441]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][107] ([i915#5519]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-tglb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-tglb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf@oa-exponents:
- shard-glk: [INCOMPLETE][109] ([i915#5213]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk5/igt@perf@oa-exponents.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk1/igt@perf@oa-exponents.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][111] ([i915#5639]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-glk9/igt@perf@polling-parameterized.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-glk3/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][113] ([i915#4525]) -> [FAIL][114] ([i915#6117])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][115] ([i915#658]) -> [SKIP][116] ([i915#2920])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb4/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][117] ([i915#2920]) -> [SKIP][118] ([fdo#111068] / [i915#658])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb4/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][119] ([i915#2920]) -> [SKIP][120] ([i915#658])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl7/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12203/shard-apl3/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl3/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl7/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl1/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5314]: https://gitlab.freedesktop.org/drm/intel/issues/5314
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7006]: https://gitlab.freedesktop.org/drm/intel/issues/7006
Build changes
-------------
* Linux: CI_DRM_12203 -> Patchwork_109284v2
CI-20190529: 20190529
CI_DRM_12203: 40460fc26c763f07130fdafc72c39ba4110ad19b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109284v2: 40460fc26c763f07130fdafc72c39ba4110ad19b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109284v2/index.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-01 16:01 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-09-30 5:09 [Intel-gfx] [PATCH 0/3] drm/i915: Improve register state context init Lucas De Marchi
2022-09-30 5:09 ` [Intel-gfx] [PATCH 1/3] drm/i915: Fix __gen125_emit_bb_start() without WA Lucas De Marchi
2022-09-30 17:49 ` Matt Roper
2022-09-30 5:09 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Document function to decode register state context Lucas De Marchi
2022-09-30 17:55 ` Matt Roper
2022-09-30 5:09 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Fix platform prefix Lucas De Marchi
2022-09-30 17:56 ` Matt Roper
2022-09-30 6:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Improve register state context init Patchwork
2022-09-30 18:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve register state context init (rev2) Patchwork
2022-10-01 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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