* [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display
@ 2025-03-25 12:36 Jani Nikula
2025-03-25 12:36 ` [PATCH 1/6] drm/i915/dpll: convert intel_dpll.[ch] " Jani Nikula
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
We're getting there!
Jani Nikula (6):
drm/i915/dpll: convert intel_dpll.[ch] to struct intel_display
drm/i915/ddi: convert intel_ddi.c to struct intel_display
drm/i915/crc: convert intel_pipe_crc.c to struct intel_display
drm/i915/psr: further conversions to struct intel_display
drm/i915/wa: convert intel_display_wa.[ch] to struct intel_display
drm/i915/display: drop some unnecessary intel_de_* compatibility
wrappers
drivers/gpu/drm/i915/display/intel_ddi.c | 904 +++++++++---------
drivers/gpu/drm/i915/display/intel_de.h | 16 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_driver.c | 7 +-
.../gpu/drm/i915/display/intel_display_wa.c | 30 +-
.../gpu/drm/i915/display/intel_display_wa.h | 11 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 312 +++---
drivers/gpu/drm/i915/display/intel_dpll.h | 13 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 137 ++-
drivers/gpu/drm/i915/display/intel_pps.c | 5 +-
drivers/gpu/drm/i915/display/intel_psr.c | 85 +-
drivers/gpu/drm/xe/display/xe_display_wa.c | 6 +-
13 files changed, 729 insertions(+), 803 deletions(-)
--
2.39.5
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/6] drm/i915/dpll: convert intel_dpll.[ch] to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 12:36 ` [PATCH 2/6] drm/i915/ddi: convert intel_ddi.c " Jani Nikula ` (8 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_dpll.[ch] to struct intel_display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_driver.c | 4 +- drivers/gpu/drm/i915/display/intel_dpll.c | 312 +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll.h | 13 +- drivers/gpu/drm/i915/display/intel_pps.c | 5 +- 5 files changed, 160 insertions(+), 178 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 48282611db3e..5e2c210fcd84 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2146,9 +2146,9 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { if (display->platform.cherryview) - chv_disable_pll(dev_priv, pipe); + chv_disable_pll(display, pipe); else if (display->platform.valleyview) - vlv_disable_pll(dev_priv, pipe); + vlv_disable_pll(display, pipe); else i9xx_disable_pll(old_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index e4fbf1e5b2bb..61748525da0b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -181,8 +181,6 @@ static void intel_plane_possible_crtcs_init(struct intel_display *display) void intel_display_driver_early_probe(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (!HAS_DISPLAY(display)) return; @@ -198,7 +196,7 @@ void intel_display_driver_early_probe(struct intel_display *display) intel_color_init_hooks(display); intel_init_cdclk_hooks(display); intel_audio_hooks_init(display); - intel_dpll_init_clock_hook(i915); + intel_dpll_init_clock_hook(display); intel_init_display_hooks(display); intel_fdi_init_hook(display); intel_dmc_wl_init(display); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 23f4e01c3e8f..0481b1365b85 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -373,14 +373,15 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) - return i915->display.vbt.lvds_ssc_freq; + return display->vbt.lvds_ssc_freq; else if (HAS_PCH_SPLIT(i915)) return 120000; - else if (DISPLAY_VER(i915) != 2) + else if (DISPLAY_VER(display) != 2) return 96000; else return 48000; @@ -389,27 +390,27 @@ static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, struct intel_dpll_hw_state *dpll_hw_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { u32 tmp; /* No way to read it out on pipes B and C */ - if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) - tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; + if (display->platform.cherryview && crtc->pipe != PIPE_A) + tmp = display->state.chv_dpll_md[crtc->pipe]; else - tmp = intel_de_read(dev_priv, - DPLL_MD(dev_priv, crtc->pipe)); + tmp = intel_de_read(display, + DPLL_MD(display, crtc->pipe)); hw_state->dpll_md = tmp; } - hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); + hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe)); - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { - hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); - hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); + if (!display->platform.valleyview && !display->platform.cherryview) { + hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe)); + hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe)); } else { /* Mask out read-only status bits. */ hw_state->dpll &= ~(DPLL_LOCK_VLV | @@ -423,7 +424,6 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; u32 dpll = hw_state->dpll; u32 fp; @@ -437,7 +437,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) fp = hw_state->fp1; clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; - if (IS_PINEVIEW(dev_priv)) { + if (display->platform.pineview) { clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; } else { @@ -445,8 +445,8 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; } - if (DISPLAY_VER(dev_priv) != 2) { - if (IS_PINEVIEW(dev_priv)) + if (DISPLAY_VER(display) != 2) { + if (display->platform.pineview) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); else @@ -463,23 +463,23 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) 7 : 14; break; default: - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unknown DPLL mode %08x in programmed " "mode\n", (int)(dpll & DPLL_MODE_MASK)); return; } - if (IS_PINEVIEW(dev_priv)) + if (display->platform.pineview) port_clock = pnv_calc_dpll_params(refclk, &clock); else port_clock = i9xx_calc_dpll_params(refclk, &clock); } else { enum pipe lvds_pipe; - if (IS_I85X(dev_priv) && + if (display->platform.i85x && intel_lvds_port_enabled(display, LVDS, &lvds_pipe) && lvds_pipe == crtc->pipe) { - u32 lvds = intel_de_read(dev_priv, LVDS); + u32 lvds = intel_de_read(display, LVDS); clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> DPLL_FPA01_P1_POST_DIV_SHIFT); @@ -578,7 +578,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) * Returns whether the given set of divisors are valid for a given refclk with * the given connectors. */ -static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, +static bool intel_pll_is_valid(struct intel_display *display, const struct intel_limit *limit, const struct dpll *clock) { @@ -591,14 +591,14 @@ static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) return false; - if (!IS_PINEVIEW(dev_priv) && - !IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (!display->platform.pineview && + !display->platform.valleyview && !display->platform.cherryview && + !display->platform.broxton && !display->platform.geminilake) if (clock->m1 <= clock->m2) return false; - if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv)) { + if (!display->platform.valleyview && !display->platform.cherryview && + !display->platform.broxton && !display->platform.geminilake) { if (clock->p < limit->p.min || limit->p.max < clock->p) return false; if (clock->m < limit->m.min || limit->m.max < clock->m) @@ -657,7 +657,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int err = target; @@ -678,7 +678,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit, int this_err; i9xx_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -715,7 +715,7 @@ pnv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int err = target; @@ -734,7 +734,7 @@ pnv_find_best_dpll(const struct intel_limit *limit, int this_err; pnv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -771,7 +771,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; int max_n; bool found = false; @@ -795,7 +795,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, int this_err; i9xx_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; @@ -818,7 +818,7 @@ g4x_find_best_dpll(const struct intel_limit *limit, * Check if the calculated PLL configuration is more optimal compared to the * best configuration and error found so far. Return the calculated error. */ -static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, +static bool vlv_PLL_is_optimal(struct intel_display *display, int target_freq, const struct dpll *calculated_clock, const struct dpll *best_clock, unsigned int best_error_ppm, @@ -828,13 +828,13 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, * For CHV ignore the error and consider only the P value. * Prefer a bigger P value based on HW requirements. */ - if (IS_CHERRYVIEW(to_i915(dev))) { + if (display->platform.cherryview) { *error_ppm = 0; return calculated_clock->p > best_clock->p; } - if (drm_WARN_ON_ONCE(dev, !target_freq)) + if (drm_WARN_ON_ONCE(display->drm, !target_freq)) return false; *error_ppm = div_u64(1000000ULL * @@ -865,8 +865,7 @@ vlv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_device *dev = crtc->base.dev; + struct intel_display *display = to_intel_display(crtc_state); struct dpll clock; unsigned int bestppm = 1000000; /* min update 19.2 MHz */ @@ -890,12 +889,12 @@ vlv_find_best_dpll(const struct intel_limit *limit, vlv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), + if (!intel_pll_is_valid(display, limit, &clock)) continue; - if (!vlv_PLL_is_optimal(dev, target, + if (!vlv_PLL_is_optimal(display, target, &clock, best_clock, bestppm, &ppm)) @@ -923,8 +922,7 @@ chv_find_best_dpll(const struct intel_limit *limit, const struct dpll *match_clock, struct dpll *best_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_device *dev = crtc->base.dev; + struct intel_display *display = to_intel_display(crtc_state); unsigned int best_error_ppm; struct dpll clock; u64 m2; @@ -959,10 +957,10 @@ chv_find_best_dpll(const struct intel_limit *limit, chv_calc_dpll_params(refclk, &clock); - if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) + if (!intel_pll_is_valid(display, limit, &clock)) continue; - if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, + if (!vlv_PLL_is_optimal(display, target, &clock, best_clock, best_error_ppm, &error_ppm)) continue; @@ -1006,8 +1004,6 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; @@ -1017,8 +1013,8 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, else dpll |= DPLLB_MODE_DAC_SERIAL; - if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { + if (display->platform.i945g || display->platform.i945gm || + display->platform.g33 || display->platform.pineview) { dpll |= (crtc_state->pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; } @@ -1031,10 +1027,10 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, dpll |= DPLL_SDVO_HIGH_SPEED; /* compute bitmask from p1 value */ - if (IS_G4X(dev_priv)) { + if (display->platform.g4x) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; - } else if (IS_PINEVIEW(dev_priv)) { + } else if (display->platform.pineview) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; WARN_ON(reduced_clock->p1 != clock->p1); } else { @@ -1058,7 +1054,7 @@ static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, } WARN_ON(reduced_clock->p2 != clock->p2); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -1076,11 +1072,10 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - if (IS_PINEVIEW(dev_priv)) { + if (display->platform.pineview) { hw_state->fp0 = pnv_dpll_compute_fp(clock); hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); } else { @@ -1090,7 +1085,7 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) hw_state->dpll_md = i965_dpll_md(crtc_state); } @@ -1099,8 +1094,6 @@ static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; @@ -1130,7 +1123,7 @@ static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, * both DPLLS. The spec says we should disable the DVO 2X clock * when not needed, but this seems to work fine in practice. */ - if (IS_I830(dev_priv) || + if (display->platform.i830 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) dpll |= DPLL_DVO_2X_MODE; @@ -1158,14 +1151,14 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, static int hsw_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); int ret; - if (DISPLAY_VER(dev_priv) < 11 && + if (DISPLAY_VER(display) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -1187,13 +1180,13 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); - if (DISPLAY_VER(dev_priv) < 11 && + if (DISPLAY_VER(display) < 11 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; @@ -1246,7 +1239,7 @@ static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state) struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && - ((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) || + ((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) || (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(display)))) return 25; @@ -1277,8 +1270,6 @@ static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; dpll = DPLL_VCO_ENABLE; @@ -1312,7 +1303,7 @@ static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, * clear if it''s a win or loss power wise. No point in doing * this on ILK at all since it has a fixed DPLL<->pipe mapping. */ - if (INTEL_NUM_PIPES(dev_priv) == 3 && + if (INTEL_NUM_PIPES(display) == 3 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) dpll |= DPLL_SDVO_HIGH_SPEED; @@ -1363,7 +1354,6 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1376,10 +1366,10 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", - dev_priv->display.vbt.lvds_ssc_freq); - refclk = dev_priv->display.vbt.lvds_ssc_freq; + display->vbt.lvds_ssc_freq); + refclk = display->vbt.lvds_ssc_freq; } if (intel_is_dual_link_lvds(display)) { @@ -1540,7 +1530,6 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1548,8 +1537,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1590,7 +1579,6 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1598,8 +1586,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1629,7 +1617,6 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1637,8 +1624,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1670,7 +1657,6 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_limit *limit; @@ -1678,8 +1664,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(display)) { - refclk = dev_priv->display.vbt.lvds_ssc_freq; - drm_dbg_kms(&dev_priv->drm, + refclk = display->vbt.lvds_ssc_freq; + drm_dbg_kms(display->drm, "using SSC reference clock of %d kHz\n", refclk); } @@ -1752,12 +1738,12 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = { int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; - drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); + drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); @@ -1765,9 +1751,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, if (!crtc_state->hw.enable) return 0; - ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); + ret = display->funcs.dpll->crtc_compute_clock(state, crtc); if (ret) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", crtc->base.base.id, crtc->base.name); return ret; } @@ -1778,23 +1764,23 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; - drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); - drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); + drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); if (!crtc_state->hw.enable || crtc_state->shared_dpll) return 0; - if (!i915->display.funcs.dpll->crtc_get_shared_dpll) + if (!display->funcs.dpll->crtc_get_shared_dpll) return 0; - ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); + ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc); if (ret) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", crtc->base.base.id, crtc->base.name); return ret; } @@ -1803,43 +1789,44 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, } void -intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) -{ - if (DISPLAY_VER(dev_priv) >= 14) - dev_priv->display.funcs.dpll = &mtl_dpll_funcs; - else if (IS_DG2(dev_priv)) - dev_priv->display.funcs.dpll = &dg2_dpll_funcs; - else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) - dev_priv->display.funcs.dpll = &hsw_dpll_funcs; +intel_dpll_init_clock_hook(struct intel_display *display) +{ + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 14) + display->funcs.dpll = &mtl_dpll_funcs; + else if (display->platform.dg2) + display->funcs.dpll = &dg2_dpll_funcs; + else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display)) + display->funcs.dpll = &hsw_dpll_funcs; else if (HAS_PCH_SPLIT(dev_priv)) - dev_priv->display.funcs.dpll = &ilk_dpll_funcs; - else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &chv_dpll_funcs; - else if (IS_VALLEYVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &vlv_dpll_funcs; - else if (IS_G4X(dev_priv)) - dev_priv->display.funcs.dpll = &g4x_dpll_funcs; - else if (IS_PINEVIEW(dev_priv)) - dev_priv->display.funcs.dpll = &pnv_dpll_funcs; - else if (DISPLAY_VER(dev_priv) != 2) - dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; + display->funcs.dpll = &ilk_dpll_funcs; + else if (display->platform.cherryview) + display->funcs.dpll = &chv_dpll_funcs; + else if (display->platform.valleyview) + display->funcs.dpll = &vlv_dpll_funcs; + else if (display->platform.g4x) + display->funcs.dpll = &g4x_dpll_funcs; + else if (display->platform.pineview) + display->funcs.dpll = &pnv_dpll_funcs; + else if (DISPLAY_VER(display) != 2) + display->funcs.dpll = &i9xx_dpll_funcs; else - dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; + display->funcs.dpll = &i8xx_dpll_funcs; } -static bool i9xx_has_pps(struct drm_i915_private *dev_priv) +static bool i9xx_has_pps(struct intel_display *display) { - if (IS_I830(dev_priv)) + if (display->platform.i830) return false; - return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); + return display->platform.pineview || display->platform.mobile; } void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; int i; @@ -1847,27 +1834,27 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) assert_transcoder_disabled(display, crtc_state->cpu_transcoder); /* PLL is protected by panel, make sure we can write it */ - if (i9xx_has_pps(dev_priv)) + if (i9xx_has_pps(display)) assert_pps_unlocked(display, pipe); - intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); - intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); + intel_de_write(display, FP0(pipe), hw_state->fp0); + intel_de_write(display, FP1(pipe), hw_state->fp1); /* * Apparently we need to have VGA mode enabled prior to changing * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); - if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + if (DISPLAY_VER(display) >= 4) { + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); } else { /* The pixel multiplier can only be updated once the @@ -1875,20 +1862,21 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) * * So write it again. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); /* wait for warmup */ } } -static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, +static void vlv_pllb_recal_opamp(struct intel_display *display, enum dpio_phy phy, enum dpio_channel ch) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 tmp; /* @@ -1917,6 +1905,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; @@ -1931,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) /* PLL B needs special handling */ if (pipe == PIPE_B) - vlv_pllb_recal_opamp(dev_priv, phy, ch); + vlv_pllb_recal_opamp(display, phy, ch); /* Set up Tx target for periodic Rcomp update */ vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); @@ -2004,24 +1993,23 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); - if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) - drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); + if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) + drm_err(display->drm, "DPLL %d failed to lock\n", pipe); } void vlv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; @@ -2031,7 +2019,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(display, pipe); /* Enable Refclk */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2039,8 +2027,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) _vlv_enable_pll(crtc_state); } - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); + intel_de_posting_read(display, DPLL_MD(display, pipe)); } static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) @@ -2134,6 +2122,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; @@ -2157,18 +2146,17 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) udelay(1); /* Enable PLL */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_write(display, DPLL(display, pipe), hw_state->dpll); /* Check PLL is locked */ - if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) - drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); + if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) + drm_err(display->drm, "PLL %d failed to lock\n", pipe); } void chv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; @@ -2178,7 +2166,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(display, pipe); /* Enable Refclk and SSC */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), hw_state->dpll & ~DPLL_VCO_ENABLE); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2193,29 +2181,29 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * DPLLCMD is AWOL. Use chicken bits to propagate * the value from DPLLBMD to either pipe B or C. */ - intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B), + intel_de_write(display, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); + intel_de_write(display, DPLL_MD(display, PIPE_B), hw_state->dpll_md); - intel_de_write(dev_priv, CBR4_VLV, 0); - dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; + intel_de_write(display, CBR4_VLV, 0); + display->state.chv_dpll_md[pipe] = hw_state->dpll_md; /* * DPLLB VGA mode also seems to cause problems. * We should always have it disabled. */ - drm_WARN_ON(&dev_priv->drm, - (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & + drm_WARN_ON(display->drm, + (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { - intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + intel_de_write(display, DPLL_MD(display, pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); + intel_de_posting_read(display, DPLL_MD(display, pipe)); } } /** * vlv_force_pll_on - forcibly enable just the PLL - * @dev_priv: i915 private structure + * @display: display device * @pipe: pipe PLL to enable * @dpll: PLL configuration * @@ -2223,10 +2211,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * in cases where we need the PLL enabled even when @pipe is not going to * be enabled. */ -int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, +int vlv_force_pll_on(struct intel_display *display, enum pipe pipe, const struct dpll *dpll) { - struct intel_display *display = &dev_priv->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); struct intel_crtc_state *crtc_state; @@ -2239,7 +2226,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, crtc_state->dpll = *dpll; crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { chv_compute_dpll(crtc_state); chv_enable_pll(crtc_state); } else { @@ -2252,9 +2239,8 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, return 0; } -void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +void vlv_disable_pll(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; u32 val; /* Make sure the pipe isn't still relying on us */ @@ -2269,9 +2255,9 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) intel_de_posting_read(display, DPLL(display, pipe)); } -void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) +void chv_disable_pll(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -2317,18 +2303,18 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) /** * vlv_force_pll_off - forcibly disable just the PLL - * @dev_priv: i915 private structure + * @display: display device * @pipe: pipe PLL to disable * * Disable the PLL for @pipe. To be used in cases where we need * the PLL enabled even when @pipe is not going to be enabled. */ -void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) +void vlv_force_pll_off(struct intel_display *display, enum pipe pipe) { - if (IS_CHERRYVIEW(dev_priv)) - chv_disable_pll(dev_priv, pipe); + if (display->platform.cherryview) + chv_disable_pll(display, pipe); else - vlv_disable_pll(dev_priv, pipe); + vlv_disable_pll(display, pipe); } /* Only for pre-ILK configs */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index 21d06cbd2ce7..280e90a57c87 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -8,16 +8,15 @@ #include <linux/types.h> +enum pipe; struct dpll; -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dpll_hw_state; -enum pipe; -void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv); +void intel_dpll_init_clock_hook(struct intel_display *display); int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc); int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, @@ -29,14 +28,14 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, void vlv_compute_dpll(struct intel_crtc_state *crtc_state); void chv_compute_dpll(struct intel_crtc_state *crtc_state); -int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, +int vlv_force_pll_on(struct intel_display *display, enum pipe pipe, const struct dpll *dpll); -void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); +void vlv_force_pll_off(struct intel_display *display, enum pipe pipe); void chv_enable_pll(const struct intel_crtc_state *crtc_state); -void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); +void chv_disable_pll(struct intel_display *display, enum pipe pipe); void vlv_enable_pll(const struct intel_crtc_state *crtc_state); -void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); +void vlv_disable_pll(struct intel_display *display, enum pipe pipe); void i9xx_enable_pll(const struct intel_crtc_state *crtc_state); void i9xx_disable_pll(const struct intel_crtc_state *crtc_state); bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 6a92acfa1634..7154d5e06c7b 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -91,7 +91,6 @@ static void vlv_power_sequencer_kick(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps.vlv_pps_pipe; bool pll_enabled, release_cl_override = false; @@ -134,7 +133,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) release_cl_override = display->platform.cherryview && !chv_phy_powergate_ch(display, phy, ch, true); - if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) { + if (vlv_force_pll_on(display, pipe, vlv_get_dpll(display))) { drm_err(display->drm, "Failed to force on PLL for pipe %c!\n", pipe_name(pipe)); @@ -158,7 +157,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) intel_de_posting_read(display, intel_dp->output_reg); if (!pll_enabled) { - vlv_force_pll_off(dev_priv, pipe); + vlv_force_pll_off(display, pipe); if (release_cl_override) chv_phy_powergate_ch(display, phy, ch, false); -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/6] drm/i915/ddi: convert intel_ddi.c to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula 2025-03-25 12:36 ` [PATCH 1/6] drm/i915/dpll: convert intel_dpll.[ch] " Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 12:36 ` [PATCH 3/6] drm/i915/crc: convert intel_pipe_crc.c " Jani Nikula ` (7 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_ddi.c to struct intel_display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 904 +++++++++++------------ 1 file changed, 437 insertions(+), 467 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f38c998935b9..864e97a7a4d4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -106,14 +106,14 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder, return level; } -static bool has_buf_trans_select(struct drm_i915_private *i915) +static bool has_buf_trans_select(struct intel_display *display) { - return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); + return DISPLAY_VER(display) < 10 && !display->platform.broxton; } -static bool has_iboost(struct drm_i915_private *i915) +static bool has_iboost(struct intel_display *display) { - return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); + return DISPLAY_VER(display) == 9 && !display->platform.broxton; } /* @@ -124,25 +124,25 @@ static bool has_iboost(struct drm_i915_private *i915) void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; const struct intel_ddi_buf_trans *trans; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; /* If we're boosting the current, set bit 31 of trans1 */ - if (has_iboost(dev_priv) && + if (has_iboost(display) && intel_bios_dp_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; for (i = 0; i < n_entries; i++) { - intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), + intel_de_write(display, DDI_BUF_TRANS_LO(port, i), trans->entries[i].hsw.trans1 | iboost_bit); - intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), + intel_de_write(display, DDI_BUF_TRANS_HI(port, i), trans->entries[i].hsw.trans2); } } @@ -155,7 +155,7 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); int level = intel_ddi_level(encoder, crtc_state, 0); u32 iboost_bit = 0; int n_entries; @@ -163,27 +163,25 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, const struct intel_ddi_buf_trans *trans; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; /* If we're boosting the current, set bit 31 of trans1 */ - if (has_iboost(dev_priv) && + if (has_iboost(display) && intel_bios_hdmi_boost_level(encoder->devdata)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; /* Entry 9 is for HDMI: */ - intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), + intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), trans->entries[level].hsw.trans1 | iboost_bit); - intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), + intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), trans->entries[level].hsw.trans2); } static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 14) - return XELPDP_PORT_BUF_CTL1(i915, port); + return XELPDP_PORT_BUF_CTL1(display, port); else return DDI_BUF_CTL(port); } @@ -346,7 +344,6 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -359,14 +356,14 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (dig_port->ddi_a_4_lanes) intel_dp->DP |= DDI_A_4_LANES; - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(display) >= 14) { if (intel_dp_is_uhbr(crtc_state)) intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; else intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; } - if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { + if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; @@ -379,8 +376,7 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, } } -static int icl_calc_tbt_pll_link(struct intel_display *display, - enum port port) +static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) { u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; @@ -414,15 +410,14 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 temp; if (!intel_crtc_has_dp_encoder(crtc_state)) return; - drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); + drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); temp = DP_MSA_MISC_SYNC_CLOCK; @@ -445,7 +440,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, } /* nonsense combination */ - drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + drm_WARN_ON(display->drm, crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) @@ -468,7 +463,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) temp |= DP_MSA_MISC_COLOR_VSC_SDP; - intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), temp); } @@ -507,8 +502,8 @@ static u32 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum port port = encoder->port; @@ -516,7 +511,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ temp = TRANS_DDI_FUNC_ENABLE; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) temp |= TGL_TRANS_DDI_SELECT_PORT(port); else temp |= TRANS_DDI_SELECT_PORT(port); @@ -578,7 +573,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_HDMI_SCRAMBLING; if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; @@ -591,11 +586,11 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_DP_MST; temp |= DDI_PORT_WIDTH(crtc_state->lane_count); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { enum transcoder master; master = crtc_state->mst_master_transcoder; - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, master == INVALID_TRANSCODER); temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); } @@ -604,7 +599,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= DDI_PORT_WIDTH(crtc_state->lane_count); } - if (IS_DISPLAY_VER(dev_priv, 8, 10) && + if (IS_DISPLAY_VER(display, 8, 10) && crtc_state->master_transcoder != INVALID_TRANSCODER) { u8 master_select = bdw_trans_port_sync_master_select(crtc_state->master_transcoder); @@ -619,11 +614,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { enum transcoder master_transcoder = crtc_state->master_transcoder; u32 ctl2 = 0; @@ -635,12 +629,12 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, PORT_SYNC_MODE_MASTER_SELECT(master_select); } - intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + intel_de_write(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), ctl2); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state)); } @@ -654,8 +648,7 @@ void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; @@ -663,7 +656,7 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder, ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); ctl &= ~TRANS_DDI_FUNC_ENABLE; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), ctl); } @@ -677,27 +670,26 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; - if (DISPLAY_VER(dev_priv) >= 11) - intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + if (DISPLAY_VER(display) >= 11) + intel_de_write(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0); - ctl = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + ctl = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); ctl &= ~TRANS_DDI_FUNC_ENABLE; - if (IS_DISPLAY_VER(dev_priv, 8, 10)) + if (IS_DISPLAY_VER(display, 8, 10)) ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { if (!intel_dp_mst_is_master_trans(crtc_state)) { ctl &= ~(TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); @@ -706,7 +698,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), ctl); if (intel_dp_mst_is_slave_trans(crtc_state)) @@ -725,17 +717,15 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool enable, u32 hdcp_mask) { struct intel_display *display = to_intel_display(intel_encoder); - struct drm_device *dev = intel_encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); intel_wakeref_t wakeref; int ret = 0; wakeref = intel_display_power_get_if_enabled(display, intel_encoder->power_domain); - if (drm_WARN_ON(dev, !wakeref)) + if (drm_WARN_ON(display->drm, !wakeref)) return -ENXIO; - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), hdcp_mask, enable ? hdcp_mask : 0); intel_display_power_put(display, intel_encoder->power_domain, wakeref); return ret; @@ -744,7 +734,6 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) { struct intel_display *display = to_intel_display(intel_connector); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder = intel_attached_encoder(intel_connector); int type = intel_connector->base.connector_type; enum port port = encoder->port; @@ -765,12 +754,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) goto out; } - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) cpu_transcoder = TRANSCODER_EDP; else cpu_transcoder = (enum transcoder) pipe; - ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & + ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_MODE_SELECT_MASK; if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || @@ -804,7 +793,6 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u8 *pipe_mask, bool *is_dp_mst) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum port port = encoder->port; intel_wakeref_t wakeref; enum pipe p; @@ -819,13 +807,13 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!wakeref) return; - tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + tmp = intel_de_read(display, DDI_BUF_CTL(port)); if (!(tmp & DDI_BUF_CTL_ENABLE)) goto out; - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: @@ -846,7 +834,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, goto out; } - for_each_pipe(dev_priv, p) { + for_each_pipe(display, p) { enum transcoder cpu_transcoder = (enum transcoder)p; u32 port_mask, ddi_select, ddi_mode; intel_wakeref_t trans_wakeref; @@ -856,7 +844,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!trans_wakeref) continue; - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { port_mask = TGL_TRANS_DDI_PORT_MASK; ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); } else { @@ -864,8 +852,8 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, ddi_select = TRANS_DDI_SELECT_PORT(port); } - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); @@ -883,7 +871,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (!*pipe_mask) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "No pipe for [ENCODER:%d:%s] found\n", encoder->base.base.id, encoder->base.name); @@ -906,7 +894,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", encoder->base.base.id, encoder->base.name, *pipe_mask); @@ -914,7 +902,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", encoder->base.base.id, encoder->base.name, *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); @@ -922,12 +910,12 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, *is_dp_mst = mst_pipe_mask; out: - if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { - tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); + if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { + tmp = intel_de_read(display, BXT_PHY_CTL(port)); if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) - drm_err(&dev_priv->drm, + drm_err(display->drm, "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", encoder->base.base.id, encoder->base.name, tmp); } @@ -1041,8 +1029,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum phy phy = intel_encoder_to_phy(encoder); u32 val; @@ -1050,53 +1037,53 @@ void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, if (cpu_transcoder == TRANSCODER_EDP) return; - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) val = TGL_TRANS_CLK_SEL_PORT(phy); - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) val = TGL_TRANS_CLK_SEL_PORT(encoder->port); else val = TRANS_CLK_SEL_PORT(encoder->port); - intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); + intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); } void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val; if (cpu_transcoder == TRANSCODER_EDP) return; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) val = TGL_TRANS_CLK_SEL_DISABLED; else val = TRANS_CLK_SEL_DISABLED; - intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); + intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); } -static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, +static void _skl_ddi_set_iboost(struct intel_display *display, enum port port, u8 iboost) { u32 tmp; - tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); + tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); if (iboost) tmp |= iboost << BALANCE_LEG_SHIFT(port); else tmp |= BALANCE_LEG_DISABLE(port); - intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); + intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); } static void skl_ddi_set_iboost(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int level) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u8 iboost; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) @@ -1109,7 +1096,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, int n_entries; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; iboost = trans->entries[level].hsw.i_boost; @@ -1117,28 +1104,28 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, /* Make sure that the requested I_boost is valid */ if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { - drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); + drm_err(display->drm, "Invalid I_boost value %u\n", iboost); return; } - _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); + _skl_ddi_set_iboost(display, encoder->port, iboost); if (encoder->port == PORT_A && dig_port->max_lanes == 4) - _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); + _skl_ddi_set_iboost(display, PORT_E, iboost); } static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int n_entries; encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) + if (drm_WARN_ON(display->drm, n_entries < 1)) n_entries = 1; - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) n_entries = ARRAY_SIZE(index_to_dp_signal_levels); @@ -1171,14 +1158,14 @@ static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_stat static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_encoder_to_phy(encoder); int n_entries, ln; u32 val; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { @@ -1186,25 +1173,25 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; intel_dp->hobl_active = is_hobl_buf_trans(trans); - intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, + intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, intel_dp->hobl_active ? val : 0); } /* Set PORT_TX_DW5 */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | COEFF_POLARITY | CURSOR_PROGRAM | TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); /* Program PORT_TX_DW2 */ for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | @@ -1216,7 +1203,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | @@ -1227,7 +1214,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, for (ln = 0; ln < 4; ln++) { int level = intel_ddi_level(encoder, crtc_state, ln); - intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), N_SCALAR_MASK, N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); } @@ -1236,7 +1223,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); u32 val; int ln; @@ -1246,12 +1233,12 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, * set PORT_PCS_DW1 cmnkeeper_enable to 1b, * else clear to 0b. */ - val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) val &= ~COMMON_KEEPER_EN; else val |= COMMON_KEEPER_EN; - intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); /* 2. Program loadgen select */ /* @@ -1261,33 +1248,33 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln < 4; ln++) { - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), LOADGEN_SELECT, icl_combo_phy_loadgen_select(crtc_state, ln)); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ - intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), + intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG); /* 4. Clear training enable to change swing values */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~TX_TRAINING_EN; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ icl_ddi_combo_vswing_program(encoder, crtc_state); /* 6. Set training enable to trigger update */ - val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); val |= TX_TRAINING_EN; - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); } static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); const struct intel_ddi_buf_trans *trans; int n_entries, ln; @@ -1296,13 +1283,13 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, return; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), + intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), CRI_USE_FS32, 0); - intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), + intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), CRI_USE_FS32, 0); } @@ -1312,13 +1299,13 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_17_12_MASK, CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_17_12_MASK, CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); } @@ -1329,7 +1316,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK, CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | @@ -1338,7 +1325,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), + intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK, CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | @@ -1354,21 +1341,21 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, * values from table for which TX1 and TX2 enabled. */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), + intel_de_rmw(display, MG_CLKHUB(ln, tc_port), CFG_LOW_RATE_LKREN_EN, crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); } /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), + intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | CFG_AMI_CK_DIV_OVERRIDE_EN, crtc_state->port_clock > 500000 ? CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | CFG_AMI_CK_DIV_OVERRIDE_EN : 0); - intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), + intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | CFG_AMI_CK_DIV_OVERRIDE_EN, crtc_state->port_clock > 500000 ? @@ -1378,9 +1365,9 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, /* Program MG_TX_PISO_READLOAD with values from vswing table */ for (ln = 0; ln < 2; ln++) { - intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), + intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 0, CRI_CALCINIT); - intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), + intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 0, CRI_CALCINIT); } } @@ -1490,12 +1477,12 @@ int intel_ddi_level(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int lane) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; int level, n_entries; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&i915->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return 0; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) @@ -1504,7 +1491,7 @@ int intel_ddi_level(struct intel_encoder *encoder, level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, lane); - if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) + if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) level = n_entries - 1; return level; @@ -1514,13 +1501,13 @@ static void hsw_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); int level = intel_ddi_level(encoder, crtc_state, 0); enum port port = encoder->port; u32 signal_levels; - if (has_iboost(dev_priv)) + if (has_iboost(display)) skl_ddi_set_iboost(encoder, crtc_state, level); /* HDMI ignores the rest */ @@ -1529,46 +1516,46 @@ hsw_set_signal_levels(struct intel_encoder *encoder, signal_levels = DDI_BUF_TRANS_SELECT(level); - drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", + drm_dbg_kms(display->drm, "Using signal levels %08x\n", signal_levels); intel_dp->DP &= ~DDI_BUF_EMP_MASK; intel_dp->DP |= signal_levels; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); + intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); + intel_de_posting_read(display, DDI_BUF_CTL(port)); } -static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); + intel_de_rmw(display, reg, clk_sel_mask, clk_sel); /* * "This step and the step before must be * done with separate register writes." */ - intel_de_rmw(i915, reg, clk_off, 0); + intel_de_rmw(display, reg, clk_off, 0); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } -static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, +static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, u32 clk_off) { - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, reg, 0, clk_off); + intel_de_rmw(display, reg, 0, clk_off); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } -static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, +static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, u32 clk_off) { - return !(intel_de_read(i915, reg) & clk_off); + return !(intel_de_read(display, reg) & clk_off); } static struct intel_shared_dpll * @@ -1585,14 +1572,14 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, static void adls_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1600,19 +1587,19 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder, static void adls_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), + _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), + return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1629,14 +1616,14 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) static void rkl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1644,19 +1631,19 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, static void rkl_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1673,23 +1660,23 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys */ - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) return; - _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), + _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1697,19 +1684,19 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, static void dg1_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), + _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), + return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1739,14 +1726,14 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_encoder_to_phy(encoder); - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); @@ -1754,19 +1741,19 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, + _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } @@ -1783,39 +1770,39 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; /* * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. * MG does not exist, but the programming is required to ungate DDIC and DDID." */ - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); icl_ddi_combo_enable_clock(encoder, crtc_state); } static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; icl_ddi_combo_disable_clock(encoder); - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; u32 tmp; - tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + tmp = intel_de_read(display, DDI_CLK_SEL(port)); if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) return false; @@ -1826,54 +1813,54 @@ static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - intel_de_write(i915, DDI_CLK_SEL(port), + intel_de_write(display, DDI_CLK_SEL(port), icl_pll_to_ddi_clk_sel(encoder, crtc_state)); - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + intel_de_rmw(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, + intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); - intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); + intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; u32 tmp; - tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + tmp = intel_de_read(display, DDI_CLK_SEL(port)); if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) return false; - tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); + tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); } @@ -1934,47 +1921,47 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, DPLL_CTRL2, + intel_de_rmw(display, DPLL_CTRL2, DPLL_CTRL2_DDI_CLK_OFF(port) | DPLL_CTRL2_DDI_CLK_SEL_MASK(port), DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static void skl_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); - intel_de_rmw(i915, DPLL_CTRL2, + intel_de_rmw(display, DPLL_CTRL2, 0, DPLL_CTRL2_DDI_CLK_OFF(port)); - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; /* * FIXME Not sure if the override affects both * the PLL selection and the CLK_OFF bit. */ - return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); + return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); } static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) @@ -2002,30 +1989,30 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; - intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); + intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); } void hsw_ddi_disable_clock(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); + intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; + return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; } static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) @@ -2081,7 +2068,7 @@ void intel_ddi_disable_clock(struct intel_encoder *encoder) void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); u32 port_mask; bool ddi_clk_needed; @@ -2101,7 +2088,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * In the unlikely case that BIOS enables DP in MST mode, just * warn since our MST HW readout is incomplete. */ - if (drm_WARN_ON(&i915->drm, is_mst)) + if (drm_WARN_ON(display->drm, is_mst)) return; } @@ -2116,11 +2103,11 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * Sanity check that we haven't incorrectly registered another * encoder using any of the ports of this DSI encoder. */ - for_each_intel_encoder(&i915->drm, other_encoder) { + for_each_intel_encoder(display->drm, other_encoder) { if (other_encoder == encoder) continue; - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, port_mask & BIT(other_encoder->port))) return; } @@ -2135,7 +2122,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) !encoder->is_clock_enabled(encoder)) return; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", encoder->base.base.id, encoder->base.name); @@ -2255,10 +2242,10 @@ tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_CTL(dev_priv, + if (DISPLAY_VER(display) >= 12) + return TGL_DP_TP_CTL(display, tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_CTL(encoder->port); @@ -2267,10 +2254,10 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_STATUS(dev_priv, + if (DISPLAY_VER(display) >= 12) + return TGL_DP_TP_STATUS(display, tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_STATUS(encoder->port); @@ -2445,14 +2432,14 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, static void intel_ddi_disable_fec(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); if (!crtc_state->fec_enable) return; - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_FEC_ENABLE, 0); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); } static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, @@ -2474,11 +2461,11 @@ static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, * Splitter enable for eDP MSO is limited to certain pipes, on certain * platforms. */ -static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) +static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) { - if (DISPLAY_VER(i915) > 20) + if (DISPLAY_VER(display) > 20) return ~0; - else if (IS_ALDERLAKE_P(i915)) + else if (display->platform.alderlake_p) return BIT(PIPE_A) | BIT(PIPE_B); else return BIT(PIPE_A); @@ -2487,28 +2474,28 @@ static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) static void intel_ddi_mso_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(pipe_config); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; - dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); + dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; if (!pipe_config->splitter.enable) return; - if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { + if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { pipe_config->splitter.enable = false; return; } switch (dss1 & SPLITTER_CONFIGURATION_MASK) { default: - drm_WARN(&i915->drm, true, + drm_WARN(display->drm, true, "Invalid splitter configuration, dss1=0x%08x\n", dss1); fallthrough; case SPLITTER_CONFIGURATION_2_SEGMENT: @@ -2524,12 +2511,12 @@ static void intel_ddi_mso_get_config(struct intel_encoder *encoder, static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 dss1 = 0; - if (!HAS_MSO(i915)) + if (!HAS_MSO(display)) return; if (crtc_state->splitter.enable) { @@ -2541,7 +2528,7 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; } - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), + intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK, dss1); } @@ -2549,27 +2536,27 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) static void mtl_ddi_enable_d2d(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; i915_reg_t reg; u32 set_bits, wait_bits; - if (DISPLAY_VER(dev_priv) < 14) + if (DISPLAY_VER(display) < 14) return; - if (DISPLAY_VER(dev_priv) >= 20) { + if (DISPLAY_VER(display) >= 20) { reg = DDI_BUF_CTL(port); set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; } else { - reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); + reg = XELPDP_PORT_BUF_CTL1(display, port); set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; } - intel_de_rmw(dev_priv, reg, 0, set_bits); - if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { - drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", + intel_de_rmw(display, reg, 0, set_bits); + if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { + drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", port_name(port)); } } @@ -2599,13 +2586,13 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u32 val; val = intel_tc_port_in_tbt_alt_mode(dig_port) ? XELPDP_PORT_BUF_IO_SELECT_TBT : 0; - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), XELPDP_PORT_BUF_IO_SELECT_TBT, val); } @@ -2734,7 +2721,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int ret; @@ -2778,7 +2764,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2882,16 +2868,15 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - if (DISPLAY_VER(dev_priv) < 11) - drm_WARN_ON(&dev_priv->drm, + if (DISPLAY_VER(display) < 11) + drm_WARN_ON(display->drm, is_mst && (port == PORT_A || port == PORT_E)); else - drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); + drm_WARN_ON(display->drm, is_mst && port == PORT_A); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, @@ -2908,14 +2893,14 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_enable_clock(encoder, crtc_state); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } icl_program_mg_dp_mode(dig_port, crtc_state); - if (has_buf_trans_select(dev_priv)) + if (has_buf_trans_select(display)) hsw_prepare_dp_ddi_buffers(encoder, crtc_state); encoder->set_signal_levels(encoder, crtc_state); @@ -2931,7 +2916,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); intel_dp_start_link_train(state, intel_dp, crtc_state); - if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && + if ((port != PORT_A || DISPLAY_VER(display) >= 9) && !is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp, crtc_state); @@ -2979,12 +2964,11 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); intel_ddi_enable_clock(encoder, crtc_state); - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); @@ -3022,10 +3006,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); + drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); intel_set_cpu_fifo_underrun_reporting(display, pipe, true); @@ -3050,27 +3033,27 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, static void mtl_ddi_disable_d2d(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; i915_reg_t reg; u32 clr_bits, wait_bits; - if (DISPLAY_VER(dev_priv) < 14) + if (DISPLAY_VER(display) < 14) return; - if (DISPLAY_VER(dev_priv) >= 20) { + if (DISPLAY_VER(display) >= 20) { reg = DDI_BUF_CTL(port); clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; } else { - reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); + reg = XELPDP_PORT_BUF_CTL1(display, port); clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; } - intel_de_rmw(dev_priv, reg, clr_bits, 0); - if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) - drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", + intel_de_rmw(display, reg, clr_bits, 0); + if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) + drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", port_name(port)); } @@ -3089,10 +3072,9 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); + intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); if (DISPLAY_VER(display) >= 14) intel_wait_ddi_buf_idle(display, port); @@ -3100,7 +3082,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder, mtl_ddi_disable_d2d(encoder); if (intel_crtc_has_dp_encoder(crtc_state)) { - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); } @@ -3118,7 +3100,6 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; intel_wakeref_t wakeref; @@ -3135,12 +3116,12 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, */ intel_dp_set_power(intel_dp, DP_SET_POWER_D3); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - intel_de_rmw(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + intel_de_rmw(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder), TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 0); } @@ -3160,7 +3141,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, * Configure Transcoder Clock select to direct no clock to the * transcoder" */ - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); intel_pps_vdd_on(intel_dp); @@ -3176,8 +3157,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_clock(encoder); /* De-select Thunderbolt */ - if (DISPLAY_VER(dev_priv) >= 14) - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), + if (DISPLAY_VER(display) >= 14) + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), XELPDP_PORT_BUF_IO_SELECT_TBT, 0); } @@ -3187,7 +3168,6 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; intel_wakeref_t wakeref; @@ -3195,12 +3175,12 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); - if (DISPLAY_VER(dev_priv) < 12) + if (DISPLAY_VER(display) < 12) intel_ddi_disable_transcoder_clock(old_crtc_state); intel_ddi_buf_disable(encoder, old_crtc_state); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); @@ -3220,7 +3200,6 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *pipe_crtc; bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); @@ -3257,7 +3236,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, intel_dsc_disable(old_pipe_crtc_state); - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_scaler_disable(old_pipe_crtc_state); else ilk_pfit_disable(old_pipe_crtc_state); @@ -3359,12 +3338,12 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; - if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) + if (port == PORT_A && DISPLAY_VER(display) < 9) intel_dp_stop_link_train(intel_dp, crtc_state); drm_connector_update_privacy_screen(conn_state); @@ -3401,7 +3380,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; @@ -3410,11 +3388,11 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, crtc_state->hdmi_scrambling)) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); - if (has_buf_trans_select(dev_priv)) + if (has_buf_trans_select(display)) hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); /* e. Enable D2D Link for C10/C20 Phy */ @@ -3423,7 +3401,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, encoder->set_signal_levels(encoder, crtc_state); /* Display WA #1143: skl,kbl,cfl */ - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { + if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { /* * For some reason these chicken bits have been * stuffed into a transcoder register, event though @@ -3433,7 +3411,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); u32 val; - val = intel_de_read(dev_priv, reg); + val = intel_de_read(display, reg); if (port == PORT_E) val |= DDIE_TRAINING_OVERRIDE_ENABLE | @@ -3442,8 +3420,8 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, val |= DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE; - intel_de_write(dev_priv, reg, val); - intel_de_posting_read(dev_priv, reg); + intel_de_write(display, reg, val); + intel_de_posting_read(display, reg); udelay(1); @@ -3454,7 +3432,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE); - intel_de_write(dev_priv, reg, val); + intel_de_write(display, reg, val); } intel_ddi_power_up_lanes(encoder, crtc_state); @@ -3475,7 +3453,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (dig_port->ddi_a_4_lanes) buf_ctl |= DDI_A_4_LANES; - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { u32 port_buf = 0; port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); @@ -3483,15 +3461,15 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, if (dig_port->lane_reversal) port_buf |= XELPDP_PORT_REVERSAL; - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); - if (DISPLAY_VER(dev_priv) >= 20) + if (DISPLAY_VER(display) >= 20) buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { - drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); + } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { + drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } @@ -3584,12 +3562,12 @@ static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = old_conn_state->connector; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, false, false)) - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", connector->base.id, connector->name); } @@ -3653,16 +3631,16 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; /* FIXME: Add MTL pll_mgr */ - if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) + if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(crtc_state)) intel_update_active_dpll(state, pipe_crtc, encoder); } @@ -3678,7 +3656,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_tc_port = intel_encoder_is_tc(encoder); @@ -3697,7 +3675,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, * Type-C ports. Skip this step for TBT. */ intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + else if (display->platform.geminilake || display->platform.broxton) bxt_dpio_phy_set_lane_optim_mask(encoder, crtc_state->lane_lat_optim_mask); } @@ -3765,10 +3743,9 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 dp_tp_ctl; - dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); @@ -3781,10 +3758,10 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, if (crtc_state->enhanced_framing) dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; } - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); + intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - if (IS_ALDERLAKE_P(dev_priv) && + if (display->platform.alderlake_p && (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) adlp_tbt_to_dp_alt_switch_wa(encoder); @@ -3796,11 +3773,11 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, u8 dp_train_pat) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 temp; - temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); + temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; switch (intel_dp_training_pattern_symbol(dp_train_pat)) { @@ -3821,17 +3798,17 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, break; } - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); + intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); } static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); /* @@ -3841,28 +3818,26 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, * In this case there is requirement to wait for a minimum number of * idle patterns to be sent. */ - if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) + if (port == PORT_A && DISPLAY_VER(display) < 12) return; - if (intel_de_wait_for_set(dev_priv, + if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), DP_TP_STATUS_IDLE_DONE, 2)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Timed out waiting for DP idle patterns\n"); } -static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, +static bool intel_ddi_is_audio_enabled(struct intel_display *display, enum transcoder cpu_transcoder) { - struct intel_display *display = &dev_priv->display; - if (cpu_transcoder == TRANSCODER_EDP) return false; if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) return false; - return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & + return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & AUDIO_OUTPUT_ENABLE(cpu_transcoder); } @@ -3892,34 +3867,34 @@ static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (display->platform.jasperlake || display->platform.elkhartlake) crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(display) >= 11) crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); } -static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, +static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, enum transcoder cpu_transcoder) { u32 master_select; - if (DISPLAY_VER(dev_priv) >= 11) { - u32 ctl2 = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); + if (DISPLAY_VER(display) >= 11) { + u32 ctl2 = intel_de_read(display, + TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) return INVALID_TRANSCODER; master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); } else { - u32 ctl = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + u32 ctl = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) return INVALID_TRANSCODER; @@ -3936,15 +3911,14 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum transcoder cpu_transcoder; crtc_state->master_transcoder = - bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); + bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { + for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { enum intel_display_power_domain power_domain; intel_wakeref_t trans_wakeref; @@ -3955,14 +3929,14 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) if (!trans_wakeref) continue; - if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == + if (bdw_transcoder_master_readout(display, cpu_transcoder) == crtc_state->cpu_transcoder) crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); intel_display_power_put(display, power_domain, trans_wakeref); } - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask); } @@ -4085,11 +4059,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; u32 ddi_func_ctl, ddi_mode, flags = 0; - ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); if (ddi_func_ctl & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; else @@ -4152,11 +4125,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, static void intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; /* XXX: DSI transcoder paranoia */ - if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) + if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) return; intel_ddi_read_func_ctl(encoder, pipe_config); @@ -4164,14 +4137,14 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_ddi_mso_get_config(encoder, pipe_config); pipe_config->has_audio = - intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); + intel_ddi_is_audio_enabled(display, cpu_transcoder); if (encoder->type == INTEL_OUTPUT_EDP) intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); ddi_dotclock_get(pipe_config); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) pipe_config->lane_lat_optim_mask = bxt_dpio_phy_get_lane_lat_optim_mask(encoder); @@ -4192,7 +4165,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, HDMI_INFOFRAME_TYPE_DRM, &pipe_config->infoframes.drm); - if (DISPLAY_VER(dev_priv) >= 8) + if (DISPLAY_VER(display) >= 8) bdw_get_trans_port_sync_config(pipe_config); intel_psr_get_config(encoder, pipe_config); @@ -4285,10 +4258,10 @@ static enum icl_port_dpll_id icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return ICL_PORT_DPLL_DEFAULT; if (icl_ddi_tc_pll_is_tbt(pll)) @@ -4382,11 +4355,11 @@ static void intel_ddi_sync_state(struct intel_encoder *encoder, static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); bool fastset = true; if (intel_encoder_is_tc(encoder)) { - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", encoder->base.base.id, encoder->base.name); crtc_state->uapi.mode_changed = true; fastset = false; @@ -4421,12 +4394,12 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; int ret; - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) + if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) pipe_config->cpu_transcoder = TRANSCODER_EDP; if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { @@ -4441,13 +4414,13 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, if (ret) return ret; - if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && + if (display->platform.haswell && crtc->pipe == PIPE_A && pipe_config->cpu_transcoder == TRANSCODER_EDP) pipe_config->pch_pfit.force_thru = pipe_config->pch_pfit.enabled || pipe_config->crc_enabled; - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); @@ -4498,9 +4471,9 @@ static u8 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, int tile_group_id) { + struct intel_display *display = to_intel_display(ref_crtc_state); struct drm_connector *connector; const struct drm_connector_state *conn_state; - struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); struct intel_atomic_state *state = to_intel_atomic_state(ref_crtc_state->uapi.state); u8 transcoders = 0; @@ -4510,7 +4483,7 @@ intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, * We don't enable port sync on BDW due to missing w/as and * due to not having adjusted the modeset sequence appropriately. */ - if (DISPLAY_VER(dev_priv) < 9) + if (DISPLAY_VER(display) < 9) return 0; if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) @@ -4542,11 +4515,11 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = conn_state->connector; u8 port_sync_transcoders = 0; - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", encoder->base.base.id, encoder->base.name, crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); @@ -4618,7 +4591,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); struct intel_connector *connector; enum port port = dig_port->base.port; @@ -4627,7 +4600,7 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return -ENOMEM; dig_port->dp.output_reg = DDI_BUF_CTL(port); - if (DISPLAY_VER(i915) >= 14) + if (DISPLAY_VER(display) >= 14) dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; else dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; @@ -4643,15 +4616,14 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) } if (dig_port->base.type == INTEL_OUTPUT_EDP) { - struct drm_device *dev = dig_port->base.base.dev; struct drm_privacy_screen *privacy_screen; - privacy_screen = drm_privacy_screen_get(dev->dev, NULL); + privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); if (!IS_ERR(privacy_screen)) { drm_connector_attach_privacy_screen_provider(&connector->base, privacy_screen); } else if (PTR_ERR(privacy_screen) != -ENODEV) { - drm_warn(dev, "Error getting privacy-screen\n"); + drm_warn(display->drm, "Error getting privacy-screen\n"); } } @@ -4662,7 +4634,6 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); struct intel_connector *connector = hdmi->attached_connector; struct i2c_adapter *ddc = connector->base.ddc; @@ -4675,7 +4646,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, if (connector->base.status != connector_status_connected) return 0; - ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, ctx); if (ret) return ret; @@ -4692,7 +4663,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); if (!crtc_state->hw.active) @@ -4708,7 +4679,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); if (ret < 0) { - drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", + drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", connector->base.base.id, connector->base.name, ret); return 0; } @@ -4733,11 +4704,11 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, static void intel_ddi_link_check(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); /* TODO: Move checking the HDMI link state here as well. */ - drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); + drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); intel_dp_link_check(encoder); } @@ -4800,26 +4771,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder, static bool lpt_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, SDEISR) & bit; + return intel_de_read(display, SDEISR) & bit; } static bool hsw_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, DEISR) & bit; + return intel_de_read(display, DEISR) & bit; } static bool bdw_digital_port_connected(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; + struct intel_display *display = to_intel_display(encoder); + u32 bit = display->hotplug.hpd[encoder->hpd_pin]; - return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; + return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; } static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) @@ -4848,7 +4819,7 @@ static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); if (dig_port->base.port != PORT_A) return false; @@ -4859,7 +4830,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only * supported configuration */ - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) return true; return false; @@ -4868,15 +4839,15 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) static int intel_ddi_max_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum port port = dig_port->base.port; int max_lanes = 4; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return max_lanes; if (port == PORT_A || port == PORT_E) { - if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) max_lanes = port == PORT_A ? 4 : 0; else /* Both A and E share 2 lanes */ @@ -4889,7 +4860,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) * so we use the proper lane count for our calculations. */ if (intel_ddi_a_force_4_lanes(dig_port)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Forcing DDI_A_4_LANES for port A\n"); dig_port->ddi_a_4_lanes = true; max_lanes = 4; @@ -4898,8 +4869,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) return max_lanes; } -static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_D_XELPD) return HPD_PORT_D + port - PORT_D_XELPD; @@ -4909,8 +4879,7 @@ static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_TC1) return HPD_PORT_C + port - PORT_TC1; @@ -4918,8 +4887,7 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_TC1) return HPD_PORT_TC1 + port - PORT_TC1; @@ -4927,11 +4895,12 @@ static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (HAS_PCH_TGP(dev_priv)) - return tgl_hpd_pin(dev_priv, port); + return tgl_hpd_pin(display, port); if (port >= PORT_TC1) return HPD_PORT_C + port - PORT_TC1; @@ -4939,8 +4908,7 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) { if (port >= PORT_C) return HPD_PORT_TC1 + port - PORT_C; @@ -4948,31 +4916,34 @@ static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, - enum port port) +static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (port == PORT_D) return HPD_PORT_A; if (HAS_PCH_TGP(dev_priv)) - return icl_hpd_pin(dev_priv, port); + return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; } -static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) +static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (HAS_PCH_TGP(dev_priv)) - return icl_hpd_pin(dev_priv, port); + return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; } -static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) +static bool intel_ddi_is_tc(struct intel_display *display, enum port port) { - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) return port >= PORT_TC1; - else if (DISPLAY_VER(i915) >= 11) + else if (DISPLAY_VER(display) >= 11) return port >= PORT_C; else return false; @@ -5015,21 +4986,21 @@ static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder #define port_tc_name(port) ((port) - PORT_TC1 + '1') #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') -static bool port_strap_detected(struct drm_i915_private *i915, enum port port) +static bool port_strap_detected(struct intel_display *display, enum port port) { /* straps not used on skl+ */ - if (DISPLAY_VER(i915) >= 9) + if (DISPLAY_VER(display) >= 9) return true; switch (port) { case PORT_A: - return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; + return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; case PORT_B: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; case PORT_C: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; case PORT_D: - return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; + return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; case PORT_E: return true; /* no strap for DDI-E */ default: @@ -5043,18 +5014,18 @@ static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) return init_dp || intel_encoder_is_tc(encoder); } -static bool assert_has_icl_dsi(struct drm_i915_private *i915) +static bool assert_has_icl_dsi(struct intel_display *display) { - return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && - !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, + return !drm_WARN(display->drm, !display->platform.alderlake_p && + !display->platform.tigerlake && DISPLAY_VER(display) != 11, "Platform does not support DSI\n"); } -static bool port_in_use(struct drm_i915_private *i915, enum port port) +static bool port_in_use(struct intel_display *display, enum port port) { struct intel_encoder *encoder; - for_each_intel_encoder(&i915->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { /* FIXME what about second port for dual link DSI? */ if (encoder->port == port) return true; @@ -5066,7 +5037,6 @@ static bool port_in_use(struct drm_i915_private *i915, enum port port) void intel_ddi_init(struct intel_display *display, const struct intel_bios_encoder_data *devdata) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp; @@ -5078,8 +5048,8 @@ void intel_ddi_init(struct intel_display *display, if (port == PORT_NONE) return; - if (!port_strap_detected(dev_priv, port)) { - drm_dbg_kms(&dev_priv->drm, + if (!port_strap_detected(display, port)) { + drm_dbg_kms(display->drm, "Port %c strap not detected\n", port_name(port)); return; } @@ -5087,15 +5057,15 @@ void intel_ddi_init(struct intel_display *display, if (!assert_port_valid(display, port)) return; - if (port_in_use(dev_priv, port)) { - drm_dbg_kms(&dev_priv->drm, + if (port_in_use(display, port)) { + drm_dbg_kms(display->drm, "Port %c already claimed\n", port_name(port)); return; } if (intel_bios_encoder_supports_dsi(devdata)) { /* BXT/GLK handled elsewhere, for now at least */ - if (!assert_has_icl_dsi(dev_priv)) + if (!assert_has_icl_dsi(display)) return; icl_dsi_init(display, devdata); @@ -5111,7 +5081,7 @@ void intel_ddi_init(struct intel_display *display, * outputs. */ if (intel_hti_uses_phy(display, phy)) { - drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", + drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", port_name(port), phy_name(phy)); return; } @@ -5128,20 +5098,20 @@ void intel_ddi_init(struct intel_display *display, */ init_dp = true; init_hdmi = false; - drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", + drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", port_name(port)); } if (!init_dp && !init_hdmi) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", port_name(port)); return; } if (intel_phy_is_snps(display, phy) && - dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { - drm_dbg_kms(&dev_priv->drm, + display->snps.phy_failed_calibration & BIT(phy)) { + drm_dbg_kms(display->drm, "SNPS PHY %c failed to calibrate, proceeding anyway\n", phy_name(phy)); } @@ -5155,26 +5125,26 @@ void intel_ddi_init(struct intel_display *display, encoder = &dig_port->base; encoder->devdata = devdata; - if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c/PHY %c", port_name(port - PORT_D_XELPD + PORT_D), phy_name(phy)); - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { enum tc_port tc_port = intel_port_to_tc(display, port); - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %s%c/PHY %s%c", port >= PORT_TC1 ? "TC" : "", port >= PORT_TC1 ? port_tc_name(port) : port_name(port), tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { enum tc_port tc_port = intel_port_to_tc(display, port); - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c%s/PHY %s%c", port_name(port), @@ -5182,7 +5152,7 @@ void intel_ddi_init(struct intel_display *display, tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); } else { - drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, + drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c/PHY %c", port_name(port), phy_name(phy)); } @@ -5218,32 +5188,32 @@ void intel_ddi_init(struct intel_display *display, encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; encoder->get_config = mtl_ddi_get_config; - } else if (IS_DG2(dev_priv)) { + } else if (display->platform.dg2) { encoder->enable_clock = intel_mpllb_enable; encoder->disable_clock = intel_mpllb_disable; encoder->get_config = dg2_ddi_get_config; - } else if (IS_ALDERLAKE_S(dev_priv)) { + } else if (display->platform.alderlake_s) { encoder->enable_clock = adls_ddi_enable_clock; encoder->disable_clock = adls_ddi_disable_clock; encoder->is_clock_enabled = adls_ddi_is_clock_enabled; encoder->get_config = adls_ddi_get_config; - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (display->platform.rocketlake) { encoder->enable_clock = rkl_ddi_enable_clock; encoder->disable_clock = rkl_ddi_disable_clock; encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; encoder->get_config = rkl_ddi_get_config; - } else if (IS_DG1(dev_priv)) { + } else if (display->platform.dg1) { encoder->enable_clock = dg1_ddi_enable_clock; encoder->disable_clock = dg1_ddi_disable_clock; encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; encoder->get_config = dg1_ddi_get_config; - } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { - if (intel_ddi_is_tc(dev_priv, port)) { + } else if (display->platform.jasperlake || display->platform.elkhartlake) { + if (intel_ddi_is_tc(display, port)) { encoder->enable_clock = jsl_ddi_tc_enable_clock; encoder->disable_clock = jsl_ddi_tc_disable_clock; encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; @@ -5255,8 +5225,8 @@ void intel_ddi_init(struct intel_display *display, encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; encoder->get_config = icl_ddi_combo_get_config; } - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (intel_ddi_is_tc(dev_priv, port)) { + } else if (DISPLAY_VER(display) >= 11) { + if (intel_ddi_is_tc(display, port)) { encoder->enable_clock = icl_ddi_tc_enable_clock; encoder->disable_clock = icl_ddi_tc_disable_clock; encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; @@ -5268,36 +5238,36 @@ void intel_ddi_init(struct intel_display *display, encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; encoder->get_config = icl_ddi_combo_get_config; } - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { /* BXT/GLK have fixed PLL->port mapping */ encoder->get_config = bxt_ddi_get_config; - } else if (DISPLAY_VER(dev_priv) == 9) { + } else if (DISPLAY_VER(display) == 9) { encoder->enable_clock = skl_ddi_enable_clock; encoder->disable_clock = skl_ddi_disable_clock; encoder->is_clock_enabled = skl_ddi_is_clock_enabled; encoder->get_config = skl_ddi_get_config; - } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + } else if (display->platform.broadwell || display->platform.haswell) { encoder->enable_clock = hsw_ddi_enable_clock; encoder->disable_clock = hsw_ddi_disable_clock; encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; encoder->get_config = hsw_ddi_get_config; } - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; - } else if (IS_DG2(dev_priv)) { + } else if (display->platform.dg2) { encoder->set_signal_levels = intel_snps_phy_set_signal_levels; - } else if (DISPLAY_VER(dev_priv) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { if (intel_encoder_is_combo(encoder)) encoder->set_signal_levels = icl_combo_phy_set_signal_levels; else encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { if (intel_encoder_is_combo(encoder)) encoder->set_signal_levels = icl_combo_phy_set_signal_levels; else encoder->set_signal_levels = icl_mg_phy_set_signal_levels; - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; } else { encoder->set_signal_levels = hsw_set_signal_levels; @@ -5305,29 +5275,29 @@ void intel_ddi_init(struct intel_display *display, intel_ddi_buf_trans_init(encoder); - if (DISPLAY_VER(dev_priv) >= 13) - encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); - else if (IS_DG1(dev_priv)) - encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); - else if (IS_ROCKETLAKE(dev_priv)) - encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) >= 12) - encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) - encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) == 11) - encoder->hpd_pin = icl_hpd_pin(dev_priv, port); - else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - encoder->hpd_pin = skl_hpd_pin(dev_priv, port); + if (DISPLAY_VER(display) >= 13) + encoder->hpd_pin = xelpd_hpd_pin(display, port); + else if (display->platform.dg1) + encoder->hpd_pin = dg1_hpd_pin(display, port); + else if (display->platform.rocketlake) + encoder->hpd_pin = rkl_hpd_pin(display, port); + else if (DISPLAY_VER(display) >= 12) + encoder->hpd_pin = tgl_hpd_pin(display, port); + else if (display->platform.jasperlake || display->platform.elkhartlake) + encoder->hpd_pin = ehl_hpd_pin(display, port); + else if (DISPLAY_VER(display) == 11) + encoder->hpd_pin = icl_hpd_pin(display, port); + else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) + encoder->hpd_pin = skl_hpd_pin(display, port); else encoder->hpd_pin = intel_hpd_pin_default(port); - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; - dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; + dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; dig_port->dp.output_reg = INVALID_MMIO_REG; dig_port->max_lanes = intel_ddi_max_lanes(dig_port); @@ -5346,7 +5316,7 @@ void intel_ddi_init(struct intel_display *display, if (!is_legacy && init_hdmi) { is_legacy = !init_dp; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", port_name(port), str_yes_no(init_dp), @@ -5363,24 +5333,24 @@ void intel_ddi_init(struct intel_display *display, goto err; } - drm_WARN_ON(&dev_priv->drm, port > PORT_I); + drm_WARN_ON(display->drm, port > PORT_I); dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { if (intel_encoder_is_tc(encoder)) dig_port->connected = intel_tc_port_connected; else dig_port->connected = lpt_digital_port_connected; - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { dig_port->connected = bdw_digital_port_connected; - } else if (DISPLAY_VER(dev_priv) == 9) { + } else if (DISPLAY_VER(display) == 9) { dig_port->connected = lpt_digital_port_connected; - } else if (IS_BROADWELL(dev_priv)) { + } else if (display->platform.broadwell) { if (port == PORT_A) dig_port->connected = bdw_digital_port_connected; else dig_port->connected = lpt_digital_port_connected; - } else if (IS_HASWELL(dev_priv)) { + } else if (display->platform.haswell) { if (port == PORT_A) dig_port->connected = hsw_digital_port_connected; else @@ -5396,7 +5366,7 @@ void intel_ddi_init(struct intel_display *display, dig_port->hpd_pulse = intel_dp_hpd_pulse; if (dig_port->dp.mso_link_count) - encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); + encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); } /* -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/6] drm/i915/crc: convert intel_pipe_crc.c to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula 2025-03-25 12:36 ` [PATCH 1/6] drm/i915/dpll: convert intel_dpll.[ch] " Jani Nikula 2025-03-25 12:36 ` [PATCH 2/6] drm/i915/ddi: convert intel_ddi.c " Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 12:36 ` [PATCH 4/6] drm/i915/psr: further conversions " Jani Nikula ` (6 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_pipe_crc.c to struct intel_display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 137 +++++++++--------- 1 file changed, 68 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 65f60615f387..6182f484b5bd 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -75,7 +75,7 @@ static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, return 0; } -static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, +static void i9xx_pipe_crc_auto_source(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source) { @@ -85,8 +85,8 @@ static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, *source = INTEL_PIPE_CRC_SOURCE_PIPE; - drm_modeset_lock_all(&dev_priv->drm); - for_each_intel_encoder(&dev_priv->drm, encoder) { + drm_modeset_lock_all(display->drm); + for_each_intel_encoder(display->drm, encoder) { if (!encoder->base.crtc) continue; @@ -113,7 +113,7 @@ static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, *source = INTEL_PIPE_CRC_SOURCE_DP_D; break; default: - drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n", + drm_WARN(display->drm, 1, "nonexisting DP port %c\n", port_name(dig_port->base.port)); break; } @@ -122,10 +122,10 @@ static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, break; } } - drm_modeset_unlock_all(&dev_priv->drm); + drm_modeset_unlock_all(display->drm); } -static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, +static int vlv_pipe_crc_ctl_reg(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source, u32 *val) @@ -133,7 +133,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, bool need_stable_symbols = false; if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) - i9xx_pipe_crc_auto_source(dev_priv, pipe, source); + i9xx_pipe_crc_auto_source(display, pipe, source); switch (*source) { case INTEL_PIPE_CRC_SOURCE_PIPE: @@ -148,7 +148,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, need_stable_symbols = true; break; case INTEL_PIPE_CRC_SOURCE_DP_D: - if (!IS_CHERRYVIEW(dev_priv)) + if (!display->platform.cherryview) return -EINVAL; *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; need_stable_symbols = true; @@ -170,7 +170,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, * - DisplayPort scrambling: used for EMI reduction */ if (need_stable_symbols) { - u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); + u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display)); tmp |= DC_BALANCE_RESET_VLV; switch (pipe) { @@ -186,26 +186,26 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, default: return -EINVAL; } - intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); + intel_de_write(display, PORT_DFT2_G4X(display), tmp); } return 0; } -static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, +static int i9xx_pipe_crc_ctl_reg(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source, u32 *val) { if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) - i9xx_pipe_crc_auto_source(dev_priv, pipe, source); + i9xx_pipe_crc_auto_source(display, pipe, source); switch (*source) { case INTEL_PIPE_CRC_SOURCE_PIPE: *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; break; case INTEL_PIPE_CRC_SOURCE_TV: - if (!SUPPORTS_TV(dev_priv)) + if (!SUPPORTS_TV(display)) return -EINVAL; *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; break; @@ -229,10 +229,10 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, return 0; } -static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, +static void vlv_undo_pipe_scramble_reset(struct intel_display *display, enum pipe pipe) { - u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); + u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display)); switch (pipe) { case PIPE_A: @@ -249,7 +249,7 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, } if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) tmp &= ~DC_BALANCE_RESET_VLV; - intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); + intel_de_write(display, PORT_DFT2_G4X(display), tmp); } static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, @@ -282,18 +282,17 @@ static void intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *pipe_config; struct drm_atomic_state *state; struct drm_modeset_acquire_ctx ctx; int ret; - if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) + if (display->platform.i945gm || display->platform.i915gm) i915gm_irq_cstate_wa(display, enable); drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(&dev_priv->drm); + state = drm_atomic_state_alloc(display->drm); if (!state) { ret = -ENOMEM; goto unlock; @@ -312,7 +311,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) pipe_config->uapi.mode_changed = pipe_config->has_psr; pipe_config->crc_enabled = enable; - if (IS_HASWELL(dev_priv) && + if (display->platform.haswell && pipe_config->hw.active && crtc->pipe == PIPE_A && pipe_config->cpu_transcoder == TRANSCODER_EDP) pipe_config->uapi.mode_changed = true; @@ -328,13 +327,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) drm_atomic_state_put(state); unlock: - drm_WARN(&dev_priv->drm, ret, + drm_WARN(display->drm, ret, "Toggling workaround to %i returns %i\n", enable, ret); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); } -static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, +static int ivb_pipe_crc_ctl_reg(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source, u32 *val) @@ -362,7 +361,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, return 0; } -static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, +static int skl_pipe_crc_ctl_reg(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source, u32 *val) @@ -405,22 +404,22 @@ static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, return 0; } -static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, +static int get_new_crc_ctl_reg(struct intel_display *display, enum pipe pipe, enum intel_pipe_crc_source *source, u32 *val) { - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) return i8xx_pipe_crc_ctl_reg(source, val); - else if (DISPLAY_VER(dev_priv) < 5) - return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) + else if (DISPLAY_VER(display) < 5) + return i9xx_pipe_crc_ctl_reg(display, pipe, source, val); + else if (display->platform.valleyview || display->platform.cherryview) + return vlv_pipe_crc_ctl_reg(display, pipe, source, val); + else if (display->platform.ironlake || display->platform.sandybridge) return ilk_pipe_crc_ctl_reg(source, val); - else if (DISPLAY_VER(dev_priv) < 9) - return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val); + else if (DISPLAY_VER(display) < 9) + return ivb_pipe_crc_ctl_reg(display, pipe, source, val); else - return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val); + return skl_pipe_crc_ctl_reg(display, pipe, source, val); } static int @@ -448,7 +447,7 @@ void intel_crtc_crc_init(struct intel_crtc *crtc) spin_lock_init(&pipe_crc->lock); } -static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv, +static int i8xx_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -460,7 +459,7 @@ static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv, } } -static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv, +static int i9xx_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -473,7 +472,7 @@ static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv, } } -static int vlv_crc_source_valid(struct drm_i915_private *dev_priv, +static int vlv_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -488,7 +487,7 @@ static int vlv_crc_source_valid(struct drm_i915_private *dev_priv, } } -static int ilk_crc_source_valid(struct drm_i915_private *dev_priv, +static int ilk_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -502,7 +501,7 @@ static int ilk_crc_source_valid(struct drm_i915_private *dev_priv, } } -static int ivb_crc_source_valid(struct drm_i915_private *dev_priv, +static int ivb_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -516,7 +515,7 @@ static int ivb_crc_source_valid(struct drm_i915_private *dev_priv, } } -static int skl_crc_source_valid(struct drm_i915_private *dev_priv, +static int skl_crc_source_valid(struct intel_display *display, const enum intel_pipe_crc_source source) { switch (source) { @@ -536,21 +535,21 @@ static int skl_crc_source_valid(struct drm_i915_private *dev_priv, } static int -intel_is_valid_crc_source(struct drm_i915_private *dev_priv, +intel_is_valid_crc_source(struct intel_display *display, const enum intel_pipe_crc_source source) { - if (DISPLAY_VER(dev_priv) == 2) - return i8xx_crc_source_valid(dev_priv, source); - else if (DISPLAY_VER(dev_priv) < 5) - return i9xx_crc_source_valid(dev_priv, source); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - return vlv_crc_source_valid(dev_priv, source); - else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) - return ilk_crc_source_valid(dev_priv, source); - else if (DISPLAY_VER(dev_priv) < 9) - return ivb_crc_source_valid(dev_priv, source); + if (DISPLAY_VER(display) == 2) + return i8xx_crc_source_valid(display, source); + else if (DISPLAY_VER(display) < 5) + return i9xx_crc_source_valid(display, source); + else if (display->platform.valleyview || display->platform.cherryview) + return vlv_crc_source_valid(display, source); + else if (display->platform.ironlake || display->platform.sandybridge) + return ilk_crc_source_valid(display, source); + else if (DISPLAY_VER(display) < 9) + return ivb_crc_source_valid(display, source); else - return skl_crc_source_valid(dev_priv, source); + return skl_crc_source_valid(display, source); } const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, @@ -563,16 +562,16 @@ const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt) { - struct drm_i915_private *dev_priv = to_i915(crtc->dev); + struct intel_display *display = to_intel_display(crtc->dev); enum intel_pipe_crc_source source; if (display_crc_ctl_parse_source(source_name, &source) < 0) { - drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); + drm_dbg_kms(display->drm, "unknown source %s\n", source_name); return -EINVAL; } if (source == INTEL_PIPE_CRC_SOURCE_AUTO || - intel_is_valid_crc_source(dev_priv, source) == 0) { + intel_is_valid_crc_source(display, source) == 0) { *values_cnt = 5; return 0; } @@ -584,7 +583,6 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) { struct intel_crtc *crtc = to_intel_crtc(_crtc); struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; @@ -595,14 +593,14 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) bool enable; if (display_crc_ctl_parse_source(source_name, &source) < 0) { - drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); + drm_dbg_kms(display->drm, "unknown source %s\n", source_name); return -EINVAL; } power_domain = POWER_DOMAIN_PIPE(pipe); wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Trying to capture CRC while pipe is off\n"); return -EIO; } @@ -611,17 +609,17 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) if (enable) intel_crtc_crc_setup_workarounds(crtc, true); - ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val); + ret = get_new_crc_ctl_reg(display, pipe, &source, &val); if (ret != 0) goto out; pipe_crc->source = source; - intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); + intel_de_write(display, PIPE_CRC_CTL(display, pipe), val); + intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); if (!source) { - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - vlv_undo_pipe_scramble_reset(dev_priv, pipe); + if (display->platform.valleyview || display->platform.cherryview) + vlv_undo_pipe_scramble_reset(display, pipe); } pipe_crc->skipped = 0; @@ -637,7 +635,7 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum pipe pipe = crtc->pipe; u32 val = 0; @@ -645,19 +643,20 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) if (!crtc->base.crc.opened) return; - if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0) + if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0) return; /* Don't need pipe_crc->lock here, IRQs are not generated. */ pipe_crc->skipped = 0; - intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); + intel_de_write(display, PIPE_CRC_CTL(display, pipe), val); + intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); } void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum pipe pipe = crtc->pipe; @@ -666,7 +665,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) pipe_crc->skipped = INT_MIN; spin_unlock_irq(&pipe_crc->lock); - intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); + intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0); + intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); intel_synchronize_irq(dev_priv); } -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/6] drm/i915/psr: further conversions to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (2 preceding siblings ...) 2025-03-25 12:36 ` [PATCH 3/6] drm/i915/crc: convert intel_pipe_crc.c " Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 12:36 ` [PATCH 5/6] drm/i915/wa: convert intel_display_wa.[ch] " Jani Nikula ` (5 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula intel_psr.c still uses the old platform identification macros. Convert them and some other stragglers to struct intel_display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 85 +++++++++--------------- 1 file changed, 30 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 708fbcfa9089..c4be3f46511f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -464,8 +464,8 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) if (DISPLAY_VER(display) >= 9) { u32 val; - val = intel_de_rmw(dev_priv, - PSR_EVENT(dev_priv, cpu_transcoder), + val = intel_de_rmw(display, + PSR_EVENT(display, cpu_transcoder), 0, 0); psr_event_print(display, val, intel_dp->psr.sel_update_enabled); @@ -690,7 +690,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) static void hsw_psr_setup_aux(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 aux_clock_divider, aux_ctl; /* write DP_SET_POWER=D0 */ @@ -705,7 +704,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) BUILD_BUG_ON(sizeof(aux_msg) > 20); for (i = 0; i < sizeof(aux_msg); i += 4) - intel_de_write(dev_priv, + intel_de_write(display, psr_aux_data_reg(display, cpu_transcoder, i >> 2), intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); @@ -840,7 +839,6 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = intel_dp->attached_connector; - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val = 0; if (DISPLAY_VER(display) >= 11) @@ -874,7 +872,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) * WA 0479: hsw,bdw * "Do not skip both TP1 and TP2/TP3" */ - if (DISPLAY_VER(dev_priv) < 9 && + if (DISPLAY_VER(display) < 9 && connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) val |= EDP_PSR_TP2_TP3_TIME_100us; @@ -910,7 +908,6 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) static void hsw_activate_psr1(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 max_sleep_time = 0x1f; u32 val = EDP_PSR_ENABLE; @@ -920,7 +917,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (DISPLAY_VER(display) < 20) val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); - if (IS_HASWELL(dev_priv)) + if (display->platform.haswell) val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; if (intel_dp->psr.link_standby) @@ -1014,14 +1011,13 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 val = EDP_PSR2_ENABLE; u32 psr_val = 0; val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); - if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv)) + if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) val |= EDP_SU_TRACK_ENABLE; if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) @@ -1039,7 +1035,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) } /* Wa_22012278275:adl-p */ - if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) { + if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) { static const u8 map[] = { 2, /* 5 lines */ 1, /* 6 lines */ @@ -1104,9 +1100,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) static bool transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) + if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; else if (DISPLAY_VER(display) >= 12) return cpu_transcoder == TRANSCODER_A; @@ -1184,10 +1178,9 @@ dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; - struct drm_i915_private *dev_priv = to_i915(display->drm); enum port port = dig_port->base.port; - if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) + if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) return pipe <= PIPE_B && port <= PORT_B; else return pipe == PIPE_A && port == PORT_A; @@ -1198,7 +1191,6 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; struct i915_power_domains *power_domains = &display->power.domains; u32 exit_scanlines; @@ -1224,7 +1216,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, return; /* Wa_16011303918:adl-p */ - if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) + if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) return; /* @@ -1265,7 +1257,6 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; @@ -1287,7 +1278,7 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, * For other platforms with SW tracking we can adjust the y coordinates * to match sink requirement if multiple of 4. */ - if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) + if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) y_granularity = intel_dp->psr.su_y_granularity; else if (intel_dp->psr.su_y_granularity <= 2) y_granularity = 4; @@ -1413,7 +1404,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; @@ -1422,20 +1412,20 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; /* JSL and EHL only supports eDP 1.3 */ - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + if (display->platform.jasperlake || display->platform.elkhartlake) { drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); return false; } /* Wa_16011181250 */ - if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || - IS_DG2(dev_priv)) { + if (display->platform.rocketlake || display->platform.alderlake_s || + display->platform.dg2) { drm_dbg_kms(display->drm, "PSR2 is defeatured for this platform\n"); return false; } - if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { + if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { drm_dbg_kms(display->drm, "PSR2 not completely functional in this stepping\n"); return false; @@ -1454,7 +1444,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, * over PSR2. */ if (crtc_state->dsc.compression_enable && - (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))) { + (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { drm_dbg_kms(display->drm, "PSR2 cannot be enabled since DSC is enabled\n"); return false; @@ -1487,7 +1477,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, /* Wa_16011303918:adl-p */ if (crtc_state->vrr.enable && - IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { + display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { drm_dbg_kms(display->drm, "PSR2 not enabled, not compatible with HW stepping + VRR\n"); return false; @@ -1828,7 +1818,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 mask = 0; @@ -1867,7 +1856,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * As a workaround leave LPSP unmasked to prevent PSR entry * when external displays are active. */ - if (DISPLAY_VER(display) >= 8 || IS_HASWELL_ULT(dev_priv)) + if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) mask |= EDP_PSR_DEBUG_MASK_LPSP; if (DISPLAY_VER(display) < 20) @@ -1881,7 +1870,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; /* allow PSR with sprite enabled */ - if (IS_HASWELL(dev_priv)) + if (display->platform.haswell) mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; } @@ -1926,7 +1915,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, */ if (!intel_dp->psr.panel_replay_enabled && (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(dev_priv))) + display->platform.alderlake_p)) intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); @@ -1937,7 +1926,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 0, MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (display->platform.alderlake_p) intel_de_rmw(display, CLKGATE_DIS_MISC, 0, CLKGATE_DIS_MISC_DMASC_GATING_DIS); } @@ -2105,7 +2094,6 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) static void intel_psr_disable_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; lockdep_assert_held(&intel_dp->psr.lock); @@ -2137,7 +2125,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_de_rmw(display, MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); - else if (IS_ALDERLAKE_P(dev_priv)) + else if (display->platform.alderlake_p) intel_de_rmw(display, CLKGATE_DIS_MISC, CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); } @@ -2315,35 +2303,27 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? 0 : + return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : PSR2_MAN_TRK_CTL_ENABLE; } static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? + return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; } static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? + return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; } static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? + return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; } @@ -2406,8 +2386,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, bool full_update) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 val = man_trk_ctl_enable_bit_get(display); /* SF partial frame enable has to be set even on full update */ @@ -2421,7 +2399,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, if (crtc_state->psr2_su_area.y1 == -1) goto exit; - if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) { + if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); } else { @@ -2475,13 +2453,12 @@ static void clip_area_update(struct drm_rect *overlap_damage_area, static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; u16 y_alignment; /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ if (crtc_state->dsc.compression_enable && - (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)) + (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) y_alignment = vdsc_cfg->slice_height; else y_alignment = crtc_state->su_y_granularity; @@ -2602,12 +2579,11 @@ static void intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); /* Wa_14014971492 */ if (!crtc_state->has_panel_replay && ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && + display->platform.alderlake_p || display->platform.tigerlake)) && crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; @@ -2808,7 +2784,6 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = @@ -2840,7 +2815,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, new_crtc_state->has_sel_update != psr->sel_update_enabled || new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || new_crtc_state->has_panel_replay != psr->panel_replay_enabled || - (DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled)) + (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) intel_psr_disable_locked(intel_dp); else if (new_crtc_state->wm_level_disabled) /* Wa_14015648006 */ -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/6] drm/i915/wa: convert intel_display_wa.[ch] to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (3 preceding siblings ...) 2025-03-25 12:36 ` [PATCH 4/6] drm/i915/psr: further conversions " Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 12:36 ` [PATCH 6/6] drm/i915/display: drop some unnecessary intel_de_* compatibility wrappers Jani Nikula ` (4 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_display_wa.[ch] to struct intel_display. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- .../drm/i915/display/intel_display_driver.c | 3 +- .../gpu/drm/i915/display/intel_display_wa.c | 30 +++++++++---------- .../gpu/drm/i915/display/intel_display_wa.h | 11 ++++--- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/xe/display/xe_display_wa.c | 6 ++-- 5 files changed, 28 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 61748525da0b..4edadebad13b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -82,7 +82,6 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev) void intel_display_driver_init_hw(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_cdclk_state *cdclk_state; if (!HAS_DISPLAY(display)) @@ -94,7 +93,7 @@ void intel_display_driver_init_hw(struct intel_display *display) intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; - intel_display_wa_apply(i915); + intel_display_wa_apply(display); } static const struct drm_mode_config_funcs intel_mode_funcs = { diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index e5a8022db664..da429c332914 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -3,38 +3,38 @@ * Copyright © 2023 Intel Corporation */ -#include "i915_drv.h" #include "i915_reg.h" #include "intel_de.h" +#include "intel_display_core.h" #include "intel_display_wa.h" -static void gen11_display_wa_apply(struct drm_i915_private *i915) +static void gen11_display_wa_apply(struct intel_display *display) { /* Wa_14010594013 */ - intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); } -static void xe_d_display_wa_apply(struct drm_i915_private *i915) +static void xe_d_display_wa_apply(struct intel_display *display) { /* Wa_14013723622 */ - intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); + intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); } -static void adlp_display_wa_apply(struct drm_i915_private *i915) +static void adlp_display_wa_apply(struct intel_display *display) { /* Wa_22011091694:adlp */ - intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); + intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); /* Bspec/49189 Initialize Sequence */ - intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); } -void intel_display_wa_apply(struct drm_i915_private *i915) +void intel_display_wa_apply(struct intel_display *display) { - if (IS_ALDERLAKE_P(i915)) - adlp_display_wa_apply(i915); - else if (DISPLAY_VER(i915) == 12) - xe_d_display_wa_apply(i915); - else if (DISPLAY_VER(i915) == 11) - gen11_display_wa_apply(i915); + if (display->platform.alderlake_p) + adlp_display_wa_apply(display); + else if (DISPLAY_VER(display) == 12) + xe_d_display_wa_apply(display); + else if (DISPLAY_VER(display) == 11) + gen11_display_wa_apply(display); } diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h index be644ab6ae00..babd9d16603d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.h +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h @@ -8,14 +8,17 @@ #include <linux/types.h> -struct drm_i915_private; +struct intel_display; -void intel_display_wa_apply(struct drm_i915_private *i915); +void intel_display_wa_apply(struct intel_display *display); #ifdef I915 -static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; } +static inline bool intel_display_needs_wa_16023588340(struct intel_display *display) +{ + return false; +} #else -bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915); +bool intel_display_needs_wa_16023588340(struct intel_display *display); #endif #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ea3123874cbf..e89cee323d8b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1437,7 +1437,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - if (intel_display_needs_wa_16023588340(i915)) { + if (intel_display_needs_wa_16023588340(display)) { plane_state->no_fbc_reason = "Wa_16023588340"; return 0; } diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c index 68e3d1959ad6..2933ca97d673 100644 --- a/drivers/gpu/drm/xe/display/xe_display_wa.c +++ b/drivers/gpu/drm/xe/display/xe_display_wa.c @@ -10,7 +10,9 @@ #include <generated/xe_wa_oob.h> -bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) +bool intel_display_needs_wa_16023588340(struct intel_display *display) { - return XE_WA(xe_root_mmio_gt(i915), 16023588340); + struct xe_device *xe = to_xe_device(display->drm); + + return XE_WA(xe_root_mmio_gt(xe), 16023588340); } -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/6] drm/i915/display: drop some unnecessary intel_de_* compatibility wrappers 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (4 preceding siblings ...) 2025-03-25 12:36 ` [PATCH 5/6] drm/i915/wa: convert intel_display_wa.[ch] " Jani Nikula @ 2025-03-25 12:36 ` Jani Nikula 2025-03-25 18:54 ` ✗ Fi.CI.SPARSE: warning for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Patchwork ` (3 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-25 12:36 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula intel_de_wait_for_set(), intel_de_wait_for_clear(), intel_de_read_fw(), and intel_de_write_fw() are only passed struct intel_display. Remove the unnecessary compatibility wrappers. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_de.h | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index b7399e9d11cc..655467a6ba87 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -181,20 +181,18 @@ intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, } static inline int -__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, - u32 mask, unsigned int timeout) +intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, + u32 mask, unsigned int timeout) { return intel_de_wait(display, reg, mask, mask, timeout); } -#define intel_de_wait_for_set(p,...) __intel_de_wait_for_set(__to_intel_display(p), __VA_ARGS__) static inline int -__intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, - u32 mask, unsigned int timeout) +intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, + u32 mask, unsigned int timeout) { return intel_de_wait(display, reg, mask, 0, timeout); } -#define intel_de_wait_for_clear(p,...) __intel_de_wait_for_clear(__to_intel_display(p), __VA_ARGS__) /* * Unlocked mmio-accessors, think carefully before using these. @@ -205,7 +203,7 @@ __intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, * a more localised lock guarding all access to that bank of registers. */ static inline u32 -__intel_de_read_fw(struct intel_display *display, i915_reg_t reg) +intel_de_read_fw(struct intel_display *display, i915_reg_t reg) { u32 val; @@ -214,15 +212,13 @@ __intel_de_read_fw(struct intel_display *display, i915_reg_t reg) return val; } -#define intel_de_read_fw(p,...) __intel_de_read_fw(__to_intel_display(p), __VA_ARGS__) static inline void -__intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) { trace_i915_reg_rw(true, reg, val, sizeof(val), true); intel_uncore_write_fw(__to_uncore(display), reg, val); } -#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__) static inline u32 intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) -- 2.39.5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (5 preceding siblings ...) 2025-03-25 12:36 ` [PATCH 6/6] drm/i915/display: drop some unnecessary intel_de_* compatibility wrappers Jani Nikula @ 2025-03-25 18:54 ` Patchwork 2025-03-25 19:16 ` ✓ i915.CI.BAT: success " Patchwork ` (2 subsequent siblings) 9 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2025-03-25 18:54 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display URL : https://patchwork.freedesktop.org/series/146730/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:243:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:243:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:243:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:245:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:245:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:245:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:137:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:137:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:137:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:139:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:139:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:139:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'break' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'break' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'break' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'continue' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'continue' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'continue' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:23: warning: unreplaced symbol '___p1' +./include/asm-generic/bitops/generic-non-atomic.h:140:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:140:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:140:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:151:1: warning: too many warnings +./include/asm-generic/bitops/instrumented-non-atomic.h:151:1: warning: too many warnings +./include/asm-generic/bitops/instrumented-non-atomic.h:151:1: warning: too many warnings +./include/asm-generic/bitops/instrumented-non-atomic.h:154:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:154:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:154:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return' /home/kbuild/linux/maintainer-tools/dim: line 2109: echo: write error: Broken pipe ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ i915.CI.BAT: success for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (6 preceding siblings ...) 2025-03-25 18:54 ` ✗ Fi.CI.SPARSE: warning for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Patchwork @ 2025-03-25 19:16 ` Patchwork 2025-03-25 21:47 ` ✗ i915.CI.Full: failure " Patchwork 2025-03-28 10:58 ` [PATCH 0/6] " Ville Syrjälä 9 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2025-03-25 19:16 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 2408 bytes --] == Series Details == Series: drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display URL : https://patchwork.freedesktop.org/series/146730/ State : success == Summary == CI Bug Log - changes from CI_DRM_16317 -> Patchwork_146730v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/index.html Participating hosts (41 -> 39) ------------------------------ Missing (2): bat-arlh-2 fi-snb-2520m Known issues ------------ Here are the changes found in Patchwork_146730v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_module_load@load: - bat-mtlp-9: [PASS][1] -> [DMESG-WARN][2] ([i915#13494]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/bat-mtlp-9/igt@i915_module_load@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/bat-mtlp-9/igt@i915_module_load@load.html * igt@i915_selftest@live: - bat-mtlp-8: [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/bat-mtlp-8/igt@i915_selftest@live.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/bat-mtlp-8/igt@i915_selftest@live.html * igt@i915_selftest@live@workarounds: - bat-mtlp-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/bat-mtlp-6/igt@i915_selftest@live@workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494 Build changes ------------- * Linux: CI_DRM_16317 -> Patchwork_146730v1 CI-20190529: 20190529 CI_DRM_16317: 8de9ba4a4539f21e6809b9fb42c04cb3be9c1e76 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8283: e4eb2265f06fc69e37e56cb6b609e019b6071435 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_146730v1: 8de9ba4a4539f21e6809b9fb42c04cb3be9c1e76 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/index.html [-- Attachment #2: Type: text/html, Size: 3136 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ i915.CI.Full: failure for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (7 preceding siblings ...) 2025-03-25 19:16 ` ✓ i915.CI.BAT: success " Patchwork @ 2025-03-25 21:47 ` Patchwork 2025-03-28 10:58 ` [PATCH 0/6] " Ville Syrjälä 9 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2025-03-25 21:47 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 97124 bytes --] == Series Details == Series: drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display URL : https://patchwork.freedesktop.org/series/146730/ State : failure == Summary == CI Bug Log - changes from CI_DRM_16317_full -> Patchwork_146730v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_146730v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_146730v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_146730v1_full: ### IGT changes ### #### Possible regressions #### * igt@i915_pm_rpm@system-suspend: - shard-rkl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-7/igt@i915_pm_rpm@system-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-3/igt@i915_pm_rpm@system-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-rkl: [PASS][3] -> [FAIL][4] +2 other tests fail [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@plain-flip-ts-check: - shard-tglu: [PASS][5] -> [FAIL][6] +1 other test fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-tglu-4/igt@kms_flip@plain-flip-ts-check.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-2/igt@kms_flip@plain-flip-ts-check.html * igt@kms_flip@wf_vblank-ts-check@a-edp1: - shard-mtlp: [PASS][7] -> [FAIL][8] +2 other tests fail [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check@a-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-6/igt@kms_flip@wf_vblank-ts-check@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render: - shard-snb: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-snb2/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-snb1/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html Known issues ------------ Here are the changes found in Patchwork_146730v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8411]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@api_intel_bb@blit-reloc-keep-cache.html * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2-9: NOTRUN -> [SKIP][12] ([i915#8411]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@api_intel_bb@blit-reloc-purge-cache.html * igt@device_reset@cold-reset-bound: - shard-tglu: NOTRUN -> [SKIP][13] ([i915#11078]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@device_reset@cold-reset-bound.html * igt@drm_fdinfo@busy-check-all@ccs0: - shard-dg2-9: NOTRUN -> [SKIP][14] ([i915#11527] / [i915#8414]) +7 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@drm_fdinfo@busy-check-all@ccs0.html * igt@drm_fdinfo@isolation: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#8414]) +7 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@drm_fdinfo@isolation.html * igt@drm_fdinfo@most-busy-check-all@vecs0: - shard-dg2-9: NOTRUN -> [SKIP][16] ([i915#8414]) +7 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@drm_fdinfo@most-busy-check-all@vecs0.html * igt@gem_basic@multigpu-create-close: - shard-dg2-9: NOTRUN -> [SKIP][17] ([i915#7697]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_basic@multigpu-create-close.html * igt@gem_busy@semaphore: - shard-dg2-9: NOTRUN -> [SKIP][18] ([i915#3936]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_busy@semaphore.html * igt@gem_ccs@ctrl-surf-copy: - shard-rkl: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy.html * igt@gem_ccs@large-ctrl-surf-copy: - shard-tglu: NOTRUN -> [SKIP][20] ([i915#13008]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_ccs@large-ctrl-surf-copy.html * igt@gem_close_race@multigpu-basic-process: - shard-rkl: NOTRUN -> [SKIP][21] ([i915#7697]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: NOTRUN -> [ABORT][22] ([i915#13427]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-tglu: NOTRUN -> [SKIP][23] ([i915#6335]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_create@create-ext-cpu-access-sanity-check.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][24] ([i915#8562]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gem_create@create-ext-set-pat.html * igt@gem_ctx_persistence@heartbeat-hostile: - shard-dg2: NOTRUN -> [SKIP][25] ([i915#8555]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@gem_ctx_persistence@heartbeat-hostile.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg2-9: NOTRUN -> [SKIP][26] ([i915#8555]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_ctx_persistence@heartbeat-many.html * igt@gem_ctx_sseu@invalid-sseu: - shard-tglu: NOTRUN -> [SKIP][27] ([i915#280]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_ctx_sseu@invalid-sseu.html * igt@gem_eio@wait-1us: - shard-mtlp: [PASS][28] -> [ABORT][29] ([i915#13193]) +1 other test abort [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-8/igt@gem_eio@wait-1us.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-7/igt@gem_eio@wait-1us.html * igt@gem_exec_balancer@bonded-semaphore: - shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_balancer@bonded-semaphore.html * igt@gem_exec_balancer@bonded-sync: - shard-dg2-9: NOTRUN -> [SKIP][31] ([i915#4771]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_exec_balancer@bonded-sync.html * igt@gem_exec_balancer@parallel: - shard-tglu: NOTRUN -> [SKIP][32] ([i915#4525]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_exec_balancer@parallel.html * igt@gem_exec_balancer@parallel-ordering: - shard-rkl: NOTRUN -> [SKIP][33] ([i915#4525]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_exec_balancer@parallel-ordering.html * igt@gem_exec_capture@capture-invisible@smem0: - shard-tglu: NOTRUN -> [SKIP][34] ([i915#6334]) +1 other test skip [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@gem_exec_capture@capture-invisible@smem0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852]) +1 other test skip [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_flush@basic-uc-set-default: - shard-dg2-9: NOTRUN -> [SKIP][36] ([i915#3539]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_exec_flush@basic-uc-set-default.html * igt@gem_exec_params@rsvd2-dirt: - shard-dg2: NOTRUN -> [SKIP][37] ([i915#5107]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_params@rsvd2-dirt.html * igt@gem_exec_reloc@basic-gtt-read-active: - shard-dg2-9: NOTRUN -> [SKIP][38] ([i915#3281]) +3 other tests skip [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_exec_reloc@basic-gtt-read-active.html * igt@gem_exec_reloc@basic-softpin: - shard-rkl: NOTRUN -> [SKIP][39] ([i915#3281]) +4 other tests skip [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_exec_reloc@basic-softpin.html * igt@gem_exec_reloc@basic-write-read-active: - shard-dg2: NOTRUN -> [SKIP][40] ([i915#3281]) +7 other tests skip [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@gem_exec_reloc@basic-write-read-active.html * igt@gem_exec_schedule@preempt-queue-contexts: - shard-dg2-9: NOTRUN -> [SKIP][41] ([i915#4537] / [i915#4812]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts.html * igt@gem_exec_schedule@reorder-wide: - shard-dg2: NOTRUN -> [SKIP][42] ([i915#4537] / [i915#4812]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_schedule@reorder-wide.html * igt@gem_exec_suspend@basic-s0: - shard-rkl: [PASS][43] -> [INCOMPLETE][44] ([i915#13304]) +1 other test incomplete [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-7/igt@gem_exec_suspend@basic-s0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-3/igt@gem_exec_suspend@basic-s0.html * igt@gem_exec_suspend@basic-s4-devices: - shard-rkl: [PASS][45] -> [ABORT][46] ([i915#7975] / [i915#8213]) +1 other test abort [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-8/igt@gem_exec_suspend@basic-s4-devices.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@gem_exec_suspend@basic-s4-devices.html * igt@gem_fence_thrash@bo-write-verify-threaded-none: - shard-dg2-9: NOTRUN -> [SKIP][47] ([i915#4860]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_fence_thrash@bo-write-verify-threaded-none.html * igt@gem_fenced_exec_thrash@no-spare-fences: - shard-dg2: NOTRUN -> [SKIP][48] ([i915#4860]) +1 other test skip [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_fenced_exec_thrash@no-spare-fences.html * igt@gem_lmem_evict@dontneed-evict-race: - shard-rkl: NOTRUN -> [SKIP][49] ([i915#4613] / [i915#7582]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_lmem_evict@dontneed-evict-race.html * igt@gem_lmem_swapping@heavy-multi: - shard-tglu-1: NOTRUN -> [SKIP][50] ([i915#4613]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@gem_lmem_swapping@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-tglu: NOTRUN -> [SKIP][51] ([i915#4613]) +2 other tests skip [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_lmem_swapping@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@smem-oom: - shard-dg2-9: NOTRUN -> [TIMEOUT][52] ([i915#5493]) +1 other test timeout [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_lmem_swapping@smem-oom.html * igt@gem_lmem_swapping@verify-random-ccs: - shard-rkl: NOTRUN -> [SKIP][53] ([i915#4613]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_lmem_swapping@verify-random-ccs.html * igt@gem_media_fill@media-fill: - shard-dg2: NOTRUN -> [SKIP][54] ([i915#8289]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gem_media_fill@media-fill.html * igt@gem_mmap_gtt@basic-small-bo-tiledy: - shard-dg2-9: NOTRUN -> [SKIP][55] ([i915#4077]) +3 other tests skip [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_mmap_gtt@basic-small-bo-tiledy.html * igt@gem_mmap_gtt@zero-extend: - shard-dg2: NOTRUN -> [SKIP][56] ([i915#4077]) +5 other tests skip [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@gem_mmap_gtt@zero-extend.html * igt@gem_mmap_wc@copy: - shard-dg2: NOTRUN -> [SKIP][57] ([i915#4083]) +4 other tests skip [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@gem_mmap_wc@copy.html * igt@gem_mmap_wc@write: - shard-dg2-9: NOTRUN -> [SKIP][58] ([i915#4083]) +4 other tests skip [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_mmap_wc@write.html * igt@gem_partial_pwrite_pread@reads: - shard-dg2: NOTRUN -> [SKIP][59] ([i915#3282]) +2 other tests skip [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@gem_partial_pwrite_pread@reads.html * igt@gem_partial_pwrite_pread@write-snoop: - shard-rkl: NOTRUN -> [SKIP][60] ([i915#3282]) +3 other tests skip [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@gem_partial_pwrite_pread@write-snoop.html * igt@gem_pread@uncached: - shard-dg2-9: NOTRUN -> [SKIP][61] ([i915#3282]) +4 other tests skip [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_pread@uncached.html * igt@gem_pxp@display-protected-crc: - shard-dg2: NOTRUN -> [SKIP][62] ([i915#4270]) +2 other tests skip [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_pxp@display-protected-crc.html * igt@gem_pxp@fail-invalid-protected-context: - shard-dg2-9: NOTRUN -> [SKIP][63] ([i915#4270]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_pxp@fail-invalid-protected-context.html * igt@gem_pxp@hw-rejects-pxp-context: - shard-rkl: NOTRUN -> [TIMEOUT][64] ([i915#12917] / [i915#12964]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_pxp@hw-rejects-pxp-context.html * igt@gem_pxp@reject-modify-context-protection-off-1: - shard-rkl: [PASS][65] -> [TIMEOUT][66] ([i915#12917] / [i915#12964]) +2 other tests timeout [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@gem_pxp@reject-modify-context-protection-off-1.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-rkl: NOTRUN -> [SKIP][67] ([i915#4270]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs: - shard-dg2-9: NOTRUN -> [SKIP][68] ([i915#5190] / [i915#8428]) +1 other test skip [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-dg2: NOTRUN -> [SKIP][69] ([i915#5190] / [i915#8428]) +8 other tests skip [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_render_tiled_blits@basic: - shard-dg2: NOTRUN -> [SKIP][70] ([i915#4079]) +2 other tests skip [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gem_render_tiled_blits@basic.html * igt@gem_set_tiling_vs_blt@tiled-to-untiled: - shard-rkl: NOTRUN -> [SKIP][71] ([i915#8411]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html * igt@gem_softpin@evict-snoop: - shard-dg2: NOTRUN -> [SKIP][72] ([i915#4885]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gem_softpin@evict-snoop.html * igt@gem_userptr_blits@coherency-unsync: - shard-tglu: NOTRUN -> [SKIP][73] ([i915#3297]) +1 other test skip [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-dg2: NOTRUN -> [SKIP][74] ([i915#3297]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gem_userptr_blits@dmabuf-sync: - shard-rkl: NOTRUN -> [SKIP][75] ([i915#3297] / [i915#3323]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_userptr_blits@dmabuf-sync.html - shard-tglu-1: NOTRUN -> [SKIP][76] ([i915#3297] / [i915#3323]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-rkl: NOTRUN -> [SKIP][77] ([i915#3297]) +1 other test skip [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-dg2-9: NOTRUN -> [SKIP][78] ([i915#3297] / [i915#4880]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@readonly-unsync: - shard-dg2-9: NOTRUN -> [SKIP][79] ([i915#3297]) +2 other tests skip [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gem_userptr_blits@readonly-unsync.html * igt@gem_userptr_blits@relocations: - shard-rkl: NOTRUN -> [SKIP][80] ([i915#3281] / [i915#3297]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gem_userptr_blits@relocations.html * igt@gen9_exec_parse@allowed-single: - shard-tglu-1: NOTRUN -> [SKIP][81] ([i915#2527] / [i915#2856]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@basic-rejected: - shard-tglu: NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856]) +1 other test skip [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@gen9_exec_parse@basic-rejected.html * igt@gen9_exec_parse@batch-invalid-length: - shard-dg2: NOTRUN -> [SKIP][83] ([i915#2856]) +2 other tests skip [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@gen9_exec_parse@batch-invalid-length.html * igt@gen9_exec_parse@bb-start-far: - shard-dg2-9: NOTRUN -> [SKIP][84] ([i915#2856]) +1 other test skip [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@gen9_exec_parse@bb-start-far.html * igt@gen9_exec_parse@bb-start-param: - shard-rkl: NOTRUN -> [SKIP][85] ([i915#2527]) +1 other test skip [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@gen9_exec_parse@bb-start-param.html * igt@i915_hangman@hangcheck-unterminated: - shard-rkl: NOTRUN -> [DMESG-WARN][86] ([i915#12964]) +8 other tests dmesg-warn [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@i915_hangman@hangcheck-unterminated.html * igt@i915_pm_freq_api@freq-basic-api: - shard-tglu: NOTRUN -> [SKIP][87] ([i915#8399]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@i915_pm_freq_api@freq-basic-api.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-tglu: NOTRUN -> [WARN][88] ([i915#13790] / [i915#2681]) +4 other tests warn [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle.html * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0: - shard-dg1: [PASS][89] -> [FAIL][90] ([i915#3591]) +1 other test fail [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html * igt@i915_pm_rpm@system-suspend: - shard-glk: NOTRUN -> [INCOMPLETE][91] ([i915#12797]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk1/igt@i915_pm_rpm@system-suspend.html * igt@i915_pm_rps@thresholds: - shard-dg2: NOTRUN -> [SKIP][92] ([i915#11681]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@i915_pm_rps@thresholds.html * igt@i915_query@hwconfig_table: - shard-rkl: NOTRUN -> [SKIP][93] ([i915#6245]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@i915_query@hwconfig_table.html * igt@i915_suspend@basic-s3-without-i915: - shard-tglu-1: NOTRUN -> [INCOMPLETE][94] ([i915#4817] / [i915#7443]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_addfb_basic@invalid-smem-bo-on-discrete: - shard-tglu-1: NOTRUN -> [SKIP][95] ([i915#12454] / [i915#12712]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-1-4-mc-ccs: - shard-dg2: NOTRUN -> [SKIP][96] ([i915#8709]) +7 other tests skip [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-1-4-mc-ccs.html * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-y-rc-ccs-cc: - shard-rkl: NOTRUN -> [SKIP][97] ([i915#8709]) +2 other tests skip [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-c-hdmi-a-2-y-rc-ccs-cc.html * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-y-rc-ccs-cc: - shard-dg1: NOTRUN -> [SKIP][98] ([i915#8709]) +3 other tests skip [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-y-rc-ccs-cc.html * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs: - shard-rkl: [PASS][99] -> [DMESG-WARN][100] ([i915#12964]) +11 other tests dmesg-warn [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-dg2: [PASS][101] -> [FAIL][102] ([i915#5956]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html - shard-tglu: NOTRUN -> [FAIL][103] ([i915#11808]) +1 other test fail [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1: - shard-dg2: NOTRUN -> [FAIL][104] ([i915#5956]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1: - shard-mtlp: [PASS][105] -> [FAIL][106] ([i915#11808] / [i915#5956]) +1 other test fail [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html * igt@kms_big_fb@4-tiled-32bpp-rotate-270: - shard-rkl: NOTRUN -> [SKIP][107] ([i915#5286]) +2 other tests skip [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html * igt@kms_big_fb@4-tiled-64bpp-rotate-0: - shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#5286]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow: - shard-tglu: NOTRUN -> [SKIP][109] ([i915#5286]) +4 other tests skip [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0: - shard-mtlp: [PASS][110] -> [FAIL][111] ([i915#5138]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][112] ([i915#3638]) +4 other tests skip [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_big_fb@linear-64bpp-rotate-90.html * igt@kms_big_fb@y-tiled-32bpp-rotate-270: - shard-dg2-9: NOTRUN -> [SKIP][113] ([i915#4538] / [i915#5190]) +3 other tests skip [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html * igt@kms_big_fb@y-tiled-8bpp-rotate-180: - shard-dg2: NOTRUN -> [SKIP][114] ([i915#4538] / [i915#5190]) +9 other tests skip [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-dg1: [PASS][115] -> [DMESG-WARN][116] ([i915#4423]) +1 other test dmesg-warn [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-13/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-16/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-tglu-1: NOTRUN -> [SKIP][117] +21 other tests skip [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-glk: NOTRUN -> [SKIP][118] +7 other tests skip [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1: - shard-tglu-1: NOTRUN -> [SKIP][119] ([i915#6095]) +19 other tests skip [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs: - shard-tglu: NOTRUN -> [SKIP][120] ([i915#12313]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs: - shard-dg2: NOTRUN -> [SKIP][121] ([i915#12313]) +1 other test skip [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs: - shard-tglu-1: NOTRUN -> [SKIP][122] ([i915#12313]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][123] ([i915#10307] / [i915#6095]) +182 other tests skip [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3: - shard-dg1: NOTRUN -> [SKIP][124] ([i915#6095]) +139 other tests skip [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-d-hdmi-a-3.html * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs: - shard-tglu: NOTRUN -> [SKIP][125] ([i915#12805]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][126] ([i915#6095]) +8 other tests skip [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][127] ([i915#6095]) +54 other tests skip [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-b-hdmi-a-2: - shard-dg2-9: NOTRUN -> [SKIP][128] ([i915#10307] / [i915#6095]) +29 other tests skip [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-b-hdmi-a-2.html * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1: - shard-dg2: NOTRUN -> [SKIP][129] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs: - shard-rkl: NOTRUN -> [SKIP][130] ([i915#12313]) +1 other test skip [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][131] ([i915#6095]) +71 other tests skip [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html * igt@kms_cdclk@mode-transition: - shard-rkl: NOTRUN -> [SKIP][132] ([i915#3742]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_cdclk@mode-transition.html * igt@kms_cdclk@mode-transition@pipe-d-dp-4: - shard-dg2: NOTRUN -> [SKIP][133] ([i915#13781]) +3 other tests skip [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][134] ([i915#13783]) +3 other tests skip [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html * igt@kms_chamelium_color@ctm-0-25: - shard-dg2-9: NOTRUN -> [SKIP][135] +4 other tests skip [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_chamelium_color@ctm-0-25.html * igt@kms_chamelium_edid@dp-edid-change-during-suspend: - shard-rkl: NOTRUN -> [SKIP][136] ([i915#11151] / [i915#7828]) +5 other tests skip [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html * igt@kms_chamelium_frames@dp-crc-multiple: - shard-dg2-9: NOTRUN -> [SKIP][137] ([i915#11151] / [i915#7828]) +4 other tests skip [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_chamelium_frames@dp-crc-multiple.html * igt@kms_chamelium_frames@dp-crc-single: - shard-tglu-1: NOTRUN -> [SKIP][138] ([i915#11151] / [i915#7828]) +1 other test skip [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html * igt@kms_chamelium_frames@hdmi-crc-single: - shard-dg2: NOTRUN -> [SKIP][139] ([i915#11151] / [i915#7828]) +9 other tests skip [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_chamelium_frames@hdmi-crc-single.html * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe: - shard-tglu: NOTRUN -> [SKIP][140] ([i915#11151] / [i915#7828]) +5 other tests skip [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html * igt@kms_content_protection@atomic: - shard-dg2: NOTRUN -> [SKIP][141] ([i915#7118] / [i915#9424]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_content_protection@atomic.html * igt@kms_content_protection@atomic-dpms@pipe-a-dp-3: - shard-dg2: NOTRUN -> [FAIL][142] ([i915#7173]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-3.html * igt@kms_content_protection@dp-mst-lic-type-1: - shard-tglu: NOTRUN -> [SKIP][143] ([i915#3116] / [i915#3299]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_content_protection@dp-mst-lic-type-1.html * igt@kms_content_protection@dp-mst-type-0: - shard-dg2-9: NOTRUN -> [SKIP][144] ([i915#3299]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_content_protection@dp-mst-type-0.html * igt@kms_content_protection@dp-mst-type-1: - shard-dg2: NOTRUN -> [SKIP][145] ([i915#3299]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@srm: - shard-tglu-1: NOTRUN -> [SKIP][146] ([i915#6944] / [i915#7116] / [i915#7118]) [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_content_protection@srm.html * igt@kms_content_protection@type1: - shard-tglu: NOTRUN -> [SKIP][147] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_content_protection@type1.html * igt@kms_cursor_crc@cursor-offscreen-512x512: - shard-tglu: NOTRUN -> [SKIP][148] ([i915#13049]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html * igt@kms_cursor_crc@cursor-onscreen-256x85: - shard-tglu: [PASS][149] -> [FAIL][150] ([i915#13566]) +1 other test fail [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-256x85.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-dg2: NOTRUN -> [SKIP][151] ([i915#13049]) +1 other test skip [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-rkl: NOTRUN -> [SKIP][152] ([i915#13049]) +1 other test skip [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1: - shard-tglu: NOTRUN -> [FAIL][153] ([i915#13566]) +1 other test fail [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html * igt@kms_cursor_crc@cursor-rapid-movement-32x32: - shard-rkl: NOTRUN -> [SKIP][154] ([i915#3555]) +1 other test skip [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html * igt@kms_cursor_crc@cursor-sliding-32x10: - shard-dg2: NOTRUN -> [SKIP][155] ([i915#3555]) +3 other tests skip [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_cursor_crc@cursor-sliding-32x10.html * igt@kms_cursor_crc@cursor-sliding-512x170: - shard-dg2-9: NOTRUN -> [SKIP][156] ([i915#13049]) [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_cursor_crc@cursor-sliding-512x170.html * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2: - shard-rkl: NOTRUN -> [FAIL][157] ([i915#13566]) +2 other tests fail [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-1/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-dg2-9: NOTRUN -> [SKIP][158] ([i915#13046] / [i915#5354]) +1 other test skip [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size: - shard-dg2-9: NOTRUN -> [SKIP][159] ([i915#4103] / [i915#4213]) +1 other test skip [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size: - shard-dg2: NOTRUN -> [SKIP][160] ([i915#13046] / [i915#5354]) +1 other test skip [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy: - shard-rkl: NOTRUN -> [SKIP][161] +15 other tests skip [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-rkl: [PASS][162] -> [FAIL][163] ([i915#2346]) [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot: - shard-tglu: NOTRUN -> [SKIP][164] ([i915#9067]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size: - shard-rkl: NOTRUN -> [SKIP][165] ([i915#4103]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html * igt@kms_display_modes@extended-mode-basic: - shard-tglu-1: NOTRUN -> [SKIP][166] ([i915#13691]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_display_modes@extended-mode-basic.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc: - shard-rkl: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3804]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][168] ([i915#3804]) [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html * igt@kms_dp_aux_dev: - shard-dg2: [PASS][169] -> [SKIP][170] ([i915#1257]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-11/igt@kms_dp_aux_dev.html [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-5/igt@kms_dp_aux_dev.html * igt@kms_dp_link_training@non-uhbr-mst: - shard-tglu: NOTRUN -> [SKIP][171] ([i915#13749]) [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_dp_link_training@non-uhbr-mst.html * igt@kms_dp_link_training@uhbr-mst: - shard-dg2-9: NOTRUN -> [SKIP][172] ([i915#13748]) [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_dp_link_training@uhbr-mst.html * igt@kms_dp_linktrain_fallback@dp-fallback: - shard-dg2: [PASS][173] -> [SKIP][174] ([i915#13707]) [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-11/igt@kms_dp_linktrain_fallback@dp-fallback.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_dp_linktrain_fallback@dp-fallback.html * igt@kms_dsc@dsc-basic: - shard-dg2: NOTRUN -> [SKIP][175] ([i915#3555] / [i915#3840]) +1 other test skip [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_dsc@dsc-basic.html * igt@kms_dsc@dsc-with-bpc-formats: - shard-rkl: NOTRUN -> [SKIP][176] ([i915#3555] / [i915#3840]) [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_dsc@dsc-with-bpc-formats.html * igt@kms_dsc@dsc-with-formats: - shard-tglu: NOTRUN -> [SKIP][177] ([i915#3555] / [i915#3840]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_dsc@dsc-with-formats.html * igt@kms_dsc@dsc-with-output-formats-with-bpc: - shard-rkl: NOTRUN -> [SKIP][178] ([i915#3840] / [i915#9053]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_dsc@dsc-with-output-formats-with-bpc.html * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests: - shard-tglu-1: NOTRUN -> [SKIP][179] ([i915#2575]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html * igt@kms_fbcon_fbt@psr: - shard-tglu-1: NOTRUN -> [SKIP][180] ([i915#3469]) [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_fbcon_fbt@psr.html * igt@kms_fbcon_fbt@psr-suspend: - shard-rkl: NOTRUN -> [SKIP][181] ([i915#3955]) [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_feature_discovery@display-2x: - shard-rkl: NOTRUN -> [SKIP][182] ([i915#1839]) [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_feature_discovery@display-2x.html * igt@kms_feature_discovery@display-3x: - shard-dg2: NOTRUN -> [SKIP][183] ([i915#1839]) [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_feature_discovery@display-3x.html * igt@kms_feature_discovery@dp-mst: - shard-dg2: NOTRUN -> [SKIP][184] ([i915#9337]) [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_feature_discovery@dp-mst.html * igt@kms_feature_discovery@psr2: - shard-tglu: NOTRUN -> [SKIP][185] ([i915#658]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_feature_discovery@psr2.html * igt@kms_flip@2x-absolute-wf_vblank-interruptible: - shard-tglu-1: NOTRUN -> [SKIP][186] ([i915#3637]) +2 other tests skip [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset: - shard-dg2-9: NOTRUN -> [SKIP][187] ([i915#9934]) +1 other test skip [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html * igt@kms_flip@2x-flip-vs-fences-interruptible: - shard-dg2: NOTRUN -> [SKIP][188] ([i915#8381]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_flip@2x-flip-vs-fences-interruptible.html * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-dg2: NOTRUN -> [SKIP][189] ([i915#9934]) +3 other tests skip [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_flip@2x-modeset-vs-vblank-race.html * igt@kms_flip@2x-plain-flip-interruptible: - shard-rkl: NOTRUN -> [SKIP][190] ([i915#9934]) +3 other tests skip [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_flip@2x-plain-flip-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check: - shard-tglu: NOTRUN -> [SKIP][191] ([i915#3637]) +6 other tests skip [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_flip@2x-wf_vblank-ts-check.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2: - shard-glk: [PASS][192] -> [FAIL][193] ([i915#13027]) +1 other test fail [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling: - shard-dg2: NOTRUN -> [SKIP][194] ([i915#2672] / [i915#3555]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling: - shard-rkl: NOTRUN -> [SKIP][195] ([i915#2672] / [i915#3555]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][196] ([i915#2672]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling: - shard-tglu-1: NOTRUN -> [SKIP][197] ([i915#2672] / [i915#3555]) [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode: - shard-tglu-1: NOTRUN -> [SKIP][198] ([i915#2587] / [i915#2672]) [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling: - shard-tglu: NOTRUN -> [SKIP][199] ([i915#2672] / [i915#3555]) +1 other test skip [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode: - shard-tglu: NOTRUN -> [SKIP][200] ([i915#2587] / [i915#2672]) +1 other test skip [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling: - shard-dg2: NOTRUN -> [SKIP][201] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode: - shard-dg2: NOTRUN -> [SKIP][202] ([i915#2672]) +2 other tests skip [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite: - shard-dg2: [PASS][203] -> [FAIL][204] ([i915#6880]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc: - shard-snb: [PASS][205] -> [SKIP][206] +4 other tests skip [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbc-tiling-4: - shard-tglu: NOTRUN -> [SKIP][207] ([i915#5439]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt: - shard-dg2-9: NOTRUN -> [SKIP][208] ([i915#5354]) +11 other tests skip [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render: - shard-dg2: NOTRUN -> [SKIP][209] ([i915#5354]) +20 other tests skip [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y: - shard-dg2: NOTRUN -> [SKIP][210] ([i915#10055]) [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move: - shard-dg2: NOTRUN -> [SKIP][211] ([i915#3458]) +11 other tests skip [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt: - shard-dg2-9: NOTRUN -> [SKIP][212] ([i915#3458]) +11 other tests skip [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt: - shard-rkl: NOTRUN -> [SKIP][213] ([i915#3023]) +16 other tests skip [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-dg2: NOTRUN -> [SKIP][214] ([i915#8708]) +19 other tests skip [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-dg2-9: NOTRUN -> [SKIP][215] ([i915#8708]) +4 other tests skip [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt: - shard-rkl: NOTRUN -> [SKIP][216] ([i915#1825]) +21 other tests skip [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc: - shard-tglu: NOTRUN -> [SKIP][217] +57 other tests skip [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_hdr@invalid-metadata-sizes: - shard-tglu: NOTRUN -> [SKIP][218] ([i915#3555] / [i915#8228]) +1 other test skip [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_hdr@invalid-metadata-sizes.html * igt@kms_hdr@static-swap: - shard-dg2: [PASS][219] -> [SKIP][220] ([i915#3555] / [i915#8228]) +1 other test skip [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-10/igt@kms_hdr@static-swap.html [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_hdr@static-swap.html * igt@kms_hdr@static-toggle-dpms: - shard-dg2-9: NOTRUN -> [SKIP][221] ([i915#3555] / [i915#8228]) [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_hdr@static-toggle-dpms.html * igt@kms_joiner@basic-force-big-joiner: - shard-dg2: NOTRUN -> [SKIP][222] ([i915#12388]) [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_joiner@basic-force-big-joiner.html * igt@kms_joiner@basic-force-ultra-joiner: - shard-rkl: NOTRUN -> [SKIP][223] ([i915#12394]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_joiner@basic-force-ultra-joiner.html * igt@kms_joiner@basic-ultra-joiner: - shard-dg2-9: NOTRUN -> [SKIP][224] ([i915#12339]) [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_joiner@basic-ultra-joiner.html * igt@kms_joiner@invalid-modeset-force-big-joiner: - shard-dg2: [PASS][225] -> [SKIP][226] ([i915#12388]) [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html * igt@kms_joiner@invalid-modeset-ultra-joiner: - shard-dg2: NOTRUN -> [SKIP][227] ([i915#12339]) [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_joiner@invalid-modeset-ultra-joiner.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-dg2: NOTRUN -> [SKIP][228] ([i915#4816]) [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_panel_fitting@legacy: - shard-dg2-9: NOTRUN -> [SKIP][229] ([i915#6301]) [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_panel_fitting@legacy.html * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes: - shard-dg2: NOTRUN -> [SKIP][230] +10 other tests skip [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html * igt@kms_plane_cursor@viewport@pipe-a-hdmi-a-2-size-128: - shard-rkl: [PASS][231] -> [DMESG-WARN][232] ([i915#12917] / [i915#12964]) +1 other test dmesg-warn [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-8/igt@kms_plane_cursor@viewport@pipe-a-hdmi-a-2-size-128.html [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@kms_plane_cursor@viewport@pipe-a-hdmi-a-2-size-128.html * igt@kms_plane_lowres@tiling-yf: - shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#3555]) +2 other tests skip [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_plane_lowres@tiling-yf.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b: - shard-tglu: NOTRUN -> [SKIP][234] ([i915#12247]) +3 other tests skip [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html * igt@kms_plane_scaling@planes-downscale-factor-0-25: - shard-tglu-1: NOTRUN -> [SKIP][235] ([i915#12247] / [i915#6953]) [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b: - shard-tglu-1: NOTRUN -> [SKIP][236] ([i915#12247]) +3 other tests skip [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25: - shard-rkl: NOTRUN -> [SKIP][237] ([i915#12247] / [i915#3555]) [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a: - shard-rkl: NOTRUN -> [SKIP][238] ([i915#12247]) +1 other test skip [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25: - shard-dg2: NOTRUN -> [SKIP][239] ([i915#12247] / [i915#6953] / [i915#9423]) [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d: - shard-dg2: NOTRUN -> [SKIP][240] ([i915#12247]) +3 other tests skip [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d.html * igt@kms_pm_backlight@bad-brightness: - shard-tglu: NOTRUN -> [SKIP][241] ([i915#9812]) [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_pm_backlight@bad-brightness.html * igt@kms_pm_backlight@brightness-with-dpms: - shard-tglu-1: NOTRUN -> [SKIP][242] ([i915#12343]) [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_pm_backlight@brightness-with-dpms.html * igt@kms_pm_backlight@fade-with-suspend: - shard-rkl: NOTRUN -> [SKIP][243] ([i915#5354]) [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_pm_backlight@fade-with-suspend.html * igt@kms_pm_dc@dc5-retention-flops: - shard-tglu: NOTRUN -> [SKIP][244] ([i915#3828]) [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_pm_dc@dc5-retention-flops.html * igt@kms_pm_dc@dc6-dpms: - shard-tglu: NOTRUN -> [FAIL][245] ([i915#9295]) [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_pm_dc@dc6-dpms.html * igt@kms_pm_lpsp@kms-lpsp: - shard-tglu-1: NOTRUN -> [SKIP][246] ([i915#3828]) [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html * igt@kms_pm_lpsp@screens-disabled: - shard-dg2-9: NOTRUN -> [SKIP][247] ([i915#8430]) [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_pm_lpsp@screens-disabled.html * igt@kms_pm_rpm@dpms-lpsp: - shard-dg2: [PASS][248] -> [SKIP][249] ([i915#9519]) +2 other tests skip [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-3/igt@kms_pm_rpm@dpms-lpsp.html * igt@kms_pm_rpm@dpms-mode-unset-lpsp: - shard-rkl: [PASS][250] -> [SKIP][251] ([i915#9519]) [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait: - shard-dg2: NOTRUN -> [SKIP][252] ([i915#9519]) [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@kms_pm_rpm@modeset-non-lpsp-stress: - shard-rkl: NOTRUN -> [SKIP][253] ([i915#9519]) [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html - shard-tglu-1: NOTRUN -> [SKIP][254] ([i915#9519]) [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-tglu: NOTRUN -> [SKIP][255] ([i915#9519]) [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@kms_prime@basic-crc-hybrid: - shard-rkl: NOTRUN -> [SKIP][256] ([i915#6524]) [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area: - shard-dg2: NOTRUN -> [SKIP][257] ([i915#11520]) +6 other tests skip [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf: - shard-rkl: NOTRUN -> [SKIP][258] ([i915#11520]) +5 other tests skip [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html * igt@kms_psr2_sf@pr-cursor-plane-update-sf: - shard-tglu: NOTRUN -> [SKIP][259] ([i915#11520]) +6 other tests skip [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf: - shard-tglu-1: NOTRUN -> [SKIP][260] ([i915#11520]) +1 other test skip [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html - shard-glk: NOTRUN -> [SKIP][261] ([i915#11520]) [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk1/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf: - shard-dg2-9: NOTRUN -> [SKIP][262] ([i915#11520]) +4 other tests skip [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr@fbc-psr2-primary-blt: - shard-tglu-1: NOTRUN -> [SKIP][263] ([i915#9732]) +5 other tests skip [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@kms_psr@fbc-psr2-primary-blt.html * igt@kms_psr@psr-basic: - shard-tglu: NOTRUN -> [SKIP][264] ([i915#9732]) +14 other tests skip [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_psr@psr-basic.html * igt@kms_psr@psr-primary-blt: - shard-dg2: NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +17 other tests skip [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_psr@psr-primary-blt.html * igt@kms_psr@psr-sprite-plane-onoff: - shard-rkl: NOTRUN -> [SKIP][266] ([i915#1072] / [i915#9732]) +14 other tests skip [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_psr@psr-sprite-plane-onoff.html * igt@kms_psr@psr2-cursor-plane-onoff: - shard-dg2-9: NOTRUN -> [SKIP][267] ([i915#1072] / [i915#9732]) +9 other tests skip [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_psr@psr2-cursor-plane-onoff.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-dg2-9: NOTRUN -> [SKIP][268] ([i915#9685]) [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-dg2: NOTRUN -> [SKIP][269] ([i915#9685]) [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0: - shard-rkl: NOTRUN -> [SKIP][270] ([i915#5289]) [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0: - shard-dg2-9: NOTRUN -> [SKIP][271] ([i915#5190]) +1 other test skip [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-tglu: NOTRUN -> [SKIP][272] ([i915#5289]) [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_rotation_crc@sprite-rotation-90: - shard-dg2-9: NOTRUN -> [SKIP][273] ([i915#12755]) [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_rotation_crc@sprite-rotation-90.html * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0: - shard-dg2: NOTRUN -> [SKIP][274] ([i915#12755]) [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html * igt@kms_scaling_modes@scaling-mode-full: - shard-tglu: NOTRUN -> [SKIP][275] ([i915#3555]) +4 other tests skip [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_scaling_modes@scaling-mode-full.html * igt@kms_setmode@invalid-clone-exclusive-crtc: - shard-dg2-9: NOTRUN -> [SKIP][276] ([i915#3555]) +2 other tests skip [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_setmode@invalid-clone-exclusive-crtc.html * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1: - shard-glk: [PASS][277] -> [INCOMPLETE][278] ([i915#12276]) [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-glk7/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html * igt@kms_vrr@flip-basic-fastset: - shard-dg2: NOTRUN -> [SKIP][279] ([i915#9906]) [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@kms_vrr@flip-basic-fastset.html * igt@kms_vrr@lobf: - shard-rkl: NOTRUN -> [SKIP][280] ([i915#11920]) [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_vrr@lobf.html * igt@kms_vrr@negative-basic: - shard-rkl: NOTRUN -> [SKIP][281] ([i915#3555] / [i915#9906]) [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_vrr@negative-basic.html - shard-mtlp: [PASS][282] -> [FAIL][283] ([i915#10393]) +1 other test fail [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-6/igt@kms_vrr@negative-basic.html [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-2/igt@kms_vrr@negative-basic.html * igt@kms_vrr@seamless-rr-switch-virtual: - shard-tglu: NOTRUN -> [SKIP][284] ([i915#9906]) [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@kms_vrr@seamless-rr-switch-virtual.html * igt@kms_writeback@writeback-check-output: - shard-dg2-9: NOTRUN -> [SKIP][285] ([i915#2437]) [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-9/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-fb-id-xrgb2101010: - shard-rkl: NOTRUN -> [SKIP][286] ([i915#2437] / [i915#9412]) [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@kms_writeback@writeback-fb-id-xrgb2101010.html * igt@kms_writeback@writeback-invalid-parameters: - shard-dg2: NOTRUN -> [SKIP][287] ([i915#2437]) [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@kms_writeback@writeback-invalid-parameters.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-rkl: NOTRUN -> [SKIP][288] ([i915#2436]) [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-7/igt@perf@gen8-unprivileged-single-ctx-counters.html * igt@perf_pmu@busy-double-start@vecs1: - shard-dg2: [PASS][289] -> [FAIL][290] ([i915#4349]) +4 other tests fail [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-5/igt@perf_pmu@busy-double-start@vecs1.html * igt@perf_pmu@invalid-init: - shard-tglu: NOTRUN -> [FAIL][291] ([i915#13663]) [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-5/igt@perf_pmu@invalid-init.html * igt@perf_pmu@rc6@other-idle-gt0: - shard-dg2: NOTRUN -> [SKIP][292] ([i915#8516]) [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@perf_pmu@rc6@other-idle-gt0.html * igt@prime_vgem@basic-fence-read: - shard-rkl: NOTRUN -> [SKIP][293] ([i915#3291] / [i915#3708]) +1 other test skip [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@prime_vgem@basic-fence-read.html * igt@prime_vgem@basic-read: - shard-dg2: NOTRUN -> [SKIP][294] ([i915#3291] / [i915#3708]) [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@prime_vgem@basic-read.html * igt@prime_vgem@fence-write-hang: - shard-dg2: NOTRUN -> [SKIP][295] ([i915#3708]) [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-2/igt@prime_vgem@fence-write-hang.html * igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-random: - shard-tglu-1: NOTRUN -> [FAIL][296] ([i915#12910]) +9 other tests fail [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-random.html * igt@sriov_basic@enable-vfs-autoprobe-on: - shard-tglu: NOTRUN -> [FAIL][297] ([i915#12910]) +19 other tests fail [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-tglu-9/igt@sriov_basic@enable-vfs-autoprobe-on.html * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all: - shard-dg2: NOTRUN -> [SKIP][298] ([i915#9917]) [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html #### Possible fixes #### * igt@gem_eio@reset-stress: - shard-dg1: [FAIL][299] ([i915#12543] / [i915#5784]) -> [PASS][300] [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-13/igt@gem_eio@reset-stress.html [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-16/igt@gem_eio@reset-stress.html * igt@gem_exec_suspend@basic-s0: - shard-dg2: [INCOMPLETE][301] ([i915#11441] / [i915#13304]) -> [PASS][302] [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-2/igt@gem_exec_suspend@basic-s0.html [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_suspend@basic-s0.html * igt@gem_exec_suspend@basic-s0@lmem0: - shard-dg2: [INCOMPLETE][303] ([i915#11441]) -> [PASS][304] [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-2/igt@gem_exec_suspend@basic-s0@lmem0.html [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-7/igt@gem_exec_suspend@basic-s0@lmem0.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg1: [TIMEOUT][305] ([i915#5493]) -> [PASS][306] +1 other test pass [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_pxp@create-valid-protected-context: - shard-rkl: [TIMEOUT][307] ([i915#12964]) -> [PASS][308] [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-3/igt@gem_pxp@create-valid-protected-context.html [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@gem_pxp@create-valid-protected-context.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [ABORT][309] ([i915#5566]) -> [PASS][310] [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-glk2/igt@gen9_exec_parse@allowed-single.html [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-glk1/igt@gen9_exec_parse@allowed-single.html * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0: - shard-dg1: [FAIL][311] ([i915#3591]) -> [PASS][312] [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc: - shard-dg1: [DMESG-WARN][313] ([i915#4423]) -> [PASS][314] +2 other tests pass [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-14/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-19/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible: - shard-snb: [FAIL][315] ([i915#11832] / [i915#13734]) -> [PASS][316] [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-snb6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-snb6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check: - shard-snb: [FAIL][317] ([i915#11832]) -> [PASS][318] +2 other tests pass [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-snb4/igt@kms_flip@2x-wf_vblank-ts-check.html [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-snb5/igt@kms_flip@2x-wf_vblank-ts-check.html * igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1: - shard-mtlp: [FAIL][319] ([i915#13734]) -> [PASS][320] +1 other test pass [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-1/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-rkl: [SKIP][321] ([i915#9519]) -> [PASS][322] [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@kms_vrr@negative-basic: - shard-dg2: [SKIP][323] ([i915#3555] / [i915#9906]) -> [PASS][324] [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-1/igt@kms_vrr@negative-basic.html [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-10/igt@kms_vrr@negative-basic.html * igt@perf_pmu@busy-accuracy-50@vecs0: - shard-rkl: [DMESG-WARN][325] ([i915#12964]) -> [PASS][326] +2 other tests pass [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-4/igt@perf_pmu@busy-accuracy-50@vecs0.html [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-6/igt@perf_pmu@busy-accuracy-50@vecs0.html #### Warnings #### * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-a-hdmi-a-4: - shard-dg1: [SKIP][327] ([i915#4423] / [i915#6095]) -> [SKIP][328] ([i915#6095]) +3 other tests skip [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-14/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-a-hdmi-a-4.html [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-19/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-a-hdmi-a-4.html * igt@kms_content_protection@atomic-dpms: - shard-dg2: [SKIP][329] ([i915#7118] / [i915#9424]) -> [FAIL][330] ([i915#7173]) [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@legacy: - shard-dg2: [FAIL][331] ([i915#7173]) -> [SKIP][332] ([i915#7118] / [i915#9424]) [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-11/igt@kms_content_protection@legacy.html [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-5/igt@kms_content_protection@legacy.html * igt@kms_flip@2x-blocking-wf_vblank: - shard-dg1: [SKIP][333] ([i915#4423] / [i915#9934]) -> [SKIP][334] ([i915#9934]) [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg1-18/igt@kms_flip@2x-blocking-wf_vblank.html [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg1-17/igt@kms_flip@2x-blocking-wf_vblank.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-dg2: [SKIP][335] ([i915#10433] / [i915#3458]) -> [SKIP][336] ([i915#3458]) +1 other test skip [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite: - shard-dg2: [SKIP][337] ([i915#3458]) -> [SKIP][338] ([i915#10433] / [i915#3458]) +1 other test skip [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_hdr@brightness-with-hdr: - shard-mtlp: [SKIP][339] ([i915#12713]) -> [SKIP][340] ([i915#1187] / [i915#12713]) [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-mtlp-5/igt@kms_hdr@brightness-with-hdr.html [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-mtlp-1/igt@kms_hdr@brightness-with-hdr.html - shard-dg2: [SKIP][341] ([i915#13331]) -> [SKIP][342] ([i915#12713]) [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-dg2-11/igt@kms_hdr@brightness-with-hdr.html [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-dg2-8/igt@kms_hdr@brightness-with-hdr.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-rkl: [SKIP][343] ([i915#4816]) -> [SKIP][344] ([i915#1839] / [i915#4816]) [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_pm_lpsp@kms-lpsp: - shard-rkl: [SKIP][345] ([i915#3828]) -> [SKIP][346] ([i915#9340]) [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html * igt@kms_pm_rpm@modeset-pc8-residency-stress: - shard-rkl: [SKIP][347] -> [SKIP][348] ([i915#12916]) [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16317/shard-rkl-8/igt@kms_pm_rpm@modeset-pc8-residency-stress.html [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/shard-rkl-5/igt@kms_pm_rpm@modeset-pc8-residency-stress.html [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055 [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307 [i915#10393]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10393 [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433 [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434 [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072 [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078 [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151 [i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441 [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520 [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527 [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681 [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808 [i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832 [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187 [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920 [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247 [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276 [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313 [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339 [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343 [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388 [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394 [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454 [i915#12543]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12543 [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257 [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712 [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713 [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755 [i915#12797]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12797 [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805 [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910 [i915#12916]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12916 [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917 [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964 [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008 [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027 [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046 [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049 [i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193 [i915#13304]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13304 [i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331 [i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427 [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566 [i915#13663]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13663 [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691 [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707 [i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734 [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748 [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749 [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781 [i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783 [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790 [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839 [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346 [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681 [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280 [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023 [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299 [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323 [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638 [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708 [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742 [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804 [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828 [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840 [i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936 [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955 [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103 [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213 [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270 [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349 [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423 [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525 [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537 [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812 [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816 [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817 [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852 [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860 [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880 [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885 [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107 [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138 [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190 [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286 [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289 [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354 [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439 [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493 [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566 [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784 [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956 [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095 [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245 [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301 [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334 [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335 [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658 [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944 [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953 [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118 [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173 [i915#7443]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7443 [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582 [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697 [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828 [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975 [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228 [i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289 [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381 [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399 [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411 [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428 [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430 [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516 [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555 [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562 [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709 [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053 [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067 [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295 [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323 [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337 [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340 [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412 [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423 [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424 [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519 [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685 [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732 [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812 [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906 [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917 [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934 Build changes ------------- * Linux: CI_DRM_16317 -> Patchwork_146730v1 CI-20190529: 20190529 CI_DRM_16317: 8de9ba4a4539f21e6809b9fb42c04cb3be9c1e76 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_8283: e4eb2265f06fc69e37e56cb6b609e019b6071435 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_146730v1: 8de9ba4a4539f21e6809b9fb42c04cb3be9c1e76 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_146730v1/index.html [-- Attachment #2: Type: text/html, Size: 120147 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula ` (8 preceding siblings ...) 2025-03-25 21:47 ` ✗ i915.CI.Full: failure " Patchwork @ 2025-03-28 10:58 ` Ville Syrjälä 2025-03-28 14:01 ` Jani Nikula 9 siblings, 1 reply; 12+ messages in thread From: Ville Syrjälä @ 2025-03-28 10:58 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe On Tue, Mar 25, 2025 at 02:36:32PM +0200, Jani Nikula wrote: > We're getting there! > > Jani Nikula (6): > drm/i915/dpll: convert intel_dpll.[ch] to struct intel_display > drm/i915/ddi: convert intel_ddi.c to struct intel_display > drm/i915/crc: convert intel_pipe_crc.c to struct intel_display > drm/i915/psr: further conversions to struct intel_display > drm/i915/wa: convert intel_display_wa.[ch] to struct intel_display > drm/i915/display: drop some unnecessary intel_de_* compatibility > wrappers Series is Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > drivers/gpu/drm/i915/display/intel_ddi.c | 904 +++++++++--------- > drivers/gpu/drm/i915/display/intel_de.h | 16 +- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../drm/i915/display/intel_display_driver.c | 7 +- > .../gpu/drm/i915/display/intel_display_wa.c | 30 +- > .../gpu/drm/i915/display/intel_display_wa.h | 11 +- > drivers/gpu/drm/i915/display/intel_dpll.c | 312 +++--- > drivers/gpu/drm/i915/display/intel_dpll.h | 13 +- > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > drivers/gpu/drm/i915/display/intel_pipe_crc.c | 137 ++- > drivers/gpu/drm/i915/display/intel_pps.c | 5 +- > drivers/gpu/drm/i915/display/intel_psr.c | 85 +- > drivers/gpu/drm/xe/display/xe_display_wa.c | 6 +- > 13 files changed, 729 insertions(+), 803 deletions(-) > > -- > 2.39.5 -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display 2025-03-28 10:58 ` [PATCH 0/6] " Ville Syrjälä @ 2025-03-28 14:01 ` Jani Nikula 0 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2025-03-28 14:01 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, intel-xe On Fri, 28 Mar 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Mar 25, 2025 at 02:36:32PM +0200, Jani Nikula wrote: >> We're getting there! >> >> Jani Nikula (6): >> drm/i915/dpll: convert intel_dpll.[ch] to struct intel_display >> drm/i915/ddi: convert intel_ddi.c to struct intel_display >> drm/i915/crc: convert intel_pipe_crc.c to struct intel_display >> drm/i915/psr: further conversions to struct intel_display >> drm/i915/wa: convert intel_display_wa.[ch] to struct intel_display >> drm/i915/display: drop some unnecessary intel_de_* compatibility >> wrappers > > Series is > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks, pushed to din. BR, Jani. > >> >> drivers/gpu/drm/i915/display/intel_ddi.c | 904 +++++++++--------- >> drivers/gpu/drm/i915/display/intel_de.h | 16 +- >> drivers/gpu/drm/i915/display/intel_display.c | 4 +- >> .../drm/i915/display/intel_display_driver.c | 7 +- >> .../gpu/drm/i915/display/intel_display_wa.c | 30 +- >> .../gpu/drm/i915/display/intel_display_wa.h | 11 +- >> drivers/gpu/drm/i915/display/intel_dpll.c | 312 +++--- >> drivers/gpu/drm/i915/display/intel_dpll.h | 13 +- >> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- >> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 137 ++- >> drivers/gpu/drm/i915/display/intel_pps.c | 5 +- >> drivers/gpu/drm/i915/display/intel_psr.c | 85 +- >> drivers/gpu/drm/xe/display/xe_display_wa.c | 6 +- >> 13 files changed, 729 insertions(+), 803 deletions(-) >> >> -- >> 2.39.5 -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2025-03-28 14:01 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-03-25 12:36 [PATCH 0/6] drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Jani Nikula 2025-03-25 12:36 ` [PATCH 1/6] drm/i915/dpll: convert intel_dpll.[ch] " Jani Nikula 2025-03-25 12:36 ` [PATCH 2/6] drm/i915/ddi: convert intel_ddi.c " Jani Nikula 2025-03-25 12:36 ` [PATCH 3/6] drm/i915/crc: convert intel_pipe_crc.c " Jani Nikula 2025-03-25 12:36 ` [PATCH 4/6] drm/i915/psr: further conversions " Jani Nikula 2025-03-25 12:36 ` [PATCH 5/6] drm/i915/wa: convert intel_display_wa.[ch] " Jani Nikula 2025-03-25 12:36 ` [PATCH 6/6] drm/i915/display: drop some unnecessary intel_de_* compatibility wrappers Jani Nikula 2025-03-25 18:54 ` ✗ Fi.CI.SPARSE: warning for drm/i915: dpll, ddi, crc, psr etc conversions to struct intel_display Patchwork 2025-03-25 19:16 ` ✓ i915.CI.BAT: success " Patchwork 2025-03-25 21:47 ` ✗ i915.CI.Full: failure " Patchwork 2025-03-28 10:58 ` [PATCH 0/6] " Ville Syrjälä 2025-03-28 14:01 ` Jani Nikula
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