[PATCH v6 0/7] drm/i915/xe3: FBC Dirty rect feature support

[PATCH v6 0/7] drm/i915/xe3: FBC Dirty rect feature support

[Vinod Govindapillai]

Dirty rect support for FBC in xe3 onwards based on the comments after the
initial RFC series.

v2: Dirty rect related compute and storage moved to fbc state (Ville)

V3: Dont call fbc activate if FBC is already active

v4: Dirty rect compute and programming moved within DSB scope
    New changes are added as separate patches to make it easy for review
    But could be squashed if the reviews as ok.

v5: add HAS_FBC_DIRTY_RECT()
    FBC Damage area updates in 3 steps. 
    1. As part of plane_atomic_check() get, adjust coordinates and store
       the merged damage area in plane_state
    2. Atomic_commit, update merged damage are to fbc_state and prepare the
       damage area satifying all conditions
    3  update the FBC dirty rect registers as part of DSB commit.

v6: Use dmage_merged helper earlier to handle bigjoiner cases (Ville)
    Place the damage_merged handling code under HAS_FBC_DIRTY_RECT()
    Added a variable to check if the damage_merged received from
    the helper is valid. And if it is not valid, the FBC dirty rect
    is updated with full plane reqion.

Vinod Govindapillai (7):
  drm/i915/xe3: add register definitions for fbc dirty rect support
  drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect
    support
  drm/damage-helper: add const qualifier in
    drm_atomic_helper_damage_merged()
  drm/i915/xe3: update and store the plane damage clips
  drm/i915/xe3: dirty rect support for FBC
  drm/i915/xe3: avoid calling fbc activate if fbc is active
  drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled

 drivers/gpu/drm/drm_damage_helper.c           |   2 +-
 .../gpu/drm/i915/display/intel_atomic_plane.c |  28 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 152 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fbc.h      |   6 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h |   9 ++
 .../drm/i915/display/skl_universal_plane.c    |  45 +++++-
 include/drm/drm_damage_helper.h               |   2 +-
 10 files changed, 246 insertions(+), 8 deletions(-)

-- 
2.43.0

[PATCH v6 1/7] drm/i915/xe3: add register definitions for fbc dirty rect support

[Vinod Govindapillai]

Register definitions for FBC dirty rect support

Bspec: 71675, 73424
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index ae0699c3c2fe..b1d0161a3196 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -100,6 +100,15 @@
 #define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
 #define   FBC_STRIDE(x)		REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
 
+#define XE3_FBC_DIRTY_RECT(fbc_id)	_MMIO_PIPE((fbc_id), 0x43230, 0x43270)
+#define   FBC_DIRTY_RECT_END_LINE_MASK		REG_GENMASK(31, 16)
+#define   FBC_DIRTY_RECT_END_LINE(val)		REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val))
+#define   FBC_DIRTY_RECT_START_LINE_MASK	REG_GENMASK(15, 0)
+#define   FBC_DIRTY_RECT_START_LINE(val)	REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))
+
+#define XE3_FBC_DIRTY_CTL(fbc_id)	_MMIO_PIPE((fbc_id), 0x43234, 0x43274)
+#define   FBC_DIRTY_RECT_EN		REG_BIT(31)
+
 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
 #define   ILK_FBC_RT_VALID	REG_BIT(0)
 #define   SNB_FBC_FRONT_BUFFER	REG_BIT(1)
-- 
2.43.0

RE: [PATCH v6 1/7] drm/i915/xe3: add register definitions for fbc dirty rect support

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Vinod
> Govindapillai
> Sent: Friday, January 31, 2025 2:30 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
> <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
> <jani.saarinen@intel.com>
> Subject: [PATCH v6 1/7] drm/i915/xe3: add register definitions for fbc dirty
> rect support
> 
> Register definitions for FBC dirty rect support
> 
> Bspec: 71675, 73424

Add the reference for 69003 for FBC instances
Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index ae0699c3c2fe..b1d0161a3196 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -100,6 +100,15 @@
>  #define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
>  #define   FBC_STRIDE(x)		REG_FIELD_PREP(FBC_STRIDE_MASK,
> (x))
> 
> +#define XE3_FBC_DIRTY_RECT(fbc_id)	_MMIO_PIPE((fbc_id), 0x43230,
> 0x43270)
> +#define   FBC_DIRTY_RECT_END_LINE_MASK		REG_GENMASK(31,
> 16)
> +#define   FBC_DIRTY_RECT_END_LINE(val)
> 	REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val))
> +#define   FBC_DIRTY_RECT_START_LINE_MASK	REG_GENMASK(15, 0)
> +#define   FBC_DIRTY_RECT_START_LINE(val)
> 	REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))
> +
> +#define XE3_FBC_DIRTY_CTL(fbc_id)	_MMIO_PIPE((fbc_id), 0x43234,
> 0x43274)
> +#define   FBC_DIRTY_RECT_EN		REG_BIT(31)
> +
>  #define ILK_FBC_RT_BASE		_MMIO(0x2128)
>  #define   ILK_FBC_RT_VALID	REG_BIT(0)
>  #define   SNB_FBC_FRONT_BUFFER	REG_BIT(1)
> --
> 2.43.0

[PATCH v6 2/7] drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support

[Vinod Govindapillai]

Introduce a macro to check if the platform supports FBC dirty
rect capability.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fc33791f02b9..717286981687 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -163,6 +163,7 @@ struct intel_display_platforms {
 #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
+#define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
 #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
 #define HAS_GMBUS_IRQ(__display)	(DISPLAY_VER(__display) >= 4)
-- 
2.43.0

RE: [PATCH v6 2/7] drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Vinod
> Govindapillai
> Sent: Friday, January 31, 2025 2:30 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
> <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
> <jani.saarinen@intel.com>
> Subject: [PATCH v6 2/7] drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for
> FBC dirty rect support
> 
> Introduce a macro to check if the platform supports FBC dirty rect capability.
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index fc33791f02b9..717286981687 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -163,6 +163,7 @@ struct intel_display_platforms {
>  #define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)-
> >has_dsc)
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> 12 && HAS_DSC(__display))
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)-
> >fbc_mask != 0)
> +#define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> 30)
>  #define HAS_FPGA_DBG_UNCLAIMED(__display)
> 	(DISPLAY_INFO(__display)->has_fpga_dbg)
>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> 3)
>  #define HAS_GMBUS_IRQ(__display)	(DISPLAY_VER(__display) >= 4)
> --
> 2.43.0

[PATCH v6 3/7] drm/damage-helper: add const qualifier in drm_atomic_helper_damage_merged()

[Vinod Govindapillai]

Add a const qualifier for the "state" parameter as well as we could
use this helper to get the combined damage in cases of const
drm_plane_state as well. Needed mainly for xe driver big joiner cases
where we need to track the damage from immutable plane state.

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/drm_damage_helper.c | 2 +-
 include/drm/drm_damage_helper.h     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_damage_helper.c b/drivers/gpu/drm/drm_damage_helper.c
index afb02aae707b..44a5a36806e3 100644
--- a/drivers/gpu/drm/drm_damage_helper.c
+++ b/drivers/gpu/drm/drm_damage_helper.c
@@ -308,7 +308,7 @@ EXPORT_SYMBOL(drm_atomic_helper_damage_iter_next);
  * True if there is valid plane damage otherwise false.
  */
 bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
-				     struct drm_plane_state *state,
+				     const struct drm_plane_state *state,
 				     struct drm_rect *rect)
 {
 	struct drm_atomic_helper_damage_iter iter;
diff --git a/include/drm/drm_damage_helper.h b/include/drm/drm_damage_helper.h
index effda42cce31..a58cbcd11276 100644
--- a/include/drm/drm_damage_helper.h
+++ b/include/drm/drm_damage_helper.h
@@ -78,7 +78,7 @@ bool
 drm_atomic_helper_damage_iter_next(struct drm_atomic_helper_damage_iter *iter,
 				   struct drm_rect *rect);
 bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
-				     struct drm_plane_state *state,
+				     const struct drm_plane_state *state,
 				     struct drm_rect *rect);
 
 #endif
-- 
2.43.0

Re: [PATCH v6 3/7] drm/damage-helper: add const qualifier in drm_atomic_helper_damage_merged()

[Jani Nikula]

On Thu, 30 Jan 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> Add a const qualifier for the "state" parameter as well as we could
> use this helper to get the combined damage in cases of const
> drm_plane_state as well. Needed mainly for xe driver big joiner cases
> where we need to track the damage from immutable plane state.

Needs to be sent to dri-devel.

>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/drm_damage_helper.c | 2 +-
>  include/drm/drm_damage_helper.h     | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_damage_helper.c b/drivers/gpu/drm/drm_damage_helper.c
> index afb02aae707b..44a5a36806e3 100644
> --- a/drivers/gpu/drm/drm_damage_helper.c
> +++ b/drivers/gpu/drm/drm_damage_helper.c
> @@ -308,7 +308,7 @@ EXPORT_SYMBOL(drm_atomic_helper_damage_iter_next);
>   * True if there is valid plane damage otherwise false.
>   */
>  bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
> -				     struct drm_plane_state *state,
> +				     const struct drm_plane_state *state,
>  				     struct drm_rect *rect)
>  {
>  	struct drm_atomic_helper_damage_iter iter;
> diff --git a/include/drm/drm_damage_helper.h b/include/drm/drm_damage_helper.h
> index effda42cce31..a58cbcd11276 100644
> --- a/include/drm/drm_damage_helper.h
> +++ b/include/drm/drm_damage_helper.h
> @@ -78,7 +78,7 @@ bool
>  drm_atomic_helper_damage_iter_next(struct drm_atomic_helper_damage_iter *iter,
>  				   struct drm_rect *rect);
>  bool drm_atomic_helper_damage_merged(const struct drm_plane_state *old_state,
> -				     struct drm_plane_state *state,
> +				     const struct drm_plane_state *state,
>  				     struct drm_rect *rect);
>  
>  #endif

-- 
Jani Nikula, Intel

[PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Vinod Govindapillai]

Userspace can pass damage area clips per plane to track
changes in a plane and some display components can utilze
these damage clips for efficiently handling use cases like
FBC, PSR etc. A merged damage area is generated and its
coordinates are updated relative to viewport and HW and
stored in the plane_state. This merged damage areas will be
used for FBC dirty rect support in xe3 in the follow-up
patch.

Big thanks to Ville Syrjala for his contribuitions in shaping
up of this series.

v1: - Move damage_merged helper to cover bigjoiner case and use
    the correct plane state for damage find helper (Ville)
    - Damage handling code under HAS_FBC_DIRTY_RECT() so the
    the related part will be executed only for xe3+
    - Changed dev_priv to i915 in one of the functions

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
 .../drm/i915/display/intel_display_types.h    |  2 +
 .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
 3 files changed, 71 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c558143f4f82..f55f7044dc67 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -36,6 +36,7 @@
 
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_blend.h>
+#include <drm/drm_damage_helper.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_gem.h>
 #include <drm/drm_gem_atomic_helper.h>
@@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 }
 
+static void
+intel_plane_check_plane_damage(struct intel_plane_state *new_plane_state,
+			       const struct intel_plane_state *old_primary_plane_state,
+			       const struct intel_plane_state *new_primary_plane_state)
+{
+	struct intel_display *display = to_intel_display(new_plane_state);
+	struct drm_rect *damage_merged = &new_plane_state->damage_merged;
+
+	if (!HAS_FBC_DIRTY_RECT(display))
+		return;
+
+	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state->uapi,
+					     &new_primary_plane_state->uapi,
+					     damage_merged))
+		/* Incase helper fails, mark whole plane region as damage */
+		*damage_merged =
+			drm_plane_state_src(&new_primary_plane_state->uapi);
+}
+
 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 				       const struct intel_plane_state *from_plane_state,
 				       struct intel_crtc *crtc)
@@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
 	const struct intel_plane_state *old_plane_state =
 		intel_atomic_get_old_plane_state(state, plane);
 	const struct intel_plane_state *new_primary_crtc_plane_state;
+	const struct intel_plane_state *old_primary_crtc_plane_state;
 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
@@ -705,10 +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
 
 		new_primary_crtc_plane_state =
 			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
+		old_primary_crtc_plane_state =
+			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
 	} else {
 		new_primary_crtc_plane_state = new_plane_state;
+		old_primary_crtc_plane_state = old_plane_state;
 	}
 
+	intel_plane_check_plane_damage(new_plane_state,
+				       old_primary_crtc_plane_state,
+				       new_primary_crtc_plane_state);
+
 	intel_plane_copy_uapi_to_hw_state(new_plane_state,
 					  new_primary_crtc_plane_state,
 					  crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index cb51b7936f93..8d53bcca9614 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -695,6 +695,8 @@ struct intel_plane_state {
 	u64 ccval;
 
 	const char *no_fbc_reason;
+
+	struct drm_rect damage_merged;
 };
 
 struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 301ad3a22c4c..b90a7d52c071 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2249,11 +2249,42 @@ static void check_protection(struct intel_plane_state *plane_state)
 		!plane_state->decrypt;
 }
 
+static void
+skl_plane_check_damage_with_viewport(struct intel_plane_state *plane_state)
+{
+	struct drm_rect *damage_merged = &plane_state->damage_merged;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
+	struct drm_rect *src = &plane_state->uapi.src;
+
+	if (drm_rotation_90_or_270(rotation)) {
+		drm_rect_rotate(damage_merged, fb->width, fb->height,
+				DRM_MODE_ROTATE_270);
+		drm_rect_translate(damage_merged, -(src->y1 >> 16),
+				   -(src->x1 >> 16));
+	} else {
+		drm_rect_translate(damage_merged, -(src->x1 >> 16),
+				   -(src->y1 >> 16));
+	}
+}
+
+static void
+skl_plane_check_damage_with_plane_surf(struct intel_plane_state *plane_state)
+{
+	struct drm_rect *damage_merged = &plane_state->damage_merged;
+	struct drm_rect src;
+
+	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
+	drm_rect_translate(damage_merged, src.x1, src.y1);
+	drm_rect_intersect(damage_merged, &src);
+}
+
 static int skl_plane_check(struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *plane_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	struct drm_i915_private *i915 = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int min_scale = DRM_PLANE_NO_SCALING;
 	int max_scale = DRM_PLANE_NO_SCALING;
@@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 	/* use scaler when colorkey is not required */
 	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
 		min_scale = 1;
-		max_scale = skl_plane_max_scale(dev_priv, fb);
+		max_scale = skl_plane_max_scale(i915, fb);
 	}
 
 	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
@@ -2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
+	if (HAS_FBC_DIRTY_RECT(display))
+		skl_plane_check_damage_with_viewport(plane_state);
+
 	ret = skl_check_plane_surface(plane_state);
 	if (ret)
 		return ret;
@@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
+	if (HAS_FBC_DIRTY_RECT(display))
+		skl_plane_check_damage_with_plane_surf(plane_state);
+
 	ret = skl_plane_check_nv12_rotation(plane_state);
 	if (ret)
 		return ret;
@@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 
 	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
 
-	if (DISPLAY_VER(dev_priv) >= 10)
+	if (DISPLAY_VER(display) >= 10)
 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
 							     plane_state);
 
 	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
-	    icl_is_hdr_plane(dev_priv, plane->id))
+	    icl_is_hdr_plane(i915, plane->id))
 		/* Enable and use MPEG-2 chroma siting */
 		plane_state->cus_ctl = PLANE_CUS_ENABLE |
 			PLANE_CUS_HPHASE_0 |
-- 
2.43.0

RE: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Vinod
> Govindapillai
> Sent: Friday, January 31, 2025 2:30 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
> <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
> <jani.saarinen@intel.com>
> Subject: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage
> clips
> 
> Userspace can pass damage area clips per plane to track changes in a plane
> and some display components can utilze these damage clips for efficiently
> handling use cases like FBC, PSR etc. A merged damage area is generated and
> its coordinates are updated relative to viewport and HW and stored in the
> plane_state. This merged damage areas will be used for FBC dirty rect support
> in xe3 in the follow-up patch.
> 
> Big thanks to Ville Syrjala for his contribuitions in shaping up of this series.
> 
> v1: - Move damage_merged helper to cover bigjoiner case and use
>     the correct plane state for damage find helper (Ville)
>     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
>     the related part will be executed only for xe3+
>     - Changed dev_priv to i915 in one of the functions
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
>  3 files changed, 71 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c558143f4f82..f55f7044dc67 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -36,6 +36,7 @@
> 
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_blend.h>
> +#include <drm/drm_damage_helper.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_gem.h>
>  #include <drm/drm_gem_atomic_helper.h>
> @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct
> intel_plane_state *plane_state)
>  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));  }
> 
> +static void
> +intel_plane_check_plane_damage(struct intel_plane_state
> *new_plane_state,
> +			       const struct intel_plane_state
> *old_primary_plane_state,
> +			       const struct intel_plane_state
> *new_primary_plane_state) {
> +	struct intel_display *display = to_intel_display(new_plane_state);
> +	struct drm_rect *damage_merged = &new_plane_state-
> >damage_merged;
> +
> +	if (!HAS_FBC_DIRTY_RECT(display))
> +		return;
> +
> +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state-
> >uapi,
> +					     &new_primary_plane_state->uapi,
> +					     damage_merged))
> +		/* Incase helper fails, mark whole plane region as damage */
> +		*damage_merged =
> +			drm_plane_state_src(&new_primary_plane_state-
> >uapi);
> +}
> +
>  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
> *plane_state,
>  				       const struct intel_plane_state
> *from_plane_state,
>  				       struct intel_crtc *crtc)
> @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct
> intel_atomic_state *state,
>  	const struct intel_plane_state *old_plane_state =
>  		intel_atomic_get_old_plane_state(state, plane);
>  	const struct intel_plane_state *new_primary_crtc_plane_state;
> +	const struct intel_plane_state *old_primary_crtc_plane_state;
>  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc); @@ -705,10
> +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> 
>  		new_primary_crtc_plane_state =
>  			intel_atomic_get_new_plane_state(state,
> primary_crtc_plane);
> +		old_primary_crtc_plane_state =
> +			intel_atomic_get_old_plane_state(state,
> primary_crtc_plane);
>  	} else {
>  		new_primary_crtc_plane_state = new_plane_state;
> +		old_primary_crtc_plane_state = old_plane_state;
>  	}
> 
> +	intel_plane_check_plane_damage(new_plane_state,
> +				       old_primary_crtc_plane_state,
> +				       new_primary_crtc_plane_state);
> +
>  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
>  					  new_primary_crtc_plane_state,
>  					  crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index cb51b7936f93..8d53bcca9614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -695,6 +695,8 @@ struct intel_plane_state {
>  	u64 ccval;
> 
>  	const char *no_fbc_reason;
> +
> +	struct drm_rect damage_merged;
>  };
> 
>  struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 301ad3a22c4c..b90a7d52c071 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2249,11 +2249,42 @@ static void check_protection(struct
> intel_plane_state *plane_state)
>  		!plane_state->decrypt;
>  }
> 
> +static void
> +skl_plane_check_damage_with_viewport(struct intel_plane_state
> +*plane_state) {
> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +	unsigned int rotation = plane_state->hw.rotation;
> +	struct drm_rect *src = &plane_state->uapi.src;
> +
> +	if (drm_rotation_90_or_270(rotation)) {
> +		drm_rect_rotate(damage_merged, fb->width, fb->height,
> +				DRM_MODE_ROTATE_270);
> +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
> +				   -(src->x1 >> 16));
> +	} else {
> +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
> +				   -(src->y1 >> 16));
> +	}
> +}
> +
> +static void
> +skl_plane_check_damage_with_plane_surf(struct intel_plane_state
> +*plane_state) {
> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> +	struct drm_rect src;
> +
> +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
> +	drm_rect_translate(damage_merged, src.x1, src.y1);
> +	drm_rect_intersect(damage_merged, &src); }
> +
>  static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *plane_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);

This change of moving from dev_priv naming to i915 and to start using intel_display
Is a refactor and should be in a patch of its own.

Regards,
Suraj Kandpal

>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int min_scale = DRM_PLANE_NO_SCALING;
>  	int max_scale = DRM_PLANE_NO_SCALING;
> @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state
> *crtc_state,
>  	/* use scaler when colorkey is not required */
>  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
>  		min_scale = 1;
> -		max_scale = skl_plane_max_scale(dev_priv, fb);
> +		max_scale = skl_plane_max_scale(i915, fb);
>  	}
> 
>  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -
> 2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state
> *crtc_state,
>  	if (ret)
>  		return ret;
> 
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		skl_plane_check_damage_with_viewport(plane_state);
> +
>  	ret = skl_check_plane_surface(plane_state);
>  	if (ret)
>  		return ret;
> @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state
> *crtc_state,
>  	if (ret)
>  		return ret;
> 
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		skl_plane_check_damage_with_plane_surf(plane_state);
> +
>  	ret = skl_plane_check_nv12_rotation(plane_state);
>  	if (ret)
>  		return ret;
> @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state
> *crtc_state,
> 
>  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> 
> -	if (DISPLAY_VER(dev_priv) >= 10)
> +	if (DISPLAY_VER(display) >= 10)
>  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
>  							     plane_state);
> 
>  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> -	    icl_is_hdr_plane(dev_priv, plane->id))
> +	    icl_is_hdr_plane(i915, plane->id))
>  		/* Enable and use MPEG-2 chroma siting */
>  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
>  			PLANE_CUS_HPHASE_0 |
> --
> 2.43.0

RE: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Jani Nikula]

On Wed, 05 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Vinod
>> Govindapillai
>> Sent: Friday, January 31, 2025 2:30 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
>> <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
>> <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
>> <jani.saarinen@intel.com>
>> Subject: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage
>> clips
>> 
>> Userspace can pass damage area clips per plane to track changes in a plane
>> and some display components can utilze these damage clips for efficiently
>> handling use cases like FBC, PSR etc. A merged damage area is generated and
>> its coordinates are updated relative to viewport and HW and stored in the
>> plane_state. This merged damage areas will be used for FBC dirty rect support
>> in xe3 in the follow-up patch.
>> 
>> Big thanks to Ville Syrjala for his contribuitions in shaping up of this series.
>> 
>> v1: - Move damage_merged helper to cover bigjoiner case and use
>>     the correct plane state for damage find helper (Ville)
>>     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
>>     the related part will be executed only for xe3+
>>     - Changed dev_priv to i915 in one of the functions
>> 
>> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
>>  .../drm/i915/display/intel_display_types.h    |  2 +
>>  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
>>  3 files changed, 71 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index c558143f4f82..f55f7044dc67 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -36,6 +36,7 @@
>> 
>>  #include <drm/drm_atomic_helper.h>
>>  #include <drm/drm_blend.h>
>> +#include <drm/drm_damage_helper.h>
>>  #include <drm/drm_fourcc.h>
>>  #include <drm/drm_gem.h>
>>  #include <drm/drm_gem_atomic_helper.h>
>> @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct
>> intel_plane_state *plane_state)
>>  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));  }
>> 
>> +static void
>> +intel_plane_check_plane_damage(struct intel_plane_state
>> *new_plane_state,
>> +			       const struct intel_plane_state
>> *old_primary_plane_state,
>> +			       const struct intel_plane_state
>> *new_primary_plane_state) {
>> +	struct intel_display *display = to_intel_display(new_plane_state);
>> +	struct drm_rect *damage_merged = &new_plane_state-
>> >damage_merged;
>> +
>> +	if (!HAS_FBC_DIRTY_RECT(display))
>> +		return;
>> +
>> +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state-
>> >uapi,
>> +					     &new_primary_plane_state->uapi,
>> +					     damage_merged))
>> +		/* Incase helper fails, mark whole plane region as damage */
>> +		*damage_merged =
>> +			drm_plane_state_src(&new_primary_plane_state-
>> >uapi);
>> +}
>> +
>>  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
>> *plane_state,
>>  				       const struct intel_plane_state
>> *from_plane_state,
>>  				       struct intel_crtc *crtc)
>> @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct
>> intel_atomic_state *state,
>>  	const struct intel_plane_state *old_plane_state =
>>  		intel_atomic_get_old_plane_state(state, plane);
>>  	const struct intel_plane_state *new_primary_crtc_plane_state;
>> +	const struct intel_plane_state *old_primary_crtc_plane_state;
>>  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
>>  	const struct intel_crtc_state *old_crtc_state =
>>  		intel_atomic_get_old_crtc_state(state, crtc); @@ -705,10
>> +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
>> 
>>  		new_primary_crtc_plane_state =
>>  			intel_atomic_get_new_plane_state(state,
>> primary_crtc_plane);
>> +		old_primary_crtc_plane_state =
>> +			intel_atomic_get_old_plane_state(state,
>> primary_crtc_plane);
>>  	} else {
>>  		new_primary_crtc_plane_state = new_plane_state;
>> +		old_primary_crtc_plane_state = old_plane_state;
>>  	}
>> 
>> +	intel_plane_check_plane_damage(new_plane_state,
>> +				       old_primary_crtc_plane_state,
>> +				       new_primary_crtc_plane_state);
>> +
>>  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
>>  					  new_primary_crtc_plane_state,
>>  					  crtc);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index cb51b7936f93..8d53bcca9614 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -695,6 +695,8 @@ struct intel_plane_state {
>>  	u64 ccval;
>> 
>>  	const char *no_fbc_reason;
>> +
>> +	struct drm_rect damage_merged;
>>  };
>> 
>>  struct intel_initial_plane_config {
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 301ad3a22c4c..b90a7d52c071 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -2249,11 +2249,42 @@ static void check_protection(struct
>> intel_plane_state *plane_state)
>>  		!plane_state->decrypt;
>>  }
>> 
>> +static void
>> +skl_plane_check_damage_with_viewport(struct intel_plane_state
>> +*plane_state) {
>> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
>> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
>> +	unsigned int rotation = plane_state->hw.rotation;
>> +	struct drm_rect *src = &plane_state->uapi.src;
>> +
>> +	if (drm_rotation_90_or_270(rotation)) {
>> +		drm_rect_rotate(damage_merged, fb->width, fb->height,
>> +				DRM_MODE_ROTATE_270);
>> +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
>> +				   -(src->x1 >> 16));
>> +	} else {
>> +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
>> +				   -(src->y1 >> 16));
>> +	}
>> +}
>> +
>> +static void
>> +skl_plane_check_damage_with_plane_surf(struct intel_plane_state
>> +*plane_state) {
>> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
>> +	struct drm_rect src;
>> +
>> +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
>> +	drm_rect_translate(damage_merged, src.x1, src.y1);
>> +	drm_rect_intersect(damage_merged, &src); }
>> +
>>  static int skl_plane_check(struct intel_crtc_state *crtc_state,
>>  			   struct intel_plane_state *plane_state)  {
>> +	struct intel_display *display = to_intel_display(crtc_state);
>>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
>
> This change of moving from dev_priv naming to i915 and to start using intel_display
> Is a refactor and should be in a patch of its own.

I think a small amount of opportunistic i915 -> display changes are
okay. But the s/dev_priv/i915/ is IMO just useless. All of them need to
go eventually, calling it i915 is not helping at this point.

BR,
Jani.

>
> Regards,
> Suraj Kandpal
>
>>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>>  	int min_scale = DRM_PLANE_NO_SCALING;
>>  	int max_scale = DRM_PLANE_NO_SCALING;
>> @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state
>> *crtc_state,
>>  	/* use scaler when colorkey is not required */
>>  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
>>  		min_scale = 1;
>> -		max_scale = skl_plane_max_scale(dev_priv, fb);
>> +		max_scale = skl_plane_max_scale(i915, fb);
>>  	}
>> 
>>  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -
>> 2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state
>> *crtc_state,
>>  	if (ret)
>>  		return ret;
>> 
>> +	if (HAS_FBC_DIRTY_RECT(display))
>> +		skl_plane_check_damage_with_viewport(plane_state);
>> +
>>  	ret = skl_check_plane_surface(plane_state);
>>  	if (ret)
>>  		return ret;
>> @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state
>> *crtc_state,
>>  	if (ret)
>>  		return ret;
>> 
>> +	if (HAS_FBC_DIRTY_RECT(display))
>> +		skl_plane_check_damage_with_plane_surf(plane_state);
>> +
>>  	ret = skl_plane_check_nv12_rotation(plane_state);
>>  	if (ret)
>>  		return ret;
>> @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state
>> *crtc_state,
>> 
>>  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
>> 
>> -	if (DISPLAY_VER(dev_priv) >= 10)
>> +	if (DISPLAY_VER(display) >= 10)
>>  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
>>  							     plane_state);
>> 
>>  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
>> -	    icl_is_hdr_plane(dev_priv, plane->id))
>> +	    icl_is_hdr_plane(i915, plane->id))
>>  		/* Enable and use MPEG-2 chroma siting */
>>  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
>>  			PLANE_CUS_HPHASE_0 |
>> --
>> 2.43.0
>

-- 
Jani Nikula, Intel

Re: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Govindapillai, Vinod]

On Wed, 2025-02-05 at 12:08 +0200, Jani Nikula wrote:
> On Wed, 05 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Vinod
> > > Govindapillai
> > > Sent: Friday, January 31, 2025 2:30 AM
> > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> > > <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
> > > <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
> > > <jani.saarinen@intel.com>
> > > Subject: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage
> > > clips
> > > 
> > > Userspace can pass damage area clips per plane to track changes in a plane
> > > and some display components can utilze these damage clips for efficiently
> > > handling use cases like FBC, PSR etc. A merged damage area is generated and
> > > its coordinates are updated relative to viewport and HW and stored in the
> > > plane_state. This merged damage areas will be used for FBC dirty rect support
> > > in xe3 in the follow-up patch.
> > > 
> > > Big thanks to Ville Syrjala for his contribuitions in shaping up of this series.
> > > 
> > > v1: - Move damage_merged helper to cover bigjoiner case and use
> > >     the correct plane state for damage find helper (Ville)
> > >     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
> > >     the related part will be executed only for xe3+
> > >     - Changed dev_priv to i915 in one of the functions
> > > 
> > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
> > >  .../drm/i915/display/intel_display_types.h    |  2 +
> > >  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
> > >  3 files changed, 71 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index c558143f4f82..f55f7044dc67 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -36,6 +36,7 @@
> > > 
> > >  #include <drm/drm_atomic_helper.h>
> > >  #include <drm/drm_blend.h>
> > > +#include <drm/drm_damage_helper.h>
> > >  #include <drm/drm_fourcc.h>
> > >  #include <drm/drm_gem.h>
> > >  #include <drm/drm_gem_atomic_helper.h>
> > > @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct
> > > intel_plane_state *plane_state)
> > >  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));  }
> > > 
> > > +static void
> > > +intel_plane_check_plane_damage(struct intel_plane_state
> > > *new_plane_state,
> > > +			       const struct intel_plane_state
> > > *old_primary_plane_state,
> > > +			       const struct intel_plane_state
> > > *new_primary_plane_state) {
> > > +	struct intel_display *display = to_intel_display(new_plane_state);
> > > +	struct drm_rect *damage_merged = &new_plane_state-
> > > > damage_merged;
> > > +
> > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > +		return;
> > > +
> > > +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state-
> > > > uapi,
> > > +					     &new_primary_plane_state->uapi,
> > > +					     damage_merged))
> > > +		/* Incase helper fails, mark whole plane region as damage */
> > > +		*damage_merged =
> > > +			drm_plane_state_src(&new_primary_plane_state-
> > > > uapi);
> > > +}
> > > +
> > >  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state
> > > *plane_state,
> > >  				       const struct intel_plane_state
> > > *from_plane_state,
> > >  				       struct intel_crtc *crtc)
> > > @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct
> > > intel_atomic_state *state,
> > >  	const struct intel_plane_state *old_plane_state =
> > >  		intel_atomic_get_old_plane_state(state, plane);
> > >  	const struct intel_plane_state *new_primary_crtc_plane_state;
> > > +	const struct intel_plane_state *old_primary_crtc_plane_state;
> > >  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
> > >  	const struct intel_crtc_state *old_crtc_state =
> > >  		intel_atomic_get_old_crtc_state(state, crtc); @@ -705,10
> > > +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> > > 
> > >  		new_primary_crtc_plane_state =
> > >  			intel_atomic_get_new_plane_state(state,
> > > primary_crtc_plane);
> > > +		old_primary_crtc_plane_state =
> > > +			intel_atomic_get_old_plane_state(state,
> > > primary_crtc_plane);
> > >  	} else {
> > >  		new_primary_crtc_plane_state = new_plane_state;
> > > +		old_primary_crtc_plane_state = old_plane_state;
> > >  	}
> > > 
> > > +	intel_plane_check_plane_damage(new_plane_state,
> > > +				       old_primary_crtc_plane_state,
> > > +				       new_primary_crtc_plane_state);
> > > +
> > >  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > >  					  new_primary_crtc_plane_state,
> > >  					  crtc);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index cb51b7936f93..8d53bcca9614 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -695,6 +695,8 @@ struct intel_plane_state {
> > >  	u64 ccval;
> > > 
> > >  	const char *no_fbc_reason;
> > > +
> > > +	struct drm_rect damage_merged;
> > >  };
> > > 
> > >  struct intel_initial_plane_config {
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 301ad3a22c4c..b90a7d52c071 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -2249,11 +2249,42 @@ static void check_protection(struct
> > > intel_plane_state *plane_state)
> > >  		!plane_state->decrypt;
> > >  }
> > > 
> > > +static void
> > > +skl_plane_check_damage_with_viewport(struct intel_plane_state
> > > +*plane_state) {
> > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > +	unsigned int rotation = plane_state->hw.rotation;
> > > +	struct drm_rect *src = &plane_state->uapi.src;
> > > +
> > > +	if (drm_rotation_90_or_270(rotation)) {
> > > +		drm_rect_rotate(damage_merged, fb->width, fb->height,
> > > +				DRM_MODE_ROTATE_270);
> > > +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
> > > +				   -(src->x1 >> 16));
> > > +	} else {
> > > +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
> > > +				   -(src->y1 >> 16));
> > > +	}
> > > +}
> > > +
> > > +static void
> > > +skl_plane_check_damage_with_plane_surf(struct intel_plane_state
> > > +*plane_state) {
> > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > +	struct drm_rect src;
> > > +
> > > +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
> > > +	drm_rect_translate(damage_merged, src.x1, src.y1);
> > > +	drm_rect_intersect(damage_merged, &src); }
> > > +
> > >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  			   struct intel_plane_state *plane_state)  {
> > > +	struct intel_display *display = to_intel_display(crtc_state);
> > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > > -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > 
> > This change of moving from dev_priv naming to i915 and to start using intel_display
> > Is a refactor and should be in a patch of its own.
Such minor local changes to use intel_display are okay as per the practices so far! Before
intel_display related changes, dev_priv was being replaced by i915 and was also acceptable without a
separate patch as long as the changes are minimal and within the local context. But the recent
intel_display usage has made dev_priv replacements redundant. But replacing dev_priv to use
intel_display in this specific case needed a bigger attention to other parts! So i just combined the
previous practices! 

> 
> I think a small amount of opportunistic i915 -> display changes are
> okay. But the s/dev_priv/i915/ is IMO just useless. All of them need to
> go eventually, calling it i915 is not helping at this point.
Yeah.. just wanted to avoid someone commenting about "dev_priv" :-) 
Fully getting rid of that "dev_priv/i915" need bit bigger changes! 

BR
Vinod

> 
> BR,
> Jani.
> 
> > 
> > Regards,
> > Suraj Kandpal
> > 
> > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  	int min_scale = DRM_PLANE_NO_SCALING;
> > >  	int max_scale = DRM_PLANE_NO_SCALING;
> > > @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state
> > > *crtc_state,
> > >  	/* use scaler when colorkey is not required */
> > >  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
> > >  		min_scale = 1;
> > > -		max_scale = skl_plane_max_scale(dev_priv, fb);
> > > +		max_scale = skl_plane_max_scale(i915, fb);
> > >  	}
> > > 
> > >  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -
> > > 2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state
> > > *crtc_state,
> > >  	if (ret)
> > >  		return ret;
> > > 
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		skl_plane_check_damage_with_viewport(plane_state);
> > > +
> > >  	ret = skl_check_plane_surface(plane_state);
> > >  	if (ret)
> > >  		return ret;
> > > @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state
> > > *crtc_state,
> > >  	if (ret)
> > >  		return ret;
> > > 
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		skl_plane_check_damage_with_plane_surf(plane_state);
> > > +
> > >  	ret = skl_plane_check_nv12_rotation(plane_state);
> > >  	if (ret)
> > >  		return ret;
> > > @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state
> > > *crtc_state,
> > > 
> > >  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> > > 
> > > -	if (DISPLAY_VER(dev_priv) >= 10)
> > > +	if (DISPLAY_VER(display) >= 10)
> > >  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
> > >  							     plane_state);
> > > 
> > >  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> > > -	    icl_is_hdr_plane(dev_priv, plane->id))
> > > +	    icl_is_hdr_plane(i915, plane->id))
> > >  		/* Enable and use MPEG-2 chroma siting */
> > >  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> > >  			PLANE_CUS_HPHASE_0 |
> > > --
> > > 2.43.0
> > 
> 

Re: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Ville Syrjälä]

On Thu, Jan 30, 2025 at 11:00:23PM +0200, Vinod Govindapillai wrote:
> Userspace can pass damage area clips per plane to track
> changes in a plane and some display components can utilze
> these damage clips for efficiently handling use cases like
> FBC, PSR etc. A merged damage area is generated and its
> coordinates are updated relative to viewport and HW and
> stored in the plane_state. This merged damage areas will be
> used for FBC dirty rect support in xe3 in the follow-up
> patch.
> 
> Big thanks to Ville Syrjala for his contribuitions in shaping
> up of this series.
> 
> v1: - Move damage_merged helper to cover bigjoiner case and use
>     the correct plane state for damage find helper (Ville)
>     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
>     the related part will be executed only for xe3+
>     - Changed dev_priv to i915 in one of the functions
> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
>  3 files changed, 71 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c558143f4f82..f55f7044dc67 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -36,6 +36,7 @@
>  
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_blend.h>
> +#include <drm/drm_damage_helper.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_gem.h>
>  #include <drm/drm_gem_atomic_helper.h>
> @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
>  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
>  }
>  
> +static void
> +intel_plane_check_plane_damage(struct intel_plane_state *new_plane_state,
> +			       const struct intel_plane_state *old_primary_plane_state,
> +			       const struct intel_plane_state *new_primary_plane_state)

"primary_plane_state" is a confusing name because "primary plane"
generally means something totally different than what's used here.
probably we should just call these "uapi_plane_state" or something.

> +{
> +	struct intel_display *display = to_intel_display(new_plane_state);
> +	struct drm_rect *damage_merged = &new_plane_state->damage_merged;
> +
> +	if (!HAS_FBC_DIRTY_RECT(display))
> +		return;
> +
> +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state->uapi,
> +					     &new_primary_plane_state->uapi,
> +					     damage_merged))
> +		/* Incase helper fails, mark whole plane region as damage */
> +		*damage_merged =
> +			drm_plane_state_src(&new_primary_plane_state->uapi);
> +}
> +
>  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>  				       const struct intel_plane_state *from_plane_state,
>  				       struct intel_crtc *crtc)
> @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
>  	const struct intel_plane_state *old_plane_state =
>  		intel_atomic_get_old_plane_state(state, plane);
>  	const struct intel_plane_state *new_primary_crtc_plane_state;
> +	const struct intel_plane_state *old_primary_crtc_plane_state;
>  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
> @@ -705,10 +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
>  
>  		new_primary_crtc_plane_state =
>  			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
> +		old_primary_crtc_plane_state =
> +			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
>  	} else {
>  		new_primary_crtc_plane_state = new_plane_state;
> +		old_primary_crtc_plane_state = old_plane_state;
>  	}
>  
> +	intel_plane_check_plane_damage(new_plane_state,
> +				       old_primary_crtc_plane_state,
> +				       new_primary_crtc_plane_state);
> +
>  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
>  					  new_primary_crtc_plane_state,
>  					  crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index cb51b7936f93..8d53bcca9614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -695,6 +695,8 @@ struct intel_plane_state {
>  	u64 ccval;
>  
>  	const char *no_fbc_reason;
> +
> +	struct drm_rect damage_merged;

Since this is only used for the fbc stuff I would just
call it 'fbc_dirty'. Though I suppose if we were to also
use this for the PSR stuff then "damage" might be a decent
name. The _merged part is pointless imo.

>  };
>  
>  struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 301ad3a22c4c..b90a7d52c071 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2249,11 +2249,42 @@ static void check_protection(struct intel_plane_state *plane_state)
>  		!plane_state->decrypt;
>  }
>  
> +static void
> +skl_plane_check_damage_with_viewport(struct intel_plane_state *plane_state)
> +{
> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +	unsigned int rotation = plane_state->hw.rotation;
> +	struct drm_rect *src = &plane_state->uapi.src;

const

> +
> +	if (drm_rotation_90_or_270(rotation)) {
> +		drm_rect_rotate(damage_merged, fb->width, fb->height,

fb might be NULL here. 

I guess we might as well do something like:
if (!visible) -> make the dirty rect empty

> +				DRM_MODE_ROTATE_270);
> +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
> +				   -(src->x1 >> 16));
> +	} else {
> +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
> +				   -(src->y1 >> 16));
> +	}
> +}
> +
> +static void
> +skl_plane_check_damage_with_plane_surf(struct intel_plane_state *plane_state)

the "with" stuff in the name is a bit confusing. What we are doing 
is make the rectangle relative to plane SURF. Same story with the
other function.

> +{
> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> +	struct drm_rect src;
> +
> +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
> +	drm_rect_translate(damage_merged, src.x1, src.y1);
> +	drm_rect_intersect(damage_merged, &src);

Missing the "make it at last one scanline" here. Though if we do
decide to use this also for PSR then I guess we'd need to handle
that elsewhere. For now it could just be here.

> +}
> +
>  static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  			   struct intel_plane_state *plane_state)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int min_scale = DRM_PLANE_NO_SCALING;
>  	int max_scale = DRM_PLANE_NO_SCALING;
> @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  	/* use scaler when colorkey is not required */
>  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
>  		min_scale = 1;
> -		max_scale = skl_plane_max_scale(dev_priv, fb);
> +		max_scale = skl_plane_max_scale(i915, fb);
>  	}
>  
>  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> @@ -2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		skl_plane_check_damage_with_viewport(plane_state);
> +
>  	ret = skl_check_plane_surface(plane_state);
>  	if (ret)
>  		return ret;
> @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		skl_plane_check_damage_with_plane_surf(plane_state);
> +
>  	ret = skl_plane_check_nv12_rotation(plane_state);
>  	if (ret)
>  		return ret;
> @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  
>  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
>  
> -	if (DISPLAY_VER(dev_priv) >= 10)
> +	if (DISPLAY_VER(display) >= 10)
>  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
>  							     plane_state);
>  
>  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> -	    icl_is_hdr_plane(dev_priv, plane->id))
> +	    icl_is_hdr_plane(i915, plane->id))
>  		/* Enable and use MPEG-2 chroma siting */
>  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
>  			PLANE_CUS_HPHASE_0 |
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Govindapillai, Vinod]

Thanks Ville for the review..

Some responses and clarifications inline..

On Wed, 2025-02-05 at 14:43 +0200, Ville Syrjälä wrote:
> On Thu, Jan 30, 2025 at 11:00:23PM +0200, Vinod Govindapillai wrote:
> > Userspace can pass damage area clips per plane to track
> > changes in a plane and some display components can utilze
> > these damage clips for efficiently handling use cases like
> > FBC, PSR etc. A merged damage area is generated and its
> > coordinates are updated relative to viewport and HW and
> > stored in the plane_state. This merged damage areas will be
> > used for FBC dirty rect support in xe3 in the follow-up
> > patch.
> > 
> > Big thanks to Ville Syrjala for his contribuitions in shaping
> > up of this series.
> > 
> > v1: - Move damage_merged helper to cover bigjoiner case and use
> >     the correct plane state for damage find helper (Ville)
> >     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
> >     the related part will be executed only for xe3+
> >     - Changed dev_priv to i915 in one of the functions
> > 
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
> >  .../drm/i915/display/intel_display_types.h    |  2 +
> >  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
> >  3 files changed, 71 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index c558143f4f82..f55f7044dc67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -36,6 +36,7 @@
> >  
> >  #include <drm/drm_atomic_helper.h>
> >  #include <drm/drm_blend.h>
> > +#include <drm/drm_damage_helper.h>
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_gem.h>
> >  #include <drm/drm_gem_atomic_helper.h>
> > @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state
> > *plane_state)
> >  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
> >  }
> >  
> > +static void
> > +intel_plane_check_plane_damage(struct intel_plane_state *new_plane_state,
> > +			       const struct intel_plane_state *old_primary_plane_state,
> > +			       const struct intel_plane_state *new_primary_plane_state)
> 
> "primary_plane_state" is a confusing name because "primary plane"
> generally means something totally different than what's used here.
> probably we should just call these "uapi_plane_state" or something.

Okay! At this function call it is still intel_plane_state, could it be old_primary_crtc_plane_sate
and new_primary_crtc_plane_state? Or do you meant to change these parameters to old_uapi_plane_state
and new_uapi_plane_state?

> 
> > +{
> > +	struct intel_display *display = to_intel_display(new_plane_state);
> > +	struct drm_rect *damage_merged = &new_plane_state->damage_merged;
> > +
> > +	if (!HAS_FBC_DIRTY_RECT(display))
> > +		return;
> > +
> > +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state->uapi,
> > +					     &new_primary_plane_state->uapi,
> > +					     damage_merged))
> > +		/* Incase helper fails, mark whole plane region as damage */
> > +		*damage_merged =
> > +			drm_plane_state_src(&new_primary_plane_state->uapi);
> > +}
> > +
> >  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> >  				       const struct intel_plane_state *from_plane_state,
> >  				       struct intel_crtc *crtc)
> > @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> >  	const struct intel_plane_state *old_plane_state =
> >  		intel_atomic_get_old_plane_state(state, plane);
> >  	const struct intel_plane_state *new_primary_crtc_plane_state;
> > +	const struct intel_plane_state *old_primary_crtc_plane_state;
> >  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
> >  	const struct intel_crtc_state *old_crtc_state =
> >  		intel_atomic_get_old_crtc_state(state, crtc);
> > @@ -705,10 +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> >  
> >  		new_primary_crtc_plane_state =
> >  			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
> > +		old_primary_crtc_plane_state =
> > +			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
> >  	} else {
> >  		new_primary_crtc_plane_state = new_plane_state;
> > +		old_primary_crtc_plane_state = old_plane_state;
> >  	}
> >  
> > +	intel_plane_check_plane_damage(new_plane_state,
> > +				       old_primary_crtc_plane_state,
> > +				       new_primary_crtc_plane_state);
> > +
> >  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
> >  					  new_primary_crtc_plane_state,
> >  					  crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index cb51b7936f93..8d53bcca9614 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -695,6 +695,8 @@ struct intel_plane_state {
> >  	u64 ccval;
> >  
> >  	const char *no_fbc_reason;
> > +
> > +	struct drm_rect damage_merged;
> 
> Since this is only used for the fbc stuff I would just
> call it 'fbc_dirty'. Though I suppose if we were to also
> use this for the PSR stuff then "damage" might be a decent
> name. The _merged part is pointless imo.

Yes. I was thinking if PSR can also use it at some point. But I can change it to fbc_dirty

> 
> >  };
> >  
> >  struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 301ad3a22c4c..b90a7d52c071 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2249,11 +2249,42 @@ static void check_protection(struct intel_plane_state *plane_state)
> >  		!plane_state->decrypt;
> >  }
> >  
> > +static void
> > +skl_plane_check_damage_with_viewport(struct intel_plane_state *plane_state)
> > +{
> > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > +	unsigned int rotation = plane_state->hw.rotation;
> > +	struct drm_rect *src = &plane_state->uapi.src;
> 
> const

Ack.

> 
> > +
> > +	if (drm_rotation_90_or_270(rotation)) {
> > +		drm_rect_rotate(damage_merged, fb->width, fb->height,
> 
> fb might be NULL here. 
> 
> I guess we might as well do something like:
> if (!visible) -> make the dirty rect empty

Actually, the drm_atomic_helper_damage_merged() returns false in case the plane not visible. Then
intel_plane_check_plane_damage() makes the damage area as a full plane region!

So will check if (plane_state->uapi.visible) before calling the functions to make rect relative to
viewport and plane SURF.

So the fbc_dirty will point to whole plane in such cases. And in the FBC dirty rect handling part
plane->visible condition is checked.

What do you think about this?

> 
> > +				DRM_MODE_ROTATE_270);
> > +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
> > +				   -(src->x1 >> 16));
> > +	} else {
> > +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
> > +				   -(src->y1 >> 16));
> > +	}
> > +}
> > +
> > +static void
> > +skl_plane_check_damage_with_plane_surf(struct intel_plane_state *plane_state)
> 
> the "with" stuff in the name is a bit confusing. What we are doing 
> is make the rectangle relative to plane SURF. Same story with the
> other function.

Sure. How about
skl_plane_check_fbc_dirty_relativeto_viewport()
skl_plane_check_fbc_dirty_relativeto_plane_surf()

> 
> > +{
> > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > +	struct drm_rect src;
> > +
> > +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
> > +	drm_rect_translate(damage_merged, src.x1, src.y1);
> > +	drm_rect_intersect(damage_merged, &src);
> 
> Missing the "make it at last one scanline" here. Though if we do
> decide to use this also for PSR then I guess we'd need to handle
> that elsewhere. For now it could just be here.

I am doing that as part of the FBC dirty prepare.
Isnt it really a FBC dirty rect validation restriction than here?

BR
Vinod

> 
> > +}
> > +
> >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  			   struct intel_plane_state *plane_state)
> >  {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> >  	int min_scale = DRM_PLANE_NO_SCALING;
> >  	int max_scale = DRM_PLANE_NO_SCALING;
> > @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  	/* use scaler when colorkey is not required */
> >  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
> >  		min_scale = 1;
> > -		max_scale = skl_plane_max_scale(dev_priv, fb);
> > +		max_scale = skl_plane_max_scale(i915, fb);
> >  	}
> >  
> >  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > @@ -2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > +	if (HAS_FBC_DIRTY_RECT(display))
> > +		skl_plane_check_damage_with_viewport(plane_state);
> > +
> >  	ret = skl_check_plane_surface(plane_state);
> >  	if (ret)
> >  		return ret;
> > @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > +	if (HAS_FBC_DIRTY_RECT(display))
> > +		skl_plane_check_damage_with_plane_surf(plane_state);
> > +
> >  	ret = skl_plane_check_nv12_rotation(plane_state);
> >  	if (ret)
> >  		return ret;
> > @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> >  
> >  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> >  
> > -	if (DISPLAY_VER(dev_priv) >= 10)
> > +	if (DISPLAY_VER(display) >= 10)
> >  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
> >  							     plane_state);
> >  
> >  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> > -	    icl_is_hdr_plane(dev_priv, plane->id))
> > +	    icl_is_hdr_plane(i915, plane->id))
> >  		/* Enable and use MPEG-2 chroma siting */
> >  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> >  			PLANE_CUS_HPHASE_0 |
> > -- 
> > 2.43.0
> 

Re: [PATCH v6 4/7] drm/i915/xe3: update and store the plane damage clips

[Ville Syrjälä]

On Wed, Feb 05, 2025 at 01:29:30PM +0000, Govindapillai, Vinod wrote:
> Thanks Ville for the review..
> 
> Some responses and clarifications inline..
> 
> On Wed, 2025-02-05 at 14:43 +0200, Ville Syrjälä wrote:
> > On Thu, Jan 30, 2025 at 11:00:23PM +0200, Vinod Govindapillai wrote:
> > > Userspace can pass damage area clips per plane to track
> > > changes in a plane and some display components can utilze
> > > these damage clips for efficiently handling use cases like
> > > FBC, PSR etc. A merged damage area is generated and its
> > > coordinates are updated relative to viewport and HW and
> > > stored in the plane_state. This merged damage areas will be
> > > used for FBC dirty rect support in xe3 in the follow-up
> > > patch.
> > > 
> > > Big thanks to Ville Syrjala for his contribuitions in shaping
> > > up of this series.
> > > 
> > > v1: - Move damage_merged helper to cover bigjoiner case and use
> > >     the correct plane state for damage find helper (Ville)
> > >     - Damage handling code under HAS_FBC_DIRTY_RECT() so the
> > >     the related part will be executed only for xe3+
> > >     - Changed dev_priv to i915 in one of the functions
> > > 
> > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_atomic_plane.c | 28 ++++++++++++
> > >  .../drm/i915/display/intel_display_types.h    |  2 +
> > >  .../drm/i915/display/skl_universal_plane.c    | 45 +++++++++++++++++--
> > >  3 files changed, 71 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index c558143f4f82..f55f7044dc67 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -36,6 +36,7 @@
> > >  
> > >  #include <drm/drm_atomic_helper.h>
> > >  #include <drm/drm_blend.h>
> > > +#include <drm/drm_damage_helper.h>
> > >  #include <drm/drm_fourcc.h>
> > >  #include <drm/drm_gem.h>
> > >  #include <drm/drm_gem_atomic_helper.h>
> > > @@ -322,6 +323,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state
> > > *plane_state)
> > >  	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
> > >  }
> > >  
> > > +static void
> > > +intel_plane_check_plane_damage(struct intel_plane_state *new_plane_state,
> > > +			       const struct intel_plane_state *old_primary_plane_state,
> > > +			       const struct intel_plane_state *new_primary_plane_state)
> > 
> > "primary_plane_state" is a confusing name because "primary plane"
> > generally means something totally different than what's used here.
> > probably we should just call these "uapi_plane_state" or something.
> 
> Okay! At this function call it is still intel_plane_state, could it be old_primary_crtc_plane_sate
> and new_primary_crtc_plane_state? Or do you meant to change these parameters to old_uapi_plane_state
> and new_uapi_plane_state?

We should probably change all of them. But that should be a separate
patch.

> 
> > 
> > > +{
> > > +	struct intel_display *display = to_intel_display(new_plane_state);
> > > +	struct drm_rect *damage_merged = &new_plane_state->damage_merged;
> > > +
> > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > +		return;
> > > +
> > > +	if (!drm_atomic_helper_damage_merged(&old_primary_plane_state->uapi,
> > > +					     &new_primary_plane_state->uapi,
> > > +					     damage_merged))
> > > +		/* Incase helper fails, mark whole plane region as damage */
> > > +		*damage_merged =
> > > +			drm_plane_state_src(&new_primary_plane_state->uapi);
> > > +}
> > > +
> > >  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> > >  				       const struct intel_plane_state *from_plane_state,
> > >  				       struct intel_crtc *crtc)
> > > @@ -691,6 +711,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> > >  	const struct intel_plane_state *old_plane_state =
> > >  		intel_atomic_get_old_plane_state(state, plane);
> > >  	const struct intel_plane_state *new_primary_crtc_plane_state;
> > > +	const struct intel_plane_state *old_primary_crtc_plane_state;
> > >  	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
> > >  	const struct intel_crtc_state *old_crtc_state =
> > >  		intel_atomic_get_old_crtc_state(state, crtc);
> > > @@ -705,10 +726,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> > >  
> > >  		new_primary_crtc_plane_state =
> > >  			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
> > > +		old_primary_crtc_plane_state =
> > > +			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
> > >  	} else {
> > >  		new_primary_crtc_plane_state = new_plane_state;
> > > +		old_primary_crtc_plane_state = old_plane_state;
> > >  	}
> > >  
> > > +	intel_plane_check_plane_damage(new_plane_state,
> > > +				       old_primary_crtc_plane_state,
> > > +				       new_primary_crtc_plane_state);
> > > +
> > >  	intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > >  					  new_primary_crtc_plane_state,
> > >  					  crtc);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index cb51b7936f93..8d53bcca9614 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -695,6 +695,8 @@ struct intel_plane_state {
> > >  	u64 ccval;
> > >  
> > >  	const char *no_fbc_reason;
> > > +
> > > +	struct drm_rect damage_merged;
> > 
> > Since this is only used for the fbc stuff I would just
> > call it 'fbc_dirty'. Though I suppose if we were to also
> > use this for the PSR stuff then "damage" might be a decent
> > name. The _merged part is pointless imo.
> 
> Yes. I was thinking if PSR can also use it at some point. But I can change it to fbc_dirty

Hmm. Maybe leave it as "damage". And since it's ephemeral it should
be cleared out in intel_plane_duplicate_state(). And then the "we need
at least one scanline for FBC" thing does need to be handle somewhere
later.

> 
> > 
> > >  };
> > >  
> > >  struct intel_initial_plane_config {
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 301ad3a22c4c..b90a7d52c071 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -2249,11 +2249,42 @@ static void check_protection(struct intel_plane_state *plane_state)
> > >  		!plane_state->decrypt;
> > >  }
> > >  
> > > +static void
> > > +skl_plane_check_damage_with_viewport(struct intel_plane_state *plane_state)
> > > +{
> > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > +	unsigned int rotation = plane_state->hw.rotation;
> > > +	struct drm_rect *src = &plane_state->uapi.src;
> > 
> > const
> 
> Ack.
> 
> > 
> > > +
> > > +	if (drm_rotation_90_or_270(rotation)) {
> > > +		drm_rect_rotate(damage_merged, fb->width, fb->height,
> > 
> > fb might be NULL here. 
> > 
> > I guess we might as well do something like:
> > if (!visible) -> make the dirty rect empty
> 
> Actually, the drm_atomic_helper_damage_merged() returns false in case the plane not visible. Then
> intel_plane_check_plane_damage() makes the damage area as a full plane region!
> 
> So will check if (plane_state->uapi.visible) before calling the functions to make rect relative to
> viewport and plane SURF.
> 
> So the fbc_dirty will point to whole plane in such cases. And in the FBC dirty rect handling part
> plane->visible condition is checked.
> 
> What do you think about this?

If the plane is invisible there should be no damage.

> 
> > 
> > > +				DRM_MODE_ROTATE_270);
> > > +		drm_rect_translate(damage_merged, -(src->y1 >> 16),
> > > +				   -(src->x1 >> 16));
> > > +	} else {
> > > +		drm_rect_translate(damage_merged, -(src->x1 >> 16),
> > > +				   -(src->y1 >> 16));
> > > +	}
> > > +}
> > > +
> > > +static void
> > > +skl_plane_check_damage_with_plane_surf(struct intel_plane_state *plane_state)
> > 
> > the "with" stuff in the name is a bit confusing. What we are doing 
> > is make the rectangle relative to plane SURF. Same story with the
> > other function.
> 
> Sure. How about
> skl_plane_check_fbc_dirty_relativeto_viewport()
> skl_plane_check_fbc_dirty_relativeto_plane_surf()

Still rather confusing to me. If we do leave it as just "damage" maybe
we should in fact keep it viewport relative always, then the latter
function could be called just clip_damage()/etc. The first one I
guess should be called something like make_damage_viewport_relative().

I suppose what we should really do is have
intel_atomic_plane_check_clipping() do all of it already. But that
does mean we might have to move the src coordinate tweaking
from intel_plane_check_src_coordinates() into there already.
But I haven't really though through the full implications what it
means for sub-pixel coordinates and such (not that we handle those
properly anyway atm).

> 
> > 
> > > +{
> > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > +	struct drm_rect src;
> > > +
> > > +	drm_rect_fp_to_int(&src, &plane_state->uapi.src);
> > > +	drm_rect_translate(damage_merged, src.x1, src.y1);
> > > +	drm_rect_intersect(damage_merged, &src);
> > 
> > Missing the "make it at last one scanline" here. Though if we do
> > decide to use this also for PSR then I guess we'd need to handle
> > that elsewhere. For now it could just be here.
> 
> I am doing that as part of the FBC dirty prepare.
> Isnt it really a FBC dirty rect validation restriction than here?
> 
> BR
> Vinod
> 
> > 
> > > +}
> > > +
> > >  static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  			   struct intel_plane_state *plane_state)
> > >  {
> > > +	struct intel_display *display = to_intel_display(crtc_state);
> > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > > -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  	int min_scale = DRM_PLANE_NO_SCALING;
> > >  	int max_scale = DRM_PLANE_NO_SCALING;
> > > @@ -2266,7 +2297,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  	/* use scaler when colorkey is not required */
> > >  	if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
> > >  		min_scale = 1;
> > > -		max_scale = skl_plane_max_scale(dev_priv, fb);
> > > +		max_scale = skl_plane_max_scale(i915, fb);
> > >  	}
> > >  
> > >  	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
> > > @@ -2274,6 +2305,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  	if (ret)
> > >  		return ret;
> > >  
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		skl_plane_check_damage_with_viewport(plane_state);
> > > +
> > >  	ret = skl_check_plane_surface(plane_state);
> > >  	if (ret)
> > >  		return ret;
> > > @@ -2289,6 +2323,9 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  	if (ret)
> > >  		return ret;
> > >  
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		skl_plane_check_damage_with_plane_surf(plane_state);
> > > +
> > >  	ret = skl_plane_check_nv12_rotation(plane_state);
> > >  	if (ret)
> > >  		return ret;
> > > @@ -2301,12 +2338,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > >  
> > >  	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> > >  
> > > -	if (DISPLAY_VER(dev_priv) >= 10)
> > > +	if (DISPLAY_VER(display) >= 10)
> > >  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
> > >  							     plane_state);
> > >  
> > >  	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> > > -	    icl_is_hdr_plane(dev_priv, plane->id))
> > > +	    icl_is_hdr_plane(i915, plane->id))
> > >  		/* Enable and use MPEG-2 chroma siting */
> > >  		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> > >  			PLANE_CUS_HPHASE_0 |
> > > -- 
> > > 2.43.0
> > 
> 

-- 
Ville Syrjälä
Intel

[PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Vinod Govindapillai]

Dirty rectangle feature allows FBC to recompress a subsection
of a frame. When this feature is enabled, display will read
the scan lines between dirty rectangle start line and dirty
rectangle end line in subsequent frames.

Use the merged damage clip stored in the plane state to
configure the FBC dirty rect areas.

v2: - Move dirty rect handling to fbc state (Ville)

v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
    - Split plane damage collection and dirty rect preparation
    - Handle case where dirty rect fall outside the visible region

v4: - A state variable to check if we need to update dirty rect
    registers in case intel_fbc_can_flip_nuke() (Ville)

Bspec: 68881, 71675, 73424
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |   7 +
 drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
 3 files changed, 145 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d68d652c1bc..33277f892279 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 
 		commit_pipe_pre_planes(state, crtc);
 
+		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
+
 		intel_crtc_planes_update_arm(NULL, state, crtc);
 
 		commit_pipe_post_planes(state, crtc);
@@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 						 new_crtc_state);
 		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
 					       state, crtc);
+		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
+						  state, crtc);
 
 		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
 
@@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	intel_atomic_prepare_plane_clear_colors(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+		intel_fbc_prepare_dirty_rect(state, crtc);
+
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
 		intel_atomic_dsb_finish(state, crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index df05904bac8a..24736c7a79a6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -88,6 +88,10 @@ struct intel_fbc_state {
 	u16 override_cfb_stride;
 	u16 interval;
 	s8 fence_id;
+	struct {
+		struct drm_rect rect;
+		bool valid;
+	} fbc_dirty_rect;
 };
 
 struct intel_fbc {
@@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
 	struct intel_display *display = fbc->display;
 	u32 dpfc_ctl;
 
+	if (HAS_FBC_DIRTY_RECT(display))
+		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
+
 	/* Disable compression */
 	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
 	if (dpfc_ctl & DPFC_CTL_EN) {
@@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
 	if (DISPLAY_VER(display) >= 20)
 		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
 
+	if (HAS_FBC_DIRTY_RECT(display))
+		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
+			       FBC_DIRTY_RECT_EN);
+
 	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
 		       DPFC_CTL_EN | dpfc_ctl);
 }
@@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
 		return i8xx_fbc_tiling_valid(plane_state);
 }
 
+static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc,
+				    struct intel_plane *plane);
+
+static void
+intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
+{
+	struct intel_display *display = to_intel_display(plane);
+	struct intel_fbc *fbc = plane->fbc;
+	struct intel_fbc_state *fbc_state = &fbc->state;
+	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
+
+	if (fbc_state->plane != plane)
+		return;
+
+	if (!fbc_state->fbc_dirty_rect.valid)
+		return;
+
+	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
+			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
+			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
+
+	fbc_state->fbc_dirty_rect.valid = false;
+}
+
+void
+intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
+				  struct intel_atomic_state *state,
+				  struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
+	int i;
+
+	if (!HAS_FBC_DIRTY_RECT(display))
+		return;
+
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		struct intel_fbc *fbc = plane->fbc;
+
+		if (!fbc || plane->pipe != crtc->pipe)
+			continue;
+
+		if (!plane_state->uapi.visible)
+			continue;
+
+		intel_fbc_dirty_rect_update(dsb, plane);
+	}
+}
+
+static void
+validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
+			     struct drm_rect *dirty_rect)
+{
+	int y_offset = plane_state->view.color_plane[0].y;
+	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
+	int max_endline = y_offset + plane_height - 1;
+
+	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
+	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
+}
+
+static void
+__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
+			       struct intel_plane_state *plane_state,
+			       bool fbc_dirty_rect_valid)
+{
+	struct intel_fbc_state *fbc_state = &plane->fbc->state;
+	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
+	struct drm_rect *damage_merged = &plane_state->damage_merged;
+	int y_offset = plane_state->view.color_plane[0].y;
+
+	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
+
+	if (drm_rect_visible(damage_merged)) {
+		fbc_dirty_rect->y1 = damage_merged->y1;
+		fbc_dirty_rect->y2 = damage_merged->y2;
+	} else {
+		/* If not visible, we need to set one single line */
+		fbc_dirty_rect->y1 = y_offset;
+		fbc_dirty_rect->y2 = y_offset;
+	}
+	fbc_dirty_rect->x1 = damage_merged->x1;
+	fbc_dirty_rect->x2 = damage_merged->x2;
+
+	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
+}
+
+void
+intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
+	int i;
+
+	if (!HAS_FBC_DIRTY_RECT(display))
+		return;
+
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		struct intel_fbc *fbc = plane->fbc;
+
+		if (!fbc || plane->pipe != crtc->pipe)
+			continue;
+
+		if (!fbc->state.plane)
+			continue;
+
+		/* If plane not visible, dirty rect might have invalid coordinates */
+		if (!plane_state->uapi.visible)
+			continue;
+
+		__intel_fbc_prepare_dirty_rect(plane, plane_state,
+					       intel_fbc_can_flip_nuke(state,
+								       crtc,
+								       plane));
+	}
+}
+
 static void intel_fbc_update_state(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc,
 				   struct intel_plane *plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index ceae55458e14..8f1b11c6f4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -14,6 +14,7 @@ struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
+struct intel_dsb;
 struct intel_fbc;
 struct intel_plane;
 struct intel_plane_state;
@@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
 void intel_fbc_reset_underrun(struct intel_display *display);
 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
 void intel_fbc_debugfs_register(struct intel_display *display);
+void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc);
+void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
+				       struct intel_atomic_state *state,
+				       struct intel_crtc *crtc);
 
 #endif /* __INTEL_FBC_H__ */
-- 
2.43.0

Re: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Ville Syrjälä]

On Thu, Jan 30, 2025 at 11:00:24PM +0200, Vinod Govindapillai wrote:
> Dirty rectangle feature allows FBC to recompress a subsection
> of a frame. When this feature is enabled, display will read
> the scan lines between dirty rectangle start line and dirty
> rectangle end line in subsequent frames.
> 
> Use the merged damage clip stored in the plane state to
> configure the FBC dirty rect areas.
> 
> v2: - Move dirty rect handling to fbc state (Ville)
> 
> v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
>     - Split plane damage collection and dirty rect preparation
>     - Handle case where dirty rect fall outside the visible region
> 
> v4: - A state variable to check if we need to update dirty rect
>     registers in case intel_fbc_can_flip_nuke() (Ville)
> 
> Bspec: 68881, 71675, 73424
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |   7 +
>  drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
>  3 files changed, 145 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7d68d652c1bc..33277f892279 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>  
>  		commit_pipe_pre_planes(state, crtc);
>  
> +		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
> +

That is not the right place for _noarm() stuff.

Hmm, maybe we should just do this as part of intel_plane_update_noarm()?
How does the dirty rect interact with async flips?

>  		intel_crtc_planes_update_arm(NULL, state, crtc);
>  
>  		commit_pipe_post_planes(state, crtc);
> @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  						 new_crtc_state);
>  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
>  					       state, crtc);
> +		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
> +						  state, crtc);
>  
>  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
>  
> @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  	intel_atomic_prepare_plane_clear_colors(state);
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> +		intel_fbc_prepare_dirty_rect(state, crtc);
> +
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>  		intel_atomic_dsb_finish(state, crtc);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index df05904bac8a..24736c7a79a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -88,6 +88,10 @@ struct intel_fbc_state {
>  	u16 override_cfb_stride;
>  	u16 interval;
>  	s8 fence_id;
> +	struct {
> +		struct drm_rect rect;
> +		bool valid;
> +	} fbc_dirty_rect;
>  };
>  
>  struct intel_fbc {
> @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
>  	struct intel_display *display = fbc->display;
>  	u32 dpfc_ctl;
>  
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
> +
>  	/* Disable compression */
>  	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
>  	if (dpfc_ctl & DPFC_CTL_EN) {
> @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
>  	if (DISPLAY_VER(display) >= 20)
>  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
>  
> +	if (HAS_FBC_DIRTY_RECT(display))
> +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
> +			       FBC_DIRTY_RECT_EN);
> +
>  	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
>  		       DPFC_CTL_EN | dpfc_ctl);
>  }
> @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
>  		return i8xx_fbc_tiling_valid(plane_state);
>  }
>  
> +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc,
> +				    struct intel_plane *plane);

You should put the code into a place that doesn't need this extra
declaration.

> +
> +static void
> +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
> +{
> +	struct intel_display *display = to_intel_display(plane);
> +	struct intel_fbc *fbc = plane->fbc;
> +	struct intel_fbc_state *fbc_state = &fbc->state;
> +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> +
> +	if (fbc_state->plane != plane)
> +		return;
> +
> +	if (!fbc_state->fbc_dirty_rect.valid)
> +		return;

I think that extra flag can be thrown out and you can just
check if the rect is visible here.

> +
> +	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> +			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> +			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> +
> +	fbc_state->fbc_dirty_rect.valid = false;

Why?

> +}
> +
> +void
> +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> +				  struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_plane_state *plane_state;

const, although it seems to me we can just rely on the rect being valid
or not and then the plane visiblility is also already covered.

> +	struct intel_plane *plane;
> +	int i;
> +
> +	if (!HAS_FBC_DIRTY_RECT(display))
> +		return;
> +
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		struct intel_fbc *fbc = plane->fbc;
> +
> +		if (!fbc || plane->pipe != crtc->pipe)
> +			continue;
> +
> +		if (!plane_state->uapi.visible)
> +			continue;

That check would also disappear.

This does need to check if the plane is the one using FBC
currently. Oh, I see you put that check inside
intel_fbc_dirty_rect_update(). I think the check belongs
here because that is how we do it everwhere else.

I was pondering if we need to keep this lockless or not.
I guess we don't since we are doing it from the noarm()
section (assuming we're not planing to implement mailbox
flips tomorrow). So for now I think we can just do the proper
locking here too. If we do need to make this lockless in
then we need to explain what makes it safe/correct.

> +
> +		intel_fbc_dirty_rect_update(dsb, plane);
> +	}
> +}
> +
> +static void
> +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
> +			     struct drm_rect *dirty_rect)
> +{
> +	int y_offset = plane_state->view.color_plane[0].y;
> +	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
> +	int max_endline = y_offset + plane_height - 1;
> +
> +	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
> +	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
> +}

This is not needed.

> +
> +static void
> +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
> +			       struct intel_plane_state *plane_state,
> +			       bool fbc_dirty_rect_valid)
> +{
> +	struct intel_fbc_state *fbc_state = &plane->fbc->state;
> +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> +	int y_offset = plane_state->view.color_plane[0].y;
> +
> +	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
> +
> +	if (drm_rect_visible(damage_merged)) {
> +		fbc_dirty_rect->y1 = damage_merged->y1;
> +		fbc_dirty_rect->y2 = damage_merged->y2;
> +	} else {
> +		/* If not visible, we need to set one single line */
> +		fbc_dirty_rect->y1 = y_offset;
> +		fbc_dirty_rect->y2 = y_offset;
> +	}
> +	fbc_dirty_rect->x1 = damage_merged->x1;
> +	fbc_dirty_rect->x2 = damage_merged->x2;
> +
> +	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
> +}
> +
> +void
> +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_plane_state *plane_state;
> +	struct intel_plane *plane;
> +	int i;
> +
> +	if (!HAS_FBC_DIRTY_RECT(display))
> +		return;
> +
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		struct intel_fbc *fbc = plane->fbc;
> +
> +		if (!fbc || plane->pipe != crtc->pipe)
> +			continue;
> +
> +		if (!fbc->state.plane)
> +			continue;

fbc->state.plane != plane

Also needs locking.

> +
> +		/* If plane not visible, dirty rect might have invalid coordinates */
> +		if (!plane_state->uapi.visible)
> +			continue;

Seems like a redundant check.

> +
> +		__intel_fbc_prepare_dirty_rect(plane, plane_state,
> +					       intel_fbc_can_flip_nuke(state,
> +								       crtc,
> +								       plane));
> +	}
> +}
> +
>  static void intel_fbc_update_state(struct intel_atomic_state *state,
>  				   struct intel_crtc *crtc,
>  				   struct intel_plane *plane)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index ceae55458e14..8f1b11c6f4d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -14,6 +14,7 @@ struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_display;
> +struct intel_dsb;
>  struct intel_fbc;
>  struct intel_plane;
>  struct intel_plane_state;
> @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
>  void intel_fbc_reset_underrun(struct intel_display *display);
>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
>  void intel_fbc_debugfs_register(struct intel_display *display);
> +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc);
> +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> +				       struct intel_atomic_state *state,
> +				       struct intel_crtc *crtc);
>  
>  #endif /* __INTEL_FBC_H__ */
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Govindapillai, Vinod]

So based on your comments on the previous patch and this one, let me conclude the changes to be done
here!

1. As part of the previous patch, we collect the fbc_dirty rect from the damage_helper call. Make
damage empty if the plane not visible. 

2. Update the FBC dirty rect registes. This do two things
	2.1 Prepare the collected FBC dirty and copy it to the correct fbc_state - 	  	
intel_fbc_prepare_dirty_rect()

	2.2 Write to the registers - intel_fbc_dirty_rect_update_noarm()

2.1 AT the beginning of the atomic_commit_tail() within the DSB block handling, calls
intel_fbc_prepare_dirty_rect() to populate fbc_state's fbc_dirty_rect structs

In the intel_fbc_prepare_dirty_rect(), 
	iterate through each plane in the atomic_state
        check the correct plane, pipe etc. Then,

	if (drm_rect_visible(damage_merged)
		update fbc_state's fbc dirty rect 
        else
		Make at it atleast one scan line and update the fbc_state's fbc_dirty rect 

2.2 Then call intel_fbc_dirty_rect_update_noarm() form intel_plane_update_noarm()
	And within in intel_fbc_dirty_rect_update_noarm() just update the FBC dirty registers with
the values from corresponding fbc_state->fbc_dirty 


I think last time when we discussed, we decided keep that valid flag to track
intel_fbc_can_flip_nuke() case. So I guess that is not required anymore

Regarding the async flip cases, I thought nothing specific need to be done for the fbc dirty rect.
Atleast the some the tests I tried were passing with dirty rect enabled.

I will add the locks in these new functions.

BR
Vinod


On Wed, 2025-02-05 at 15:31 +0200, Ville Syrjälä wrote:
> On Thu, Jan 30, 2025 at 11:00:24PM +0200, Vinod Govindapillai wrote:
> > Dirty rectangle feature allows FBC to recompress a subsection
> > of a frame. When this feature is enabled, display will read
> > the scan lines between dirty rectangle start line and dirty
> > rectangle end line in subsequent frames.
> > 
> > Use the merged damage clip stored in the plane state to
> > configure the FBC dirty rect areas.
> > 
> > v2: - Move dirty rect handling to fbc state (Ville)
> > 
> > v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
> >     - Split plane damage collection and dirty rect preparation
> >     - Handle case where dirty rect fall outside the visible region
> > 
> > v4: - A state variable to check if we need to update dirty rect
> >     registers in case intel_fbc_can_flip_nuke() (Ville)
> > 
> > Bspec: 68881, 71675, 73424
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c |   7 +
> >  drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
> >  3 files changed, 145 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7d68d652c1bc..33277f892279 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> >  
> >  		commit_pipe_pre_planes(state, crtc);
> >  
> > +		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
> > +
> 
> That is not the right place for _noarm() stuff.
> 
> Hmm, maybe we should just do this as part of intel_plane_update_noarm()?
> How does the dirty rect interact with async flips?

Ok.

I thought no need to handle anything specific to dirty_rect in case of async flips.
Atleast the the tests that I tried were ok! 

> 
> >  		intel_crtc_planes_update_arm(NULL, state, crtc);
> >  
> >  		commit_pipe_post_planes(state, crtc);
> > @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> >  						 new_crtc_state);
> >  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
> >  					       state, crtc);
> > +		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
> > +						  state, crtc);
> >  
> >  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> >  
> > @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  
> >  	intel_atomic_prepare_plane_clear_colors(state);
> >  
> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > +		intel_fbc_prepare_dirty_rect(state, crtc);
> > +
> >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> >  		intel_atomic_dsb_finish(state, crtc);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index df05904bac8a..24736c7a79a6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -88,6 +88,10 @@ struct intel_fbc_state {
> >  	u16 override_cfb_stride;
> >  	u16 interval;
> >  	s8 fence_id;
> > +	struct {
> > +		struct drm_rect rect;
> > +		bool valid;
> > +	} fbc_dirty_rect;
> >  };
> >  
> >  struct intel_fbc {
> > @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> >  	struct intel_display *display = fbc->display;
> >  	u32 dpfc_ctl;
> >  
> > +	if (HAS_FBC_DIRTY_RECT(display))
> > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
> > +
> >  	/* Disable compression */
> >  	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
> >  	if (dpfc_ctl & DPFC_CTL_EN) {
> > @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> >  	if (DISPLAY_VER(display) >= 20)
> >  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> >  
> > +	if (HAS_FBC_DIRTY_RECT(display))
> > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
> > +			       FBC_DIRTY_RECT_EN);
> > +
> >  	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
> >  		       DPFC_CTL_EN | dpfc_ctl);
> >  }
> > @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
> >  		return i8xx_fbc_tiling_valid(plane_state);
> >  }
> >  
> > +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> > +				    struct intel_crtc *crtc,
> > +				    struct intel_plane *plane);
> 
> You should put the code into a place that doesn't need this extra
> declaration.
> 
> > +
> > +static void
> > +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
> > +{
> > +	struct intel_display *display = to_intel_display(plane);
> > +	struct intel_fbc *fbc = plane->fbc;
> > +	struct intel_fbc_state *fbc_state = &fbc->state;
> > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > +
> > +	if (fbc_state->plane != plane)
> > +		return;
> > +
> > +	if (!fbc_state->fbc_dirty_rect.valid)
> > +		return;
> 
> I think that extra flag can be thrown out and you can just
> check if the rect is visible here.
> > +
> > +	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> > +			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> > +			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> > +
> > +	fbc_state->fbc_dirty_rect.valid = false;
> 
> Why?
> 
> > +}
> > +
> > +void
> > +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > +				  struct intel_atomic_state *state,
> > +				  struct intel_crtc *crtc)
> > +{
> > +	struct intel_display *display = to_intel_display(state);
> > +	struct intel_plane_state *plane_state;
> 
> const, although it seems to me we can just rely on the rect being valid
> or not and then the plane visiblility is also already covered.
> 
> > +	struct intel_plane *plane;
> > +	int i;
> > +
> > +	if (!HAS_FBC_DIRTY_RECT(display))
> > +		return;
> > +
> > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > +		struct intel_fbc *fbc = plane->fbc;
> > +
> > +		if (!fbc || plane->pipe != crtc->pipe)
> > +			continue;
> > +
> > +		if (!plane_state->uapi.visible)
> > +			continue;
> 
> That check would also disappear.
> 
> This does need to check if the plane is the one using FBC
> currently. Oh, I see you put that check inside
> intel_fbc_dirty_rect_update(). I think the check belongs
> here because that is how we do it everwhere else.
> 
> I was pondering if we need to keep this lockless or not.
> I guess we don't since we are doing it from the noarm()
> section (assuming we're not planing to implement mailbox
> flips tomorrow). So for now I think we can just do the proper
> locking here too. If we do need to make this lockless in
> then we need to explain what makes it safe/correct.
> 
> > +
> > +		intel_fbc_dirty_rect_update(dsb, plane);
> > +	}
> > +}
> > +
> > +static void
> > +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
> > +			     struct drm_rect *dirty_rect)
> > +{
> > +	int y_offset = plane_state->view.color_plane[0].y;
> > +	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
> > +	int max_endline = y_offset + plane_height - 1;
> > +
> > +	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
> > +	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
> > +}
> 
> This is not needed.
> 
> > +
> > +static void
> > +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
> > +			       struct intel_plane_state *plane_state,
> > +			       bool fbc_dirty_rect_valid)
> > +{
> > +	struct intel_fbc_state *fbc_state = &plane->fbc->state;
> > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > +	int y_offset = plane_state->view.color_plane[0].y;
> > +
> > +	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
> > +
> > +	if (drm_rect_visible(damage_merged)) {
> > +		fbc_dirty_rect->y1 = damage_merged->y1;
> > +		fbc_dirty_rect->y2 = damage_merged->y2;
> > +	} else {
> > +		/* If not visible, we need to set one single line */
> > +		fbc_dirty_rect->y1 = y_offset;
> > +		fbc_dirty_rect->y2 = y_offset;
> > +	}
> > +	fbc_dirty_rect->x1 = damage_merged->x1;
> > +	fbc_dirty_rect->x2 = damage_merged->x2;
> > +
> > +	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
> > +}
> > +
> > +void
> > +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > +			     struct intel_crtc *crtc)
> > +{
> > +	struct intel_display *display = to_intel_display(state);
> > +	struct intel_plane_state *plane_state;
> > +	struct intel_plane *plane;
> > +	int i;
> > +
> > +	if (!HAS_FBC_DIRTY_RECT(display))
> > +		return;
> > +
> > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > +		struct intel_fbc *fbc = plane->fbc;
> > +
> > +		if (!fbc || plane->pipe != crtc->pipe)
> > +			continue;
> > +
> > +		if (!fbc->state.plane)
> > +			continue;
> 
> fbc->state.plane != plane
> 
> Also needs locking.
> 
> > +
> > +		/* If plane not visible, dirty rect might have invalid coordinates */
> > +		if (!plane_state->uapi.visible)
> > +			continue;
> 
> Seems like a redundant check.
> 
> > +
> > +		__intel_fbc_prepare_dirty_rect(plane, plane_state,
> > +					       intel_fbc_can_flip_nuke(state,
> > +								       crtc,
> > +								       plane));
> > +	}
> > +}
> > +
> >  static void intel_fbc_update_state(struct intel_atomic_state *state,
> >  				   struct intel_crtc *crtc,
> >  				   struct intel_plane *plane)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> > index ceae55458e14..8f1b11c6f4d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > @@ -14,6 +14,7 @@ struct intel_atomic_state;
> >  struct intel_crtc;
> >  struct intel_crtc_state;
> >  struct intel_display;
> > +struct intel_dsb;
> >  struct intel_fbc;
> >  struct intel_plane;
> >  struct intel_plane_state;
> > @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> >  void intel_fbc_reset_underrun(struct intel_display *display);
> >  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
> >  void intel_fbc_debugfs_register(struct intel_display *display);
> > +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > +				  struct intel_crtc *crtc);
> > +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > +				       struct intel_atomic_state *state,
> > +				       struct intel_crtc *crtc);
> >  
> >  #endif /* __INTEL_FBC_H__ */
> > -- 
> > 2.43.0
> 

Re: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Ville Syrjälä]

On Wed, Feb 05, 2025 at 02:49:46PM +0000, Govindapillai, Vinod wrote:
> So based on your comments on the previous patch and this one, let me conclude the changes to be done
> here!
> 
> 1. As part of the previous patch, we collect the fbc_dirty rect from the damage_helper call. Make
> damage empty if the plane not visible. 
> 
> 2. Update the FBC dirty rect registes. This do two things
> 	2.1 Prepare the collected FBC dirty and copy it to the correct fbc_state - 	  	
> intel_fbc_prepare_dirty_rect()
> 
> 	2.2 Write to the registers - intel_fbc_dirty_rect_update_noarm()
> 
> 2.1 AT the beginning of the atomic_commit_tail() within the DSB block handling, calls
> intel_fbc_prepare_dirty_rect() to populate fbc_state's fbc_dirty_rect structs
> 
> In the intel_fbc_prepare_dirty_rect(), 
> 	iterate through each plane in the atomic_state
>         check the correct plane, pipe etc. Then,
> 
> 	if (drm_rect_visible(damage_merged)
> 		update fbc_state's fbc dirty rect 
>         else
> 		Make at it atleast one scan line and update the fbc_state's fbc_dirty rect 
> 
> 2.2 Then call intel_fbc_dirty_rect_update_noarm() form intel_plane_update_noarm()
> 	And within in intel_fbc_dirty_rect_update_noarm() just update the FBC dirty registers with
> the values from corresponding fbc_state->fbc_dirty 
> 
> 
> I think last time when we discussed, we decided keep that valid flag to track
> intel_fbc_can_flip_nuke() case. So I guess that is not required anymore
> 
> Regarding the async flip cases, I thought nothing specific need to be done for the fbc dirty rect.
> Atleast the some the tests I tried were passing with dirty rect enabled.
> 
> I will add the locks in these new functions.
> 
> BR
> Vinod
> 
> 
> On Wed, 2025-02-05 at 15:31 +0200, Ville Syrjälä wrote:
> > On Thu, Jan 30, 2025 at 11:00:24PM +0200, Vinod Govindapillai wrote:
> > > Dirty rectangle feature allows FBC to recompress a subsection
> > > of a frame. When this feature is enabled, display will read
> > > the scan lines between dirty rectangle start line and dirty
> > > rectangle end line in subsequent frames.
> > > 
> > > Use the merged damage clip stored in the plane state to
> > > configure the FBC dirty rect areas.
> > > 
> > > v2: - Move dirty rect handling to fbc state (Ville)
> > > 
> > > v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
> > >     - Split plane damage collection and dirty rect preparation
> > >     - Handle case where dirty rect fall outside the visible region
> > > 
> > > v4: - A state variable to check if we need to update dirty rect
> > >     registers in case intel_fbc_can_flip_nuke() (Ville)
> > > 
> > > Bspec: 68881, 71675, 73424
> > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c |   7 +
> > >  drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
> > >  3 files changed, 145 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 7d68d652c1bc..33277f892279 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > >  
> > >  		commit_pipe_pre_planes(state, crtc);
> > >  
> > > +		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
> > > +
> > 
> > That is not the right place for _noarm() stuff.
> > 
> > Hmm, maybe we should just do this as part of intel_plane_update_noarm()?
> > How does the dirty rect interact with async flips?
> 
> Ok.
> 
> I thought no need to handle anything specific to dirty_rect in case of async flips.
> Atleast the the tests that I tried were ok! 
>

The question is whether async flip:
- results in full nuke or does it use the dirty rect?
- if it uses the dirty rect does that mean the new
  dirty rect (*) takes effect alongside the the async flip
  or is it still using a previously latched dirty rect?

(*) ie. one that was written into the register just before
    the surface register write, without there being a start
    of vblank in between the two writes

Should be easy to confirm with something like:
1. set up a framebuffer with some color
2. scan out from said framebuffer
3. write the dirty rect register with some small area of the screen
4. write SURF to trigger a sync flip
5. wait for vblank
6. rewrite the fb with some other color
7. set the async flip bit on PLANE_CTL
8. read the frame counter
9. write the dirty rect register with some other small area
10. write SURF to trigger an async flip
11. re-read frame counter and confirm it is still the same value
    as in step 8.
12. observe visually which area of the screen changed

That should at least tell us whether the new dirty rect gets latched due
to an async flip or not, and whether we get a full nuke or not.

And if the new dirty rect does get latched I suppose we can then
rinse an repeat this  with a full screen dirty rectangle, and then
we should be able to tell whether the dirty rect gets latched alongside
SURF during the async flip (tearing should be visible), or if it gets
delayed until the next vblank (no tearing should be visible, assuming
the entire fb did get compressed, which should hopefully be the case
for a solid color fb).

 > 
> > >  		intel_crtc_planes_update_arm(NULL, state, crtc);
> > >  
> > >  		commit_pipe_post_planes(state, crtc);
> > > @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> > >  						 new_crtc_state);
> > >  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
> > >  					       state, crtc);
> > > +		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
> > > +						  state, crtc);
> > >  
> > >  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> > >  
> > > @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > >  
> > >  	intel_atomic_prepare_plane_clear_colors(state);
> > >  
> > > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > +		intel_fbc_prepare_dirty_rect(state, crtc);
> > > +
> > >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > >  		intel_atomic_dsb_finish(state, crtc);
> > >  
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index df05904bac8a..24736c7a79a6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -88,6 +88,10 @@ struct intel_fbc_state {
> > >  	u16 override_cfb_stride;
> > >  	u16 interval;
> > >  	s8 fence_id;
> > > +	struct {
> > > +		struct drm_rect rect;
> > > +		bool valid;
> > > +	} fbc_dirty_rect;
> > >  };
> > >  
> > >  struct intel_fbc {
> > > @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> > >  	struct intel_display *display = fbc->display;
> > >  	u32 dpfc_ctl;
> > >  
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
> > > +
> > >  	/* Disable compression */
> > >  	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
> > >  	if (dpfc_ctl & DPFC_CTL_EN) {
> > > @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > >  	if (DISPLAY_VER(display) >= 20)
> > >  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > >  
> > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
> > > +			       FBC_DIRTY_RECT_EN);
> > > +
> > >  	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
> > >  		       DPFC_CTL_EN | dpfc_ctl);
> > >  }
> > > @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
> > >  		return i8xx_fbc_tiling_valid(plane_state);
> > >  }
> > >  
> > > +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> > > +				    struct intel_crtc *crtc,
> > > +				    struct intel_plane *plane);
> > 
> > You should put the code into a place that doesn't need this extra
> > declaration.
> > 
> > > +
> > > +static void
> > > +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
> > > +{
> > > +	struct intel_display *display = to_intel_display(plane);
> > > +	struct intel_fbc *fbc = plane->fbc;
> > > +	struct intel_fbc_state *fbc_state = &fbc->state;
> > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > +
> > > +	if (fbc_state->plane != plane)
> > > +		return;
> > > +
> > > +	if (!fbc_state->fbc_dirty_rect.valid)
> > > +		return;
> > 
> > I think that extra flag can be thrown out and you can just
> > check if the rect is visible here.
> > > +
> > > +	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> > > +			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> > > +			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> > > +
> > > +	fbc_state->fbc_dirty_rect.valid = false;
> > 
> > Why?
> > 
> > > +}
> > > +
> > > +void
> > > +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > +				  struct intel_atomic_state *state,
> > > +				  struct intel_crtc *crtc)
> > > +{
> > > +	struct intel_display *display = to_intel_display(state);
> > > +	struct intel_plane_state *plane_state;
> > 
> > const, although it seems to me we can just rely on the rect being valid
> > or not and then the plane visiblility is also already covered.
> > 
> > > +	struct intel_plane *plane;
> > > +	int i;
> > > +
> > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > +		return;
> > > +
> > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > +		struct intel_fbc *fbc = plane->fbc;
> > > +
> > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > +			continue;
> > > +
> > > +		if (!plane_state->uapi.visible)
> > > +			continue;
> > 
> > That check would also disappear.
> > 
> > This does need to check if the plane is the one using FBC
> > currently. Oh, I see you put that check inside
> > intel_fbc_dirty_rect_update(). I think the check belongs
> > here because that is how we do it everwhere else.
> > 
> > I was pondering if we need to keep this lockless or not.
> > I guess we don't since we are doing it from the noarm()
> > section (assuming we're not planing to implement mailbox
> > flips tomorrow). So for now I think we can just do the proper
> > locking here too. If we do need to make this lockless in
> > then we need to explain what makes it safe/correct.
> > 
> > > +
> > > +		intel_fbc_dirty_rect_update(dsb, plane);
> > > +	}
> > > +}
> > > +
> > > +static void
> > > +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
> > > +			     struct drm_rect *dirty_rect)
> > > +{
> > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > +	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > +	int max_endline = y_offset + plane_height - 1;
> > > +
> > > +	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
> > > +	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
> > > +}
> > 
> > This is not needed.
> > 
> > > +
> > > +static void
> > > +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
> > > +			       struct intel_plane_state *plane_state,
> > > +			       bool fbc_dirty_rect_valid)
> > > +{
> > > +	struct intel_fbc_state *fbc_state = &plane->fbc->state;
> > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > +
> > > +	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
> > > +
> > > +	if (drm_rect_visible(damage_merged)) {
> > > +		fbc_dirty_rect->y1 = damage_merged->y1;
> > > +		fbc_dirty_rect->y2 = damage_merged->y2;
> > > +	} else {
> > > +		/* If not visible, we need to set one single line */
> > > +		fbc_dirty_rect->y1 = y_offset;
> > > +		fbc_dirty_rect->y2 = y_offset;
> > > +	}
> > > +	fbc_dirty_rect->x1 = damage_merged->x1;
> > > +	fbc_dirty_rect->x2 = damage_merged->x2;
> > > +
> > > +	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
> > > +}
> > > +
> > > +void
> > > +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > +			     struct intel_crtc *crtc)
> > > +{
> > > +	struct intel_display *display = to_intel_display(state);
> > > +	struct intel_plane_state *plane_state;
> > > +	struct intel_plane *plane;
> > > +	int i;
> > > +
> > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > +		return;
> > > +
> > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > +		struct intel_fbc *fbc = plane->fbc;
> > > +
> > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > +			continue;
> > > +
> > > +		if (!fbc->state.plane)
> > > +			continue;
> > 
> > fbc->state.plane != plane
> > 
> > Also needs locking.
> > 
> > > +
> > > +		/* If plane not visible, dirty rect might have invalid coordinates */
> > > +		if (!plane_state->uapi.visible)
> > > +			continue;
> > 
> > Seems like a redundant check.
> > 
> > > +
> > > +		__intel_fbc_prepare_dirty_rect(plane, plane_state,
> > > +					       intel_fbc_can_flip_nuke(state,
> > > +								       crtc,
> > > +								       plane));
> > > +	}
> > > +}
> > > +
> > >  static void intel_fbc_update_state(struct intel_atomic_state *state,
> > >  				   struct intel_crtc *crtc,
> > >  				   struct intel_plane *plane)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > index ceae55458e14..8f1b11c6f4d2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > @@ -14,6 +14,7 @@ struct intel_atomic_state;
> > >  struct intel_crtc;
> > >  struct intel_crtc_state;
> > >  struct intel_display;
> > > +struct intel_dsb;
> > >  struct intel_fbc;
> > >  struct intel_plane;
> > >  struct intel_plane_state;
> > > @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> > >  void intel_fbc_reset_underrun(struct intel_display *display);
> > >  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
> > >  void intel_fbc_debugfs_register(struct intel_display *display);
> > > +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > +				  struct intel_crtc *crtc);
> > > +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > +				       struct intel_atomic_state *state,
> > > +				       struct intel_crtc *crtc);
> > >  
> > >  #endif /* __INTEL_FBC_H__ */
> > > -- 
> > > 2.43.0
> > 
> 

-- 
Ville Syrjälä
Intel

Re: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Govindapillai, Vinod]

Hi Ville,

I need to check the async flip tests for dirty rect cases.

But could you please clarify some of your comments before i send another version.. 

On Wed, 2025-02-05 at 17:45 +0200, Ville Syrjälä wrote:
> On Wed, Feb 05, 2025 at 02:49:46PM +0000, Govindapillai, Vinod wrote:
> > So based on your comments on the previous patch and this one, let me conclude the changes to be
> > done
> > here!
> > 
> > 1. As part of the previous patch, we collect the fbc_dirty rect from the damage_helper call.
> > Make
> > damage empty if the plane not visible. 
> > 
> > 2. Update the FBC dirty rect registes. This do two things
> > 	2.1 Prepare the collected FBC dirty and copy it to the correct fbc_state -
> >  	  	
> > intel_fbc_prepare_dirty_rect()
> > 
> > 	2.2 Write to the registers - intel_fbc_dirty_rect_update_noarm()
> > 
> > 2.1 AT the beginning of the atomic_commit_tail() within the DSB block handling, calls
> > intel_fbc_prepare_dirty_rect() to populate fbc_state's fbc_dirty_rect structs
> > 
> > In the intel_fbc_prepare_dirty_rect(), 
> > 	iterate through each plane in the atomic_state
> >         check the correct plane, pipe etc. Then,
> > 
> > 	if (drm_rect_visible(damage_merged)
> > 		update fbc_state's fbc dirty rect 
> >         else
> > 		Make at it atleast one scan line and update the fbc_state's fbc_dirty rect 
> > 
> > 2.2 Then call intel_fbc_dirty_rect_update_noarm() form intel_plane_update_noarm()
> > 	And within in intel_fbc_dirty_rect_update_noarm() just update the FBC dirty registers
> > with
> > the values from corresponding fbc_state->fbc_dirty 
> > 
> > 
> > I think last time when we discussed, we decided keep that valid flag to track
> > intel_fbc_can_flip_nuke() case. So I guess that is not required anymore
> > 
> > Regarding the async flip cases, I thought nothing specific need to be done for the fbc dirty
> > rect.
> > Atleast the some the tests I tried were passing with dirty rect enabled.
> > 
> > I will add the locks in these new functions.
> > 
> > BR
> > Vinod
> > 
> > 
> > On Wed, 2025-02-05 at 15:31 +0200, Ville Syrjälä wrote:
> > > On Thu, Jan 30, 2025 at 11:00:24PM +0200, Vinod Govindapillai wrote:
> > > > Dirty rectangle feature allows FBC to recompress a subsection
> > > > of a frame. When this feature is enabled, display will read
> > > > the scan lines between dirty rectangle start line and dirty
> > > > rectangle end line in subsequent frames.
> > > > 
> > > > Use the merged damage clip stored in the plane state to
> > > > configure the FBC dirty rect areas.
> > > > 
> > > > v2: - Move dirty rect handling to fbc state (Ville)
> > > > 
> > > > v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
> > > >     - Split plane damage collection and dirty rect preparation
> > > >     - Handle case where dirty rect fall outside the visible region
> > > > 
> > > > v4: - A state variable to check if we need to update dirty rect
> > > >     registers in case intel_fbc_can_flip_nuke() (Ville)
> > > > 
> > > > Bspec: 68881, 71675, 73424
> > > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c |   7 +
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
> > > >  drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
> > > >  3 files changed, 145 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 7d68d652c1bc..33277f892279 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > >  
> > > >  		commit_pipe_pre_planes(state, crtc);
> > > >  
> > > > +		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
> > > > +
> > > 
> > > That is not the right place for _noarm() stuff.
> > > 
> > > Hmm, maybe we should just do this as part of intel_plane_update_noarm()?
> > > How does the dirty rect interact with async flips?
> > 
> > Ok.
> > 
> > I thought no need to handle anything specific to dirty_rect in case of async flips.
> > Atleast the the tests that I tried were ok! 
> > 
> 
> The question is whether async flip:
> - results in full nuke or does it use the dirty rect?
> - if it uses the dirty rect does that mean the new
>   dirty rect (*) takes effect alongside the the async flip
>   or is it still using a previously latched dirty rect?
> 
> (*) ie. one that was written into the register just before
>     the surface register write, without there being a start
>     of vblank in between the two writes
> 
> Should be easy to confirm with something like:
> 1. set up a framebuffer with some color
> 2. scan out from said framebuffer
> 3. write the dirty rect register with some small area of the screen
> 4. write SURF to trigger a sync flip
> 5. wait for vblank
> 6. rewrite the fb with some other color
> 7. set the async flip bit on PLANE_CTL
> 8. read the frame counter
> 9. write the dirty rect register with some other small area
> 10. write SURF to trigger an async flip
> 11. re-read frame counter and confirm it is still the same value
>     as in step 8.
> 12. observe visually which area of the screen changed
> 
> That should at least tell us whether the new dirty rect gets latched due
> to an async flip or not, and whether we get a full nuke or not.
> 
> And if the new dirty rect does get latched I suppose we can then
> rinse an repeat this  with a full screen dirty rectangle, and then
> we should be able to tell whether the dirty rect gets latched alongside
> SURF during the async flip (tearing should be visible), or if it gets
> delayed until the next vblank (no tearing should be visible, assuming
> the entire fb did get compressed, which should hopefully be the case
> for a solid color fb).
> 
>  > 
> > > >  		intel_crtc_planes_update_arm(NULL, state, crtc);
> > > >  
> > > >  		commit_pipe_post_planes(state, crtc);
> > > > @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> > > >  						 new_crtc_state);
> > > >  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
> > > >  					       state, crtc);
> > > > +		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
> > > > +						  state, crtc);
> > > >  
> > > >  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> > > >  
> > > > @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > >  
> > > >  	intel_atomic_prepare_plane_clear_colors(state);
> > > >  
> > > > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > > +		intel_fbc_prepare_dirty_rect(state, crtc);
> > > > +
> > > >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > >  		intel_atomic_dsb_finish(state, crtc);
> > > >  
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index df05904bac8a..24736c7a79a6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -88,6 +88,10 @@ struct intel_fbc_state {
> > > >  	u16 override_cfb_stride;
> > > >  	u16 interval;
> > > >  	s8 fence_id;
> > > > +	struct {
> > > > +		struct drm_rect rect;
> > > > +		bool valid;
> > > > +	} fbc_dirty_rect;
> > > >  };
> > > >  
> > > >  struct intel_fbc {
> > > > @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> > > >  	struct intel_display *display = fbc->display;
> > > >  	u32 dpfc_ctl;
> > > >  
> > > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
> > > > +
> > > >  	/* Disable compression */
> > > >  	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
> > > >  	if (dpfc_ctl & DPFC_CTL_EN) {
> > > > @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > > >  	if (DISPLAY_VER(display) >= 20)
> > > >  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > > >  
> > > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
> > > > +			       FBC_DIRTY_RECT_EN);
> > > > +
> > > >  	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
> > > >  		       DPFC_CTL_EN | dpfc_ctl);
> > > >  }
> > > > @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state
> > > > *plane_state)
> > > >  		return i8xx_fbc_tiling_valid(plane_state);
> > > >  }
> > > >  
> > > > +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> > > > +				    struct intel_crtc *crtc,
> > > > +				    struct intel_plane *plane);
> > > 
> > > You should put the code into a place that doesn't need this extra
> > > declaration.
> > > 
> > > > +
> > > > +static void
> > > > +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
> > > > +{
> > > > +	struct intel_display *display = to_intel_display(plane);
> > > > +	struct intel_fbc *fbc = plane->fbc;
> > > > +	struct intel_fbc_state *fbc_state = &fbc->state;
> > > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > > +
> > > > +	if (fbc_state->plane != plane)
> > > > +		return;
> > > > +
> > > > +	if (!fbc_state->fbc_dirty_rect.valid)
> > > > +		return;
> > > 
> > > I think that extra flag can be thrown out and you can just
> > > check if the rect is visible here.

HAS recommends to program one line in case damage area rect is not visible! So not sure how can we
use rect is visible here.

Earlier in our discussions, you mentioned we might need to check "intel_fbc_can_flip_nuke()" before
updating the dirty_rect. So that extra flag was mainly tracking intel_fbc_can_flip_nuke()!

I see mainly two cases where "intel_fbc_can_flip_nuke" can have a impact - at the time of enabling
FBC and disabling FBC. In case of enabling FBC, HW ignores what is programmed in dirty rect
registers for the first frame after FBC is enabled. It fetches the entire frame. And in case of
Disabling FBC, anyway dirty rect registers will be ignored as FBC will be disabled. 

In intel_fbc_prepare_dirty_rect() which is called from commit tail..

 if (fbc && plane->pipe == crtc->pipe && fbc->state.plane != plane) {
	fbc_dirty_rect->y1 = drm_rect_visible(damage) ? damage->y1 : y_offset;
	fbc_dirty_rect->y2 = drm_rect_visible(damage) ? damage->y2 : y_offset;
	fbc_dirty_rect->x1 = damage->x1;
	fbc_dirty_rect->x2 = damage->x2;
}

And in intel_fbc_dirty_rect_update_noarm() which is called from intel_plane_update_noarm()

if (fbc && fbc->state.plane != plane) {
	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
}

> > > > +
> > > > +	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> > > > +			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> > > > +			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> > > > +
> > > > +	fbc_state->fbc_dirty_rect.valid = false;
> > > 
> > > Why?
> > > 
> > > > +}
> > > > +
> > > > +void
> > > > +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > > +				  struct intel_atomic_state *state,
> > > > +				  struct intel_crtc *crtc)
> > > > +{
> > > > +	struct intel_display *display = to_intel_display(state);
> > > > +	struct intel_plane_state *plane_state;
> > > 
> > > const, although it seems to me we can just rely on the rect being valid
> > > or not and then the plane visiblility is also already covered.
> > > 
> > > > +	struct intel_plane *plane;
> > > > +	int i;
> > > > +
> > > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > > +		return;
> > > > +
> > > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > > +		struct intel_fbc *fbc = plane->fbc;
> > > > +
> > > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > > +			continue;
> > > > +
> > > > +		if (!plane_state->uapi.visible)
> > > > +			continue;
> > > 
> > > That check would also disappear.
> > > 
> > > This does need to check if the plane is the one using FBC
> > > currently. Oh, I see you put that check inside
> > > intel_fbc_dirty_rect_update(). I think the check belongs
> > > here because that is how we do it everwhere else.
> > > 
> > > I was pondering if we need to keep this lockless or not.
> > > I guess we don't since we are doing it from the noarm()
> > > section (assuming we're not planing to implement mailbox
> > > flips tomorrow). So for now I think we can just do the proper
> > > locking here too. If we do need to make this lockless in
> > > then we need to explain what makes it safe/correct.
> > > 
> > > > +
> > > > +		intel_fbc_dirty_rect_update(dsb, plane);
> > > > +	}
> > > > +}
> > > > +
> > > > +static void
> > > > +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
> > > > +			     struct drm_rect *dirty_rect)
> > > > +{
> > > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > > +	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > > +	int max_endline = y_offset + plane_height - 1;
> > > > +
> > > > +	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
> > > > +	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
> > > > +}
> > > 
> > > This is not needed.

But I noticed that from one of the test cases created, if the damage area set as (0, 0)
(plane_width, plane_height), without that clipping, we will set 
dirty_rect->y1 = 0 and dirty_rect->y2 = height. 
With this screen is not updated correctly.
To get this working correctly I had to make dirty_rect->y2 as plane_height -1.

Wonder if I am I missing anything here?

BR
Vinod

> > > 
> > > > +
> > > > +static void
> > > > +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
> > > > +			       struct intel_plane_state *plane_state,
> > > > +			       bool fbc_dirty_rect_valid)
> > > > +{
> > > > +	struct intel_fbc_state *fbc_state = &plane->fbc->state;
> > > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > > +
> > > > +	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
> > > > +
> > > > +	if (drm_rect_visible(damage_merged)) {
> > > > +		fbc_dirty_rect->y1 = damage_merged->y1;
> > > > +		fbc_dirty_rect->y2 = damage_merged->y2;
> > > > +	} else {
> > > > +		/* If not visible, we need to set one single line */
> > > > +		fbc_dirty_rect->y1 = y_offset;
> > > > +		fbc_dirty_rect->y2 = y_offset;
> > > > +	}
> > > > +	fbc_dirty_rect->x1 = damage_merged->x1;
> > > > +	fbc_dirty_rect->x2 = damage_merged->x2;
> > > > +
> > > > +	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
> > > > +}
> > > > +
> > > > +void
> > > > +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > > +			     struct intel_crtc *crtc)
> > > > +{
> > > > +	struct intel_display *display = to_intel_display(state);
> > > > +	struct intel_plane_state *plane_state;
> > > > +	struct intel_plane *plane;
> > > > +	int i;
> > > > +
> > > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > > +		return;
> > > > +
> > > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > > +		struct intel_fbc *fbc = plane->fbc;
> > > > +
> > > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > > +			continue;
> > > > +
> > > > +		if (!fbc->state.plane)
> > > > +			continue;
> > > 
> > > fbc->state.plane != plane
> > > 
> > > Also needs locking.
> > > 
> > > > +
> > > > +		/* If plane not visible, dirty rect might have invalid coordinates */
> > > > +		if (!plane_state->uapi.visible)
> > > > +			continue;
> > > 
> > > Seems like a redundant check.
> > > 
> > > > +
> > > > +		__intel_fbc_prepare_dirty_rect(plane, plane_state,
> > > > +					       intel_fbc_can_flip_nuke(state,
> > > > +								       crtc,
> > > > +								       plane));
> > > > +	}
> > > > +}
> > > > +
> > > >  static void intel_fbc_update_state(struct intel_atomic_state *state,
> > > >  				   struct intel_crtc *crtc,
> > > >  				   struct intel_plane *plane)
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > index ceae55458e14..8f1b11c6f4d2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > @@ -14,6 +14,7 @@ struct intel_atomic_state;
> > > >  struct intel_crtc;
> > > >  struct intel_crtc_state;
> > > >  struct intel_display;
> > > > +struct intel_dsb;
> > > >  struct intel_fbc;
> > > >  struct intel_plane;
> > > >  struct intel_plane_state;
> > > > @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> > > >  void intel_fbc_reset_underrun(struct intel_display *display);
> > > >  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
> > > >  void intel_fbc_debugfs_register(struct intel_display *display);
> > > > +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > > +				  struct intel_crtc *crtc);
> > > > +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > > +				       struct intel_atomic_state *state,
> > > > +				       struct intel_crtc *crtc);
> > > >  
> > > >  #endif /* __INTEL_FBC_H__ */
> > > > -- 
> > > > 2.43.0
> > > 
> > 
> 

Re: [PATCH v6 5/7] drm/i915/xe3: dirty rect support for FBC

[Govindapillai, Vinod]

Hi Ville,

Regarding the async_clip I was trying a new test case but noticed that it was nuking on asyn_flip.

So I checked with HW folks, then confirmed that FBC will nuke on async_flip. Dirty rectangle only
works with sync flip. He pointed out that in the bspec (I overlooked that aspect though!),  
"When the Dirty Rectangle Enable bit is set in the FBC_DIRTY_CTL register, and there is a *sync flip
indication, display will read the scanlines between....."

Well.. basically this is now confirmed from my trials as well.

BR
Vinod


On Mon, 2025-02-10 at 14:15 +0200, Govindapillai, Vinod wrote:
> Hi Ville,
> 
> I need to check the async flip tests for dirty rect cases.
> 
> But could you please clarify some of your comments before i send another version.. 
> 
> On Wed, 2025-02-05 at 17:45 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 05, 2025 at 02:49:46PM +0000, Govindapillai, Vinod wrote:
> > > So based on your comments on the previous patch and this one, let me conclude the changes to
> > > be
> > > done
> > > here!
> > > 
> > > 1. As part of the previous patch, we collect the fbc_dirty rect from the damage_helper call.
> > > Make
> > > damage empty if the plane not visible. 
> > > 
> > > 2. Update the FBC dirty rect registes. This do two things
> > > 	2.1 Prepare the collected FBC dirty and copy it to the correct fbc_state -
> > >  	  	
> > > intel_fbc_prepare_dirty_rect()
> > > 
> > > 	2.2 Write to the registers - intel_fbc_dirty_rect_update_noarm()
> > > 
> > > 2.1 AT the beginning of the atomic_commit_tail() within the DSB block handling, calls
> > > intel_fbc_prepare_dirty_rect() to populate fbc_state's fbc_dirty_rect structs
> > > 
> > > In the intel_fbc_prepare_dirty_rect(), 
> > > 	iterate through each plane in the atomic_state
> > >         check the correct plane, pipe etc. Then,
> > > 
> > > 	if (drm_rect_visible(damage_merged)
> > > 		update fbc_state's fbc dirty rect 
> > >         else
> > > 		Make at it atleast one scan line and update the fbc_state's fbc_dirty rect 
> > > 
> > > 2.2 Then call intel_fbc_dirty_rect_update_noarm() form intel_plane_update_noarm()
> > > 	And within in intel_fbc_dirty_rect_update_noarm() just update the FBC dirty registers
> > > with
> > > the values from corresponding fbc_state->fbc_dirty 
> > > 
> > > 
> > > I think last time when we discussed, we decided keep that valid flag to track
> > > intel_fbc_can_flip_nuke() case. So I guess that is not required anymore
> > > 
> > > Regarding the async flip cases, I thought nothing specific need to be done for the fbc dirty
> > > rect.
> > > Atleast the some the tests I tried were passing with dirty rect enabled.
> > > 
> > > I will add the locks in these new functions.
> > > 
> > > BR
> > > Vinod
> > > 
> > > 
> > > On Wed, 2025-02-05 at 15:31 +0200, Ville Syrjälä wrote:
> > > > On Thu, Jan 30, 2025 at 11:00:24PM +0200, Vinod Govindapillai wrote:
> > > > > Dirty rectangle feature allows FBC to recompress a subsection
> > > > > of a frame. When this feature is enabled, display will read
> > > > > the scan lines between dirty rectangle start line and dirty
> > > > > rectangle end line in subsequent frames.
> > > > > 
> > > > > Use the merged damage clip stored in the plane state to
> > > > > configure the FBC dirty rect areas.
> > > > > 
> > > > > v2: - Move dirty rect handling to fbc state (Ville)
> > > > > 
> > > > > v3: - Use intel_fbc_dirty_rect_update_noarm (Ville)
> > > > >     - Split plane damage collection and dirty rect preparation
> > > > >     - Handle case where dirty rect fall outside the visible region
> > > > > 
> > > > > v4: - A state variable to check if we need to update dirty rect
> > > > >     registers in case intel_fbc_can_flip_nuke() (Ville)
> > > > > 
> > > > > Bspec: 68881, 71675, 73424
> > > > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_display.c |   7 +
> > > > >  drivers/gpu/drm/i915/display/intel_fbc.c     | 132 +++++++++++++++++++
> > > > >  drivers/gpu/drm/i915/display/intel_fbc.h     |   6 +
> > > > >  3 files changed, 145 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 7d68d652c1bc..33277f892279 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7263,6 +7263,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > > >  
> > > > >  		commit_pipe_pre_planes(state, crtc);
> > > > >  
> > > > > +		intel_fbc_dirty_rect_update_noarm(NULL, state, crtc);
> > > > > +
> > > > 
> > > > That is not the right place for _noarm() stuff.
> > > > 
> > > > Hmm, maybe we should just do this as part of intel_plane_update_noarm()?
> > > > How does the dirty rect interact with async flips?
> > > 
> > > Ok.
> > > 
> > > I thought no need to handle anything specific to dirty_rect in case of async flips.
> > > Atleast the the tests that I tried were ok! 
> > > 
> > 
> > The question is whether async flip:
> > - results in full nuke or does it use the dirty rect?
> > - if it uses the dirty rect does that mean the new
> >   dirty rect (*) takes effect alongside the the async flip
> >   or is it still using a previously latched dirty rect?
> > 
> > (*) ie. one that was written into the register just before
> >     the surface register write, without there being a start
> >     of vblank in between the two writes
> > 
> > Should be easy to confirm with something like:
> > 1. set up a framebuffer with some color
> > 2. scan out from said framebuffer
> > 3. write the dirty rect register with some small area of the screen
> > 4. write SURF to trigger a sync flip
> > 5. wait for vblank
> > 6. rewrite the fb with some other color
> > 7. set the async flip bit on PLANE_CTL
> > 8. read the frame counter
> > 9. write the dirty rect register with some other small area
> > 10. write SURF to trigger an async flip
> > 11. re-read frame counter and confirm it is still the same value
> >     as in step 8.
> > 12. observe visually which area of the screen changed
> > 
> > That should at least tell us whether the new dirty rect gets latched due
> > to an async flip or not, and whether we get a full nuke or not.
> > 
> > And if the new dirty rect does get latched I suppose we can then
> > rinse an repeat this  with a full screen dirty rectangle, and then
> > we should be able to tell whether the dirty rect gets latched alongside
> > SURF during the async flip (tearing should be visible), or if it gets
> > delayed until the next vblank (no tearing should be visible, assuming
> > the entire fb did get compressed, which should hopefully be the case
> > for a solid color fb).
> > 
> >  > 
> > > > >  		intel_crtc_planes_update_arm(NULL, state, crtc);
> > > > >  
> > > > >  		commit_pipe_post_planes(state, crtc);
> > > > > @@ -7723,6 +7725,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state
> > > > > *state,
> > > > >  						 new_crtc_state);
> > > > >  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
> > > > >  					       state, crtc);
> > > > > +		intel_fbc_dirty_rect_update_noarm(new_crtc_state->dsb_commit,
> > > > > +						  state, crtc);
> > > > >  
> > > > >  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> > > > >  
> > > > > @@ -7769,6 +7773,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state
> > > > > *state)
> > > > >  
> > > > >  	intel_atomic_prepare_plane_clear_colors(state);
> > > > >  
> > > > > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > > > +		intel_fbc_prepare_dirty_rect(state, crtc);
> > > > > +
> > > > >  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> > > > >  		intel_atomic_dsb_finish(state, crtc);
> > > > >  
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > index df05904bac8a..24736c7a79a6 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > @@ -88,6 +88,10 @@ struct intel_fbc_state {
> > > > >  	u16 override_cfb_stride;
> > > > >  	u16 interval;
> > > > >  	s8 fence_id;
> > > > > +	struct {
> > > > > +		struct drm_rect rect;
> > > > > +		bool valid;
> > > > > +	} fbc_dirty_rect;
> > > > >  };
> > > > >  
> > > > >  struct intel_fbc {
> > > > > @@ -527,6 +531,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> > > > >  	struct intel_display *display = fbc->display;
> > > > >  	u32 dpfc_ctl;
> > > > >  
> > > > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
> > > > > +
> > > > >  	/* Disable compression */
> > > > >  	dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
> > > > >  	if (dpfc_ctl & DPFC_CTL_EN) {
> > > > > @@ -670,6 +677,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> > > > >  	if (DISPLAY_VER(display) >= 20)
> > > > >  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> > > > >  
> > > > > +	if (HAS_FBC_DIRTY_RECT(display))
> > > > > +		intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
> > > > > +			       FBC_DIRTY_RECT_EN);
> > > > > +
> > > > >  	intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
> > > > >  		       DPFC_CTL_EN | dpfc_ctl);
> > > > >  }
> > > > > @@ -1203,6 +1214,127 @@ static bool tiling_is_valid(const struct intel_plane_state
> > > > > *plane_state)
> > > > >  		return i8xx_fbc_tiling_valid(plane_state);
> > > > >  }
> > > > >  
> > > > > +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> > > > > +				    struct intel_crtc *crtc,
> > > > > +				    struct intel_plane *plane);
> > > > 
> > > > You should put the code into a place that doesn't need this extra
> > > > declaration.
> > > > 
> > > > > +
> > > > > +static void
> > > > > +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_plane *plane)
> > > > > +{
> > > > > +	struct intel_display *display = to_intel_display(plane);
> > > > > +	struct intel_fbc *fbc = plane->fbc;
> > > > > +	struct intel_fbc_state *fbc_state = &fbc->state;
> > > > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > > > +
> > > > > +	if (fbc_state->plane != plane)
> > > > > +		return;
> > > > > +
> > > > > +	if (!fbc_state->fbc_dirty_rect.valid)
> > > > > +		return;
> > > > 
> > > > I think that extra flag can be thrown out and you can just
> > > > check if the rect is visible here.
> 
> HAS recommends to program one line in case damage area rect is not visible! So not sure how can we
> use rect is visible here.
> 
> Earlier in our discussions, you mentioned we might need to check "intel_fbc_can_flip_nuke()"
> before
> updating the dirty_rect. So that extra flag was mainly tracking intel_fbc_can_flip_nuke()!
> 
> I see mainly two cases where "intel_fbc_can_flip_nuke" can have a impact - at the time of enabling
> FBC and disabling FBC. In case of enabling FBC, HW ignores what is programmed in dirty rect
> registers for the first frame after FBC is enabled. It fetches the entire frame. And in case of
> Disabling FBC, anyway dirty rect registers will be ignored as FBC will be disabled. 
> 
> In intel_fbc_prepare_dirty_rect() which is called from commit tail..
> 
>  if (fbc && plane->pipe == crtc->pipe && fbc->state.plane != plane) {
> 	fbc_dirty_rect->y1 = drm_rect_visible(damage) ? damage->y1 : y_offset;
> 	fbc_dirty_rect->y2 = drm_rect_visible(damage) ? damage->y2 : y_offset;
> 	fbc_dirty_rect->x1 = damage->x1;
> 	fbc_dirty_rect->x2 = damage->x2;
> }
> 
> And in intel_fbc_dirty_rect_update_noarm() which is called from intel_plane_update_noarm()
> 
> if (fbc && fbc->state.plane != plane) {
> 	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> 			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> 			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> }
> 
> > > > > +
> > > > > +	intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
> > > > > +			   FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
> > > > > +			   FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2));
> > > > > +
> > > > > +	fbc_state->fbc_dirty_rect.valid = false;
> > > > 
> > > > Why?
> > > > 
> > > > > +}
> > > > > +
> > > > > +void
> > > > > +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > > > +				  struct intel_atomic_state *state,
> > > > > +				  struct intel_crtc *crtc)
> > > > > +{
> > > > > +	struct intel_display *display = to_intel_display(state);
> > > > > +	struct intel_plane_state *plane_state;
> > > > 
> > > > const, although it seems to me we can just rely on the rect being valid
> > > > or not and then the plane visiblility is also already covered.
> > > > 
> > > > > +	struct intel_plane *plane;
> > > > > +	int i;
> > > > > +
> > > > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > > > +		return;
> > > > > +
> > > > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > > > +		struct intel_fbc *fbc = plane->fbc;
> > > > > +
> > > > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > > > +			continue;
> > > > > +
> > > > > +		if (!plane_state->uapi.visible)
> > > > > +			continue;
> > > > 
> > > > That check would also disappear.
> > > > 
> > > > This does need to check if the plane is the one using FBC
> > > > currently. Oh, I see you put that check inside
> > > > intel_fbc_dirty_rect_update(). I think the check belongs
> > > > here because that is how we do it everwhere else.
> > > > 
> > > > I was pondering if we need to keep this lockless or not.
> > > > I guess we don't since we are doing it from the noarm()
> > > > section (assuming we're not planing to implement mailbox
> > > > flips tomorrow). So for now I think we can just do the proper
> > > > locking here too. If we do need to make this lockless in
> > > > then we need to explain what makes it safe/correct.
> > > > 
> > > > > +
> > > > > +		intel_fbc_dirty_rect_update(dsb, plane);
> > > > > +	}
> > > > > +}
> > > > > +
> > > > > +static void
> > > > > +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state,
> > > > > +			     struct drm_rect *dirty_rect)
> > > > > +{
> > > > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > > > +	int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > > > +	int max_endline = y_offset + plane_height - 1;
> > > > > +
> > > > > +	dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline);
> > > > > +	dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline);
> > > > > +}
> > > > 
> > > > This is not needed.
> 
> But I noticed that from one of the test cases created, if the damage area set as (0, 0)
> (plane_width, plane_height), without that clipping, we will set 
> dirty_rect->y1 = 0 and dirty_rect->y2 = height. 
> With this screen is not updated correctly.
> To get this working correctly I had to make dirty_rect->y2 as plane_height -1.
> 
> Wonder if I am I missing anything here?
> 
> BR
> Vinod
> 
> > > > 
> > > > > +
> > > > > +static void
> > > > > +__intel_fbc_prepare_dirty_rect(struct intel_plane *plane,
> > > > > +			       struct intel_plane_state *plane_state,
> > > > > +			       bool fbc_dirty_rect_valid)
> > > > > +{
> > > > > +	struct intel_fbc_state *fbc_state = &plane->fbc->state;
> > > > > +	struct drm_rect *fbc_dirty_rect = &fbc_state->fbc_dirty_rect.rect;
> > > > > +	struct drm_rect *damage_merged = &plane_state->damage_merged;
> > > > > +	int y_offset = plane_state->view.color_plane[0].y;
> > > > > +
> > > > > +	fbc_state->fbc_dirty_rect.valid = fbc_dirty_rect_valid;
> > > > > +
> > > > > +	if (drm_rect_visible(damage_merged)) {
> > > > > +		fbc_dirty_rect->y1 = damage_merged->y1;
> > > > > +		fbc_dirty_rect->y2 = damage_merged->y2;
> > > > > +	} else {
> > > > > +		/* If not visible, we need to set one single line */
> > > > > +		fbc_dirty_rect->y1 = y_offset;
> > > > > +		fbc_dirty_rect->y2 = y_offset;
> > > > > +	}
> > > > > +	fbc_dirty_rect->x1 = damage_merged->x1;
> > > > > +	fbc_dirty_rect->x2 = damage_merged->x2;
> > > > > +
> > > > > +	validate_and_clip_dirty_rect(plane_state, fbc_dirty_rect);
> > > > > +}
> > > > > +
> > > > > +void
> > > > > +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > > > +			     struct intel_crtc *crtc)
> > > > > +{
> > > > > +	struct intel_display *display = to_intel_display(state);
> > > > > +	struct intel_plane_state *plane_state;
> > > > > +	struct intel_plane *plane;
> > > > > +	int i;
> > > > > +
> > > > > +	if (!HAS_FBC_DIRTY_RECT(display))
> > > > > +		return;
> > > > > +
> > > > > +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> > > > > +		struct intel_fbc *fbc = plane->fbc;
> > > > > +
> > > > > +		if (!fbc || plane->pipe != crtc->pipe)
> > > > > +			continue;
> > > > > +
> > > > > +		if (!fbc->state.plane)
> > > > > +			continue;
> > > > 
> > > > fbc->state.plane != plane
> > > > 
> > > > Also needs locking.
> > > > 
> > > > > +
> > > > > +		/* If plane not visible, dirty rect might have invalid coordinates */
> > > > > +		if (!plane_state->uapi.visible)
> > > > > +			continue;
> > > > 
> > > > Seems like a redundant check.
> > > > 
> > > > > +
> > > > > +		__intel_fbc_prepare_dirty_rect(plane, plane_state,
> > > > > +					       intel_fbc_can_flip_nuke(state,
> > > > > +								       crtc,
> > > > > +								       plane));
> > > > > +	}
> > > > > +}
> > > > > +
> > > > >  static void intel_fbc_update_state(struct intel_atomic_state *state,
> > > > >  				   struct intel_crtc *crtc,
> > > > >  				   struct intel_plane *plane)
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > > b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > > index ceae55458e14..8f1b11c6f4d2 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> > > > > @@ -14,6 +14,7 @@ struct intel_atomic_state;
> > > > >  struct intel_crtc;
> > > > >  struct intel_crtc_state;
> > > > >  struct intel_display;
> > > > > +struct intel_dsb;
> > > > >  struct intel_fbc;
> > > > >  struct intel_plane;
> > > > >  struct intel_plane_state;
> > > > > @@ -48,5 +49,10 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> > > > >  void intel_fbc_reset_underrun(struct intel_display *display);
> > > > >  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
> > > > >  void intel_fbc_debugfs_register(struct intel_display *display);
> > > > > +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
> > > > > +				  struct intel_crtc *crtc);
> > > > > +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
> > > > > +				       struct intel_atomic_state *state,
> > > > > +				       struct intel_crtc *crtc);
> > > > >  
> > > > >  #endif /* __INTEL_FBC_H__ */
> > > > > -- 
> > > > > 2.43.0
> > > > 
> > > 
> > 
> 

[PATCH v6 6/7] drm/i915/xe3: avoid calling fbc activate if fbc is active

[Vinod Govindapillai]

If FBC is already active, we don't need to call FBC activate
routine again. This is more relevant in case of dirty rect
support in FBC. Xe doesn't support legacy fences. Hence fence
programming also not required as part of this fbc_hw_activate.
Any FBC related register updates done after enabling the dirty
rect support in xe3 will trigger nuke by FBC HW. So avoid
calling fbc activate routine again if the FBC is already active.

The front buffer rendering sequence will call intel_fbc_flush()
and which will call intel_fbc_nuke() or intel_fbc_activate()
based on FBC status explicitly and won't get impacted by this
change.

v2: use HAS_FBC_DIRTY_RECT()
    move this functionality within intel_fbc_activate()

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 24736c7a79a6..b17ee1797118 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -750,8 +750,19 @@ static void intel_fbc_nuke(struct intel_fbc *fbc)
 
 static void intel_fbc_activate(struct intel_fbc *fbc)
 {
+	struct intel_display *display = fbc->display;
+
 	lockdep_assert_held(&fbc->lock);
 
+	/*
+	 * When dirty rectangle is enabled, any updates to FBC registers will
+	 * trigger nuke. So avoid calling intel_fbc_activate if fbc is already
+	 * active and for XE3 cases. Xe doesn't support legacy fences. So
+	 * no need to update the fences as well.
+	 */
+	if (HAS_FBC_DIRTY_RECT(display) && fbc->active)
+		return;
+
 	intel_fbc_hw_activate(fbc);
 	intel_fbc_nuke(fbc);
 
-- 
2.43.0

[PATCH v6 7/7] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled

[Vinod Govindapillai]

It is not recommended to have both FBC dirty rect and PSR2
selective fetch be enabled at the same time. If PSR2 selective
fetch or panel replay is on, mark FBC as not possible.

v2: fix the condition to disable FBC if PSR2 enabled (Jani)

v3: use HAS_FBC_DIRTY_RECT()

Bspec: 68881
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b17ee1797118..429e213e1dcd 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1481,9 +1481,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	 * Display 12+ is not supporting FBC with PSR2.
 	 * Recommendation is to keep this combination disabled
 	 * Bspec: 50422 HSD: 14010260002
+	 *
+	 * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot
+	 * coexist. So if PSR2 selective fetch is supported then mark that
+	 * FBC is not supported.
+	 * TODO: Need a logic to decide between PSR2 and FBC Dirty rect
 	 */
-	if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update &&
-	    !crtc_state->has_panel_replay) {
+	if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) &&
+	    crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
 		plane_state->no_fbc_reason = "PSR2 enabled";
 		return 0;
 	}
-- 
2.43.0

RE: [PATCH v6 7/7] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Vinod
> Govindapillai
> Sent: Friday, January 31, 2025 2:30 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville
> <ville.syrjala@intel.com>; Reddy Guddati, Santhosh
> <santhosh.reddy.guddati@intel.com>; Saarinen, Jani
> <jani.saarinen@intel.com>
> Subject: [PATCH v6 7/7] drm/i915/xe3: disable FBC if PSR2 selective fetch is
> enabled
> 
> It is not recommended to have both FBC dirty rect and PSR2 selective fetch be
> enabled at the same time. If PSR2 selective fetch or panel replay is on, mark
> FBC as not possible.
> 
> v2: fix the condition to disable FBC if PSR2 enabled (Jani)
> 
> v3: use HAS_FBC_DIRTY_RECT()
> 
> Bspec: 68881
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b17ee1797118..429e213e1dcd 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1481,9 +1481,14 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>  	 * Display 12+ is not supporting FBC with PSR2.
>  	 * Recommendation is to keep this combination disabled
>  	 * Bspec: 50422 HSD: 14010260002
> +	 *
> +	 * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot
> +	 * coexist. So if PSR2 selective fetch is supported then mark that
> +	 * FBC is not supported.
> +	 * TODO: Need a logic to decide between PSR2 and FBC Dirty rect
>  	 */
> -	if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update &&
> -	    !crtc_state->has_panel_replay) {
> +	if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display))
> &&
> +	    crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
>  		plane_state->no_fbc_reason = "PSR2 enabled";
>  		return 0;
>  	}
> --
> 2.43.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915/xe3: FBC Dirty rect feature support (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev7)
URL   : https://patchwork.freedesktop.org/series/141527/
State : warning

== Summary ==

Error: dim checkpatch failed
73dbd0845cac drm/i915/xe3: add register definitions for fbc dirty rect support
-:24: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:107:
+#define   FBC_DIRTY_RECT_START_LINE(val)	REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
11b227139f8a drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support
ffc3026626b5 drm/damage-helper: add const qualifier in drm_atomic_helper_damage_merged()
0ec3efcf3af0 drm/i915/xe3: update and store the plane damage clips
35d2c226a650 drm/i915/xe3: dirty rect support for FBC
f4d33535af6a drm/i915/xe3: avoid calling fbc activate if fbc is active
d2e5ce0aa316 drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled

✗ Fi.CI.SPARSE: warning for drm/i915/xe3: FBC Dirty rect feature support (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev7)
URL   : https://patchwork.freedesktop.org/series/141527/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for drm/i915/xe3: FBC Dirty rect feature support (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4285 bytes --]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev7)
URL   : https://patchwork.freedesktop.org/series/141527/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16046 -> Patchwork_141527v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_141527v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - bat-adls-6:         [PASS][1] -> [FAIL][2] ([i915#13401])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-adls-6/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-adls-6/igt@i915_pm_rpm@module-reload.html
    - bat-dg1-7:          [PASS][3] -> [FAIL][4] ([i915#13401])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-dg1-7/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live:
    - bat-twl-1:          NOTRUN -> [ABORT][5] ([i915#12435] / [i915#12919] / [i915#13503])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-twl-1/igt@i915_selftest@live.html
    - bat-arlh-2:         [PASS][6] -> [DMESG-FAIL][7] ([i915#12061] / [i915#12435])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-arlh-2/igt@i915_selftest@live.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-arlh-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@requests:
    - bat-twl-1:          [PASS][8] -> [ABORT][9] ([i915#12919])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-twl-1/igt@i915_selftest@live@requests.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-twl-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-2:         [PASS][10] -> [DMESG-FAIL][11] ([i915#12061])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-arlh-2/igt@i915_selftest@live@workarounds.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][12] -> [SKIP][13] ([i915#9197]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][14] ([i915#12061]) -> [PASS][15] +1 other test pass
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
  [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
  [i915#13401]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13401
  [i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16046 -> Patchwork_141527v7

  CI-20190529: 20190529
  CI_DRM_16046: 54974a9354d844eca54feeec70870790fac17160 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8218: fafef52e0a83fec5f8c4f8df851d27319467762b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_141527v7: 54974a9354d844eca54feeec70870790fac17160 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/index.html

[-- Attachment #2: Type: text/html, Size: 5390 bytes --]

✗ i915.CI.Full: failure for drm/i915/xe3: FBC Dirty rect feature support (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 100278 bytes --]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev7)
URL   : https://patchwork.freedesktop.org/series/141527/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16046_full -> Patchwork_141527v7_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_141527v7_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_141527v7_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/index.html

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_141527v7_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2:
    - shard-mtlp:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-7/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-7/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2.html

  * igt@gem_eio@banned:
    - shard-mtlp:         NOTRUN -> [ABORT][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_eio@banned.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg1:          NOTRUN -> [INCOMPLETE][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html

  * igt@sysfs_heartbeat_interval@nopreempt@vcs1:
    - shard-mtlp:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-5/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt@vcs1.html

  
Known issues
------------

  Here are the changes found in Patchwork_141527v7_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#6230])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@api_intel_bb@crc32.html

  * igt@debugfs_test@basic-hwmon:
    - shard-tglu:         NOTRUN -> [SKIP][8] ([i915#9318])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@debugfs_test@basic-hwmon.html

  * igt@drm_fdinfo@busy-hang@bcs0:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#8414]) +6 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@drm_fdinfo@busy-hang@bcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@ccs0:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#8414]) +13 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@drm_fdinfo@most-busy-idle-check-all@ccs0.html

  * igt@gem_bad_reloc@negative-reloc-bltcopy:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#3281]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@gem_bad_reloc@negative-reloc-bltcopy.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-mtlp:         NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-dg1:          NOTRUN -> [SKIP][13] ([i915#9323]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#3555] / [i915#9323])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-dg1:          NOTRUN -> [SKIP][15] ([i915#3555] / [i915#9323])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][16] ([i915#7297])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-6/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][17] ([i915#12392] / [i915#7297])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-6/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-mtlp:         NOTRUN -> [SKIP][18] ([i915#7697])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#7697]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_persistence@engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][20] ([i915#1099]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-snb2/igt@gem_ctx_persistence@engines-mixed-process.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#8555]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_exec_balancer@bonded-dual:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#4771])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_exec_balancer@bonded-dual.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-mtlp:         NOTRUN -> [SKIP][23] ([i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg1:          NOTRUN -> [SKIP][24] ([i915#4771])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-tglu:         NOTRUN -> [SKIP][25] ([i915#4525]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_fence@submit3:
    - shard-dg1:          NOTRUN -> [SKIP][26] ([i915#4812]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_exec_fence@submit3.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_exec_flush@basic-batch-kernel-default-uc.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#3539])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-uc-rw-default:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_exec_flush@basic-uc-rw-default.html

  * igt@gem_exec_params@secure-non-root:
    - shard-dg2:          NOTRUN -> [SKIP][30] +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_reloc@basic-concurrent0:
    - shard-mtlp:         NOTRUN -> [SKIP][31] ([i915#3281]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_exec_reloc@basic-concurrent0.html

  * igt@gem_exec_reloc@basic-gtt-wc:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#3281]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_exec_reloc@basic-gtt-wc.html

  * igt@gem_exec_reloc@basic-wc-gtt-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][33] ([i915#3281]) +9 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html

  * igt@gem_exec_schedule@reorder-wide:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#4537] / [i915#4812])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_exec_schedule@reorder-wide.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-rkl:          NOTRUN -> [ABORT][35] ([i915#7975] / [i915#8213]) +1 other test abort
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#4860])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#4860])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_fenced_exec_thrash@2-spare-fences.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg1:          NOTRUN -> [SKIP][38] ([i915#4860]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][39] ([i915#4613]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#4613]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][41] ([i915#4613]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#4613]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_mmap@bad-object:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#4083]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_mmap@bad-object.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy:
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#4077]) +9 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_mmap_gtt@cpuset-basic-small-copy.html

  * igt@gem_mmap_gtt@fault-concurrent-x:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#4077]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_mmap_gtt@fault-concurrent-x.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#4083]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_mmap_wc@write:
    - shard-mtlp:         NOTRUN -> [SKIP][47] ([i915#4083]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_mmap_wc@write.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#3282]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_pread@bench:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#3282]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@gem_pread@bench.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#3282]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#4270])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-rkl:          NOTRUN -> [TIMEOUT][52] ([i915#12917] / [i915#12964])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-dg1:          NOTRUN -> [SKIP][53] ([i915#4270]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#8428])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html

  * igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#5190] / [i915#8428]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][56] ([i915#8411])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][57] ([i915#4079])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#4885])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_pread_basic:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#4079]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_tiled_pread_basic.html

  * igt@gem_tiled_pread_pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#4079])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@gem_tiled_pread_pwrite.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-tglu:         [PASS][61] -> [FAIL][62] ([i915#12941])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-tglu-9/igt@gem_tiled_swapping@non-threaded.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-8/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_tiling_max_stride:
    - shard-mtlp:         NOTRUN -> [SKIP][63] ([i915#4077]) +4 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_tiling_max_stride.html

  * igt@gem_unfence_active_buffers:
    - shard-mtlp:         NOTRUN -> [SKIP][64] ([i915#4879])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg1:          NOTRUN -> [SKIP][65] ([i915#3297])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#3297] / [i915#3323])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#3297] / [i915#4880])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@relocations:
    - shard-dg1:          NOTRUN -> [SKIP][68] ([i915#3281] / [i915#3297])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#3297]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-mtlp:         NOTRUN -> [SKIP][70] +10 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglu:         NOTRUN -> [SKIP][71] ([i915#2527] / [i915#2856]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#2527]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#2527]) +2 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu-1:       NOTRUN -> [SKIP][74] ([i915#2527] / [i915#2856]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#2856])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@gen9_exec_parse@secure-batches.html
    - shard-mtlp:         NOTRUN -> [SKIP][76] ([i915#2856])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][77] -> [ABORT][78] ([i915#9820])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu-1:       NOTRUN -> [ABORT][79] ([i915#12817] / [i915#9820])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg2:          [PASS][80] -> [ABORT][81] ([i915#9820])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [PASS][82] -> [INCOMPLETE][83] ([i915#12455]) +1 other test incomplete
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-6/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_pm_rps@basic-api:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#11681] / [i915#6621])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@i915_pm_rps@basic-api.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#4387])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][86] -> [SKIP][87] ([i915#7984])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-3/igt@i915_power@sanity.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-7/igt@i915_power@sanity.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([i915#6188])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_selftest@mock:
    - shard-snb:          NOTRUN -> [DMESG-WARN][89] ([i915#9311]) +1 other test dmesg-warn
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-snb5/igt@i915_selftest@mock.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-dg1:          [PASS][90] -> [DMESG-WARN][91] ([i915#4391] / [i915#4423])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-12/igt@i915_suspend@basic-s2idle-without-i915.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-12/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][92] ([i915#4212]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#8709]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#8709]) +15 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-dg2:          [PASS][95] -> [FAIL][96] ([i915#5956]) +1 other test fail
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
    - shard-rkl:          NOTRUN -> [FAIL][97] ([i915#11808]) +1 other test fail
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][98] ([i915#1769] / [i915#3555])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#5286]) +2 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#5286]) +3 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
    - shard-tglu-1:       NOTRUN -> [SKIP][101] ([i915#5286]) +4 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#4538] / [i915#5286]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][103] ([i915#3638]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#3638]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][105] ([i915#5190]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_big_fb@y-tiled-addfb.html
    - shard-mtlp:         NOTRUN -> [SKIP][106] ([i915#6187])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([i915#4538] / [i915#5190]) +3 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#4538]) +3 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][109] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-8/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#12313])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][111] ([i915#6095]) +44 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#10307] / [i915#6095]) +114 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#12313])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][114] ([i915#6095]) +137 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-14/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][115] ([i915#12805])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#6095]) +69 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#6095]) +20 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][118] ([i915#12313])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][119] ([i915#6095]) +39 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][120] ([i915#6095]) +34 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#12313])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#11616] / [i915#7213]) +3 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-tglu-1:       NOTRUN -> [SKIP][123] ([i915#11151] / [i915#7828]) +6 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
    - shard-mtlp:         NOTRUN -> [SKIP][124] ([i915#11151] / [i915#7828]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#11151] / [i915#7828]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#11151] / [i915#7828]) +8 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][127] ([i915#11151] / [i915#7828]) +4 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#11151] / [i915#7828]) +4 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_color@deep-color:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([i915#3555] / [i915#9979])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#7116] / [i915#9424])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [TIMEOUT][131] ([i915#7173]) +1 other test timeout
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#7118] / [i915#9424])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@content-type-change:
    - shard-mtlp:         NOTRUN -> [SKIP][133] ([i915#6944] / [i915#9424])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([i915#3299]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#3299])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#3116])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][137] ([i915#3116] / [i915#3299])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#7118] / [i915#9424])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg1:          NOTRUN -> [SKIP][139] ([i915#9424])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-1:
    - shard-tglu:         NOTRUN -> [SKIP][140] ([i915#6944] / [i915#9424])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@uevent:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#13049])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#3555]) +5 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - shard-mtlp:         NOTRUN -> [SKIP][144] ([i915#8814]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_cursor_crc@cursor-random-256x85.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][145] ([i915#3555]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#13049]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][147] ([i915#13049])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#13046] / [i915#5354]) +4 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][149] ([i915#4103] / [i915#4213])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][150] ([i915#4103] / [i915#4213])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-mtlp:         NOTRUN -> [SKIP][151] ([i915#9809]) +3 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-mtlp:         NOTRUN -> [SKIP][152] ([i915#4213])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#4103])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#9833])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#9833])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg1:          NOTRUN -> [SKIP][156] ([i915#9723])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#1769] / [i915#3555] / [i915#3804])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][158] ([i915#3804])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#3840])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#3555] / [i915#3840])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-tglu:         NOTRUN -> [SKIP][161] ([i915#3555] / [i915#3840])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg1:          NOTRUN -> [SKIP][162] ([i915#3840] / [i915#9053])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@display-4x:
    - shard-dg1:          NOTRUN -> [SKIP][163] ([i915#1839]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][164] ([i915#9934]) +4 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#3637]) +5 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#8381])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#9934]) +5 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([i915#9934]) +5 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_flip@2x-plain-flip.html
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#3637]) +4 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2:
    - shard-rkl:          NOTRUN -> [FAIL][170] ([i915#11989])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
    - shard-mtlp:         [PASS][171] -> [FAIL][172] ([i915#11989]) +2 other tests fail
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@d-hdmi-a1:
    - shard-tglu:         [PASS][173] -> [FAIL][174] ([i915#11989])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-tglu-10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@d-hdmi-a1.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#8381])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][176] ([i915#2672] / [i915#3555]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#2672] / [i915#3555]) +4 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][178] ([i915#2672] / [i915#3555]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#2672]) +4 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#2587] / [i915#2672]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][181] ([i915#2587] / [i915#2672] / [i915#3555])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#2587] / [i915#2672] / [i915#3555])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][183] ([i915#2672] / [i915#8813])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][184] ([i915#2587] / [i915#2672]) +3 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][185] ([i915#3555] / [i915#8810] / [i915#8813])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][186] ([i915#3555] / [i915#8810])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#2672] / [i915#3555])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][188] ([i915#2672])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#2672] / [i915#3555]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#2587] / [i915#2672]) +2 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][191] ([i915#2672] / [i915#3555] / [i915#8813]) +4 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-dg2:          [PASS][192] -> [FAIL][193] ([i915#6880])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][194] ([i915#10055])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#3023]) +20 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][196] ([i915#8708]) +9 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#1825]) +26 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][198] +27 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][199] ([i915#1825]) +12 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][200] ([i915#8708]) +2 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] +57 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][202] ([i915#5439])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-dg1:          NOTRUN -> [SKIP][203] ([i915#9766])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#8708]) +9 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
    - shard-dg2:          NOTRUN -> [SKIP][205] ([i915#5354]) +11 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#3458]) +5 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][207] +41 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][208] ([i915#3458]) +14 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html

  * igt@kms_hdr@bpc-switch:
    - shard-tglu:         NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8228]) +1 other test skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][210] ([i915#3555] / [i915#8228])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#12713])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([i915#3555] / [i915#8228])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [PASS][213] -> [SKIP][214] ([i915#3555] / [i915#8228]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-10/igt@kms_hdr@static-toggle.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-4/igt@kms_hdr@static-toggle.html

  * igt@kms_invalid_mode@clock-too-high:
    - shard-mtlp:         NOTRUN -> [SKIP][215] ([i915#3555] / [i915#6403] / [i915#8826])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_invalid_mode@clock-too-high.html

  * igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][216] ([i915#9457]) +3 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_invalid_mode@clock-too-high@pipe-a-edp-1.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][217] ([i915#10656])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][218] ([i915#12388])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][219] ([i915#12394])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg1:          NOTRUN -> [SKIP][220] ([i915#12339])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [PASS][221] -> [SKIP][222] ([i915#12388])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#12388])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg1:          NOTRUN -> [SKIP][224] ([i915#6301])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#6301])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][226] ([i915#3555]) +2 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_plane_multiple@tiling-yf.html
    - shard-tglu-1:       NOTRUN -> [SKIP][227] ([i915#3555]) +1 other test skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#6953])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-dg1:          NOTRUN -> [SKIP][229] ([i915#12247]) +9 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a:
    - shard-mtlp:         NOTRUN -> [SKIP][230] ([i915#12247]) +14 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation:
    - shard-tglu:         NOTRUN -> [SKIP][231] ([i915#12247]) +4 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2:          NOTRUN -> [SKIP][232] ([i915#12247] / [i915#9423])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#12247]) +7 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][234] ([i915#12247] / [i915#6953] / [i915#9423])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75:
    - shard-rkl:          [PASS][235] -> [DMESG-WARN][236] ([i915#12964]) +8 other tests dmesg-warn
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][237] ([i915#12247] / [i915#3555])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#12247]) +1 other test skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][239] ([i915#5354])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade:
    - shard-dg1:          NOTRUN -> [SKIP][240] ([i915#5354])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg1:          NOTRUN -> [SKIP][241] ([i915#9685])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-tglu:         NOTRUN -> [SKIP][242] ([i915#9685])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][243] ([i915#3828])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-tglu-1:       NOTRUN -> [SKIP][244] ([i915#3828])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][245] ([i915#4281])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][246] ([i915#3828])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][247] ([i915#9519])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          NOTRUN -> [SKIP][248] ([i915#9519]) +1 other test skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [PASS][249] -> [SKIP][250] ([i915#9519]) +2 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
    - shard-tglu-1:       NOTRUN -> [SKIP][251] ([i915#9519])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-mtlp:         NOTRUN -> [SKIP][252] ([i915#9519])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][253] ([i915#6524]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_prime@basic-modeset-hybrid.html
    - shard-tglu-1:       NOTRUN -> [SKIP][254] ([i915#6524])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-snb:          NOTRUN -> [SKIP][255] ([i915#11520]) +4 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-snb2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][256] ([i915#11520]) +1 other test skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-tglu:         NOTRUN -> [SKIP][257] ([i915#11520]) +5 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][258] ([i915#9808]) +3 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-mtlp:         NOTRUN -> [SKIP][259] ([i915#12316]) +1 other test skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][260] ([i915#11520]) +5 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-dg1:          NOTRUN -> [SKIP][261] ([i915#11520]) +5 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          NOTRUN -> [SKIP][262] ([i915#11520]) +8 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][263] ([i915#4348])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_psr2_su@page_flip-xrgb8888.html
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#9683])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-plane-onoff:
    - shard-dg1:          NOTRUN -> [SKIP][265] ([i915#1072] / [i915#9732]) +15 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_psr@fbc-pr-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr-cursor-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][266] ([i915#9688]) +7 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_psr@fbc-psr-cursor-mmap-gtt@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][267] ([i915#9732]) +14 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2:          NOTRUN -> [SKIP][268] ([i915#1072] / [i915#9732]) +11 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr@psr-sprite-blt:
    - shard-snb:          NOTRUN -> [SKIP][269] +136 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-snb5/igt@kms_psr@psr-sprite-blt.html

  * igt@kms_psr@psr2-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][270] ([i915#9732]) +9 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_psr@psr2-cursor-plane-onoff.html

  * igt@kms_psr@psr2-primary-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][271] ([i915#4077] / [i915#9688]) +1 other test skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_psr@psr2-primary-mmap-gtt@edp-1.html

  * igt@kms_psr@psr2-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][272] ([i915#1072] / [i915#9732]) +13 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_psr@psr2-suspend.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          NOTRUN -> [SKIP][273] ([i915#9685])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][274] ([i915#9685])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][275] ([i915#5289])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-tglu-1:       NOTRUN -> [SKIP][276] ([i915#5289])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
    - shard-mtlp:         NOTRUN -> [SKIP][277] ([i915#12755])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-mtlp:         NOTRUN -> [SKIP][278] ([i915#3555] / [i915#5030] / [i915#9041])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][279] ([i915#5030]) +2 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html

  * igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][280] ([i915#5030] / [i915#9041])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-rkl:          NOTRUN -> [ABORT][281] ([i915#13179]) +1 other test abort
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-1/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
    - shard-dg2:          NOTRUN -> [ABORT][282] ([i915#13179]) +1 other test abort
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#3555])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-tglu-1:       NOTRUN -> [SKIP][284] ([i915#8623])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][285] ([i915#12917] / [i915#12964])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-6/igt@kms_vblank@query-forked-hang@pipe-a-hdmi-a-2.html

  * igt@kms_vblank@ts-continuation-idle-hang:
    - shard-dg1:          [PASS][286] -> [DMESG-WARN][287] ([i915#4423]) +3 other tests dmesg-warn
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-17/igt@kms_vblank@ts-continuation-idle-hang.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_vblank@ts-continuation-idle-hang.html

  * igt@kms_vblank@wait-forked-busy-hang:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][288] ([i915#12964]) +15 other tests dmesg-warn
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_vblank@wait-forked-busy-hang.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][289] ([i915#9906])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@lobf:
    - shard-tglu:         NOTRUN -> [SKIP][290] ([i915#11920])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-10/igt@kms_vrr@lobf.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          NOTRUN -> [SKIP][291] ([i915#3555] / [i915#9906])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg2:          NOTRUN -> [SKIP][292] ([i915#9906])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][293] ([i915#2437] / [i915#9412])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-tglu-1:       NOTRUN -> [SKIP][294] ([i915#2437])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][295] ([i915#2437] / [i915#9412]) +1 other test skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@kms_writeback@writeback-pixel-formats.html
    - shard-tglu-1:       NOTRUN -> [SKIP][296] ([i915#2437] / [i915#9412])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-1/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@mi-rpc:
    - shard-rkl:          NOTRUN -> [SKIP][297] ([i915#2434])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-7/igt@perf@mi-rpc.html

  * igt@perf_pmu@cpu-hotplug:
    - shard-rkl:          NOTRUN -> [SKIP][298] ([i915#8850])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@perf_pmu@cpu-hotplug.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-dg1:          NOTRUN -> [SKIP][299] ([i915#8516]) +1 other test skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_mmap@test_aperture_limit:
    - shard-dg2:          NOTRUN -> [WARN][300] ([i915#9351])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@prime_mmap@test_aperture_limit.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [CRASH][301] ([i915#9351])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@basic-read:
    - shard-mtlp:         NOTRUN -> [SKIP][302] ([i915#3708])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-dg2:          NOTRUN -> [SKIP][303] ([i915#3708])
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@prime_vgem@fence-flip-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg1:          NOTRUN -> [SKIP][304] ([i915#3708])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-rkl:          NOTRUN -> [SKIP][305] ([i915#9917])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@sriov_basic@bind-unbind-vf.html

  * igt@sysfs_heartbeat_interval@nopreempt:
    - shard-mtlp:         [PASS][306] -> [ABORT][307] ([i915#13193])
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-5/igt@sysfs_heartbeat_interval@nopreempt.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-rkl:          NOTRUN -> [SKIP][308] +15 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-2/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-dg2:          [ABORT][309] ([i915#13427]) -> [PASS][310]
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
    - shard-mtlp:         [DMESG-WARN][311] -> [PASS][312]
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-7/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-7/igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox.html

  * igt@gem_eio@in-flight-internal-immediate:
    - shard-mtlp:         [ABORT][313] -> [PASS][314]
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-7/igt@gem_eio@in-flight-internal-immediate.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-4/igt@gem_eio@in-flight-internal-immediate.html

  * igt@gem_eio@unwedge-stress:
    - shard-mtlp:         [ABORT][315] ([i915#13193]) -> [PASS][316] +1 other test pass
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-7/igt@gem_eio@unwedge-stress.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [INCOMPLETE][317] ([i915#11441] / [i915#13304]) -> [PASS][318] +1 other test pass
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-7/igt@gem_exec_suspend@basic-s0@smem.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [TIMEOUT][319] ([i915#5493]) -> [PASS][320] +1 other test pass
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-tglu:         [FAIL][321] ([i915#10991] / [i915#13320]) -> [PASS][322]
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-tglu-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-8/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][323] ([i915#10991]) -> [PASS][324]
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-tglu-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-8/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html

  * igt@kms_atomic@plane-overlay-legacy:
    - shard-rkl:          [DMESG-WARN][325] ([i915#12964]) -> [PASS][326] +8 other tests pass
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-3/igt@kms_atomic@plane-overlay-legacy.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-3/igt@kms_atomic@plane-overlay-legacy.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-rkl:          [FAIL][327] ([i915#13566]) -> [PASS][328] +6 other tests pass
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-128x42.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-tglu:         [FAIL][329] ([i915#13566]) -> [PASS][330] +3 other tests pass
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-128x42.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-tglu-5/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_flip@blocking-wf_vblank@b-hdmi-a2:
    - shard-rkl:          [FAIL][331] ([i915#11989]) -> [PASS][332] +2 other tests pass
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-5/igt@kms_flip@blocking-wf_vblank@b-hdmi-a2.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-5/igt@kms_flip@blocking-wf_vblank@b-hdmi-a2.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          [SKIP][333] ([i915#3555] / [i915#8228]) -> [PASS][334]
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-4/igt@kms_hdr@bpc-switch-dpms.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][335] ([i915#9519]) -> [PASS][336]
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2:          [SKIP][337] ([i915#9519]) -> [PASS][338]
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  
#### Warnings ####

  * igt@kms_chamelium_audio@dp-audio:
    - shard-dg1:          [SKIP][339] ([i915#11151] / [i915#7828]) -> [SKIP][340] ([i915#11151] / [i915#4423] / [i915#7828])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-17/igt@kms_chamelium_audio@dp-audio.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-18/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][341] ([i915#9424]) -> [SKIP][342] ([i915#9433])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-14/igt@kms_content_protection@mei-interface.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_content_protection@mei-interface.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-rkl:          [DMESG-FAIL][343] ([i915#12964]) -> [INCOMPLETE][344] ([i915#9878])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-4/igt@kms_fbcon_fbt@fbc-suspend.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-5/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][345] ([i915#10433] / [i915#3458]) -> [SKIP][346] ([i915#3458]) +2 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          [SKIP][347] ([i915#3458]) -> [SKIP][348] ([i915#10433] / [i915#3458]) +1 other test skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-mtlp:         [SKIP][349] ([i915#12713]) -> [SKIP][350] ([i915#1187] / [i915#12713])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-mtlp-2/igt@kms_hdr@brightness-with-hdr.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-mtlp-1/igt@kms_hdr@brightness-with-hdr.html
    - shard-dg1:          [SKIP][351] ([i915#12713]) -> [SKIP][352] ([i915#1187] / [i915#12713])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-dg1-17/igt@kms_hdr@brightness-with-hdr.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-dg1-13/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][353] ([i915#4816]) -> [SKIP][354] ([i915#4070] / [i915#4816])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16046/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#10991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10991
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
  [i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#12455]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12455
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
  [i915#13304]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13304
  [i915#13320]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13320
  [i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5030
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6403
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7297
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
  [i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
  [i915#9041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9041
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9457]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9457
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_16046 -> Patchwork_141527v7

  CI-20190529: 20190529
  CI_DRM_16046: 54974a9354d844eca54feeec70870790fac17160 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8218:

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_141527v7/index.html

[-- Attachment #2: Type: text/html, Size: 125866 bytes --]

Re: [PATCH v6 0/7] drm/i915/xe3: FBC Dirty rect feature support

[Jani Nikula]

On Thu, 30 Jan 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> Dirty rect support for FBC in xe3 onwards based on the comments after the
> initial RFC series.

I think "drm/i915/fbc" subject prefix is more appropriate than
"drm/i915/xe3".

(Please don't resend just for that.)

>
> v2: Dirty rect related compute and storage moved to fbc state (Ville)
>
> V3: Dont call fbc activate if FBC is already active
>
> v4: Dirty rect compute and programming moved within DSB scope
>     New changes are added as separate patches to make it easy for review
>     But could be squashed if the reviews as ok.
>
> v5: add HAS_FBC_DIRTY_RECT()
>     FBC Damage area updates in 3 steps. 
>     1. As part of plane_atomic_check() get, adjust coordinates and store
>        the merged damage area in plane_state
>     2. Atomic_commit, update merged damage are to fbc_state and prepare the
>        damage area satifying all conditions
>     3  update the FBC dirty rect registers as part of DSB commit.
>
> v6: Use dmage_merged helper earlier to handle bigjoiner cases (Ville)
>     Place the damage_merged handling code under HAS_FBC_DIRTY_RECT()
>     Added a variable to check if the damage_merged received from
>     the helper is valid. And if it is not valid, the FBC dirty rect
>     is updated with full plane reqion.
>
> Vinod Govindapillai (7):
>   drm/i915/xe3: add register definitions for fbc dirty rect support
>   drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect
>     support
>   drm/damage-helper: add const qualifier in
>     drm_atomic_helper_damage_merged()
>   drm/i915/xe3: update and store the plane damage clips
>   drm/i915/xe3: dirty rect support for FBC
>   drm/i915/xe3: avoid calling fbc activate if fbc is active
>   drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled
>
>  drivers/gpu/drm/drm_damage_helper.c           |   2 +-
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  28 ++++
>  drivers/gpu/drm/i915/display/intel_display.c  |   7 +
>  .../drm/i915/display/intel_display_device.h   |   1 +
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 152 +++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_fbc.h      |   6 +
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h |   9 ++
>  .../drm/i915/display/skl_universal_plane.c    |  45 +++++-
>  include/drm/drm_damage_helper.h               |   2 +-
>  10 files changed, 246 insertions(+), 8 deletions(-)

-- 
Jani Nikula, Intel