* [PATCH 01/11] drm/i915/dpll: Rename intel_shared_dpll_state
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 02/11] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
` (12 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename intel_shared_dpll_state to just intel_dpll_state since it may
not necessarily store share dpll state info specially since
DISPLAY_VER >= 14 PLL's are not shared.
Also change the name of variables which may have been assoiciated as
a shared_dpll.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 60 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 12 ++--
.../drm/i915/display/intel_modeset_verify.c | 2 +-
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4440521e3e9e..acb8717319a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -590,7 +590,7 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
+ struct intel_dpll_state dpll_state[I915_NUM_PLLS];
struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c825a507b905..54ae2078daa5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -119,17 +119,17 @@ struct intel_dpll_mgr {
static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
- struct intel_shared_dpll_state *shared_dpll)
+ struct intel_dpll_state *dpll_state)
{
struct intel_shared_dpll *pll;
int i;
/* Copy shared dpll state */
for_each_shared_dpll(display, pll, i)
- shared_dpll[pll->index] = pll->state;
+ dpll_state[pll->index] = pll->state;
}
-static struct intel_shared_dpll_state *
+static struct intel_dpll_state *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
@@ -141,10 +141,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
state->dpll_set = true;
intel_atomic_duplicate_dpll_state(display,
- state->shared_dpll);
+ state->dpll_state);
}
- return state->shared_dpll;
+ return state->dpll_state;
}
/**
@@ -362,11 +362,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
@@ -378,20 +378,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
continue;
/* Only want to check enabled timings first */
- if (shared_dpll[pll->index].pipe_mask == 0) {
+ if (dpll_state[pll->index].pipe_mask == 0) {
if (!unused_pll)
unused_pll = pll;
continue;
}
if (memcmp(dpll_hw_state,
- &shared_dpll[pll->index].hw_state,
+ &dpll_state[pll->index].hw_state,
sizeof(*dpll_hw_state)) == 0) {
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
- shared_dpll[pll->index].pipe_mask,
+ dpll_state[pll->index].pipe_mask,
pll->active_mask);
return pll;
}
@@ -412,20 +412,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
- shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
+ dpll_state->pipe_mask |= BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -437,34 +437,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- if (shared_dpll[pll->index].pipe_mask == 0)
- shared_dpll[pll->index].hw_state = *dpll_hw_state;
+ if (dpll_state[pll->index].pipe_mask == 0)
+ dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
* intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
- shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
+ dpll_state->pipe_mask &= ~BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -474,11 +474,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
+ struct intel_dpll_state *dpll_state = state->dpll_state;
struct intel_shared_dpll *pll;
int i;
@@ -519,7 +519,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
return;
for_each_shared_dpll(display, pll, i)
- swap(pll->state, shared_dpll[pll->index]);
+ swap(pll->state, dpll_state[pll->index]);
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
@@ -4686,8 +4686,8 @@ static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
}
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state =
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index caffb084830c..db0d5f972d6e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -280,7 +280,7 @@ struct intel_dpll_hw_state {
};
/**
- * struct intel_shared_dpll_state - hold the DPLL atomic state
+ * struct intel_dpll_state - hold the DPLL atomic state
*
* This structure holds an atomic state for the DPLL, that can represent
* either its current state (in struct &intel_shared_dpll) or a desired
@@ -289,7 +289,7 @@ struct intel_dpll_hw_state {
*
* See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
*/
-struct intel_shared_dpll_state {
+struct intel_dpll_state {
/**
* @pipe_mask: mask of pipes using this DPLL, active or not
*/
@@ -353,7 +353,7 @@ struct intel_shared_dpll {
* Store the state for the pll, including its hw state
* and CRTCs using it.
*/
- struct intel_shared_dpll_state state;
+ struct intel_dpll_state state;
/**
* @index: index for atomic state
@@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state);
+ struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
@@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
#endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index bc70e72ccc2e..5f3b1c2b081b 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -245,7 +245,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
intel_wm_state_verify(state, crtc);
verify_connector_state(state, crtc);
verify_crtc_state(state, crtc);
- intel_shared_dpll_state_verify(state, crtc);
+ intel_dpll_state_verify(state, crtc);
intel_mpllb_state_verify(state, crtc);
intel_cx0pll_state_verify(state, crtc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 02/11] drm/i915/dpll: Rename macro for_each_shared_dpll
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
2025-02-25 8:09 ` [PATCH 01/11] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 03/11] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
` (11 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename the macro for_each_shared_dpll to for_each_dpll since
this loop will not necessarily be used for only shared
dpll in future.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 9de7e512c0ab..079c7af4d7da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -642,7 +642,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
display->dpll.ref_clks.nssc,
display->dpll.ref_clks.ssc);
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
pll->info->name, pll->info->id);
drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 54ae2078daa5..d03789dfc9c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -124,8 +124,8 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- /* Copy shared dpll state */
- for_each_shared_dpll(display, pll, i)
+ /* Copy dpll state */
+ for_each_dpll(display, pll, i)
dpll_state[pll->index] = pll->state;
}
@@ -162,7 +162,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
if (pll->info->id == id)
return pll;
}
@@ -345,7 +345,7 @@ intel_dpll_mask_all(struct intel_display *display)
unsigned long dpll_mask = 0;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
dpll_mask |= BIT(pll->info->id);
@@ -518,7 +518,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
swap(pll->state, dpll_state[pll->index]);
}
@@ -4545,7 +4545,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
readout_dpll_hw_state(display, pll);
}
@@ -4574,7 +4574,7 @@ void intel_dpll_sanitize_state(struct intel_display *display)
intel_cx0_pll_power_save_wa(display);
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
sanitize_dpll_state(display, pll);
}
@@ -4723,6 +4723,6 @@ void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
verify_single_dpll_state(display, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index db0d5f972d6e..3775d2b0fbe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -30,7 +30,7 @@
#include "intel_display_power.h"
#include "intel_wakeref.h"
-#define for_each_shared_dpll(__display, __pll, __i) \
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 33467de3d115..ebec879bacf7 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -530,7 +530,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Check if any DPLLs are using the SSC source */
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
u32 temp;
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 03/11] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
2025-02-25 8:09 ` [PATCH 01/11] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
2025-02-25 8:09 ` [PATCH 02/11] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 04/11] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
` (10 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename intel_shared_dpll_funcs to intel_global_dpll_funcs
since it needs to represent both shared and individual
dplls.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d03789dfc9c5..1f336f26f08d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -61,7 +61,7 @@
*/
/* platform specific hooks for managing DPLLs */
-struct intel_shared_dpll_funcs {
+struct intel_global_dpll_funcs {
/*
* Hook for enabling the pll, called from intel_enable_shared_dpll() if
* the pll is not already enabled.
@@ -668,7 +668,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->fp1 == b->fp1;
}
-static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
+static const struct intel_global_dpll_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
@@ -1270,14 +1270,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->spll == b->spll;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
+static const struct intel_global_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
-static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
+static const struct intel_global_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
.disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
@@ -1302,7 +1302,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
return true;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
+static const struct intel_global_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
.disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
@@ -2004,14 +2004,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->cfgcr2 == b->cfgcr2;
}
-static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
+static const struct intel_global_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
+static const struct intel_global_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
.disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
@@ -2486,7 +2486,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->pcsdw12 == b->pcsdw12;
}
-static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
+static const struct intel_global_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
@@ -4131,21 +4131,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
}
-static const struct intel_shared_dpll_funcs combo_pll_funcs = {
+static const struct intel_global_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
+static const struct intel_global_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
.disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs mg_pll_funcs = {
+static const struct intel_global_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
@@ -4193,7 +4193,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.compare_hw_state = icl_compare_hw_state,
};
-static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+static const struct intel_global_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3775d2b0fbe9..5bfe14dde3f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -41,7 +41,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_shared_dpll;
-struct intel_shared_dpll_funcs;
+struct intel_global_dpll_funcs;
/**
* enum intel_dpll_id - possible DPLL ids
@@ -314,7 +314,7 @@ struct dpll_info {
/**
* @funcs: platform specific hooks
*/
- const struct intel_shared_dpll_funcs *funcs;
+ const struct intel_global_dpll_funcs *funcs;
/**
* @id: unique identifier for this DPLL
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 04/11] drm/i915/dpll: Rename intel_shared_dpll
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (2 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 03/11] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
` (9 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename intel_shared_dpll to intel_global_dpll to represent both
shared and individual dplls.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
.../gpu/drm/i915/display/intel_display_core.h | 4 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 8 +-
.../gpu/drm/i915/display/intel_pch_display.c | 10 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
15 files changed, 182 insertions(+), 182 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5d3d54922d62..bad6967d8840 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -657,7 +657,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
enum phy phy;
u32 val;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7937f4de66cb..82bcf5031a09 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -237,7 +237,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_global_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -261,7 +261,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
int clock = crtc_state->port_clock;
const enum intel_dpll_id id = pll->info->id;
@@ -1571,7 +1571,7 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
return !(intel_de_read(i915, reg) & clk_off);
}
-static struct intel_shared_dpll *
+static struct intel_global_dpll *
_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
@@ -1586,7 +1586,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1616,7 +1616,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1630,7 +1630,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1660,7 +1660,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1674,7 +1674,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1713,7 +1713,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1740,7 +1740,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1770,7 +1770,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
+struct intel_global_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1784,7 +1784,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1827,7 +1827,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum tc_port tc_port = intel_encoder_to_tc(encoder);
enum port port = encoder->port;
@@ -1878,7 +1878,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
}
-static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
@@ -1908,7 +1908,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return intel_get_shared_dpll_by_id(display, id);
}
-static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder->base.dev);
enum intel_dpll_id id;
@@ -1935,7 +1935,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(&i915->drm, !pll))
@@ -1977,7 +1977,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
}
-static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -2003,7 +2003,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(&i915->drm, !pll))
@@ -2028,7 +2028,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
}
-static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_global_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -4206,7 +4206,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
@@ -4222,7 +4222,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->global_dpll,
&crtc_state->dpll_hw_state);
}
@@ -4276,7 +4276,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(encoder, crtc_state);
}
-static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_global_dpll *pll)
{
return pll->info->id == DPLL_ID_ICL_TBTPLL;
}
@@ -4286,7 +4286,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_global_dpll *pll = crtc_state->global_dpll;
if (drm_WARN_ON(&i915->drm, !pll))
return ICL_PORT_DPLL_DEFAULT;
@@ -4309,7 +4309,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id;
@@ -4332,10 +4332,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
+ if (icl_ddi_tc_pll_is_tbt(crtc_state->global_dpll))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->global_dpll,
&crtc_state->dpll_hw_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 2faadd1441e2..2425fcb04a27 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -19,7 +19,7 @@ struct intel_display;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
-struct intel_shared_dpll;
+struct intel_global_dpll;
enum pipe;
enum port;
enum transcoder;
@@ -41,7 +41,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
void intel_ddi_disable_clock(struct intel_encoder *encoder);
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll);
+ struct intel_global_dpll *pll);
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
@@ -51,7 +51,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
+struct intel_global_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 065fdf6dbb88..4577787cb8f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1350,7 +1350,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
if (intel_crtc_needs_modeset(new_crtc_state))
continue;
- new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
+ new_crtc_state->global_dpll = old_crtc_state->global_dpll;
new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
}
}
@@ -1694,7 +1694,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_crtc_state =
intel_atomic_get_new_crtc_state(state, pipe_crtc);
- if (pipe_crtc_state->shared_dpll)
+ if (pipe_crtc_state->global_dpll)
intel_enable_shared_dpll(pipe_crtc_state);
}
@@ -2040,7 +2040,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
- if (crtc_state->shared_dpll)
+ if (crtc_state->global_dpll)
set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
if (crtc_state->dsc.compression_enable)
@@ -3121,7 +3121,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->sink_format = pipe_config->output_format;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
- pipe_config->shared_dpll = NULL;
+ pipe_config->global_dpll = NULL;
ret = false;
@@ -3503,7 +3503,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
return false;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
- pipe_config->shared_dpll = NULL;
+ pipe_config->global_dpll = NULL;
ret = false;
tmp = intel_de_read(dev_priv,
@@ -4080,7 +4080,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
POWER_DOMAIN_PIPE(crtc->pipe)))
return false;
- pipe_config->shared_dpll = NULL;
+ pipe_config->global_dpll = NULL;
active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
@@ -4663,7 +4663,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
/* preserve some things from the slave's original crtc state */
saved_state->uapi = secondary_crtc_state->uapi;
saved_state->scaler_state = secondary_crtc_state->scaler_state;
- saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
+ saved_state->global_dpll = secondary_crtc_state->global_dpll;
saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
intel_crtc_free_hw_state(secondary_crtc_state);
@@ -4726,7 +4726,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
saved_state->uapi = crtc_state->uapi;
saved_state->inherited = crtc_state->inherited;
saved_state->scaler_state = crtc_state->scaler_state;
- saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->global_dpll = crtc_state->global_dpll;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
sizeof(saved_state->icl_port_dplls));
@@ -5479,7 +5479,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
if (dev_priv->display.dpll.mgr)
- PIPE_CONF_CHECK_P(shared_dpll);
+ PIPE_CONF_CHECK_P(global_dpll);
/* FIXME convert everything over the dpll_mgr */
if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 554870d2494b..285b2d4cc130 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -125,8 +125,8 @@ struct intel_audio {
struct intel_dpll {
struct mutex lock;
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ int num_global_dpll;
+ struct intel_global_dpll global_dplls[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 079c7af4d7da..c63c9e155aee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -633,7 +633,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
drm_modeset_lock_all(display->drm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index acb8717319a2..87a7b9111ceb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1072,8 +1072,8 @@ struct intel_crtc_state {
* haswell. */
struct dpll dpll;
- /* Selected dpll when shared or NULL. */
- struct intel_shared_dpll *shared_dpll;
+ /* Selected dpll. */
+ struct intel_global_dpll *global_dpll;
/* Actual register state of the dpll, for shared dpll cross-checking. */
struct intel_dpll_hw_state dpll_hw_state;
@@ -1083,7 +1083,7 @@ struct intel_crtc_state {
* setting shared_dpll and dpll_hw_state to one of these reserved ones.
*/
struct icl_port_dpll {
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
struct intel_dpll_hw_state hw_state;
} icl_port_dplls[ICL_PORT_DPLL_COUNT];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 08a30e5aafce..96c79269c755 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1783,9 +1783,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
- drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
+ drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->global_dpll);
- if (!crtc_state->hw.enable || crtc_state->shared_dpll)
+ if (!crtc_state->hw.enable || crtc_state->global_dpll)
return 0;
if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1f336f26f08d..b26351eff7a8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -67,7 +67,7 @@ struct intel_global_dpll_funcs {
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -76,7 +76,7 @@ struct intel_global_dpll_funcs {
* tracked users for it.
*/
void (*disable)(struct intel_display *display,
- struct intel_shared_dpll *pll);
+ struct intel_global_dpll *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -84,7 +84,7 @@ struct intel_global_dpll_funcs {
* verification after a mode set.
*/
bool (*get_hw_state)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -92,7 +92,7 @@ struct intel_global_dpll_funcs {
* in state.
*/
int (*get_freq)(struct intel_display *i915,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
};
@@ -121,7 +121,7 @@ static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_dpll_state *dpll_state)
{
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
/* Copy dpll state */
@@ -155,11 +155,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* Returns:
* A pointer to the DPLL with @id
*/
-struct intel_shared_dpll *
+struct intel_global_dpll *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
for_each_dpll(display, pll, i) {
@@ -173,7 +173,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
/* For ILK+ */
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
bool state)
{
bool cur_state;
@@ -202,7 +202,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
static i915_reg_t
intel_combo_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
if (display->platform.dg1)
return DG1_DPLL_ENABLE(pll->info->id);
@@ -215,7 +215,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
static i915_reg_t
intel_tc_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -227,7 +227,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
}
static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
@@ -237,7 +237,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display,
}
static void _intel_disable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
pll->info->funcs->disable(display, pll);
pll->on = false;
@@ -256,7 +256,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
unsigned int old_mask;
@@ -302,7 +302,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
unsigned int pipe_mask = BIT(crtc->pipe);
/* PCH only available on ILK+ */
@@ -341,7 +341,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
static unsigned long
intel_dpll_mask_all(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
unsigned long dpll_mask = 0;
int i;
@@ -354,7 +354,7 @@ intel_dpll_mask_all(struct intel_display *display)
return dpll_mask;
}
-static struct intel_shared_dpll *
+static struct intel_global_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *dpll_hw_state,
@@ -363,7 +363,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
struct intel_dpll_state *dpll_state;
- struct intel_shared_dpll *unused_pll = NULL;
+ struct intel_global_dpll *unused_pll = NULL;
enum intel_dpll_id id;
dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
@@ -371,7 +371,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
pll = intel_get_shared_dpll_by_id(display, id);
if (!pll)
@@ -418,7 +418,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -434,7 +434,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void
intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
@@ -457,7 +457,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -472,7 +472,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll)
+ const struct intel_global_dpll *pll)
{
struct intel_dpll_state *dpll_state;
@@ -489,12 +489,12 @@ static void intel_put_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->global_dpll = NULL;
- if (!old_crtc_state->shared_dpll)
+ if (!old_crtc_state->global_dpll)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
+ intel_unreference_shared_dpll(state, crtc, old_crtc_state->global_dpll);
}
/**
@@ -512,7 +512,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
if (!state->dpll_set)
@@ -523,7 +523,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -559,7 +559,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
}
static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -588,7 +588,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
}
static void ibx_pch_dpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -612,7 +612,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
enum intel_dpll_id id;
if (HAS_PCH_IBX(i915)) {
@@ -638,7 +638,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->global_dpll = pll;
return 0;
}
@@ -690,7 +690,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
};
static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -702,7 +702,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
}
static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -713,7 +713,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
}
static void hsw_ddi_wrpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
struct drm_i915_private *i915 = to_i915(display->drm);
const enum intel_dpll_id id = pll->info->id;
@@ -730,7 +730,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
}
static void hsw_ddi_spll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
struct drm_i915_private *i915 = to_i915(display->drm);
enum intel_dpll_id id = pll->info->id;
@@ -747,7 +747,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
}
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -769,7 +769,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
}
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -996,7 +996,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
}
static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1059,7 +1059,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_global_dpll *
hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1090,11 +1090,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
}
}
-static struct intel_shared_dpll *
+static struct intel_global_dpll *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1122,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
}
static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
int link_clock = 0;
@@ -1162,7 +1162,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_global_dpll *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1174,7 +1174,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
}
static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1221,7 +1221,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll = NULL;
+ struct intel_global_dpll *pll = NULL;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
@@ -1236,7 +1236,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->global_dpll = pll;
return 0;
}
@@ -1285,18 +1285,18 @@ static const struct intel_global_dpll_funcs hsw_ddi_spll_funcs = {
};
static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *hw_state)
{
}
static void hsw_ddi_lcpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
}
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return true;
@@ -1364,7 +1364,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
};
static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -1378,7 +1378,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
}
static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1400,7 +1400,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
}
static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1409,7 +1409,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display,
}
static void skl_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1420,12 +1420,12 @@ static void skl_ddi_pll_disable(struct intel_display *display,
}
static void skl_ddi_dpll0_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
}
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1463,7 +1463,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
}
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1736,7 +1736,7 @@ skl_ddi_calculate_wrpll(int clock,
}
static int skl_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1884,7 +1884,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
}
static int skl_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1939,7 +1939,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
@@ -1957,13 +1957,13 @@ static int skl_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->global_dpll = pll;
return 0;
}
static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -2038,7 +2038,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
};
static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2141,7 +2141,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
}
static void bxt_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -2160,7 +2160,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
}
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2360,7 +2360,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
}
static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2429,7 +2429,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
enum intel_dpll_id id;
/* 1:1 mapping between ports and PLLs */
@@ -2442,7 +2442,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->global_dpll = pll;
return 0;
}
@@ -2757,7 +2757,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
/*
@@ -2828,7 +2828,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3201,7 +3201,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3287,7 +3287,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[port_dpll_id];
- crtc_state->shared_dpll = port_dpll->pll;
+ crtc_state->global_dpll = port_dpll->pll;
crtc_state->dpll_hw_state = port_dpll->hw_state;
}
@@ -3430,8 +3430,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
return ret;
/* this is mainly for the fastset check */
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+ if (old_crtc_state->global_dpll &&
+ old_crtc_state->global_dpll->info->id == DPLL_ID_ICL_TBTPLL)
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
@@ -3523,7 +3523,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum icl_port_dpll_id id;
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->global_dpll = NULL;
for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
const struct icl_port_dpll *old_port_dpll =
@@ -3541,7 +3541,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
}
static bool mg_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3608,7 +3608,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
}
static bool dkl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3680,7 +3680,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
}
static bool icl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
@@ -3741,7 +3741,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
}
static bool combo_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3750,14 +3750,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
}
static bool tbt_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
static void icl_dpll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -3799,7 +3799,7 @@ static void icl_dpll_write(struct intel_display *display,
}
static void icl_mg_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3842,7 +3842,7 @@ static void icl_mg_pll_write(struct intel_display *display,
}
static void dkl_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3907,7 +3907,7 @@ static void dkl_pll_write(struct intel_display *display,
}
static void icl_pll_power_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
@@ -3922,7 +3922,7 @@ static void icl_pll_power_enable(struct intel_display *display,
}
static void icl_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
@@ -3932,7 +3932,7 @@ static void icl_pll_enable(struct intel_display *display,
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
-static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_global_dpll *pll)
{
u32 val;
@@ -3957,7 +3957,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
}
static void combo_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3981,7 +3981,7 @@ static void combo_pll_enable(struct intel_display *display,
}
static void tbt_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4002,7 +4002,7 @@ static void tbt_pll_enable(struct intel_display *display,
}
static void mg_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4027,7 +4027,7 @@ static void mg_pll_enable(struct intel_display *display,
}
static void icl_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
i915_reg_t enable_reg)
{
/* The first steps are done by intel_ddi_post_disable(). */
@@ -4058,7 +4058,7 @@ static void icl_pll_disable(struct intel_display *display,
}
static void combo_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -4066,13 +4066,13 @@ static void combo_pll_disable(struct intel_display *display,
}
static void tbt_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
static void mg_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
@@ -4349,19 +4349,19 @@ void intel_shared_dpll_init(struct intel_display *display)
for (i = 0; dpll_info[i].name; i++) {
if (drm_WARN_ON(display->drm,
- i >= ARRAY_SIZE(display->dpll.shared_dplls)))
+ i >= ARRAY_SIZE(display->dpll.global_dplls)))
break;
/* must fit into unsigned long bitmask on 32bit */
if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
break;
- display->dpll.shared_dplls[i].info = &dpll_info[i];
- display->dpll.shared_dplls[i].index = i;
+ display->dpll.global_dplls[i].info = &dpll_info[i];
+ display->dpll.global_dplls[i].index = i;
}
display->dpll.mgr = dpll_mgr;
- display->dpll.num_shared_dpll = i;
+ display->dpll.num_global_dpll = i;
}
/**
@@ -4485,7 +4485,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
* Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
@@ -4503,14 +4503,14 @@ int intel_dpll_get_freq(struct intel_display *display,
* Read out @pll's hardware state into @dpll_hw_state.
*/
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
}
static void readout_dpll_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
struct intel_crtc *crtc;
@@ -4524,7 +4524,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
+ if (crtc_state->hw.active && crtc_state->global_dpll == pll)
intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4542,7 +4542,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display)
void intel_dpll_readout_hw_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
for_each_dpll(display, pll, i)
@@ -4550,7 +4550,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
}
static void sanitize_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_global_dpll *pll)
{
if (!pll->on)
return;
@@ -4569,7 +4569,7 @@ static void sanitize_dpll_state(struct intel_display *display,
void intel_dpll_sanitize_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
intel_cx0_pll_power_save_wa(display);
@@ -4626,7 +4626,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
static void
verify_single_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4679,8 +4679,8 @@ verify_single_dpll_state(struct intel_display *display,
pll->info->name);
}
-static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
- const struct intel_shared_dpll *new_pll)
+static bool has_alt_port_dpll(const struct intel_global_dpll *old_pll,
+ const struct intel_global_dpll *new_pll)
{
return old_pll && new_pll && old_pll != new_pll &&
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
@@ -4695,22 +4695,22 @@ void intel_dpll_state_verify(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- if (new_crtc_state->shared_dpll)
- verify_single_dpll_state(display, new_crtc_state->shared_dpll,
+ if (new_crtc_state->global_dpll)
+ verify_single_dpll_state(display, new_crtc_state->global_dpll,
crtc, new_crtc_state);
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+ if (old_crtc_state->global_dpll &&
+ old_crtc_state->global_dpll != new_crtc_state->global_dpll) {
u8 pipe_mask = BIT(crtc->pipe);
- struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+ struct intel_global_dpll *pll = old_crtc_state->global_dpll;
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
/* TC ports have both MG/TC and TBT PLL referenced simultaneously */
- INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
- new_crtc_state->shared_dpll) &&
+ INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->global_dpll,
+ new_crtc_state->global_dpll) &&
pll->state.pipe_mask & pipe_mask,
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
@@ -4720,7 +4720,7 @@ void intel_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
for_each_dpll(display, pll, i)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5bfe14dde3f0..6edd103eda55 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -31,8 +31,8 @@
#include "intel_wakeref.h"
#define for_each_dpll(__display, __pll, __i) \
- for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
- ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
+ for ((__i) = 0; (__i) < (__display)->dpll.num_global_dpll && \
+ ((__pll) = &(__display)->dpll.global_dplls[(__i)]) ; (__i)++)
enum tc_port;
struct drm_printer;
@@ -344,9 +344,9 @@ struct dpll_info {
};
/**
- * struct intel_shared_dpll - display PLL with tracked state and users
+ * struct intel_global_dpll - display PLL with tracked state and users
*/
-struct intel_shared_dpll {
+struct intel_global_dpll {
/**
* @state:
*
@@ -388,11 +388,11 @@ struct intel_shared_dpll {
#define SKL_DPLL3 3
/* shared dpll functions */
-struct intel_shared_dpll *
+struct intel_global_dpll *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
@@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
@@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 024d0c7e0a88..f59c4375ee14 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -921,7 +921,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
/* Configure Port Clock Select */
- drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
+ drm_WARN_ON(&dev_priv->drm, crtc_state->global_dpll->info->id != DPLL_ID_SPLL);
intel_ddi_enable_clock(encoder, crtc_state);
/* Start the training iterating through available voltages and emphasis,
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 7ed8625193fe..c5b828dc4d6c 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -250,7 +250,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(i915)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_disabled(display, crtc_state->global_dpll);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index a5a00b3ce98f..07a75be8cb12 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -91,10 +91,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->active = false;
crtc->base.enabled = false;
- if (crtc_state->shared_dpll)
+ if (crtc_state->global_dpll)
intel_unreference_shared_dpll_crtc(crtc,
- crtc_state->shared_dpll,
- &crtc_state->shared_dpll->state);
+ crtc_state->global_dpll,
+ &crtc_state->global_dpll->state);
}
static void set_encoder_for_connector(struct intel_connector *connector,
@@ -579,7 +579,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
*/
return IS_SANDYBRIDGE(i915) &&
crtc_state->hw.active &&
- crtc_state->shared_dpll &&
+ crtc_state->global_dpll &&
crtc_state->port_clock == 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 1abe0a784570..4192cfbb7af6 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_enabled(display, crtc_state->global_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, pipe);
@@ -387,7 +387,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(display, PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
- if (crtc_state->shared_dpll ==
+ if (crtc_state->global_dpll ==
intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
@@ -500,7 +500,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
enum pipe pipe = crtc->pipe;
enum intel_dpll_id pll_id;
bool pll_active;
@@ -532,8 +532,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
- pll = crtc_state->shared_dpll;
+ crtc_state->global_dpll = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = crtc_state->global_dpll;
pll_active = intel_dpll_get_hw_state(display, pll,
&crtc_state->dpll_hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index ebec879bacf7..abf9a8134866 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -494,7 +494,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
{
struct intel_display *display = &dev_priv->display;
struct intel_encoder *encoder;
- struct intel_shared_dpll *pll;
+ struct intel_global_dpll *pll;
int i;
u32 val, final;
bool has_lvds = false;
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (3 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 04/11] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:46 ` Jani Nikula
2025-02-25 8:09 ` [PATCH 06/11] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
` (8 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename functions to move away from using shared dpll in the dpll
framework as much as possible since dpll may not always be shared.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 146 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 28 ++--
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 2 +-
.../gpu/drm/i915/display/intel_pch_display.c | 12 +-
10 files changed, 114 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 82bcf5031a09..be6d88cb91d1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1579,7 +1579,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1733,7 +1733,7 @@ static struct intel_global_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
if (phy >= PHY_C)
id += DPLL_ID_DG1_DPLL2;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1905,7 +1905,7 @@ static struct intel_global_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
static struct intel_global_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
@@ -1928,7 +1928,7 @@ static struct intel_global_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1996,7 +1996,7 @@ static struct intel_global_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2063,7 +2063,7 @@ static struct intel_global_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_global_dpll_by_id(display, id);
}
void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2771,7 +2771,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* 4. Enable the port PLL.
*
* The PLL enabling itself was already done before this function by
- * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
+ * hsw_crtc_enable()->intel_enable_global_dpll(). We need only
* configure the PLL to port mapping here.
*/
intel_ddi_enable_clock(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4577787cb8f9..36e365cdb33f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1695,7 +1695,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, pipe_crtc);
if (pipe_crtc_state->global_dpll)
- intel_enable_shared_dpll(pipe_crtc_state);
+ intel_enable_global_dpll(pipe_crtc_state);
}
intel_encoders_pre_enable(state, crtc);
@@ -1824,7 +1824,7 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
intel_set_pch_fifo_underrun_reporting(display, pipe, true);
- intel_disable_shared_dpll(old_crtc_state);
+ intel_disable_global_dpll(old_crtc_state);
}
static void hsw_crtc_disable(struct intel_atomic_state *state,
@@ -1847,7 +1847,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
const struct intel_crtc_state *old_pipe_crtc_state =
intel_atomic_get_old_crtc_state(state, pipe_crtc);
- intel_disable_shared_dpll(old_pipe_crtc_state);
+ intel_disable_global_dpll(old_pipe_crtc_state);
}
intel_encoders_post_pll_disable(state, crtc);
@@ -6593,7 +6593,7 @@ int intel_atomic_check(struct drm_device *dev,
any_ms = true;
- intel_release_shared_dplls(state, crtc);
+ intel_release_global_dplls(state, crtc);
}
if (any_ms && !check_digital_port_conflicts(state)) {
@@ -7685,7 +7685,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
intel_atomic_swap_global_state(state);
- intel_shared_dpll_swap_state(state);
+ intel_dpll_swap_state(state);
intel_atomic_track_fbs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index b72b07329fbf..234cccdf7edc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
}
intel_plane_possible_crtcs_init(display);
- intel_shared_dpll_init(display);
+ intel_global_dpll_init(display);
intel_fdi_pll_freq_update(i915);
intel_update_czclk(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 96c79269c755..78cdbd54a5ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1168,7 +1168,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_compute_shared_dplls(state, crtc, encoder);
+ ret = intel_compute_global_dplls(state, crtc, encoder);
if (ret)
return ret;
@@ -1196,7 +1196,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- return intel_reserve_shared_dplls(state, crtc, encoder);
+ return intel_reserve_global_dplls(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1230,7 +1230,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
if (ret)
return ret;
- /* TODO: Do the readback via intel_compute_shared_dplls() */
+ /* TODO: Do the readback via intel_compute_global_dplls() */
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1406,7 +1406,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- ret = intel_compute_shared_dplls(state, crtc, NULL);
+ ret = intel_compute_global_dplls(state, crtc, NULL);
if (ret)
return ret;
@@ -1426,7 +1426,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->has_pch_encoder)
return 0;
- return intel_reserve_shared_dplls(state, crtc, NULL);
+ return intel_reserve_global_dplls(state, crtc, NULL);
}
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b26351eff7a8..bd623fdddfdc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -49,21 +49,21 @@
* share a PLL if their configurations match.
*
* This file provides an abstraction over display PLLs. The function
- * intel_shared_dpll_init() initializes the PLLs for the given platform. The
+ * intel_global_dpll_init() initializes the PLLs for the given platform. The
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
- * intel_reserve_shared_dplls() and previously reserved PLLs can be released
- * with intel_release_shared_dplls().
+ * intel_reserve_global_dplls() and previously reserved PLLs can be released
+ * with intel_release_global_dplls().
* Changes to the users are first staged in the atomic state, and then made
- * effective by calling intel_shared_dpll_swap_state() during the atomic
+ * effective by calling intel_dpll_swap_state() during the atomic
* commit phase.
*/
/* platform specific hooks for managing DPLLs */
struct intel_global_dpll_funcs {
/*
- * Hook for enabling the pll, called from intel_enable_shared_dpll() if
+ * Hook for enabling the pll, called from intel_enable_global_dpll() if
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
@@ -71,7 +71,7 @@ struct intel_global_dpll_funcs {
const struct intel_dpll_hw_state *dpll_hw_state);
/*
- * Hook for disabling the pll, called from intel_disable_shared_dpll()
+ * Hook for disabling the pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
@@ -130,7 +130,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
}
static struct intel_dpll_state *
-intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
+intel_atomic_get_global_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
struct intel_display *display = to_intel_display(state);
@@ -148,7 +148,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
}
/**
- * intel_get_shared_dpll_by_id - get a DPLL given its id
+ * intel_get_global_dpll_by_id - get a DPLL given its id
* @display: intel_display device instance
* @id: pll id
*
@@ -156,7 +156,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* A pointer to the DPLL with @id
*/
struct intel_global_dpll *
-intel_get_shared_dpll_by_id(struct intel_display *display,
+intel_get_global_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
struct intel_global_dpll *pll;
@@ -172,7 +172,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
}
/* For ILK+ */
-void assert_shared_dpll(struct intel_display *display,
+void assert_global_dpll(struct intel_display *display,
struct intel_global_dpll *pll,
bool state)
{
@@ -247,12 +247,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
}
/**
- * intel_enable_shared_dpll - enable a CRTC's shared DPLL
- * @crtc_state: CRTC, and its state, which has a shared DPLL
+ * intel_enable_global_dpll - enable a CRTC's global DPLL
+ * @crtc_state: CRTC, and its state, which has a DPLL
*
- * Enable the shared DPLL used by @crtc.
+ * Enable DPLL used by @crtc.
*/
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_enable_global_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -279,7 +279,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (old_mask) {
drm_WARN_ON(display->drm, !pll->on);
- assert_shared_dpll_enabled(display, pll);
+ assert_global_dpll_enabled(display, pll);
goto out;
}
drm_WARN_ON(display->drm, pll->on);
@@ -293,12 +293,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
}
/**
- * intel_disable_shared_dpll - disable a CRTC's shared DPLL
+ * intel_disable_global_dpll - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
- * Disable the shared DPLL used by @crtc.
+ * Disable DPLL used by @crtc.
*/
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_disable_global_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -323,7 +323,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
- assert_shared_dpll_enabled(display, pll);
+ assert_global_dpll_enabled(display, pll);
drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
@@ -355,7 +355,7 @@ intel_dpll_mask_all(struct intel_display *display)
}
static struct intel_global_dpll *
-intel_find_shared_dpll(struct intel_atomic_state *state,
+intel_find_global_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *dpll_hw_state,
unsigned long dpll_mask)
@@ -366,14 +366,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_global_dpll *unused_pll = NULL;
enum intel_dpll_id id;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_global_dpll_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_global_dpll *pll;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_global_dpll_by_id(display, id);
if (!pll)
continue;
@@ -409,7 +409,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
}
/**
- * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
+ * intel_reference_global_dpll_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -417,7 +417,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
-intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
+intel_reference_global_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_global_dpll *pll,
struct intel_dpll_state *dpll_state)
{
@@ -432,23 +432,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
}
static void
-intel_reference_shared_dpll(struct intel_atomic_state *state,
+intel_reference_global_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_global_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_global_dpll_state(&state->base);
if (dpll_state[pll->index].pipe_mask == 0)
dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_reference_global_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
- * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
+ * intel_unreference_global_dpll_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -456,7 +456,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
-intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
+intel_unreference_global_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_global_dpll *pll,
struct intel_dpll_state *dpll_state)
{
@@ -470,15 +470,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
crtc->base.base.id, crtc->base.name, pll->info->name);
}
-static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
+static void intel_unreference_global_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_global_dpll *pll)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_global_dpll_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_unreference_global_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -494,11 +494,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
if (!old_crtc_state->global_dpll)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->global_dpll);
+ intel_unreference_global_dpll(state, crtc, old_crtc_state->global_dpll);
}
/**
- * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
+ * intel_dpll_swap_state - make atomic DPLL configuration effective
* @state: atomic state
*
* This is the dpll version of drm_atomic_helper_swap_state() since the
@@ -508,7 +508,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
* i.e. it also puts the current state into @state, even though there is no
* need for that at this moment.
*/
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
+void intel_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
@@ -618,14 +618,14 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(i915)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
id = (enum intel_dpll_id) crtc->pipe;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_global_dpll_by_id(display, id);
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name,
pll->info->name);
} else {
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_global_dpll(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_PCH_PLL_B) |
BIT(DPLL_ID_PCH_PLL_A));
@@ -635,7 +635,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
return -EINVAL;
/* reference the pll */
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->global_dpll = pll;
@@ -1066,7 +1066,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc,
+ return intel_find_global_dpll(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_WRPLL2) |
BIT(DPLL_ID_WRPLL1));
@@ -1113,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return NULL;
}
- pll = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = intel_get_global_dpll_by_id(display, pll_id);
if (!pll)
return NULL;
@@ -1169,7 +1169,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
+ return intel_find_global_dpll(state, crtc, &crtc_state->dpll_hw_state,
BIT(DPLL_ID_SPLL));
}
@@ -1233,7 +1233,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->global_dpll = pll;
@@ -1942,11 +1942,11 @@ static int skl_get_dpll(struct intel_atomic_state *state,
struct intel_global_dpll *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_global_dpll(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_SKL_DPLL0));
else
- pll = intel_find_shared_dpll(state, crtc,
+ pll = intel_find_global_dpll(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_SKL_DPLL3) |
BIT(DPLL_ID_SKL_DPLL2) |
@@ -1954,7 +1954,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->global_dpll = pll;
@@ -2434,12 +2434,12 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_global_dpll_by_id(display, id);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
crtc_state->global_dpll = pll;
@@ -3390,13 +3390,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_hti_dpll_mask(display);
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_global_dpll(state, crtc,
&port_dpll->hw_state,
dpll_mask);
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3454,25 +3454,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
int ret;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_global_dpll(state, crtc,
&port_dpll->hw_state,
BIT(DPLL_ID_ICL_TBTPLL));
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
+ port_dpll->pll = intel_find_global_dpll(state, crtc,
&port_dpll->hw_state,
BIT(dpll_id));
if (!port_dpll->pll) {
ret = -EINVAL;
goto err_unreference_tbt_pll;
}
- intel_reference_shared_dpll(state, crtc,
+ intel_reference_global_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3481,7 +3481,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
err_unreference_tbt_pll:
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
+ intel_unreference_global_dpll(state, crtc, port_dpll->pll);
return ret;
}
@@ -3536,7 +3536,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
if (!old_port_dpll->pll)
continue;
- intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
+ intel_unreference_global_dpll(state, crtc, old_port_dpll->pll);
}
}
@@ -4302,12 +4302,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
};
/**
- * intel_shared_dpll_init - Initialize shared DPLLs
+ * intel_global_dpll_init - Initialize DPLLs
* @display: intel_display device
*
- * Initialize shared DPLLs for @display.
+ * Initialize DPLLs for @display.
*/
-void intel_shared_dpll_init(struct intel_display *display)
+void intel_global_dpll_init(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_dpll_mgr *dpll_mgr = NULL;
@@ -4365,7 +4365,7 @@ void intel_shared_dpll_init(struct intel_display *display)
}
/**
- * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * intel_compute_global_dplls - compute DPLL state CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to compute DPLLs for
* @encoder: encoder
@@ -4373,12 +4373,12 @@ void intel_shared_dpll_init(struct intel_display *display)
* This function computes the DPLL state for the given CRTC and encoder.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* Returns:
* 0 on success, negative error code on failure.
*/
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
+int intel_compute_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -4392,7 +4392,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
+ * intel_reserve_global_dplls - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
@@ -4402,16 +4402,16 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
* state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
- * intel_release_shared_dplls().
+ * intel_release_global_dplls().
*
* Returns:
* 0 if all required DPLLs were successfully reserved,
* negative error code otherwise.
*/
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+int intel_reserve_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -4425,17 +4425,17 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
+ * intel_release_global_dplls - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
- * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
+ * This function releases all DPLLs reserved by intel_reserve_global_dplls()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*/
-void intel_release_shared_dplls(struct intel_atomic_state *state,
+void intel_release_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
@@ -4444,7 +4444,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
- * the shared DPLL framework and intel_reserve_shared_dplls() is not
+ * the global DPLL framework and intel_reserve_global_dplls() is not
* called on those.
*/
if (!dpll_mgr)
@@ -4460,7 +4460,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
- * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
+ * from the port DPLLs reserved previously by intel_reserve_global_dplls(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
void intel_update_active_dpll(struct intel_atomic_state *state,
@@ -4525,7 +4525,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.active && crtc_state->global_dpll == pll)
- intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
+ intel_reference_global_dpll_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4717,7 +4717,7 @@ void intel_dpll_state_verify(struct intel_atomic_state *state,
}
}
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
+void intel_global_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_global_dpll *pll;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 6edd103eda55..ef66aca5da1d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -387,24 +387,24 @@ struct intel_global_dpll {
#define SKL_DPLL2 2
#define SKL_DPLL3 3
-/* shared dpll functions */
+/* global dpll functions */
struct intel_global_dpll *
-intel_get_shared_dpll_by_id(struct intel_display *display,
+intel_get_global_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
-void assert_shared_dpll(struct intel_display *display,
+void assert_global_dpll(struct intel_display *display,
struct intel_global_dpll *pll,
bool state);
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
+#define assert_global_dpll_enabled(d, p) assert_global_dpll(d, p, true)
+#define assert_global_dpll_disabled(d, p) assert_global_dpll(d, p, false)
+int intel_compute_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
+int intel_reserve_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-void intel_release_shared_dplls(struct intel_atomic_state *state,
+void intel_release_global_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
+void intel_unreference_global_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_global_dpll *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
@@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct intel_display *display);
+void intel_enable_global_dpll(const struct intel_crtc_state *crtc_state);
+void intel_disable_global_dpll(const struct intel_crtc_state *crtc_state);
+void intel_dpll_swap_state(struct intel_atomic_state *state);
+void intel_global_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
@@ -437,6 +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
void intel_dpll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
+void intel_global_dpll_verify_disabled(struct intel_atomic_state *state);
#endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index c5b828dc4d6c..3a5c999dc68f 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -250,7 +250,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(i915)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->global_dpll);
+ assert_global_dpll_disabled(display, crtc_state->global_dpll);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 07a75be8cb12..78b1f825f42c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -92,7 +92,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->base.enabled = false;
if (crtc_state->global_dpll)
- intel_unreference_shared_dpll_crtc(crtc,
+ intel_unreference_global_dpll_crtc(crtc,
crtc_state->global_dpll,
&crtc_state->global_dpll->state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 5f3b1c2b081b..41d4ef7afb4b 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -254,5 +254,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
{
verify_encoder_state(state);
verify_connector_state(state, NULL);
- intel_shared_dpll_verify_disabled(state);
+ intel_global_dpll_verify_disabled(state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 4192cfbb7af6..23e6651609a5 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->global_dpll);
+ assert_global_dpll_enabled(display, crtc_state->global_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, pipe);
@@ -388,7 +388,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc_state->global_dpll ==
- intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
+ intel_get_global_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
@@ -400,11 +400,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
- * Note that enable_shared_dpll tries to do the right thing, but
- * get_shared_dpll unconditionally resets the pll - we need that
+ * Note that enable_global_dpll tries to do the right thing, but
+ * get_global_dpll unconditionally resets the pll - we need that
* to have the right LVDS enable sequence.
*/
- intel_enable_shared_dpll(crtc_state);
+ intel_enable_global_dpll(crtc_state);
/* set transcoder timing, panel must allow it */
assert_pps_unlocked(display, pipe);
@@ -532,7 +532,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->global_dpll = intel_get_shared_dpll_by_id(display, pll_id);
+ crtc_state->global_dpll = intel_get_global_dpll_by_id(display, pll_id);
pll = crtc_state->global_dpll;
pll_active = intel_dpll_get_hw_state(display, pll,
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 8:09 ` [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-02-25 8:46 ` Jani Nikula
2025-02-25 8:54 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Jani Nikula @ 2025-02-25 8:46 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename functions to move away from using shared dpll in the dpll
> framework as much as possible since dpll may not always be shared.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
...
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 6edd103eda55..ef66aca5da1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -387,24 +387,24 @@ struct intel_global_dpll {
> #define SKL_DPLL2 2
> #define SKL_DPLL3 3
>
> -/* shared dpll functions */
> +/* global dpll functions */
> struct intel_global_dpll *
> -intel_get_shared_dpll_by_id(struct intel_display *display,
> +intel_get_global_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id);
> -void assert_shared_dpll(struct intel_display *display,
> +void assert_global_dpll(struct intel_display *display,
> struct intel_global_dpll *pll,
> bool state);
> -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d, p, true)
> +#define assert_global_dpll_disabled(d, p) assert_global_dpll(d, p, false)
> +int intel_compute_global_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> +int intel_reserve_global_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -void intel_release_shared_dplls(struct intel_atomic_state *state,
> +void intel_release_global_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> +void intel_unreference_global_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_global_dpll *pll,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> @@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
> bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_global_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct intel_display *display);
> +void intel_enable_global_dpll(const struct intel_crtc_state *crtc_state);
> +void intel_disable_global_dpll(const struct intel_crtc_state *crtc_state);
> +void intel_dpll_swap_state(struct intel_atomic_state *state);
> +void intel_global_dpll_init(struct intel_display *display);
> void intel_dpll_update_ref_clks(struct intel_display *display);
> void intel_dpll_readout_hw_state(struct intel_display *display);
> void intel_dpll_sanitize_state(struct intel_display *display);
> @@ -437,6 +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> void intel_dpll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
> +void intel_global_dpll_verify_disabled(struct intel_atomic_state *state);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
If you're renaming almost everything anyway, I'd appreciate moving
towards naming functions according to the file name, i.e. functions in
intel_foo.[ch] would be named intel_foo_*().
The dpll mgr is notoriously bad in this regard. I'm also open to
renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
I'm not sure if the term "global" (instead of "shared") was very well
justified in patch 3. Maybe all of these should be thought out together
for the naming.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 8:46 ` Jani Nikula
@ 2025-02-25 8:54 ` Kandpal, Suraj
2025-02-25 9:47 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Kandpal, Suraj @ 2025-02-25 8:54 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, February 25, 2025 2:17 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Kandpal,
> Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename functions to move away from using shared dpll in the dpll
> > framework as much as possible since dpll may not always be shared.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> ...
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 6edd103eda55..ef66aca5da1d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define SKL_DPLL2 2
> > #define SKL_DPLL3 3
> >
> > -/* shared dpll functions */
> > +/* global dpll functions */
> > struct intel_global_dpll *
> > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > +intel_get_global_dpll_by_id(struct intel_display *display,
> > enum intel_dpll_id id);
> > -void assert_shared_dpll(struct intel_display *display,
> > +void assert_global_dpll(struct intel_display *display,
> > struct intel_global_dpll *pll,
> > bool state);
> > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p,
> > true) -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d,
> > p, false) -int intel_compute_shared_dplls(struct intel_atomic_state
> > *state,
> > +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d, p,
> > +true) #define assert_global_dpll_disabled(d, p) assert_global_dpll(d,
> > +p, false) int intel_compute_global_dplls(struct intel_atomic_state
> > +*state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder); -int
> > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > +int intel_reserve_global_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder); -void
> > intel_release_shared_dplls(struct intel_atomic_state *state,
> > +void intel_release_global_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > *crtc,
> > +void intel_unreference_global_dpll_crtc(const struct intel_crtc
> > +*crtc,
> > const struct intel_global_dpll *pll,
> > struct intel_dpll_state
> *shared_dpll_state); void
> > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
> > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
> > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
> > struct intel_global_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state); -void
> > intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > *crtc_state); -void intel_shared_dpll_swap_state(struct
> > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> > intel_display *display);
> > +void intel_enable_global_dpll(const struct intel_crtc_state
> > +*crtc_state); void intel_disable_global_dpll(const struct
> > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
> > +intel_atomic_state *state); void intel_global_dpll_init(struct
> > +intel_display *display);
> > void intel_dpll_update_ref_clks(struct intel_display *display); void
> > intel_dpll_readout_hw_state(struct intel_display *display); void
> > intel_dpll_sanitize_state(struct intel_display *display); @@ -437,6
> > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> >
> > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > *state);
> > +void intel_global_dpll_verify_disabled(struct intel_atomic_state
> > +*state);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
>
> If you're renaming almost everything anyway, I'd appreciate moving towards
> naming functions according to the file name, i.e. functions in intel_foo.[ch]
> would be named intel_foo_*().
>
> The dpll mgr is notoriously bad in this regard. I'm also open to renaming the
> entire file, intel_dpll_mgr.[ch] isn't all that great.
>
> I'm not sure if the term "global" (instead of "shared") was very well justified in
> patch 3. Maybe all of these should be thought out together for the naming.
>
I agree with the renaming I would have very much have to keep the naming simple something like
Intel_dpll_func but that exits ! intel_dpll_mgr_funcs but intel_dpll_mgr already has some hooks defined inside
It.
I chose global since that way we will be able to represent both PLL using shared PHY and PLL with individual PHY.
Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch] making it a problem
What if we renamed the file to intel_global_dpll.[ch]
Regards,
Suraj Kandpal
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 8:54 ` Kandpal, Suraj
@ 2025-02-25 9:47 ` Kandpal, Suraj
2025-02-25 15:30 ` Jani Nikula
0 siblings, 1 reply; 30+ messages in thread
From: Kandpal, Suraj @ 2025-02-25 9:47 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
> -----Original Message-----
> From: Kandpal, Suraj
> Sent: Tuesday, February 25, 2025 2:25 PM
> To: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
>
>
> > -----Original Message-----
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Tuesday, February 25, 2025 2:17 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared
> > dpll
> >
> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > Rename functions to move away from using shared dpll in the dpll
> > > framework as much as possible since dpll may not always be shared.
> > >
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >
> > ...
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > index 6edd103eda55..ef66aca5da1d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define SKL_DPLL2
> > > 2 #define SKL_DPLL3 3
> > >
> > > -/* shared dpll functions */
> > > +/* global dpll functions */
> > > struct intel_global_dpll *
> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > > +intel_get_global_dpll_by_id(struct intel_display *display,
> > > enum intel_dpll_id id);
> > > -void assert_shared_dpll(struct intel_display *display,
> > > +void assert_global_dpll(struct intel_display *display,
> > > struct intel_global_dpll *pll,
> > > bool state);
> > > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p,
> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > assert_shared_dpll(d, p, false) -int
> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
> > > +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d, p,
> > > +true) #define assert_global_dpll_disabled(d, p)
> > > +assert_global_dpll(d, p, false) int
> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder); -int
> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > > +int intel_reserve_global_dplls(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > struct intel_encoder *encoder); -void
> > > intel_release_shared_dplls(struct intel_atomic_state *state,
> > > +void intel_release_global_dplls(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc);
> > > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > > *crtc,
> > > +void intel_unreference_global_dpll_crtc(const struct intel_crtc
> > > +*crtc,
> > > const struct intel_global_dpll *pll,
> > > struct intel_dpll_state
> > *shared_dpll_state); void
> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
> > > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
> > > struct intel_global_dpll *pll,
> > > struct intel_dpll_hw_state *dpll_hw_state); -void
> > > intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > > *crtc_state); -void intel_shared_dpll_swap_state(struct
> > > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> > > intel_display *display);
> > > +void intel_enable_global_dpll(const struct intel_crtc_state
> > > +*crtc_state); void intel_disable_global_dpll(const struct
> > > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
> > > +intel_atomic_state *state); void intel_global_dpll_init(struct
> > > +intel_display *display);
> > > void intel_dpll_update_ref_clks(struct intel_display *display);
> > > void intel_dpll_readout_hw_state(struct intel_display *display);
> > > void intel_dpll_sanitize_state(struct intel_display *display); @@
> > > -437,6
> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> > >
> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc);
> > > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > > *state);
> > > +void intel_global_dpll_verify_disabled(struct intel_atomic_state
> > > +*state);
> > >
> > > #endif /* _INTEL_DPLL_MGR_H_ */
> >
> > If you're renaming almost everything anyway, I'd appreciate moving
> > towards naming functions according to the file name, i.e. functions in
> > intel_foo.[ch] would be named intel_foo_*().
> >
> > The dpll mgr is notoriously bad in this regard. I'm also open to
> > renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
> >
> > I'm not sure if the term "global" (instead of "shared") was very well
> > justified in patch 3. Maybe all of these should be thought out together for the
> naming.
> >
>
> I agree with the renaming I would have very much have to keep the naming
> simple something like Intel_dpll_func but that exits ! intel_dpll_mgr_funcs but
> intel_dpll_mgr already has some hooks defined inside It.
> I chose global since that way we will be able to represent both PLL using shared
> PHY and PLL with individual PHY.
> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch] making it a problem
> What if we renamed the file to intel_global_dpll.[ch]
Jani what do you think of this ?
>
> Regards,
> Suraj Kandpal
>
> > BR,
> > Jani.
> >
> >
> > --
> > Jani Nikula, Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 9:47 ` Kandpal, Suraj
@ 2025-02-25 15:30 ` Jani Nikula
2025-02-27 10:18 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Jani Nikula @ 2025-02-25 15:30 UTC (permalink / raw)
To: Kandpal, Suraj, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Kandpal, Suraj
>> Sent: Tuesday, February 25, 2025 2:25 PM
>> To: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
>> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>>
>>
>>
>> > -----Original Message-----
>> > From: Jani Nikula <jani.nikula@linux.intel.com>
>> > Sent: Tuesday, February 25, 2025 2:17 PM
>> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
>> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
>> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
>> > Kandpal, Suraj <suraj.kandpal@intel.com>
>> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared
>> > dpll
>> >
>> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > > Rename functions to move away from using shared dpll in the dpll
>> > > framework as much as possible since dpll may not always be shared.
>> > >
>> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> >
>> > ...
>> >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > > index 6edd103eda55..ef66aca5da1d 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define SKL_DPLL2
>> > > 2 #define SKL_DPLL3 3
>> > >
>> > > -/* shared dpll functions */
>> > > +/* global dpll functions */
>> > > struct intel_global_dpll *
>> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
>> > > +intel_get_global_dpll_by_id(struct intel_display *display,
>> > > enum intel_dpll_id id);
>> > > -void assert_shared_dpll(struct intel_display *display,
>> > > +void assert_global_dpll(struct intel_display *display,
>> > > struct intel_global_dpll *pll,
>> > > bool state);
>> > > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p,
>> > > true) -#define assert_shared_dpll_disabled(d, p)
>> > > assert_shared_dpll(d, p, false) -int
>> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
>> > > +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d, p,
>> > > +true) #define assert_global_dpll_disabled(d, p)
>> > > +assert_global_dpll(d, p, false) int
>> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
>> > > struct intel_crtc *crtc,
>> > > struct intel_encoder *encoder); -int
>> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
>> > > +int intel_reserve_global_dplls(struct intel_atomic_state *state,
>> > > struct intel_crtc *crtc,
>> > > struct intel_encoder *encoder); -void
>> > > intel_release_shared_dplls(struct intel_atomic_state *state,
>> > > +void intel_release_global_dplls(struct intel_atomic_state *state,
>> > > struct intel_crtc *crtc);
>> > > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
>> > > *crtc,
>> > > +void intel_unreference_global_dpll_crtc(const struct intel_crtc
>> > > +*crtc,
>> > > const struct intel_global_dpll *pll,
>> > > struct intel_dpll_state
>> > *shared_dpll_state); void
>> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
>> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
>> > > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
>> > > struct intel_global_dpll *pll,
>> > > struct intel_dpll_hw_state *dpll_hw_state); -void
>> > > intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
>> > > -void intel_disable_shared_dpll(const struct intel_crtc_state
>> > > *crtc_state); -void intel_shared_dpll_swap_state(struct
>> > > intel_atomic_state *state); -void intel_shared_dpll_init(struct
>> > > intel_display *display);
>> > > +void intel_enable_global_dpll(const struct intel_crtc_state
>> > > +*crtc_state); void intel_disable_global_dpll(const struct
>> > > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
>> > > +intel_atomic_state *state); void intel_global_dpll_init(struct
>> > > +intel_display *display);
>> > > void intel_dpll_update_ref_clks(struct intel_display *display);
>> > > void intel_dpll_readout_hw_state(struct intel_display *display);
>> > > void intel_dpll_sanitize_state(struct intel_display *display); @@
>> > > -437,6
>> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
>> > >
>> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
>> > > struct intel_crtc *crtc);
>> > > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
>> > > *state);
>> > > +void intel_global_dpll_verify_disabled(struct intel_atomic_state
>> > > +*state);
>> > >
>> > > #endif /* _INTEL_DPLL_MGR_H_ */
>> >
>> > If you're renaming almost everything anyway, I'd appreciate moving
>> > towards naming functions according to the file name, i.e. functions in
>> > intel_foo.[ch] would be named intel_foo_*().
>> >
>> > The dpll mgr is notoriously bad in this regard. I'm also open to
>> > renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
>> >
>> > I'm not sure if the term "global" (instead of "shared") was very well
>> > justified in patch 3. Maybe all of these should be thought out together for the
>> naming.
>> >
>>
>> I agree with the renaming I would have very much have to keep the naming
>> simple something like Intel_dpll_func but that exits ! intel_dpll_mgr_funcs but
>> intel_dpll_mgr already has some hooks defined inside It.
>> I chose global since that way we will be able to represent both PLL using shared
>> PHY and PLL with individual PHY.
>> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch] making it a problem
>> What if we renamed the file to intel_global_dpll.[ch]
>
> Jani what do you think of this ?
I think Ville probably has opinions on this. Cc'd.
BR,
Jani.
>
>>
>> Regards,
>> Suraj Kandpal
>>
>> > BR,
>> > Jani.
>> >
>> >
>> > --
>> > Jani Nikula, Intel
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-25 15:30 ` Jani Nikula
@ 2025-02-27 10:18 ` Kandpal, Suraj
2025-02-28 14:26 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Kandpal, Suraj @ 2025-02-27 10:18 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville
Cc: Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, February 25, 2025 9:00 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> -----Original Message-----
> >> From: Kandpal, Suraj
> >> Sent: Tuesday, February 25, 2025 2:25 PM
> >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> >> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> >> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared
> >> dpll
> >>
> >>
> >>
> >> > -----Original Message-----
> >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> >> > Sent: Tuesday, February 25, 2025 2:17 PM
> >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> >> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> >> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
> >> > Kandpal, Suraj <suraj.kandpal@intel.com>
> >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> >> > shared dpll
> >> >
> >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> > > Rename functions to move away from using shared dpll in the dpll
> >> > > framework as much as possible since dpll may not always be shared.
> >> > >
> >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> >
> >> > ...
> >> >
> >> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > > index 6edd103eda55..ef66aca5da1d 100644
> >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> >> > > SKL_DPLL2
> >> > > 2 #define SKL_DPLL3 3
> >> > >
> >> > > -/* shared dpll functions */
> >> > > +/* global dpll functions */
> >> > > struct intel_global_dpll *
> >> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
> >> > > +intel_get_global_dpll_by_id(struct intel_display *display,
> >> > > enum intel_dpll_id id);
> >> > > -void assert_shared_dpll(struct intel_display *display,
> >> > > +void assert_global_dpll(struct intel_display *display,
> >> > > struct intel_global_dpll *pll,
> >> > > bool state);
> >> > > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d,
> >> > > p,
> >> > > true) -#define assert_shared_dpll_disabled(d, p)
> >> > > assert_shared_dpll(d, p, false) -int
> >> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
> >> > > +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d,
> >> > > +p,
> >> > > +true) #define assert_global_dpll_disabled(d, p)
> >> > > +assert_global_dpll(d, p, false) int
> >> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
> >> > > struct intel_crtc *crtc,
> >> > > struct intel_encoder *encoder); -int
> >> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> >> > > +int intel_reserve_global_dplls(struct intel_atomic_state *state,
> >> > > struct intel_crtc *crtc,
> >> > > struct intel_encoder *encoder); -void
> >> > > intel_release_shared_dplls(struct intel_atomic_state *state,
> >> > > +void intel_release_global_dplls(struct intel_atomic_state
> >> > > +*state,
> >> > > struct intel_crtc *crtc);
> >> > > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
> >> > > *crtc,
> >> > > +void intel_unreference_global_dpll_crtc(const struct intel_crtc
> >> > > +*crtc,
> >> > > const struct intel_global_dpll *pll,
> >> > > struct intel_dpll_state
> >> > *shared_dpll_state); void
> >> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
> >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
> >> > > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
> >> > > struct intel_global_dpll *pll,
> >> > > struct intel_dpll_hw_state *dpll_hw_state); -void
> >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> >> > > *crtc_state); -void intel_disable_shared_dpll(const struct
> >> > > intel_crtc_state *crtc_state); -void
> >> > > intel_shared_dpll_swap_state(struct
> >> > > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> >> > > intel_display *display);
> >> > > +void intel_enable_global_dpll(const struct intel_crtc_state
> >> > > +*crtc_state); void intel_disable_global_dpll(const struct
> >> > > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
> >> > > +intel_atomic_state *state); void intel_global_dpll_init(struct
> >> > > +intel_display *display);
> >> > > void intel_dpll_update_ref_clks(struct intel_display *display);
> >> > > void intel_dpll_readout_hw_state(struct intel_display *display);
> >> > > void intel_dpll_sanitize_state(struct intel_display *display); @@
> >> > > -437,6
> >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> >> > >
> >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> >> > > struct intel_crtc *crtc); -void
> >> > > intel_shared_dpll_verify_disabled(struct intel_atomic_state
> >> > > *state);
> >> > > +void intel_global_dpll_verify_disabled(struct intel_atomic_state
> >> > > +*state);
> >> > >
> >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> >> >
> >> > If you're renaming almost everything anyway, I'd appreciate moving
> >> > towards naming functions according to the file name, i.e. functions
> >> > in intel_foo.[ch] would be named intel_foo_*().
> >> >
> >> > The dpll mgr is notoriously bad in this regard. I'm also open to
> >> > renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
> >> >
> >> > I'm not sure if the term "global" (instead of "shared") was very
> >> > well justified in patch 3. Maybe all of these should be thought out
> >> > together for the
> >> naming.
> >> >
> >>
> >> I agree with the renaming I would have very much have to keep the
> >> naming simple something like Intel_dpll_func but that exits !
> >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some hooks defined
> inside It.
> >> I chose global since that way we will be able to represent both PLL
> >> using shared PHY and PLL with individual PHY.
> >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch] making it
> >> a problem What if we renamed the file to intel_global_dpll.[ch]
> >
> > Jani what do you think of this ?
>
> I think Ville probably has opinions on this. Cc'd.
Hi Ville,
Any thoughts ?
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
> >
> >>
> >> Regards,
> >> Suraj Kandpal
> >>
> >> > BR,
> >> > Jani.
> >> >
> >> >
> >> > --
> >> > Jani Nikula, Intel
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-27 10:18 ` Kandpal, Suraj
@ 2025-02-28 14:26 ` Ville Syrjälä
2025-02-28 15:31 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2025-02-28 14:26 UTC (permalink / raw)
To: Kandpal, Suraj
Cc: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Tuesday, February 25, 2025 9:00 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> > intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
> >
> > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > >> -----Original Message-----
> > >> From: Kandpal, Suraj
> > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > >> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > >> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared
> > >> dpll
> > >>
> > >>
> > >>
> > >> > -----Original Message-----
> > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > >> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > >> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
> > >> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > >> > shared dpll
> > >> >
> > >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > >> > > Rename functions to move away from using shared dpll in the dpll
> > >> > > framework as much as possible since dpll may not always be shared.
> > >> > >
> > >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > >> >
> > >> > ...
> > >> >
> > >> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > >> > > SKL_DPLL2
> > >> > > 2 #define SKL_DPLL3 3
> > >> > >
> > >> > > -/* shared dpll functions */
> > >> > > +/* global dpll functions */
> > >> > > struct intel_global_dpll *
> > >> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > >> > > +intel_get_global_dpll_by_id(struct intel_display *display,
> > >> > > enum intel_dpll_id id);
> > >> > > -void assert_shared_dpll(struct intel_display *display,
> > >> > > +void assert_global_dpll(struct intel_display *display,
> > >> > > struct intel_global_dpll *pll,
> > >> > > bool state);
> > >> > > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d,
> > >> > > p,
> > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > >> > > assert_shared_dpll(d, p, false) -int
> > >> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
> > >> > > +#define assert_global_dpll_enabled(d, p) assert_global_dpll(d,
> > >> > > +p,
> > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > >> > > +assert_global_dpll(d, p, false) int
> > >> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
> > >> > > struct intel_crtc *crtc,
> > >> > > struct intel_encoder *encoder); -int
> > >> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state *state,
> > >> > > struct intel_crtc *crtc,
> > >> > > struct intel_encoder *encoder); -void
> > >> > > intel_release_shared_dplls(struct intel_atomic_state *state,
> > >> > > +void intel_release_global_dplls(struct intel_atomic_state
> > >> > > +*state,
> > >> > > struct intel_crtc *crtc);
> > >> > > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > >> > > *crtc,
> > >> > > +void intel_unreference_global_dpll_crtc(const struct intel_crtc
> > >> > > +*crtc,
> > >> > > const struct intel_global_dpll *pll,
> > >> > > struct intel_dpll_state
> > >> > *shared_dpll_state); void
> > >> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, @@
> > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display
> > >> > > *display, bool intel_dpll_get_hw_state(struct intel_display *display,
> > >> > > struct intel_global_dpll *pll,
> > >> > > struct intel_dpll_hw_state *dpll_hw_state); -void
> > >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> > >> > > *crtc_state); -void intel_disable_shared_dpll(const struct
> > >> > > intel_crtc_state *crtc_state); -void
> > >> > > intel_shared_dpll_swap_state(struct
> > >> > > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> > >> > > intel_display *display);
> > >> > > +void intel_enable_global_dpll(const struct intel_crtc_state
> > >> > > +*crtc_state); void intel_disable_global_dpll(const struct
> > >> > > +intel_crtc_state *crtc_state); void intel_dpll_swap_state(struct
> > >> > > +intel_atomic_state *state); void intel_global_dpll_init(struct
> > >> > > +intel_display *display);
> > >> > > void intel_dpll_update_ref_clks(struct intel_display *display);
> > >> > > void intel_dpll_readout_hw_state(struct intel_display *display);
> > >> > > void intel_dpll_sanitize_state(struct intel_display *display); @@
> > >> > > -437,6
> > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> > >> > >
> > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > >> > > struct intel_crtc *crtc); -void
> > >> > > intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > >> > > *state);
> > >> > > +void intel_global_dpll_verify_disabled(struct intel_atomic_state
> > >> > > +*state);
> > >> > >
> > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > >> >
> > >> > If you're renaming almost everything anyway, I'd appreciate moving
> > >> > towards naming functions according to the file name, i.e. functions
> > >> > in intel_foo.[ch] would be named intel_foo_*().
> > >> >
> > >> > The dpll mgr is notoriously bad in this regard. I'm also open to
> > >> > renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
> > >> >
> > >> > I'm not sure if the term "global" (instead of "shared") was very
> > >> > well justified in patch 3. Maybe all of these should be thought out
> > >> > together for the
> > >> naming.
> > >> >
> > >>
> > >> I agree with the renaming I would have very much have to keep the
> > >> naming simple something like Intel_dpll_func but that exits !
> > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some hooks defined
> > inside It.
> > >> I chose global since that way we will be able to represent both PLL
> > >> using shared PHY and PLL with individual PHY.
> > >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch] making it
> > >> a problem What if we renamed the file to intel_global_dpll.[ch]
> > >
> > > Jani what do you think of this ?
> >
> > I think Ville probably has opinions on this. Cc'd.
>
> Hi Ville,
> Any thoughts ?
IMO it should just be intel_dpll_*. We want all PLLs to provide
the same uniform interface for enable/disble/readout/state_dump/etc.
Whether the PLL is shared/global or not isn't interesting outside
the actual modeset sequence and PLL selection logic.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-28 14:26 ` Ville Syrjälä
@ 2025-02-28 15:31 ` Kandpal, Suraj
2025-03-03 12:51 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Kandpal, Suraj @ 2025-02-28 15:31 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, February 28, 2025 7:57 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
> Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > Syrjala, Ville <ville.syrjala@intel.com>
> > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > shared dpll
> > >
> > > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > > >> -----Original Message-----
> > > >> From: Kandpal, Suraj
> > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > >> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > >> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > >> shared dpll
> > > >>
> > > >>
> > > >>
> > > >> > -----Original Message-----
> > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > >> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar,
> > > >> > Uma <uma.shankar@intel.com>; Kahola, Mika
> > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > >> > <suraj.kandpal@intel.com>
> > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > >> > shared dpll
> > > >> >
> > > >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > >> > > Rename functions to move away from using shared dpll in the
> > > >> > > dpll framework as much as possible since dpll may not always be
> shared.
> > > >> > >
> > > >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > >> >
> > > >> > ...
> > > >> >
> > > >> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > > >> > > SKL_DPLL2
> > > >> > > 2 #define SKL_DPLL3 3
> > > >> > >
> > > >> > > -/* shared dpll functions */
> > > >> > > +/* global dpll functions */
> > > >> > > struct intel_global_dpll *
> > > >> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > > >> > > +intel_get_global_dpll_by_id(struct intel_display *display,
> > > >> > > enum intel_dpll_id id); -void
> > > >> > > assert_shared_dpll(struct intel_display *display,
> > > >> > > +void assert_global_dpll(struct intel_display *display,
> > > >> > > struct intel_global_dpll *pll,
> > > >> > > bool state);
> > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > >> > > assert_shared_dpll(d, p,
> > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > >> > > assert_shared_dpll(d, p, false) -int
> > > >> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
> > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > >> > > +assert_global_dpll(d, p,
> > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > >> > > +assert_global_dpll(d, p, false) int
> > > >> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
> > > >> > > struct intel_crtc *crtc,
> > > >> > > struct intel_encoder *encoder); -int
> > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state
> > > >> > > +*state,
> > > >> > > struct intel_crtc *crtc,
> > > >> > > struct intel_encoder *encoder); -void
> > > >> > > intel_release_shared_dplls(struct intel_atomic_state *state,
> > > >> > > +void intel_release_global_dplls(struct intel_atomic_state
> > > >> > > +*state,
> > > >> > > struct intel_crtc *crtc); -void
> > > >> > > intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > > >> > > *crtc,
> > > >> > > +void intel_unreference_global_dpll_crtc(const struct
> > > >> > > +intel_crtc *crtc,
> > > >> > > const struct intel_global_dpll
> *pll,
> > > >> > > struct intel_dpll_state
> > > >> > *shared_dpll_state); void
> > > >> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > > >> > > @@
> > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > >> > > intel_display *display, bool intel_dpll_get_hw_state(struct
> intel_display *display,
> > > >> > > struct intel_global_dpll *pll,
> > > >> > > struct intel_dpll_hw_state *dpll_hw_state);
> -void
> > > >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> > > >> > > *crtc_state); -void intel_disable_shared_dpll(const struct
> > > >> > > intel_crtc_state *crtc_state); -void
> > > >> > > intel_shared_dpll_swap_state(struct
> > > >> > > intel_atomic_state *state); -void
> > > >> > > intel_shared_dpll_init(struct intel_display *display);
> > > >> > > +void intel_enable_global_dpll(const struct intel_crtc_state
> > > >> > > +*crtc_state); void intel_disable_global_dpll(const struct
> > > >> > > +intel_crtc_state *crtc_state); void
> > > >> > > +intel_dpll_swap_state(struct intel_atomic_state *state);
> > > >> > > +void intel_global_dpll_init(struct intel_display *display);
> > > >> > > void intel_dpll_update_ref_clks(struct intel_display
> > > >> > > *display); void intel_dpll_readout_hw_state(struct
> > > >> > > intel_display *display); void
> > > >> > > intel_dpll_sanitize_state(struct intel_display *display); @@
> > > >> > > -437,6
> > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> > > >> > >
> > > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > >> > > struct intel_crtc *crtc); -void
> > > >> > > intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > > >> > > *state);
> > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > >> > > +intel_atomic_state *state);
> > > >> > >
> > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > >> >
> > > >> > If you're renaming almost everything anyway, I'd appreciate
> > > >> > moving towards naming functions according to the file name,
> > > >> > i.e. functions in intel_foo.[ch] would be named intel_foo_*().
> > > >> >
> > > >> > The dpll mgr is notoriously bad in this regard. I'm also open
> > > >> > to renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
> > > >> >
> > > >> > I'm not sure if the term "global" (instead of "shared") was
> > > >> > very well justified in patch 3. Maybe all of these should be
> > > >> > thought out together for the
> > > >> naming.
> > > >> >
> > > >>
> > > >> I agree with the renaming I would have very much have to keep the
> > > >> naming simple something like Intel_dpll_func but that exits !
> > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some hooks
> > > >> defined
> > > inside It.
> > > >> I chose global since that way we will be able to represent both
> > > >> PLL using shared PHY and PLL with individual PHY.
> > > >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch]
> > > >> making it a problem What if we renamed the file to
> > > >> intel_global_dpll.[ch]
> > > >
> > > > Jani what do you think of this ?
> > >
> > > I think Ville probably has opinions on this. Cc'd.
> >
> > Hi Ville,
> > Any thoughts ?
>
> IMO it should just be intel_dpll_*. We want all PLLs to provide the same
> uniform interface for enable/disble/readout/state_dump/etc.
> Whether the PLL is shared/global or not isn't interesting outside the actual
> modeset sequence and PLL selection logic.
But that still leaves us with the question what would be the most appropriate way to do away with the
Intel_shared_dpll_* naming what does it become if not intel_global_dpll_* (since intel_dpll wouldn't be a
Straightforward answer to this) intel_dpll_global ?
Can we rename the file to intel_dpll_global that way we can also have all the functions follow the naming convention
As Jani said to intel_filename_foo()?
Regards,
Suraj Kandpal
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-02-28 15:31 ` Kandpal, Suraj
@ 2025-03-03 12:51 ` Ville Syrjälä
2025-03-07 12:02 ` Kahola, Mika
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2025-03-03 12:51 UTC (permalink / raw)
To: Kandpal, Suraj
Cc: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
On Fri, Feb 28, 2025 at 03:31:39PM +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Friday, February 28, 2025 7:57 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
> > intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
> > Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
> >
> > On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > Syrjala, Ville <ville.syrjala@intel.com>
> > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > shared dpll
> > > >
> > > > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > > > >> -----Original Message-----
> > > > >> From: Kandpal, Suraj
> > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > >> intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > >> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > >> shared dpll
> > > > >>
> > > > >>
> > > > >>
> > > > >> > -----Original Message-----
> > > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > >> > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar,
> > > > >> > Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > > >> > <suraj.kandpal@intel.com>
> > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > >> > shared dpll
> > > > >> >
> > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > > >> > > Rename functions to move away from using shared dpll in the
> > > > >> > > dpll framework as much as possible since dpll may not always be
> > shared.
> > > > >> > >
> > > > >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > >> >
> > > > >> > ...
> > > > >> >
> > > > >> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > > > >> > > SKL_DPLL2
> > > > >> > > 2 #define SKL_DPLL3 3
> > > > >> > >
> > > > >> > > -/* shared dpll functions */
> > > > >> > > +/* global dpll functions */
> > > > >> > > struct intel_global_dpll *
> > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > > > >> > > +intel_get_global_dpll_by_id(struct intel_display *display,
> > > > >> > > enum intel_dpll_id id); -void
> > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > >> > > +void assert_global_dpll(struct intel_display *display,
> > > > >> > > struct intel_global_dpll *pll,
> > > > >> > > bool state);
> > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > >> > > assert_shared_dpll(d, p,
> > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > >> > > intel_compute_shared_dplls(struct intel_atomic_state *state,
> > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > >> > > +assert_global_dpll(d, p,
> > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > >> > > +assert_global_dpll(d, p, false) int
> > > > >> > > +intel_compute_global_dplls(struct intel_atomic_state *state,
> > > > >> > > struct intel_crtc *crtc,
> > > > >> > > struct intel_encoder *encoder); -int
> > > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > > > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state
> > > > >> > > +*state,
> > > > >> > > struct intel_crtc *crtc,
> > > > >> > > struct intel_encoder *encoder); -void
> > > > >> > > intel_release_shared_dplls(struct intel_atomic_state *state,
> > > > >> > > +void intel_release_global_dplls(struct intel_atomic_state
> > > > >> > > +*state,
> > > > >> > > struct intel_crtc *crtc); -void
> > > > >> > > intel_unreference_shared_dpll_crtc(const struct intel_crtc
> > > > >> > > *crtc,
> > > > >> > > +void intel_unreference_global_dpll_crtc(const struct
> > > > >> > > +intel_crtc *crtc,
> > > > >> > > const struct intel_global_dpll
> > *pll,
> > > > >> > > struct intel_dpll_state
> > > > >> > *shared_dpll_state); void
> > > > >> > > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > > > >> > > @@
> > > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > > >> > > intel_display *display, bool intel_dpll_get_hw_state(struct
> > intel_display *display,
> > > > >> > > struct intel_global_dpll *pll,
> > > > >> > > struct intel_dpll_hw_state *dpll_hw_state);
> > -void
> > > > >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> > > > >> > > *crtc_state); -void intel_disable_shared_dpll(const struct
> > > > >> > > intel_crtc_state *crtc_state); -void
> > > > >> > > intel_shared_dpll_swap_state(struct
> > > > >> > > intel_atomic_state *state); -void
> > > > >> > > intel_shared_dpll_init(struct intel_display *display);
> > > > >> > > +void intel_enable_global_dpll(const struct intel_crtc_state
> > > > >> > > +*crtc_state); void intel_disable_global_dpll(const struct
> > > > >> > > +intel_crtc_state *crtc_state); void
> > > > >> > > +intel_dpll_swap_state(struct intel_atomic_state *state);
> > > > >> > > +void intel_global_dpll_init(struct intel_display *display);
> > > > >> > > void intel_dpll_update_ref_clks(struct intel_display
> > > > >> > > *display); void intel_dpll_readout_hw_state(struct
> > > > >> > > intel_display *display); void
> > > > >> > > intel_dpll_sanitize_state(struct intel_display *display); @@
> > > > >> > > -437,6
> > > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id);
> > > > >> > >
> > > > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > > >> > > struct intel_crtc *crtc); -void
> > > > >> > > intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > > > >> > > *state);
> > > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > > >> > > +intel_atomic_state *state);
> > > > >> > >
> > > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > > >> >
> > > > >> > If you're renaming almost everything anyway, I'd appreciate
> > > > >> > moving towards naming functions according to the file name,
> > > > >> > i.e. functions in intel_foo.[ch] would be named intel_foo_*().
> > > > >> >
> > > > >> > The dpll mgr is notoriously bad in this regard. I'm also open
> > > > >> > to renaming the entire file, intel_dpll_mgr.[ch] isn't all that great.
> > > > >> >
> > > > >> > I'm not sure if the term "global" (instead of "shared") was
> > > > >> > very well justified in patch 3. Maybe all of these should be
> > > > >> > thought out together for the
> > > > >> naming.
> > > > >> >
> > > > >>
> > > > >> I agree with the renaming I would have very much have to keep the
> > > > >> naming simple something like Intel_dpll_func but that exits !
> > > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some hooks
> > > > >> defined
> > > > inside It.
> > > > >> I chose global since that way we will be able to represent both
> > > > >> PLL using shared PHY and PLL with individual PHY.
> > > > >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch]
> > > > >> making it a problem What if we renamed the file to
> > > > >> intel_global_dpll.[ch]
> > > > >
> > > > > Jani what do you think of this ?
> > > >
> > > > I think Ville probably has opinions on this. Cc'd.
> > >
> > > Hi Ville,
> > > Any thoughts ?
> >
> > IMO it should just be intel_dpll_*. We want all PLLs to provide the same
> > uniform interface for enable/disble/readout/state_dump/etc.
> > Whether the PLL is shared/global or not isn't interesting outside the actual
> > modeset sequence and PLL selection logic.
>
> But that still leaves us with the question what would be the most appropriate way to do away with the
> Intel_shared_dpll_* naming what does it become if not intel_global_dpll_* (since intel_dpll wouldn't be a
> Straightforward answer to this) intel_dpll_global ?
What do you mean intel_dpll_* isn't a straightforward answer?
It is the right answer.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-03-03 12:51 ` Ville Syrjälä
@ 2025-03-07 12:02 ` Kahola, Mika
2025-03-07 13:06 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Kahola, Mika @ 2025-03-07 12:02 UTC (permalink / raw)
To: Ville Syrjälä, Kandpal, Suraj
Cc: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Monday, 3 March 2025 14.52
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal,
> Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Fri, Feb 28, 2025 at 03:31:39PM +0000, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Friday, February 28, 2025 7:57 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > > Kahola, Mika <mika.kahola@intel.com>
> > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > shared dpll
> > >
> > > On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > > Syrjala, Ville <ville.syrjala@intel.com>
> > > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > shared dpll
> > > > >
> > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > > > > >> -----Original Message-----
> > > > > >> From: Kandpal, Suraj
> > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > >> intel-xe@lists.freedesktop.org;
> > > > > >> intel-gfx@lists.freedesktop.org
> > > > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar,
> > > > > >> Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > >> <mika.kahola@intel.com>
> > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > >> using shared dpll
> > > > > >>
> > > > > >>
> > > > > >>
> > > > > >> > -----Original Message-----
> > > > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > >> > intel-xe@lists.freedesktop.org;
> > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > >> > Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > > > >> > <suraj.kandpal@intel.com>
> > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > >> > using shared dpll
> > > > > >> >
> > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com>
> wrote:
> > > > > >> > > Rename functions to move away from using shared dpll in
> > > > > >> > > the dpll framework as much as possible since dpll may not
> > > > > >> > > always be
> > > shared.
> > > > > >> > >
> > > > > >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > > >> >
> > > > > >> > ...
> > > > > >> >
> > > > > >> > > diff --git
> > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > > > > >> > > SKL_DPLL2
> > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > >> > >
> > > > > >> > > -/* shared dpll functions */
> > > > > >> > > +/* global dpll functions */
> > > > > >> > > struct intel_global_dpll *
> > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > >> > > *display,
> > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > >> > > +*display,
> > > > > >> > > enum intel_dpll_id id); -void
> > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > >> > > +void assert_global_dpll(struct intel_display *display,
> > > > > >> > > struct intel_global_dpll *pll,
> > > > > >> > > bool state);
> > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > >> > > assert_shared_dpll(d, p,
> > > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > > >> > > intel_compute_shared_dplls(struct intel_atomic_state
> > > > > >> > > *state,
> > > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > > >> > > +assert_global_dpll(d, p,
> > > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > > >> > > +assert_global_dpll(d, p, false) int
> > > > > >> > > +intel_compute_global_dplls(struct intel_atomic_state
> > > > > >> > > +*state,
> > > > > >> > > struct intel_crtc *crtc,
> > > > > >> > > struct intel_encoder *encoder); -int
> > > > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state
> > > > > >> > > *state,
> > > > > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state
> > > > > >> > > +*state,
> > > > > >> > > struct intel_crtc *crtc,
> > > > > >> > > struct intel_encoder *encoder); -void
> > > > > >> > > intel_release_shared_dplls(struct intel_atomic_state
> > > > > >> > > *state,
> > > > > >> > > +void intel_release_global_dplls(struct
> > > > > >> > > +intel_atomic_state *state,
> > > > > >> > > struct intel_crtc *crtc); -void
> > > > > >> > > intel_unreference_shared_dpll_crtc(const struct
> > > > > >> > > intel_crtc *crtc,
> > > > > >> > > +void intel_unreference_global_dpll_crtc(const struct
> > > > > >> > > +intel_crtc *crtc,
> > > > > >> > > const struct intel_global_dpll
> > > *pll,
> > > > > >> > > struct intel_dpll_state
> > > > > >> > *shared_dpll_state); void
> > > > > >> > > icl_set_active_port_dpll(struct intel_crtc_state
> > > > > >> > > *crtc_state, @@
> > > > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > > > >> > > intel_display *display, bool
> > > > > >> > > intel_dpll_get_hw_state(struct
> > > intel_display *display,
> > > > > >> > > struct intel_global_dpll *pll,
> > > > > >> > > struct intel_dpll_hw_state *dpll_hw_state);
> > > -void
> > > > > >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> > > > > >> > > *crtc_state); -void intel_disable_shared_dpll(const
> > > > > >> > > struct intel_crtc_state *crtc_state); -void
> > > > > >> > > intel_shared_dpll_swap_state(struct
> > > > > >> > > intel_atomic_state *state); -void
> > > > > >> > > intel_shared_dpll_init(struct intel_display *display);
> > > > > >> > > +void intel_enable_global_dpll(const struct
> > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > >> > > +intel_disable_global_dpll(const struct intel_crtc_state
> > > > > >> > > +*crtc_state); void intel_dpll_swap_state(struct
> > > > > >> > > +intel_atomic_state *state); void
> > > > > >> > > +intel_global_dpll_init(struct intel_display *display);
> > > > > >> > > void intel_dpll_update_ref_clks(struct intel_display
> > > > > >> > > *display); void intel_dpll_readout_hw_state(struct
> > > > > >> > > intel_display *display); void
> > > > > >> > > intel_dpll_sanitize_state(struct intel_display *display);
> > > > > >> > > @@
> > > > > >> > > -437,6
> > > > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id
> > > > > >> > > +id);
> > > > > >> > >
> > > > > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > > > >> > > struct intel_crtc *crtc); -void
> > > > > >> > > intel_shared_dpll_verify_disabled(struct
> > > > > >> > > intel_atomic_state *state);
> > > > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > > > >> > > +intel_atomic_state *state);
> > > > > >> > >
> > > > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > > > >> >
> > > > > >> > If you're renaming almost everything anyway, I'd appreciate
> > > > > >> > moving towards naming functions according to the file name,
> > > > > >> > i.e. functions in intel_foo.[ch] would be named intel_foo_*().
> > > > > >> >
> > > > > >> > The dpll mgr is notoriously bad in this regard. I'm also
> > > > > >> > open to renaming the entire file, intel_dpll_mgr.[ch] isn't all that
> great.
> > > > > >> >
> > > > > >> > I'm not sure if the term "global" (instead of "shared") was
> > > > > >> > very well justified in patch 3. Maybe all of these should
> > > > > >> > be thought out together for the
> > > > > >> naming.
> > > > > >> >
> > > > > >>
> > > > > >> I agree with the renaming I would have very much have to keep
> > > > > >> the naming simple something like Intel_dpll_func but that exits !
> > > > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some
> > > > > >> hooks defined
> > > > > inside It.
> > > > > >> I chose global since that way we will be able to represent
> > > > > >> both PLL using shared PHY and PLL with individual PHY.
> > > > > >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch]
> > > > > >> making it a problem What if we renamed the file to
> > > > > >> intel_global_dpll.[ch]
> > > > > >
> > > > > > Jani what do you think of this ?
> > > > >
> > > > > I think Ville probably has opinions on this. Cc'd.
> > > >
> > > > Hi Ville,
> > > > Any thoughts ?
> > >
> > > IMO it should just be intel_dpll_*. We want all PLLs to provide the
> > > same uniform interface for enable/disble/readout/state_dump/etc.
> > > Whether the PLL is shared/global or not isn't interesting outside
> > > the actual modeset sequence and PLL selection logic.
> >
> > But that still leaves us with the question what would be the most
> > appropriate way to do away with the
> > Intel_shared_dpll_* naming what does it become if not
> > intel_global_dpll_* (since intel_dpll wouldn't be a Straightforward answer to
> this) intel_dpll_global ?
>
> What do you mean intel_dpll_* isn't a straightforward answer?
> It is the right answer.
About this naming convention, we have defined (intel_display_core.h) structure for intel_dpll which contains structures for intel_shared_dpll and intel_dpll_mgr. Wouldn't renaming intel_shared_dpll to intel_dpll cause a conflict with already existing intel_dpll structure? Or should we keep the intel_shared_dpll structure intact and rename intel_shared_dpll_* simply intel_dpll_*?
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-03-07 12:02 ` Kahola, Mika
@ 2025-03-07 13:06 ` Ville Syrjälä
2025-03-07 13:53 ` Kahola, Mika
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2025-03-07 13:06 UTC (permalink / raw)
To: Kahola, Mika
Cc: Kandpal, Suraj, Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma
On Fri, Mar 07, 2025 at 12:02:09PM +0000, Kahola, Mika wrote:
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Monday, 3 March 2025 14.52
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org;
> > intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal,
> > Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > Kahola, Mika <mika.kahola@intel.com>
> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
> >
> > On Fri, Feb 28, 2025 at 03:31:39PM +0000, Kandpal, Suraj wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Sent: Friday, February 28, 2025 7:57 PM
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > > <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > > > Kahola, Mika <mika.kahola@intel.com>
> > > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > shared dpll
> > > >
> > > > On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > > > Syrjala, Ville <ville.syrjala@intel.com>
> > > > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > > shared dpll
> > > > > >
> > > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> > > > > > >> -----Original Message-----
> > > > > > >> From: Kandpal, Suraj
> > > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > > >> intel-xe@lists.freedesktop.org;
> > > > > > >> intel-gfx@lists.freedesktop.org
> > > > > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar,
> > > > > > >> Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > >> <mika.kahola@intel.com>
> > > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > >> using shared dpll
> > > > > > >>
> > > > > > >>
> > > > > > >>
> > > > > > >> > -----Original Message-----
> > > > > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > >> > intel-xe@lists.freedesktop.org;
> > > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > >> > Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > > > > >> > <suraj.kandpal@intel.com>
> > > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > >> > using shared dpll
> > > > > > >> >
> > > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com>
> > wrote:
> > > > > > >> > > Rename functions to move away from using shared dpll in
> > > > > > >> > > the dpll framework as much as possible since dpll may not
> > > > > > >> > > always be
> > > > shared.
> > > > > > >> > >
> > > > > > >> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > > > >> >
> > > > > > >> > ...
> > > > > > >> >
> > > > > > >> > > diff --git
> > > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll { #define
> > > > > > >> > > SKL_DPLL2
> > > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > > >> > >
> > > > > > >> > > -/* shared dpll functions */
> > > > > > >> > > +/* global dpll functions */
> > > > > > >> > > struct intel_global_dpll *
> > > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > > >> > > *display,
> > > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > > >> > > +*display,
> > > > > > >> > > enum intel_dpll_id id); -void
> > > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > > >> > > +void assert_global_dpll(struct intel_display *display,
> > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > >> > > bool state);
> > > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > > >> > > assert_shared_dpll(d, p,
> > > > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > > > >> > > intel_compute_shared_dplls(struct intel_atomic_state
> > > > > > >> > > *state,
> > > > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > > > >> > > +assert_global_dpll(d, p,
> > > > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > > > >> > > +assert_global_dpll(d, p, false) int
> > > > > > >> > > +intel_compute_global_dplls(struct intel_atomic_state
> > > > > > >> > > +*state,
> > > > > > >> > > struct intel_crtc *crtc,
> > > > > > >> > > struct intel_encoder *encoder); -int
> > > > > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state
> > > > > > >> > > *state,
> > > > > > >> > > +int intel_reserve_global_dplls(struct intel_atomic_state
> > > > > > >> > > +*state,
> > > > > > >> > > struct intel_crtc *crtc,
> > > > > > >> > > struct intel_encoder *encoder); -void
> > > > > > >> > > intel_release_shared_dplls(struct intel_atomic_state
> > > > > > >> > > *state,
> > > > > > >> > > +void intel_release_global_dplls(struct
> > > > > > >> > > +intel_atomic_state *state,
> > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > >> > > intel_unreference_shared_dpll_crtc(const struct
> > > > > > >> > > intel_crtc *crtc,
> > > > > > >> > > +void intel_unreference_global_dpll_crtc(const struct
> > > > > > >> > > +intel_crtc *crtc,
> > > > > > >> > > const struct intel_global_dpll
> > > > *pll,
> > > > > > >> > > struct intel_dpll_state
> > > > > > >> > *shared_dpll_state); void
> > > > > > >> > > icl_set_active_port_dpll(struct intel_crtc_state
> > > > > > >> > > *crtc_state, @@
> > > > > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > > > > >> > > intel_display *display, bool
> > > > > > >> > > intel_dpll_get_hw_state(struct
> > > > intel_display *display,
> > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > >> > > struct intel_dpll_hw_state *dpll_hw_state);
> > > > -void
> > > > > > >> > > intel_enable_shared_dpll(const struct intel_crtc_state
> > > > > > >> > > *crtc_state); -void intel_disable_shared_dpll(const
> > > > > > >> > > struct intel_crtc_state *crtc_state); -void
> > > > > > >> > > intel_shared_dpll_swap_state(struct
> > > > > > >> > > intel_atomic_state *state); -void
> > > > > > >> > > intel_shared_dpll_init(struct intel_display *display);
> > > > > > >> > > +void intel_enable_global_dpll(const struct
> > > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > > >> > > +intel_disable_global_dpll(const struct intel_crtc_state
> > > > > > >> > > +*crtc_state); void intel_dpll_swap_state(struct
> > > > > > >> > > +intel_atomic_state *state); void
> > > > > > >> > > +intel_global_dpll_init(struct intel_display *display);
> > > > > > >> > > void intel_dpll_update_ref_clks(struct intel_display
> > > > > > >> > > *display); void intel_dpll_readout_hw_state(struct
> > > > > > >> > > intel_display *display); void
> > > > > > >> > > intel_dpll_sanitize_state(struct intel_display *display);
> > > > > > >> > > @@
> > > > > > >> > > -437,6
> > > > > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum intel_dpll_id
> > > > > > >> > > +id);
> > > > > > >> > >
> > > > > > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > >> > > intel_shared_dpll_verify_disabled(struct
> > > > > > >> > > intel_atomic_state *state);
> > > > > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > > > > >> > > +intel_atomic_state *state);
> > > > > > >> > >
> > > > > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > > > > >> >
> > > > > > >> > If you're renaming almost everything anyway, I'd appreciate
> > > > > > >> > moving towards naming functions according to the file name,
> > > > > > >> > i.e. functions in intel_foo.[ch] would be named intel_foo_*().
> > > > > > >> >
> > > > > > >> > The dpll mgr is notoriously bad in this regard. I'm also
> > > > > > >> > open to renaming the entire file, intel_dpll_mgr.[ch] isn't all that
> > great.
> > > > > > >> >
> > > > > > >> > I'm not sure if the term "global" (instead of "shared") was
> > > > > > >> > very well justified in patch 3. Maybe all of these should
> > > > > > >> > be thought out together for the
> > > > > > >> naming.
> > > > > > >> >
> > > > > > >>
> > > > > > >> I agree with the renaming I would have very much have to keep
> > > > > > >> the naming simple something like Intel_dpll_func but that exits !
> > > > > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some
> > > > > > >> hooks defined
> > > > > > inside It.
> > > > > > >> I chose global since that way we will be able to represent
> > > > > > >> both PLL using shared PHY and PLL with individual PHY.
> > > > > > >> Also renaming intel_dpll_mgr.[ch] we have a intel_dpll.[ch]
> > > > > > >> making it a problem What if we renamed the file to
> > > > > > >> intel_global_dpll.[ch]
> > > > > > >
> > > > > > > Jani what do you think of this ?
> > > > > >
> > > > > > I think Ville probably has opinions on this. Cc'd.
> > > > >
> > > > > Hi Ville,
> > > > > Any thoughts ?
> > > >
> > > > IMO it should just be intel_dpll_*. We want all PLLs to provide the
> > > > same uniform interface for enable/disble/readout/state_dump/etc.
> > > > Whether the PLL is shared/global or not isn't interesting outside
> > > > the actual modeset sequence and PLL selection logic.
> > >
> > > But that still leaves us with the question what would be the most
> > > appropriate way to do away with the
> > > Intel_shared_dpll_* naming what does it become if not
> > > intel_global_dpll_* (since intel_dpll wouldn't be a Straightforward answer to
> > this) intel_dpll_global ?
> >
> > What do you mean intel_dpll_* isn't a straightforward answer?
> > It is the right answer.
>
> About this naming convention, we have defined (intel_display_core.h) structure for intel_dpll which contains structures for intel_shared_dpll and intel_dpll_mgr. Wouldn't renaming intel_shared_dpll to intel_dpll cause a conflict with already existing intel_dpll structure? Or should we keep the intel_shared_dpll structure intact and rename intel_shared_dpll_* simply intel_dpll_*?
I think just rename the current intel_dpll to something more
appropriate.
Or just forget about naming for now and move ahead with the
actual work. We've been doing fine with the _shared_dpll name
up to now, so clearly it's not *that* important what it's called.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-03-07 13:06 ` Ville Syrjälä
@ 2025-03-07 13:53 ` Kahola, Mika
2025-03-11 8:12 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Kahola, Mika @ 2025-03-07 13:53 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Kandpal, Suraj, Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, 7 March 2025 15.07
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit
> K <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> On Fri, Mar 07, 2025 at 12:02:09PM +0000, Kahola, Mika wrote:
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Monday, 3 March 2025 14.52
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > > Kahola, Mika <mika.kahola@intel.com>
> > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > shared dpll
> > >
> > > On Fri, Feb 28, 2025 at 03:31:39PM +0000, Kandpal, Suraj wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Sent: Friday, February 28, 2025 7:57 PM
> > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > > Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > > > <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > shared dpll
> > > > >
> > > > > On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> > > > > >
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > > intel-xe@lists.freedesktop.org;
> > > > > > > intel-gfx@lists.freedesktop.org; Syrjala, Ville
> > > > > > > <ville.syrjala@intel.com>
> > > > > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar,
> > > > > > > Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > <mika.kahola@intel.com>
> > > > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > > using shared dpll
> > > > > > >
> > > > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com>
> wrote:
> > > > > > > >> -----Original Message-----
> > > > > > > >> From: Kandpal, Suraj
> > > > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > > > >> intel-xe@lists.freedesktop.org;
> > > > > > > >> intel-gfx@lists.freedesktop.org
> > > > > > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > > >> Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > >> <mika.kahola@intel.com>
> > > > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > > >> using shared dpll
> > > > > > > >>
> > > > > > > >>
> > > > > > > >>
> > > > > > > >> > -----Original Message-----
> > > > > > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > > >> > intel-xe@lists.freedesktop.org;
> > > > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > > >> > Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > > > > > >> > <suraj.kandpal@intel.com>
> > > > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away
> > > > > > > >> > from using shared dpll
> > > > > > > >> >
> > > > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal
> > > > > > > >> > <suraj.kandpal@intel.com>
> > > wrote:
> > > > > > > >> > > Rename functions to move away from using shared dpll
> > > > > > > >> > > in the dpll framework as much as possible since dpll
> > > > > > > >> > > may not always be
> > > > > shared.
> > > > > > > >> > >
> > > > > > > >> > > Signed-off-by: Suraj Kandpal
> > > > > > > >> > > <suraj.kandpal@intel.com>
> > > > > > > >> >
> > > > > > > >> > ...
> > > > > > > >> >
> > > > > > > >> > > diff --git
> > > > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll {
> > > > > > > >> > > #define
> > > > > > > >> > > SKL_DPLL2
> > > > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > > > >> > >
> > > > > > > >> > > -/* shared dpll functions */
> > > > > > > >> > > +/* global dpll functions */
> > > > > > > >> > > struct intel_global_dpll *
> > > > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > > > >> > > *display,
> > > > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > > > >> > > +*display,
> > > > > > > >> > > enum intel_dpll_id id); -void
> > > > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > > > >> > > +void assert_global_dpll(struct intel_display
> > > > > > > >> > > +*display,
> > > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > > >> > > bool state);
> > > > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > > > >> > > assert_shared_dpll(d, p,
> > > > > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > > > > >> > > intel_compute_shared_dplls(struct intel_atomic_state
> > > > > > > >> > > *state,
> > > > > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > > > > >> > > +assert_global_dpll(d, p,
> > > > > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > > > > >> > > +assert_global_dpll(d, p, false) int
> > > > > > > >> > > +intel_compute_global_dplls(struct intel_atomic_state
> > > > > > > >> > > +*state,
> > > > > > > >> > > struct intel_crtc *crtc,
> > > > > > > >> > > struct intel_encoder *encoder); -int
> > > > > > > >> > > intel_reserve_shared_dplls(struct intel_atomic_state
> > > > > > > >> > > *state,
> > > > > > > >> > > +int intel_reserve_global_dplls(struct
> > > > > > > >> > > +intel_atomic_state *state,
> > > > > > > >> > > struct intel_crtc *crtc,
> > > > > > > >> > > struct intel_encoder *encoder); -
> void
> > > > > > > >> > > intel_release_shared_dplls(struct intel_atomic_state
> > > > > > > >> > > *state,
> > > > > > > >> > > +void intel_release_global_dplls(struct
> > > > > > > >> > > +intel_atomic_state *state,
> > > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > > >> > > intel_unreference_shared_dpll_crtc(const struct
> > > > > > > >> > > intel_crtc *crtc,
> > > > > > > >> > > +void intel_unreference_global_dpll_crtc(const struct
> > > > > > > >> > > +intel_crtc *crtc,
> > > > > > > >> > > const struct
> intel_global_dpll
> > > > > *pll,
> > > > > > > >> > > struct intel_dpll_state
> > > > > > > >> > *shared_dpll_state); void
> > > > > > > >> > > icl_set_active_port_dpll(struct intel_crtc_state
> > > > > > > >> > > *crtc_state, @@
> > > > > > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > > > > > >> > > intel_display *display, bool
> > > > > > > >> > > intel_dpll_get_hw_state(struct
> > > > > intel_display *display,
> > > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > > >> > > struct intel_dpll_hw_state
> *dpll_hw_state);
> > > > > -void
> > > > > > > >> > > intel_enable_shared_dpll(const struct
> > > > > > > >> > > intel_crtc_state *crtc_state); -void
> > > > > > > >> > > intel_disable_shared_dpll(const struct
> > > > > > > >> > > intel_crtc_state *crtc_state); -void
> > > > > > > >> > > intel_shared_dpll_swap_state(struct
> > > > > > > >> > > intel_atomic_state *state); -void
> > > > > > > >> > > intel_shared_dpll_init(struct intel_display
> > > > > > > >> > > *display);
> > > > > > > >> > > +void intel_enable_global_dpll(const struct
> > > > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > > > >> > > +intel_disable_global_dpll(const struct
> > > > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > > > >> > > +intel_dpll_swap_state(struct intel_atomic_state
> > > > > > > >> > > +*state); void intel_global_dpll_init(struct
> > > > > > > >> > > +intel_display *display);
> > > > > > > >> > > void intel_dpll_update_ref_clks(struct intel_display
> > > > > > > >> > > *display); void intel_dpll_readout_hw_state(struct
> > > > > > > >> > > intel_display *display); void
> > > > > > > >> > > intel_dpll_sanitize_state(struct intel_display
> > > > > > > >> > > *display); @@
> > > > > > > >> > > -437,6
> > > > > > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum
> > > > > > > >> > > +intel_dpll_id id);
> > > > > > > >> > >
> > > > > > > >> > > void intel_dpll_state_verify(struct intel_atomic_state *state,
> > > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > > >> > > intel_shared_dpll_verify_disabled(struct
> > > > > > > >> > > intel_atomic_state *state);
> > > > > > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > > > > > >> > > +intel_atomic_state *state);
> > > > > > > >> > >
> > > > > > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > > > > > >> >
> > > > > > > >> > If you're renaming almost everything anyway, I'd
> > > > > > > >> > appreciate moving towards naming functions according to
> > > > > > > >> > the file name, i.e. functions in intel_foo.[ch] would be named
> intel_foo_*().
> > > > > > > >> >
> > > > > > > >> > The dpll mgr is notoriously bad in this regard. I'm
> > > > > > > >> > also open to renaming the entire file,
> > > > > > > >> > intel_dpll_mgr.[ch] isn't all that
> > > great.
> > > > > > > >> >
> > > > > > > >> > I'm not sure if the term "global" (instead of "shared")
> > > > > > > >> > was very well justified in patch 3. Maybe all of these
> > > > > > > >> > should be thought out together for the
> > > > > > > >> naming.
> > > > > > > >> >
> > > > > > > >>
> > > > > > > >> I agree with the renaming I would have very much have to
> > > > > > > >> keep the naming simple something like Intel_dpll_func but that
> exits !
> > > > > > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has some
> > > > > > > >> hooks defined
> > > > > > > inside It.
> > > > > > > >> I chose global since that way we will be able to
> > > > > > > >> represent both PLL using shared PHY and PLL with individual PHY.
> > > > > > > >> Also renaming intel_dpll_mgr.[ch] we have a
> > > > > > > >> intel_dpll.[ch] making it a problem What if we renamed
> > > > > > > >> the file to intel_global_dpll.[ch]
> > > > > > > >
> > > > > > > > Jani what do you think of this ?
> > > > > > >
> > > > > > > I think Ville probably has opinions on this. Cc'd.
> > > > > >
> > > > > > Hi Ville,
> > > > > > Any thoughts ?
> > > > >
> > > > > IMO it should just be intel_dpll_*. We want all PLLs to provide
> > > > > the same uniform interface for enable/disble/readout/state_dump/etc.
> > > > > Whether the PLL is shared/global or not isn't interesting
> > > > > outside the actual modeset sequence and PLL selection logic.
> > > >
> > > > But that still leaves us with the question what would be the most
> > > > appropriate way to do away with the
> > > > Intel_shared_dpll_* naming what does it become if not
> > > > intel_global_dpll_* (since intel_dpll wouldn't be a
> > > > Straightforward answer to
> > > this) intel_dpll_global ?
> > >
> > > What do you mean intel_dpll_* isn't a straightforward answer?
> > > It is the right answer.
> >
> > About this naming convention, we have defined (intel_display_core.h) structure
> for intel_dpll which contains structures for intel_shared_dpll and intel_dpll_mgr.
> Wouldn't renaming intel_shared_dpll to intel_dpll cause a conflict with already
> existing intel_dpll structure? Or should we keep the intel_shared_dpll structure
> intact and rename intel_shared_dpll_* simply intel_dpll_*?
>
> I think just rename the current intel_dpll to something more appropriate.
>
> Or just forget about naming for now and move ahead with the actual work. We've
> been doing fine with the _shared_dpll name up to now, so clearly it's not *that*
> important what it's called.
Ok. Let's put this naming stuff on hold for a while. I will move on to cx0 pll's as part of pll framework.
Thanks!
Mika
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
2025-03-07 13:53 ` Kahola, Mika
@ 2025-03-11 8:12 ` Kandpal, Suraj
0 siblings, 0 replies; 30+ messages in thread
From: Kandpal, Suraj @ 2025-03-11 8:12 UTC (permalink / raw)
To: Kahola, Mika, Ville Syrjälä
Cc: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, Syrjala, Ville,
Nautiyal, Ankit K, Shankar, Uma
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Friday, March 7, 2025 7:24 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal,
> Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>
> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Friday, 7 March 2025 15.07
> > To: Kahola, Mika <mika.kahola@intel.com>
> > Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> > <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-
> > gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
> > Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>
> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using shared
> > dpll
> >
> > On Fri, Mar 07, 2025 at 12:02:09PM +0000, Kahola, Mika wrote:
> > > > -----Original Message-----
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Sent: Monday, 3 March 2025 14.52
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > > > Syrjala, Ville <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > > <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > shared dpll
> > > >
> > > > On Fri, Feb 28, 2025 at 03:31:39PM +0000, Kandpal, Suraj wrote:
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > Sent: Friday, February 28, 2025 7:57 PM
> > > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > > intel-xe@lists.freedesktop.org;
> > > > > > intel-gfx@lists.freedesktop.org; Syrjala, Ville
> > > > > > <ville.syrjala@intel.com>; Nautiyal, Ankit K
> > > > > > <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > > > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > > > > > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away from using
> > > > > > shared dpll
> > > > > >
> > > > > > On Thu, Feb 27, 2025 at 10:18:31AM +0000, Kandpal, Suraj wrote:
> > > > > > >
> > > > > > >
> > > > > > > > -----Original Message-----
> > > > > > > > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > > > Sent: Tuesday, February 25, 2025 9:00 PM
> > > > > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > > > intel-xe@lists.freedesktop.org;
> > > > > > > > intel-gfx@lists.freedesktop.org; Syrjala, Ville
> > > > > > > > <ville.syrjala@intel.com>
> > > > > > > > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > > > Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > > <mika.kahola@intel.com>
> > > > > > > > Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away from
> > > > > > > > using shared dpll
> > > > > > > >
> > > > > > > > On Tue, 25 Feb 2025, "Kandpal, Suraj"
> > > > > > > > <suraj.kandpal@intel.com>
> > wrote:
> > > > > > > > >> -----Original Message-----
> > > > > > > > >> From: Kandpal, Suraj
> > > > > > > > >> Sent: Tuesday, February 25, 2025 2:25 PM
> > > > > > > > >> To: Jani Nikula <jani.nikula@linux.intel.com>;
> > > > > > > > >> intel-xe@lists.freedesktop.org;
> > > > > > > > >> intel-gfx@lists.freedesktop.org
> > > > > > > > >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > > > >> Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > > >> <mika.kahola@intel.com>
> > > > > > > > >> Subject: RE: [PATCH 05/11] drm/i915/dpll: Move away
> > > > > > > > >> from using shared dpll
> > > > > > > > >>
> > > > > > > > >>
> > > > > > > > >>
> > > > > > > > >> > -----Original Message-----
> > > > > > > > >> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > > > > >> > Sent: Tuesday, February 25, 2025 2:17 PM
> > > > > > > > >> > To: Kandpal, Suraj <suraj.kandpal@intel.com>;
> > > > > > > > >> > intel-xe@lists.freedesktop.org;
> > > > > > > > >> > intel-gfx@lists.freedesktop.org
> > > > > > > > >> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> > > > > > > > >> > Shankar, Uma <uma.shankar@intel.com>; Kahola, Mika
> > > > > > > > >> > <mika.kahola@intel.com>; Kandpal, Suraj
> > > > > > > > >> > <suraj.kandpal@intel.com>
> > > > > > > > >> > Subject: Re: [PATCH 05/11] drm/i915/dpll: Move away
> > > > > > > > >> > from using shared dpll
> > > > > > > > >> >
> > > > > > > > >> > On Tue, 25 Feb 2025, Suraj Kandpal
> > > > > > > > >> > <suraj.kandpal@intel.com>
> > > > wrote:
> > > > > > > > >> > > Rename functions to move away from using shared
> > > > > > > > >> > > dpll in the dpll framework as much as possible
> > > > > > > > >> > > since dpll may not always be
> > > > > > shared.
> > > > > > > > >> > >
> > > > > > > > >> > > Signed-off-by: Suraj Kandpal
> > > > > > > > >> > > <suraj.kandpal@intel.com>
> > > > > > > > >> >
> > > > > > > > >> > ...
> > > > > > > > >> >
> > > > > > > > >> > > diff --git
> > > > > > > > >> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > > >> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > > >> > > index 6edd103eda55..ef66aca5da1d 100644
> > > > > > > > >> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > > >> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > > > > > > >> > > @@ -387,24 +387,24 @@ struct intel_global_dpll {
> > > > > > > > >> > > #define
> > > > > > > > >> > > SKL_DPLL2
> > > > > > > > >> > > 2 #define SKL_DPLL3 3
> > > > > > > > >> > >
> > > > > > > > >> > > -/* shared dpll functions */
> > > > > > > > >> > > +/* global dpll functions */
> > > > > > > > >> > > struct intel_global_dpll *
> > > > > > > > >> > > -intel_get_shared_dpll_by_id(struct intel_display
> > > > > > > > >> > > *display,
> > > > > > > > >> > > +intel_get_global_dpll_by_id(struct intel_display
> > > > > > > > >> > > +*display,
> > > > > > > > >> > > enum intel_dpll_id id); -void
> > > > > > > > >> > > assert_shared_dpll(struct intel_display *display,
> > > > > > > > >> > > +void assert_global_dpll(struct intel_display
> > > > > > > > >> > > +*display,
> > > > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > > > >> > > bool state);
> > > > > > > > >> > > -#define assert_shared_dpll_enabled(d, p)
> > > > > > > > >> > > assert_shared_dpll(d, p,
> > > > > > > > >> > > true) -#define assert_shared_dpll_disabled(d, p)
> > > > > > > > >> > > assert_shared_dpll(d, p, false) -int
> > > > > > > > >> > > intel_compute_shared_dplls(struct
> > > > > > > > >> > > intel_atomic_state *state,
> > > > > > > > >> > > +#define assert_global_dpll_enabled(d, p)
> > > > > > > > >> > > +assert_global_dpll(d, p,
> > > > > > > > >> > > +true) #define assert_global_dpll_disabled(d, p)
> > > > > > > > >> > > +assert_global_dpll(d, p, false) int
> > > > > > > > >> > > +intel_compute_global_dplls(struct
> > > > > > > > >> > > +intel_atomic_state *state,
> > > > > > > > >> > > struct intel_crtc *crtc,
> > > > > > > > >> > > struct intel_encoder *encoder); -
> int
> > > > > > > > >> > > intel_reserve_shared_dplls(struct
> > > > > > > > >> > > intel_atomic_state *state,
> > > > > > > > >> > > +int intel_reserve_global_dplls(struct
> > > > > > > > >> > > +intel_atomic_state *state,
> > > > > > > > >> > > struct intel_crtc *crtc,
> > > > > > > > >> > > struct intel_encoder *encoder); -
> > void
> > > > > > > > >> > > intel_release_shared_dplls(struct
> > > > > > > > >> > > intel_atomic_state *state,
> > > > > > > > >> > > +void intel_release_global_dplls(struct
> > > > > > > > >> > > +intel_atomic_state *state,
> > > > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > > > >> > > intel_unreference_shared_dpll_crtc(const struct
> > > > > > > > >> > > intel_crtc *crtc,
> > > > > > > > >> > > +void intel_unreference_global_dpll_crtc(const
> > > > > > > > >> > > +struct intel_crtc *crtc,
> > > > > > > > >> > > const struct
> > intel_global_dpll
> > > > > > *pll,
> > > > > > > > >> > > struct intel_dpll_state
> > > > > > > > >> > *shared_dpll_state); void
> > > > > > > > >> > > icl_set_active_port_dpll(struct intel_crtc_state
> > > > > > > > >> > > *crtc_state, @@
> > > > > > > > >> > > -418,10 +418,10 @@ int intel_dpll_get_freq(struct
> > > > > > > > >> > > intel_display *display, bool
> > > > > > > > >> > > intel_dpll_get_hw_state(struct
> > > > > > intel_display *display,
> > > > > > > > >> > > struct intel_global_dpll *pll,
> > > > > > > > >> > > struct intel_dpll_hw_state
> > *dpll_hw_state);
> > > > > > -void
> > > > > > > > >> > > intel_enable_shared_dpll(const struct
> > > > > > > > >> > > intel_crtc_state *crtc_state); -void
> > > > > > > > >> > > intel_disable_shared_dpll(const struct
> > > > > > > > >> > > intel_crtc_state *crtc_state); -void
> > > > > > > > >> > > intel_shared_dpll_swap_state(struct
> > > > > > > > >> > > intel_atomic_state *state); -void
> > > > > > > > >> > > intel_shared_dpll_init(struct intel_display
> > > > > > > > >> > > *display);
> > > > > > > > >> > > +void intel_enable_global_dpll(const struct
> > > > > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > > > > >> > > +intel_disable_global_dpll(const struct
> > > > > > > > >> > > +intel_crtc_state *crtc_state); void
> > > > > > > > >> > > +intel_dpll_swap_state(struct intel_atomic_state
> > > > > > > > >> > > +*state); void intel_global_dpll_init(struct
> > > > > > > > >> > > +intel_display *display);
> > > > > > > > >> > > void intel_dpll_update_ref_clks(struct
> > > > > > > > >> > > intel_display *display); void
> > > > > > > > >> > > intel_dpll_readout_hw_state(struct
> > > > > > > > >> > > intel_display *display); void
> > > > > > > > >> > > intel_dpll_sanitize_state(struct intel_display
> > > > > > > > >> > > *display); @@
> > > > > > > > >> > > -437,6
> > > > > > > > >> > > +437,6 @@ bool intel_dpll_is_combophy(enum
> > > > > > > > >> > > +intel_dpll_id id);
> > > > > > > > >> > >
> > > > > > > > >> > > void intel_dpll_state_verify(struct intel_atomic_state
> *state,
> > > > > > > > >> > > struct intel_crtc *crtc); -void
> > > > > > > > >> > > intel_shared_dpll_verify_disabled(struct
> > > > > > > > >> > > intel_atomic_state *state);
> > > > > > > > >> > > +void intel_global_dpll_verify_disabled(struct
> > > > > > > > >> > > +intel_atomic_state *state);
> > > > > > > > >> > >
> > > > > > > > >> > > #endif /* _INTEL_DPLL_MGR_H_ */
> > > > > > > > >> >
> > > > > > > > >> > If you're renaming almost everything anyway, I'd
> > > > > > > > >> > appreciate moving towards naming functions according
> > > > > > > > >> > to the file name, i.e. functions in intel_foo.[ch]
> > > > > > > > >> > would be named
> > intel_foo_*().
> > > > > > > > >> >
> > > > > > > > >> > The dpll mgr is notoriously bad in this regard. I'm
> > > > > > > > >> > also open to renaming the entire file,
> > > > > > > > >> > intel_dpll_mgr.[ch] isn't all that
> > > > great.
> > > > > > > > >> >
> > > > > > > > >> > I'm not sure if the term "global" (instead of
> > > > > > > > >> > "shared") was very well justified in patch 3. Maybe
> > > > > > > > >> > all of these should be thought out together for the
> > > > > > > > >> naming.
> > > > > > > > >> >
> > > > > > > > >>
> > > > > > > > >> I agree with the renaming I would have very much have
> > > > > > > > >> to keep the naming simple something like
> > > > > > > > >> Intel_dpll_func but that
> > exits !
> > > > > > > > >> intel_dpll_mgr_funcs but intel_dpll_mgr already has
> > > > > > > > >> some hooks defined
> > > > > > > > inside It.
> > > > > > > > >> I chose global since that way we will be able to
> > > > > > > > >> represent both PLL using shared PHY and PLL with individual
> PHY.
> > > > > > > > >> Also renaming intel_dpll_mgr.[ch] we have a
> > > > > > > > >> intel_dpll.[ch] making it a problem What if we renamed
> > > > > > > > >> the file to intel_global_dpll.[ch]
> > > > > > > > >
> > > > > > > > > Jani what do you think of this ?
> > > > > > > >
> > > > > > > > I think Ville probably has opinions on this. Cc'd.
> > > > > > >
> > > > > > > Hi Ville,
> > > > > > > Any thoughts ?
> > > > > >
> > > > > > IMO it should just be intel_dpll_*. We want all PLLs to
> > > > > > provide the same uniform interface for
> enable/disble/readout/state_dump/etc.
> > > > > > Whether the PLL is shared/global or not isn't interesting
> > > > > > outside the actual modeset sequence and PLL selection logic.
> > > > >
> > > > > But that still leaves us with the question what would be the
> > > > > most appropriate way to do away with the
> > > > > Intel_shared_dpll_* naming what does it become if not
> > > > > intel_global_dpll_* (since intel_dpll wouldn't be a
> > > > > Straightforward answer to
> > > > this) intel_dpll_global ?
> > > >
> > > > What do you mean intel_dpll_* isn't a straightforward answer?
> > > > It is the right answer.
> > >
> > > About this naming convention, we have defined (intel_display_core.h)
> > > structure
> > for intel_dpll which contains structures for intel_shared_dpll and
> intel_dpll_mgr.
> > Wouldn't renaming intel_shared_dpll to intel_dpll cause a conflict
> > with already existing intel_dpll structure? Or should we keep the
> > intel_shared_dpll structure intact and rename intel_shared_dpll_* simply
> intel_dpll_*?
> >
> > I think just rename the current intel_dpll to something more appropriate.
> >
> > Or just forget about naming for now and move ahead with the actual
> > work. We've been doing fine with the _shared_dpll name up to now, so
> > clearly it's not *that* important what it's called.
>
> Ok. Let's put this naming stuff on hold for a while. I will move on to cx0 pll's as
> part of pll framework.
I can have a go and float a new series using the intel_dpll_* for function naming
And using intel_dpll_global instead of intel_shared_dpll for structure naming
Regards,
Suraj Kandpal
>
> Thanks!
> Mika
> >
> > --
> > Ville Syrjälä
> > Intel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 06/11] drm/i915/dpll: Rename crtc_get_shared_dpll
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (4 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 05/11] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
` (7 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename crtc_get_shared_dpll to take into the individual PLL framework
which came in at DISPLAY_VER >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll.h | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 36e365cdb33f..8f6f787a911d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4387,7 +4387,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (intel_crtc_needs_modeset(crtc_state)) {
- ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+ ret = intel_dpll_crtc_get_global_dpll(state, crtc);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 78cdbd54a5ba..3653839d531d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -27,7 +27,7 @@
struct intel_dpll_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
- int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
+ int (*crtc_get_global_dpll)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
};
@@ -1183,7 +1183,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
+static int hsw_crtc_get_global_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -1416,7 +1416,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
return ret;
}
-static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
+static int ilk_crtc_get_global_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
@@ -1716,12 +1716,12 @@ static const struct intel_dpll_funcs dg2_dpll_funcs = {
static const struct intel_dpll_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
- .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
+ .crtc_get_global_dpll = hsw_crtc_get_global_dpll,
};
static const struct intel_dpll_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
- .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
+ .crtc_get_global_dpll = ilk_crtc_get_global_dpll,
};
static const struct intel_dpll_funcs chv_dpll_funcs = {
@@ -1774,7 +1774,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+int intel_dpll_crtc_get_global_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
@@ -1788,10 +1788,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->hw.enable || crtc_state->global_dpll)
return 0;
- if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
+ if (!i915->display.funcs.dpll->crtc_get_global_dpll)
return 0;
- ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
+ ret = i915->display.funcs.dpll->crtc_get_global_dpll(state, crtc);
if (ret) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
crtc->base.base.id, crtc->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 21d06cbd2ce7..b3ab01a2cb5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -20,7 +20,7 @@ enum pipe;
void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
+int intel_dpll_crtc_get_global_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (5 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 06/11] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-03-07 14:06 ` Ville Syrjälä
2025-02-25 8:09 ` [PATCH 08/11] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
` (6 subsequent siblings)
13 siblings, 1 reply; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Change the arguments for enable hook in intel_global_dpll_funcs to only
accept crtc_state. This is because we really don't need those extra
arguments everything can be derived from crtc_state and we need
intel_encoder for PLL enablement when DISPLAY_VER() >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++--------
1 file changed, 54 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bd623fdddfdc..c39f7d73a89f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -66,9 +66,8 @@ struct intel_global_dpll_funcs {
* Hook for enabling the pll, called from intel_enable_global_dpll() if
* the pll is not already enabled.
*/
- void (*enable)(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ void (*enable)(const struct intel_crtc_state *state,
+ struct intel_encoder *encoder);
/*
* Hook for disabling the pll, called from intel_disable_global_dpll()
@@ -226,13 +225,15 @@ intel_tc_pll_enable_reg(struct intel_display *display,
return MG_PLL_ENABLE(tc_port);
}
-static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_global_dpll *pll)
+static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
- pll->info->funcs->enable(display, pll, &pll->state.hw_state);
+ pll->info->funcs->enable(crtc_state, NULL);
pll->on = true;
}
@@ -286,7 +287,7 @@ void intel_enable_global_dpll(const struct intel_crtc_state *crtc_state)
drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
- _intel_enable_shared_dpll(display, pll);
+ _intel_enable_shared_dpll(crtc_state);
out:
mutex_unlock(&display->dpll.lock);
@@ -558,11 +559,12 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
"PCH refclk assertion failure, should be active but is disabled\n");
}
-static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void ibx_pch_dpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
@@ -689,11 +691,12 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
.compare_hw_state = ibx_compare_hw_state,
};
-static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_wrpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
const enum intel_dpll_id id = pll->info->id;
intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
@@ -701,11 +704,11 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
udelay(20);
}
-static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_spll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
intel_de_write(display, SPLL_CTL, hw_state->spll);
intel_de_posting_read(display, SPLL_CTL);
@@ -1284,9 +1287,8 @@ static const struct intel_global_dpll_funcs hsw_ddi_spll_funcs = {
.get_freq = hsw_ddi_spll_get_freq,
};
-static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+static void hsw_ddi_lcpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
}
@@ -1377,11 +1379,12 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
intel_de_posting_read(display, DPLL_CTRL1);
}
-static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1399,11 +1402,12 @@ static void skl_ddi_pll_enable(struct intel_display *display,
drm_err(display->drm, "DPLL %d not locked\n", id);
}
-static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_dpll0_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
}
@@ -2037,11 +2041,12 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.compare_hw_state = skl_compare_hw_state,
};
-static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void bxt_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy = DPIO_PHY0;
enum dpio_channel ch = DPIO_CH0;
@@ -3956,11 +3961,12 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
}
-static void combo_pll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void combo_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
@@ -3980,11 +3986,12 @@ static void combo_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void tbt_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
@@ -4001,11 +4008,12 @@ static void tbt_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void mg_pll_enable(struct intel_display *display,
- struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void mg_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
2025-02-25 8:09 ` [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
@ 2025-03-07 14:06 ` Ville Syrjälä
2025-03-11 8:15 ` Kandpal, Suraj
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2025-03-07 14:06 UTC (permalink / raw)
To: Suraj Kandpal
Cc: intel-xe, intel-gfx, ankit.k.nautiyal, uma.shankar, mika.kahola
On Tue, Feb 25, 2025 at 01:39:23PM +0530, Suraj Kandpal wrote:
> Change the arguments for enable hook in intel_global_dpll_funcs to only
> accept crtc_state. This is because we really don't need those extra
> arguments everything can be derived from crtc_state and we need
> intel_encoder for PLL enablement when DISPLAY_VER() >= 14.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++--------
> 1 file changed, 54 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bd623fdddfdc..c39f7d73a89f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -66,9 +66,8 @@ struct intel_global_dpll_funcs {
> * Hook for enabling the pll, called from intel_enable_global_dpll() if
> * the pll is not already enabled.
> */
> - void (*enable)(struct intel_display *display,
> - struct intel_global_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state);
> + void (*enable)(const struct intel_crtc_state *state,
This feels like the wrong direction. We want the plls to be
independent of crtcs. The crtc_state should only be necessary
to compute a plls's state.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
2025-03-07 14:06 ` Ville Syrjälä
@ 2025-03-11 8:15 ` Kandpal, Suraj
2025-03-11 9:50 ` Kahola, Mika
0 siblings, 1 reply; 30+ messages in thread
From: Kandpal, Suraj @ 2025-03-11 8:15 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Nautiyal, Ankit K, Shankar, Uma, Kahola, Mika
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, March 7, 2025 7:36 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal,
> Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in
> intel_global_dpll_funcs
>
> On Tue, Feb 25, 2025 at 01:39:23PM +0530, Suraj Kandpal wrote:
> > Change the arguments for enable hook in intel_global_dpll_funcs to
> > only accept crtc_state. This is because we really don't need those
> > extra arguments everything can be derived from crtc_state and we need
> > intel_encoder for PLL enablement when DISPLAY_VER() >= 14.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100
> > ++++++++++--------
> > 1 file changed, 54 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index bd623fdddfdc..c39f7d73a89f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -66,9 +66,8 @@ struct intel_global_dpll_funcs {
> > * Hook for enabling the pll, called from intel_enable_global_dpll() if
> > * the pll is not already enabled.
> > */
> > - void (*enable)(struct intel_display *display,
> > - struct intel_global_dpll *pll,
> > - const struct intel_dpll_hw_state *dpll_hw_state);
> > + void (*enable)(const struct intel_crtc_state *state,
>
> This feels like the wrong direction. We want the plls to be independent of crtcs.
> The crtc_state should only be necessary to compute a plls's state.
The problem is how much cx0 really depends on the parameters present in crtc_state which
are not a part of pll_state and wouldn't make sense to track them in pll state since they are not just pll specific.
Mika What do you think ? I feel this will be needed if you need to plug in the newer individual PHY PLL hooks
In the current dpll framework.
Regards,
Suraj Kandpal
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 30+ messages in thread* RE: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
2025-03-11 8:15 ` Kandpal, Suraj
@ 2025-03-11 9:50 ` Kahola, Mika
0 siblings, 0 replies; 30+ messages in thread
From: Kahola, Mika @ 2025-03-11 9:50 UTC (permalink / raw)
To: Kandpal, Suraj, Ville Syrjälä
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Nautiyal, Ankit K, Shankar, Uma
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 11 March 2025 10.16
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal, Ankit
> K <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in
> intel_global_dpll_funcs
>
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Friday, March 7, 2025 7:36 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> > Subject: Re: [PATCH 07/11] drm/i915/dpll: Change argument for enable
> > hook in intel_global_dpll_funcs
> >
> > On Tue, Feb 25, 2025 at 01:39:23PM +0530, Suraj Kandpal wrote:
> > > Change the arguments for enable hook in intel_global_dpll_funcs to
> > > only accept crtc_state. This is because we really don't need those
> > > extra arguments everything can be derived from crtc_state and we
> > > need intel_encoder for PLL enablement when DISPLAY_VER() >= 14.
> > >
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100
> > > ++++++++++--------
> > > 1 file changed, 54 insertions(+), 46 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index bd623fdddfdc..c39f7d73a89f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -66,9 +66,8 @@ struct intel_global_dpll_funcs {
> > > * Hook for enabling the pll, called from intel_enable_global_dpll() if
> > > * the pll is not already enabled.
> > > */
> > > - void (*enable)(struct intel_display *display,
> > > - struct intel_global_dpll *pll,
> > > - const struct intel_dpll_hw_state *dpll_hw_state);
> > > + void (*enable)(const struct intel_crtc_state *state,
> >
> > This feels like the wrong direction. We want the plls to be independent of crtcs.
> > The crtc_state should only be necessary to compute a plls's state.
>
> The problem is how much cx0 really depends on the parameters present in
> crtc_state which are not a part of pll_state and wouldn't make sense to track
> them in pll state since they are not just pll specific.
> Mika What do you think ? I feel this will be needed if you need to plug in the
> newer individual PHY PLL hooks In the current dpll framework.
It seems that we use a lot intel_crtc_has_type() function for checking different types of connectors. We could pass the required parameters separately and extract those parameters from crtc_state. In case of crtc_state changes or is updated we should remember to update these parameters as well. In that sense it feels a bit cumbersome solution. I do agree that as such a large structure intel_crtc_state is not the ideal solution either. I wonder what could be the middleground solution?
>
> Regards,
> Suraj Kandpal
>
> >
> > --
> > Ville Syrjälä
> > Intel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 08/11] drm/i915/drm: Rename disable hook in intel_dpll_global_func
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (6 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 07/11] drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 09/11] drm/i915/dpll: Introduce new hook in intel_global_dpll_func Suraj Kandpal
` (5 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Rename the disable hook to disable_shared_dpll since it will be used
only to disable shared dpll and not individual PLL going forward.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c39f7d73a89f..35fb0f6f5475 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -70,12 +70,12 @@ struct intel_global_dpll_funcs {
struct intel_encoder *encoder);
/*
- * Hook for disabling the pll, called from intel_disable_global_dpll()
+ * Hook for disabling the shared pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
- void (*disable)(struct intel_display *display,
- struct intel_global_dpll *pll);
+ void (*shared_dpll_disable)(struct intel_display *display,
+ struct intel_global_dpll *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
static void _intel_disable_shared_dpll(struct intel_display *display,
struct intel_global_dpll *pll)
{
- pll->info->funcs->disable(display, pll);
+ pll->info->funcs->shared_dpll_disable(display, pll);
pll->on = false;
if (pll->info->power_domain)
@@ -672,7 +672,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_global_dpll_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
- .disable = ibx_pch_dpll_disable,
+ .shared_dpll_disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
};
@@ -1275,14 +1275,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_global_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
- .disable = hsw_ddi_wrpll_disable,
+ .shared_dpll_disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
static const struct intel_global_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
- .disable = hsw_ddi_spll_disable,
+ .shared_dpll_disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
.get_freq = hsw_ddi_spll_get_freq,
};
@@ -1306,7 +1306,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
static const struct intel_global_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
- .disable = hsw_ddi_lcpll_disable,
+ .shared_dpll_disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
.get_freq = hsw_ddi_lcpll_get_freq,
};
@@ -2010,14 +2010,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_global_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
- .disable = skl_ddi_pll_disable,
+ .shared_dpll_disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
static const struct intel_global_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
- .disable = skl_ddi_dpll0_disable,
+ .shared_dpll_disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
@@ -2493,7 +2493,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_global_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
- .disable = bxt_ddi_pll_disable,
+ .shared_dpll_disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
.get_freq = bxt_ddi_pll_get_freq,
};
@@ -4141,21 +4141,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_global_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
- .disable = combo_pll_disable,
+ .shared_dpll_disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
static const struct intel_global_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
- .disable = tbt_pll_disable,
+ .shared_dpll_disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
static const struct intel_global_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
@@ -4203,7 +4203,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
static const struct intel_global_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/11] drm/i915/dpll: Introduce new hook in intel_global_dpll_func
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (7 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 08/11] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 10/11] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
` (4 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Introduce the disable hook to disable individual dpll which is to
be used by DISPLAY_VER() >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 35fb0f6f5475..1014ce4941e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -69,6 +69,12 @@ struct intel_global_dpll_funcs {
void (*enable)(const struct intel_crtc_state *state,
struct intel_encoder *encoder);
+ /*
+ * Hook for disabling the individual pll, used from DISPLAY_VER() >= 14
+ */
+ void (*disable)(struct intel_display *display,
+ struct intel_global_dpll *pll);
+
/*
* Hook for disabling the shared pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 10/11] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (8 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 09/11] drm/i915/dpll: Introduce new hook in intel_global_dpll_func Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 8:09 ` [PATCH 11/11] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
` (3 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Add intel_encoder argument in the get_hw_state hook as encoders
and the data stored within them are essential to read the hw state
starting DISPLAY_VER() >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++++++-------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1014ce4941e7..efb5472b69c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,7 +90,8 @@ struct intel_global_dpll_funcs {
*/
bool (*get_hw_state)(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder);
/*
* Hook for calculating the pll's output frequency based on its passed
@@ -531,7 +532,8 @@ void intel_dpll_swap_state(struct intel_atomic_state *state)
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
@@ -757,7 +759,8 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
@@ -779,7 +782,8 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
@@ -1305,7 +1309,8 @@ static void hsw_ddi_lcpll_disable(struct intel_display *display,
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return true;
}
@@ -1436,7 +1441,8 @@ static void skl_ddi_dpll0_disable(struct intel_display *display,
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -1474,7 +1480,8 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -2172,7 +2179,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -3553,7 +3561,8 @@ static void icl_put_dplls(struct intel_atomic_state *state,
static bool mg_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3620,7 +3629,8 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
static bool dkl_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3753,7 +3763,8 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
static bool combo_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3762,7 +3773,8 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
static bool tbt_pll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
@@ -4520,7 +4532,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state, NULL);
}
static void readout_dpll_hw_state(struct intel_display *display,
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 11/11] drm/i915/dpll: Change arguments for get_freq hook
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (9 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 10/11] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
@ 2025-02-25 8:09 ` Suraj Kandpal
2025-02-25 9:49 ` ✗ Fi.CI.CHECKPATCH: warning for DPLL framework redesign Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 30+ messages in thread
From: Suraj Kandpal @ 2025-02-25 8:09 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, uma.shankar, mika.kahola, Suraj Kandpal
Change the arguments for get_freq hook in intel_global_dpll_get_funcs
to use only intel_crtc_state and intel_encoder since that all we need
and the rest can be derived from the above two.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 105 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +-
3 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index be6d88cb91d1..eb9687ddf4e7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4222,8 +4222,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->global_dpll,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void mtl_ddi_get_config(struct intel_encoder *encoder,
@@ -4335,8 +4334,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
if (icl_ddi_tc_pll_is_tbt(crtc_state->global_dpll))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->global_dpll,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index efb5472b69c5..63f2c6f6c778 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -97,9 +97,8 @@ struct intel_global_dpll_funcs {
* Hook for calculating the pll's output frequency based on its passed
* in state.
*/
- int (*get_freq)(struct intel_display *i915,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ int (*get_freq)(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
};
struct intel_dpll_mgr {
@@ -1008,11 +1007,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_wrpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int refclk;
int n, p, r;
u32 wrpll = hw_state->wrpll;
@@ -1053,7 +1052,6 @@ static int
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1066,8 +1064,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = hsw_ddi_wrpll_get_freq(crtc_state, NULL);
return 0;
}
@@ -1134,10 +1131,11 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
-static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_lcpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
int link_clock = 0;
switch (pll->info->id) {
@@ -1186,11 +1184,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
-static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_spll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int link_clock = 0;
switch (hw_state->spll & SPLL_FREQ_MASK) {
@@ -1979,20 +1977,21 @@ static int skl_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int skl_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_wrpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_lcpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct intel_display *display)
@@ -2378,11 +2377,11 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int bxt_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
struct dpll clock;
clock.m1 = 2;
@@ -2410,7 +2409,6 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
struct dpll clk_div = {};
int ret;
@@ -2420,8 +2418,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = bxt_ddi_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -2775,10 +2772,11 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_tbt_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+
/*
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
@@ -2846,11 +2844,11 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_combo_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
int ref_clock = icl_wrpll_ref_clock(display);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -3219,11 +3217,11 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_mg_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3356,8 +3354,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
/* this is mainly for the fastset check */
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
- crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_combo_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -3455,8 +3452,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
- crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -4504,20 +4500,23 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
- * @display: intel_display device
- * @pll: DPLL for which to calculate the output frequency
- * @dpll_hw_state: DPLL state from which to calculate the output frequency
+ * @crtc_state: crtc_state which contains the DPLL state from which we
+ * calculate frequency
+ * @encoder: Encoder for which the freq is calculated
*
- * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
+ * Return the output frequency corresponding to @pll's passed in
+ * @crtc_state->dpll_hw_state.
*/
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_global_dpll *pll = crtc_state->global_dpll;
+
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_freq(crtc_state, encoder);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ef66aca5da1d..ea244aa612b0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -412,9 +412,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_global_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_global_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DPLL framework redesign
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (10 preceding siblings ...)
2025-02-25 8:09 ` [PATCH 11/11] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
@ 2025-02-25 9:49 ` Patchwork
2025-02-25 9:49 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-02-25 10:09 ` ✗ i915.CI.BAT: failure " Patchwork
13 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2025-02-25 9:49 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
== Series Details ==
Series: DPLL framework redesign
URL : https://patchwork.freedesktop.org/series/145381/
State : warning
== Summary ==
Error: dim checkpatch failed
9523ed1edd93 drm/i915/dpll: Rename intel_shared_dpll_state
778ac8bed0bd drm/i915/dpll: Rename macro for_each_shared_dpll
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#102: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#102: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
total: 0 errors, 0 warnings, 2 checks, 81 lines checked
565b690413ef drm/i915/dpll: Rename intel_shared_dpll_funcs
3ccf267e3b59 drm/i915/dpll: Rename intel_shared_dpll
17e951fd954d drm/i915/dpll: Move away from using shared dpll
073cbc788c76 drm/i915/dpll: Rename crtc_get_shared_dpll
bd86289dc9b2 drm/i915/dpll: Change argument for enable hook in intel_global_dpll_funcs
945d375b88eb drm/i915/drm: Rename disable hook in intel_dpll_global_func
ab2274ce0cf7 drm/i915/dpll: Introduce new hook in intel_global_dpll_func
051b5b21274c drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
14c6ba6bf5dc drm/i915/dpll: Change arguments for get_freq hook
^ permalink raw reply [flat|nested] 30+ messages in thread* ✗ Fi.CI.SPARSE: warning for DPLL framework redesign
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (11 preceding siblings ...)
2025-02-25 9:49 ` ✗ Fi.CI.CHECKPATCH: warning for DPLL framework redesign Patchwork
@ 2025-02-25 9:49 ` Patchwork
2025-02-25 10:09 ` ✗ i915.CI.BAT: failure " Patchwork
13 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2025-02-25 9:49 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
== Series Details ==
Series: DPLL framework redesign
URL : https://patchwork.freedesktop.org/series/145381/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 30+ messages in thread* ✗ i915.CI.BAT: failure for DPLL framework redesign
2025-02-25 8:09 [PATCH 00/11] DPLL framework redesign Suraj Kandpal
` (12 preceding siblings ...)
2025-02-25 9:49 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2025-02-25 10:09 ` Patchwork
13 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2025-02-25 10:09 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
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== Series Details ==
Series: DPLL framework redesign
URL : https://patchwork.freedesktop.org/series/145381/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_16176 -> Patchwork_145381v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_145381v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_145381v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/index.html
Participating hosts (42 -> 43)
------------------------------
Additional (1): bat-arlh-2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_145381v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
Known issues
------------
Here are the changes found in Patchwork_145381v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-arlh-2: NOTRUN -> [SKIP][3] ([i915#11346] / [i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@eof:
- bat-arlh-2: NOTRUN -> [SKIP][4] ([i915#11345] / [i915#11346]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@fbdev@eof.html
* igt@fbdev@info:
- bat-arlh-2: NOTRUN -> [SKIP][5] ([i915#11346] / [i915#1849])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@fbdev@info.html
* igt@gem_lmem_swapping@basic:
- bat-arlh-2: NOTRUN -> [SKIP][6] ([i915#10213] / [i915#11346] / [i915#11671]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@gem_lmem_swapping@basic.html
* igt@gem_mmap@basic:
- bat-arlh-2: NOTRUN -> [SKIP][7] ([i915#11343] / [i915#11346])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-arlh-2: NOTRUN -> [SKIP][8] ([i915#10197] / [i915#10211] / [i915#11346] / [i915#11725])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-arlh-2: NOTRUN -> [SKIP][9] ([i915#11346] / [i915#12637]) +4 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-arlh-2: NOTRUN -> [SKIP][10] ([i915#10206] / [i915#11346] / [i915#11724])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rpm@module-reload:
- bat-adls-6: [PASS][11] -> [FAIL][12] ([i915#13633])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-adls-6/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-adls-6/igt@i915_pm_rpm@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-arlh-2: NOTRUN -> [SKIP][13] ([i915#10209] / [i915#11346] / [i915#11681])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live:
- bat-twl-1: [PASS][14] -> [INCOMPLETE][15] ([i915#12435] / [i915#13761])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-twl-1/igt@i915_selftest@live.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-twl-1/igt@i915_selftest@live.html
- bat-adlp-11: [PASS][16] -> [ABORT][17] ([i915#12435] / [i915#13696])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-adlp-11/igt@i915_selftest@live.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-adlp-11/igt@i915_selftest@live.html
* igt@i915_selftest@live@guc:
- bat-adlp-11: [PASS][18] -> [ABORT][19] ([i915#13696])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-adlp-11/igt@i915_selftest@live@guc.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-adlp-11/igt@i915_selftest@live@guc.html
* igt@i915_selftest@live@ring_submission:
- bat-twl-1: [PASS][20] -> [INCOMPLETE][21] ([i915#13761])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-twl-1/igt@i915_selftest@live@ring_submission.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-twl-1/igt@i915_selftest@live@ring_submission.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-arlh-2: NOTRUN -> [SKIP][22] ([i915#10200] / [i915#11346] / [i915#11666] / [i915#12203])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-arlh-2: NOTRUN -> [SKIP][23] ([i915#10200] / [i915#11346] / [i915#11666]) +8 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: [PASS][24] -> [SKIP][25] ([i915#9197]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_psr@psr-primary-page-flip:
- bat-arlh-2: NOTRUN -> [SKIP][26] ([i915#11346]) +32 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@kms_psr@psr-primary-page-flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-arlh-2: NOTRUN -> [SKIP][27] ([i915#10208] / [i915#11346] / [i915#8809])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-arlh-2: NOTRUN -> [SKIP][28] ([i915#10212] / [i915#11346] / [i915#11726])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-arlh-2: NOTRUN -> [SKIP][29] ([i915#10214] / [i915#11346] / [i915#11726])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-arlh-2: NOTRUN -> [SKIP][30] ([i915#10216] / [i915#11346] / [i915#11723])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-2/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@reset:
- bat-twl-2: [ABORT][31] ([i915#12919] / [i915#13503]) -> [PASS][32] +1 other test pass
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-twl-2/igt@i915_selftest@live@reset.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-twl-2/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [DMESG-FAIL][33] ([i915#12061]) -> [PASS][34] +1 other test pass
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-arls-5: [DMESG-FAIL][35] ([i915#12061]) -> [PASS][36] +1 other test pass
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-arls-5/igt@i915_selftest@live@workarounds.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-arls-5/igt@i915_selftest@live@workarounds.html
* igt@kms_pm_rpm@basic-rte:
- bat-rpls-4: [DMESG-WARN][37] ([i915#13400]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16176/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html
[i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
[i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
[i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
[i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
[i915#11345]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11345
[i915#11346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11346
[i915#11666]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11666
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11723
[i915#11724]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11724
[i915#11725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11725
[i915#11726]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11726
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12203]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12203
[i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
[i915#12637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12637
[i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
[i915#13400]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13400
[i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
[i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
[i915#13696]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13696
[i915#13761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13761
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
Build changes
-------------
* Linux: CI_DRM_16176 -> Patchwork_145381v1
CI-20190529: 20190529
CI_DRM_16176: 32ff724d21f3ec064db2d1a034c47a76d800382f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8247: 8247
Patchwork_145381v1: 32ff724d21f3ec064db2d1a034c47a76d800382f @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_145381v1/index.html
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