Re: [Intel-gfx] [PATCH 08/13] drm/i915/mtl: Readout Thunderbolt HW state

[Radhakrishna Sripada <radhakrishna.sripada@intel.com>]

On Thu, Apr 20, 2023 at 03:40:45PM +0300, Mika Kahola wrote:
> Readout hw state for Thunderbolt.
> 

Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 ++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c     |  5 +++-
>  3 files changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9722d3f1b926..dc0555505e61 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2676,6 +2676,33 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
>  }
>  
> +int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +	u32 clock;
> +	u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
> +
> +	clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
> +
> +	drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
> +	drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
> +	drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
> +
> +	switch (clock) {
> +	case XELPDP_DDI_CLOCK_SELECT_TBT_162:
> +		return 162000;
> +	case XELPDP_DDI_CLOCK_SELECT_TBT_270:
> +		return 270000;
> +	case XELPDP_DDI_CLOCK_SELECT_TBT_540:
> +		return 540000;
> +	case XELPDP_DDI_CLOCK_SELECT_TBT_810:
> +		return 810000;
> +	default:
> +		MISSING_CASE(clock);
> +		return 162000;
> +	}
> +}
> +
>  static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
>  {
>  	switch (clock) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9ea6310b6d79..c1b8f7980f69 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -42,5 +42,5 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
>  void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				       const struct intel_crtc_state *crtc_state,
>  				       u32 level);
> -int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
> +int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>  #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c18226edacac..8f0f858cde31 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3852,8 +3852,11 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  
> -	if (intel_is_c10phy(i915, phy)) {
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> +		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> +	} else if (intel_is_c10phy(i915, phy)) {
>  		intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
>  		intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
>  		crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
> -- 
> 2.34.1
>