Re: [Intel-gfx] [PATCH i-g-t] intel_gpu_top: Fix frequency and rc6 counters

[Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>]

On Tue, May 23, 2023 at 04:24:07PM +0100, Tvrtko Ursulin wrote:
>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
>Need to reset aggregated counters before adding to them otherwise numbers
>will grow endlessly.
>
>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>Fixes: 3dadeff69d4a ("intel_gpu_top: Switch pmu_counter to use aggregated values")
>Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> tools/intel_gpu_top.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
>index 4e49367a70c7..a89f13d46f11 100644
>--- a/tools/intel_gpu_top.c
>+++ b/tools/intel_gpu_top.c
>@@ -710,6 +710,10 @@ static void pmu_sample(struct engines *engines)
> 	engines->ts.prev = engines->ts.cur;
> 	engines->ts.cur = pmu_read_multi(engines->fd, num_val, val);
>
>+	engines->freq_req.val.cur = engines->freq_req.val.prev = 0;
>+	engines->freq_act.val.cur = engines->freq_act.val.prev = 0;
>+	engines->rc6.val.cur = engines->rc6.val.prev = 0;
>+

lgtm,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh
> 	for (i = 0; i < engines->num_gts; i++) {
> 		update_sample(&engines->freq_req_gt[i], val);
> 		engines->freq_req.val.cur += engines->freq_req_gt[i].val.cur;
>-- 
>2.39.2
>