Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Sep 20, 2023 at 12:23:34PM +0300, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > ICL doesn't support FEC with a x1 DP link. Make sure
> > we don't try to enable FEC in such cases.
> 
> The question is, should we rather require x2 link for FEC?
> 
> I suppose x1 link with DSC+FEC is an unlikely scenario with our current
> link bandwidth policy, so probably not a big deal.

I think currently we just smash lane_count to max when using DSC.
So doesn't really matter currently. But something to keep in mind 
if/when we tune the policy.

> 
> BR,
> Jani.
> 
> >
> > Requires a bit of reordering to make sure we've computed lane_count
> > before checking it.
> >
> > Cc: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
> >  1 file changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 55ba6eeaa810..2cde8ac513bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> >  	if (DISPLAY_VER(dev_priv) >= 12)
> >  		return true;
> >  
> > -	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> > +	if (DISPLAY_VER(dev_priv) == 11 &&
> > +	    encoder->port != PORT_A && pipe_config->lane_count != 1)
> >  		return true;
> >  
> >  	return false;
> > @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  		&pipe_config->hw.adjusted_mode;
> >  	int ret;
> >  
> > -	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > -		intel_dp_supports_fec(intel_dp, pipe_config);
> > -
> > -	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > -		return -EINVAL;
> > -
> > -	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > -		return -EINVAL;
> > -
> >  	/*
> >  	 * compute pipe bpp is set to false for DP MST DSC case
> >  	 * and compressed_bpp is calculated same time once
> > @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  		}
> >  	}
> >  
> > +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > +		intel_dp_supports_fec(intel_dp, pipe_config);
> > +
> > +	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > +		return -EINVAL;
> > +
> > +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > +		return -EINVAL;
> > +
> >  	/* Calculate Slice count */
> >  	if (intel_dp_is_edp(intel_dp)) {
> >  		pipe_config->dsc.slice_count =
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel