From: Imre Deak <imre.deak@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Luca Coelho <luciano.coelho@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support
Date: Thu, 5 Oct 2023 16:13:41 +0300 [thread overview]
Message-ID: <ZR62heiKE8MM68Si@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20230913150356.9477-1-ville.syrjala@linux.intel.com>
On Wed, Sep 13, 2023 at 06:03:55PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ICL doesn't support FEC with a x1 DP link. Make sure
> we don't try to enable FEC in such cases.
>
> Requires a bit of reordering to make sure we've computed lane_count
> before checking it.
>
> Cc: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 55ba6eeaa810..2cde8ac513bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> if (DISPLAY_VER(dev_priv) >= 12)
> return true;
>
> - if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> + if (DISPLAY_VER(dev_priv) == 11 &&
> + encoder->port != PORT_A && pipe_config->lane_count != 1)
> return true;
>
> return false;
> @@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> &pipe_config->hw.adjusted_mode;
> int ret;
>
> - pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> - intel_dp_supports_fec(intel_dp, pipe_config);
> -
> - if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> - return -EINVAL;
> -
> - if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> - return -EINVAL;
> -
> /*
> * compute pipe bpp is set to false for DP MST DSC case
> * and compressed_bpp is calculated same time once
> @@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> }
> }
>
> + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> + intel_dp_supports_fec(intel_dp, pipe_config);
> +
> + if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> + return -EINVAL;
> +
> + if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> + return -EINVAL;
> +
> /* Calculate Slice count */
> if (intel_dp_is_edp(intel_dp)) {
> pipe_config->dsc.slice_count =
> --
> 2.41.0
>
prev parent reply other threads:[~2023-10-05 13:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-13 15:03 [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support Ville Syrjala
2023-09-13 15:03 ` [Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST Ville Syrjala
2023-09-20 9:20 ` Jani Nikula
2023-09-20 11:09 ` Ville Syrjälä
2023-10-04 15:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-09-13 23:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Check lane count when determining FEC support Patchwork
2023-09-14 3:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-20 9:23 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2023-09-20 11:14 ` Ville Syrjälä
2023-09-20 12:01 ` Jani Nikula
2023-10-04 22:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Check lane count when determining FEC support (rev2) Patchwork
2023-10-05 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-05 13:13 ` Imre Deak [this message]
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