From: Andi Shyti <andi.shyti@linux.intel.com>
To: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: janusz.krzysztofik@intel.com, matthew.d.roper@intel.com,
intel-gfx@lists.freedesktop.org, chris.p.wilson@linux.intel.com,
nirmoy.das@intel.com
Subject: Re: [Intel-gfx] [PATCH v5 1/4] drm/i915: Add GuC TLB Invalidation pci tags
Date: Wed, 4 Oct 2023 21:03:54 +0200 [thread overview]
Message-ID: <ZR23GiB9UzY4OYLg@ashyti-mobl2.lan> (raw)
In-Reply-To: <20231004183625.1307100-1-jonathan.cavitt@intel.com>
Hi Jonathan,
On Wed, Oct 04, 2023 at 11:36:22AM -0700, Jonathan Cavitt wrote:
> Add pci (device info) tags for if GuC TLB Invalidation is enabled.
> Since GuC based TLB invalidation is only strictly necessary for MTL
> resently, only enable GuC based TLB invalidations for MTL.
>
> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Jani was mentioning that the pci tags is not a proper title.
No need to resend, I think I will merge this series, so that, if
you agree, I can change /pci tags/pci flag/ before pushing.
In any case.
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> 3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2b7a6db4d0d44..1e25cc1e3dba1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -807,4 +807,5 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
> GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>
> +#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index df7c261410f79..c3a5d5efb45d1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -837,6 +837,7 @@ static const struct intel_device_info mtl_info = {
> .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> .require_force_probe = 1,
> + .has_guc_tlb_invalidation = 1,
> MTL_CACHELEVEL,
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 39817490b13fd..ad54db0a22470 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -173,7 +173,8 @@ enum intel_ppgtt_type {
> func(has_coherent_ggtt); \
> func(tuning_thread_rr_after_dep); \
> func(unfenced_needs_alignment); \
> - func(hws_needs_physical);
> + func(hws_needs_physical); \
> + func(has_guc_tlb_invalidation);
>
> struct intel_ip_version {
> u8 ver;
> --
> 2.25.1
next prev parent reply other threads:[~2023-10-04 19:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-04 18:36 [Intel-gfx] [PATCH v5 1/4] drm/i915: Add GuC TLB Invalidation pci tags Jonathan Cavitt
2023-10-04 18:36 ` [Intel-gfx] [PATCH v5 2/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-05 8:54 ` Tvrtko Ursulin
2023-10-05 15:08 ` Cavitt, Jonathan
2023-10-04 18:36 ` [Intel-gfx] [PATCH v5 3/4] drm/i915: No TLB invalidation on wedged or suspended GT Jonathan Cavitt
2023-10-04 18:36 ` [Intel-gfx] [PATCH v5 4/4] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-04 19:03 ` Andi Shyti [this message]
2023-10-04 19:10 ` [Intel-gfx] [PATCH v5 1/4] drm/i915: Add GuC TLB Invalidation pci tags John Harrison
2023-10-04 19:24 ` Andi Shyti
2023-10-04 19:44 ` Matt Roper
2023-10-04 19:47 ` Andi Shyti
2023-10-04 19:09 ` John Harrison
2023-10-05 2:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/4] " Patchwork
2023-10-05 2:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-05 2:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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