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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Nirmoy Das <nirmoy.das@intel.com>,
	dri-devel@lists.freedesktop.org,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3
Date: Wed, 18 Oct 2023 19:43:42 +0200	[thread overview]
Message-ID: <ZTAZTiOKuSvcLR2D@ashyti-mobl2.lan> (raw)
In-Reply-To: <20231017195309.2476088-1-vinay.belgaumkar@intel.com>

Hi Vinay,

On Tue, Oct 17, 2023 at 12:53:09PM -0700, Vinay Belgaumkar wrote:
> This bit does not cause an explicit L3 flush. We already use
> PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.
> 
> v2: Use FLUSH_L3 only pre-MTL since spec will likely remain
> the same going forward.
> 
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

pushed to drm-intel-gt-next.

Thanks,
Andi

      parent reply	other threads:[~2023-10-18 17:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-17 19:53 [Intel-gfx] [PATCH v2] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 Vinay Belgaumkar
2023-10-17 20:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5) Patchwork
2023-10-18  1:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-18 16:43   ` Andi Shyti
2023-10-19  8:14     ` Tvrtko Ursulin
2023-10-19 14:49       ` Andi Shyti
2023-10-19 15:05       ` Nirmoy Das
2023-10-19 15:44         ` Andi Shyti
2023-10-18  4:02 ` [Intel-gfx] [PATCH v2] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 Andi Shyti
2023-10-18 17:43 ` Andi Shyti [this message]

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