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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Jani Nikula <jani.nikula@linux.intel.com>
Subject: Re: [PATCH v5 2/5] drm/i915/psr: Improve fast and IO wake lines calculation
Date: Fri, 8 Mar 2024 16:37:37 +0200	[thread overview]
Message-ID: <ZesiscGvnx_a9zMK@intel.com> (raw)
In-Reply-To: <20240308110039.3900838-3-jouni.hogander@intel.com>

On Fri, Mar 08, 2024 at 01:00:36PM +0200, Jouni Högander wrote:
> Current fast and IO wake lines calculation is assuming fast wake sync
> length is 18 pulses. Let's improve this by checking actual length.
> 
> Add getter for IO buffer wake time and return 10 us there which was assumed
> with static 42 us IO wake time. Upcoming patches will extent this for
> different display versions.
> 
> Bspec: 65450
> 
> v3:
>   - s/get_io_buffer_wake_time/io_buffer_wake_time/ and use it directly in
>     calculation.
> v2:
>   - rename io_wake_time in if block to io_buffer_wake_time
>   - rename get_io_wake_time to get_io_buffer_wake_time
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6927785fd6ff..7736bdcad82d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1150,6 +1150,11 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> +static int io_buffer_wake_time(void)
> +{
> +	return 10;
> +}
> +
>  static bool _compute_alpm_params(struct intel_dp *intel_dp,
>  				 struct intel_crtc_state *crtc_state)
>  {
> @@ -1158,12 +1163,15 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp,
>  	u8 max_wake_lines;
>  
>  	if (DISPLAY_VER(i915) >= 12) {
> -		io_wake_time = 42;
> -		/*
> -		 * According to Bspec it's 42us, but based on testing
> -		 * it is not enough -> use 45 us.
> -		 */
> -		fast_wake_time = 45;
> +		int tfw_exit_latency = 20; /* eDP spec */
> +		int phy_wake = 4;	   /* eDP spec */
> +		int preamble = 8;	   /* eDP spec */
> +		int precharge = intel_dp_aux_fw_sync_len() - preamble;
> +
> +		io_wake_time = max(precharge, io_buffer_wake_time()) + preamble +
> +			phy_wake + tfw_exit_latency;
> +		fast_wake_time = precharge + preamble + phy_wake +
> +			tfw_exit_latency;
>  
>  		/* TODO: Check how we can use ALPM_CTL fast wake extended field */
>  		max_wake_lines = 12;
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2024-03-08 14:37 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-08 11:00 [PATCH v5 0/5] IO and fast wake lines calculation and increase fw sync length Jouni Högander
2024-03-08 11:00 ` [PATCH v5 1/5] drm/i915/display: Make intel_dp_aux_fw_sync_len available for PSR code Jouni Högander
2024-03-08 14:37   ` Ville Syrjälä
2024-03-08 11:00 ` [PATCH v5 2/5] drm/i915/psr: Improve fast and IO wake lines calculation Jouni Högander
2024-03-08 14:37   ` Ville Syrjälä [this message]
2024-03-08 11:00 ` [PATCH v5 3/5] drm/i915/psr: Calculate IO wake and fast wake lines for DISPLAY_VER < 12 Jouni Högander
2024-03-08 14:38   ` Ville Syrjälä
2024-03-08 11:00 ` [PATCH v5 4/5] drm/i915/psr: Add IO buffer wake times for LunarLake and beyond Jouni Högander
2024-03-08 14:39   ` Ville Syrjälä
2024-03-08 14:56     ` Ville Syrjälä
2024-03-12 11:30       ` Hogander, Jouni
2024-03-08 11:00 ` [PATCH v5 5/5] drm/i915/display: Increase number of fast wake precharge pulses Jouni Högander
2024-03-12 16:44   ` Ville Syrjälä
2024-03-13  6:20     ` Hogander, Jouni
2024-03-08 14:10 ` ✗ Fi.CI.SPARSE: warning for IO and fast wake lines calculation and increase fw sync length (rev5) Patchwork
2024-03-08 14:29 ` ✓ Fi.CI.BAT: success " Patchwork
2024-03-09  4:17 ` ✓ Fi.CI.IGT: " Patchwork

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