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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()
Date: Mon, 8 Apr 2024 20:39:08 +0300	[thread overview]
Message-ID: <ZhQrvAjDK_H-9Af4@intel.com> (raw)
In-Reply-To: <ZhQpO3lJz9TB7c-4@intel.com>

On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
> > The rawclk initialization is a bit out of place in
> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> > bit of refactoring on intel_read_rawclk().
> 
> rawclk is used outside of display.

The correct solution would likely be to extract a 
i9xx_fsb_freq(), and use that to populate both rawclk_freq
and fsb_freq (and switch over to fsb_freq in the
non-display code).

> 
> > 
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
> >  drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
> >  drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
> >  3 files changed, 11 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index d61aa5b7cbdb..64a1cf4ed45c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -3210,6 +3210,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
> >  	return intel_atomic_lock_global_state(&cdclk_state->base);
> >  }
> >  
> > +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> > +
> >  int intel_cdclk_init(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_cdclk_state *cdclk_state;
> > @@ -3221,6 +3223,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
> >  	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
> >  				     &cdclk_state->base, &intel_cdclk_funcs);
> >  
> > +	intel_rawclk_init(dev_priv);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -3578,16 +3582,13 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > -/**
> > - * intel_read_rawclk - Determine the current RAWCLK frequency
> > - * @dev_priv: i915 device
> > - *
> > - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> > - * frequency clock so this needs to done only once.
> > +/*
> > + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
> > + * this needs to done only once.
> >   */
> > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> > +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
> >  {
> > -	u32 freq;
> > +	u32 freq = 0;
> >  
> >  	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
> >  		/*
> > @@ -3606,11 +3607,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> >  		freq = vlv_hrawclk(dev_priv);
> >  	else if (DISPLAY_VER(dev_priv) >= 3)
> >  		freq = i9xx_hrawclk(dev_priv);
> > -	else
> > -		/* no rawclk on other platforms, or no need to know it */
> > -		return 0;
> >  
> > -	return freq;
> > +	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> > +	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
> >  }
> >  
> >  static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > index cfdcdec07a4d..a3f950d5a366 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> >  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> >  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> >  bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> >  			       const struct intel_cdclk_config *b);
> >  int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index a0a43ea07f11..48f0957392f9 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> >  			 "Disabling ppGTT for VT-d support\n");
> >  		runtime->ppgtt_type = INTEL_PPGTT_NONE;
> >  	}
> > -
> > -	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> > -	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> > -
> >  }
> >  
> >  /*
> > -- 
> > 2.39.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2024-04-08 17:39 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-08 17:23 [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init() Jani Nikula
2024-04-08 17:23 ` [PATCH 2/2] drm/i915: move rawclk from runtime to display runtime info Jani Nikula
2024-04-08 17:28 ` [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init() Ville Syrjälä
2024-04-08 17:39   ` Ville Syrjälä [this message]
2024-05-27 18:16     ` Jani Nikula
2024-05-27 18:25       ` Jani Nikula
2024-04-08 22:02 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork
2024-04-08 22:15 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-05-27 18:36 ` ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: move rawclk init to intel_cdclk_init() (rev2) Patchwork

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