* [PATCH 0/6] drm/i915: i915_reg.h cleanups
@ 2024-04-12 14:52 Jani Nikula
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
Continue the cleanup of i915_reg.h. Remove 1k lines from it this time
around.
Jani Nikula (6):
drm/i915/audio: move LPE audio regs to intel_audio_regs.h
drm/i915/color: move palette registers to intel_color_regs.h
drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
drm/i915/display: split out bxt_phy_regs.h from i915_reg.h
drivers/gpu/drm/i915/display/bxt_phy_regs.h | 292 +++++
.../gpu/drm/i915/display/intel_audio_regs.h | 16 +
.../gpu/drm/i915/display/intel_color_regs.h | 30 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
.../i915/display/intel_display_power_well.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 152 +++
.../gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 349 +++++
drivers/gpu/drm/i915/display/vlv_dpio_regs.h | 352 +++++
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1154 -----------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 3 +
24 files changed, 1217 insertions(+), 1156 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/bxt_phy_regs.h
create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_regs.h
--
2.39.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-12 15:15 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
` (7 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
There are too few registers to warrant a dedicated file for LPE audio
regs, but the audio reg file is better than i915_reg.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio_regs.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 16 ----------------
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index 616e7b1275c4..7a6d919481fc 100644
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -148,4 +148,20 @@
#define HBLANK_START_COUNT_96 4
#define HBLANK_START_COUNT_128 5
+/* LPE Audio */
+#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
+#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
+
+#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62f38)
+#define VLV_CHICKEN_BIT_DBG_ENABLE REG_BIT(0)
+
+#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62f20)
+#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62f30)
+#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62f34)
+#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
+ _VLV_AUD_PORT_EN_B_DBG, \
+ _VLV_AUD_PORT_EN_C_DBG, \
+ _VLV_AUD_PORT_EN_D_DBG)
+#define VLV_AMP_MUTE REG_BIT(1)
+
#endif /* __INTEL_AUDIO_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 5863763de530..93e6cac9a4ed 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -72,7 +72,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
-#include "i915_reg.h"
+#include "intel_audio_regs.h"
#include "intel_de.h"
#include "intel_lpe_audio.h"
#include "intel_pci_config.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f34efcd7d6c..c689bc7e2867 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1228,22 +1228,6 @@
#define I915_ASLE_INTERRUPT (1 << 0)
#define I915_BSD_USER_INTERRUPT (1 << 25)
-#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
-#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
-
-/* DisplayPort Audio w/ LPE */
-#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
-#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
-
-#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
-#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
-#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
-#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
- _VLV_AUD_PORT_EN_B_DBG, \
- _VLV_AUD_PORT_EN_C_DBG, \
- _VLV_AUD_PORT_EN_D_DBG)
-#define VLV_AMP_MUTE (1 << 1)
-
#define GEN6_BSD_RNCID _MMIO(0x12198)
#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-12 15:19 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
For some reason the paletter registers were missed when adding
intel_color_regs.h. Finish the job.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_color_regs.h | 30 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 30 -------------------
2 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index 9f4ae58f3e7e..969745821172 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -8,6 +8,36 @@
#include "intel_display_reg_defs.h"
+/*
+ * Palette regs
+ */
+#define _PALETTE_A 0xa000
+#define _PALETTE_B 0xa800
+#define _CHV_PALETTE_C 0xc000
+/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
+#define PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode ldw */
+#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
+#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
+#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
+/* pre-i965 10bit interpolated mode udw */
+#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
+#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
+#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
+#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
+#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
+#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
+#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
+#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
+#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
+ _PICK_EVEN_2RANGES(pipe, 2, \
+ _PALETTE_A, _PALETTE_B, \
+ _CHV_PALETTE_C, _CHV_PALETTE_C) + \
+ (i) * 4)
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c689bc7e2867..b74965383a56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1700,36 +1700,6 @@
#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
-/*
- * Palette regs
- */
-#define _PALETTE_A 0xa000
-#define _PALETTE_B 0xa800
-#define _CHV_PALETTE_C 0xc000
-/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
-#define PALETTE_RED_MASK REG_GENMASK(23, 16)
-#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
-#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode ldw */
-#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
-#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
-#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
-/* pre-i965 10bit interpolated mode udw */
-#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
-#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
-#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
-#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
-#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
-#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
-#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
-#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
-#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
-#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
- _PICK_EVEN_2RANGES(pipe, 2, \
- _PALETTE_A, _PALETTE_B, \
- _CHV_PALETTE_C, _CHV_PALETTE_C) + \
- (i) * 4)
-
#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
#define BXT_RP_STATE_CAP _MMIO(0x138170)
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
2024-04-12 14:52 ` [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-12 15:14 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
Clean up i915_reg.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 152 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 142 ----------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
6 files changed, 157 insertions(+), 142 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7c4d2b2bf20b..151dcd0c45b6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -54,6 +54,7 @@
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
+#include "intel_fbc_regs.h"
#include "intel_frontbuffer.h"
#define for_each_fbc_id(__dev_priv, __fbc_id) \
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
new file mode 100644
index 000000000000..d454d599a22c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __INTEL_FBC_REGS__
+#define __INTEL_FBC_REGS__
+
+#include "intel_display_reg_defs.h"
+
+/*
+ * Framebuffer compression (915+ only)
+ */
+
+#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
+#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
+#define FBC_CONTROL _MMIO(0x3208)
+#define FBC_CTL_EN REG_BIT(31)
+#define FBC_CTL_PERIODIC REG_BIT(30)
+#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
+#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
+#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
+#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
+#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
+#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
+#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
+#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
+#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
+#define FBC_COMMAND _MMIO(0x320c)
+#define FBC_CMD_COMPRESS REG_BIT(0)
+#define FBC_STATUS _MMIO(0x3210)
+#define FBC_STAT_COMPRESSING REG_BIT(31)
+#define FBC_STAT_COMPRESSED REG_BIT(30)
+#define FBC_STAT_MODIFIED REG_BIT(29)
+#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
+#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
+#define FBC_CTL_FENCE_DBL REG_BIT(4)
+#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
+#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
+#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
+#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
+#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
+#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
+#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
+#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
+#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
+#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
+#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
+#define FBC_MOD_NUM_VALID REG_BIT(0)
+#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
+#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
+#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
+#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
+#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
+#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
+
+#define FBC_LL_SIZE (1536)
+
+/* Framebuffer compression for GM45+ */
+#define DPFC_CB_BASE _MMIO(0x3200)
+#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+#define DPFC_CONTROL _MMIO(0x3208)
+#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
+#define DPFC_CTL_EN REG_BIT(31)
+#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
+#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
+#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
+#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
+#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
+#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
+#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
+#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
+#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
+#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
+#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
+#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
+#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
+#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
+#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
+#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
+#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
+#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
+#define DPFC_RECOMP_CTL _MMIO(0x320c)
+#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
+#define DPFC_RECOMP_STALL_EN REG_BIT(27)
+#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
+#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
+#define DPFC_STATUS _MMIO(0x3210)
+#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
+#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
+#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
+#define DPFC_STATUS2 _MMIO(0x3214)
+#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
+#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
+#define DPFC_FENCE_YOFF _MMIO(0x3218)
+#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+#define DPFC_CHICKEN _MMIO(0x3224)
+#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
+#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
+#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
+#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
+#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
+#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
+
+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
+#define FBC_STRIDE_OVERRIDE REG_BIT(15)
+#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
+#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
+
+#define ILK_FBC_RT_BASE _MMIO(0x2128)
+#define ILK_FBC_RT_VALID REG_BIT(0)
+#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
+
+#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
+#define ILK_FBCQ_DIS REG_BIT(22)
+#define ILK_PABSTRETCH_DIS REG_BIT(21)
+#define ILK_SABSTRETCH_DIS REG_BIT(20)
+#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
+#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
+#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
+#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
+#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
+#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
+#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
+#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
+#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
+#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
+
+
+/*
+ * Framebuffer compression for Sandybridge
+ *
+ * The following two registers are of type GTTMMADR
+ */
+#define SNB_DPFC_CTL_SA _MMIO(0x100100)
+#define SNB_DPFC_FENCE_EN REG_BIT(29)
+#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
+#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
+#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
+
+/* Framebuffer compression for Ivybridge */
+#define IVB_FBC_RT_BASE _MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
+
+#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
+#define FBC_REND_NUKE REG_BIT(2)
+#define FBC_REND_CACHE_CLEAN REG_BIT(1)
+
+#define CHICKEN_MISC_4 _MMIO(0x4208c)
+#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
+#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
+#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
+
+#endif /* __INTEL_FBC_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 68b6aa11bcf7..40e79f0dc257 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -17,6 +17,8 @@
#include "intel_ring.h"
#include "intel_workarounds.h"
+#include "display/intel_fbc_regs.h"
+
/**
* DOC: Hardware workarounds
*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74965383a56..8c44a21977a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1248,148 +1248,11 @@
#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
-/*
- * Framebuffer compression (915+ only)
- */
-
-#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
-#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
-#define FBC_CONTROL _MMIO(0x3208)
-#define FBC_CTL_EN REG_BIT(31)
-#define FBC_CTL_PERIODIC REG_BIT(30)
-#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
-#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
-#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
-#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
-#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
-#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
-#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
-#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
-#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
-#define FBC_COMMAND _MMIO(0x320c)
-#define FBC_CMD_COMPRESS REG_BIT(0)
-#define FBC_STATUS _MMIO(0x3210)
-#define FBC_STAT_COMPRESSING REG_BIT(31)
-#define FBC_STAT_COMPRESSED REG_BIT(30)
-#define FBC_STAT_MODIFIED REG_BIT(29)
-#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
-#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
-#define FBC_CTL_FENCE_DBL REG_BIT(4)
-#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
-#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
-#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
-#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
-#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
-#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
-#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
-#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
-#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
-#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
-#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
-#define FBC_MOD_NUM_VALID REG_BIT(0)
-#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
-#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
-#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
-#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
-#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
-#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
-
-#define FBC_LL_SIZE (1536)
-
-/* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE _MMIO(0x3200)
-#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
-#define DPFC_CONTROL _MMIO(0x3208)
-#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
-#define DPFC_CTL_EN REG_BIT(31)
-#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
-#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
-#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
-#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
-#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
-#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
-#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
-#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
-#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
-#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
-#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
-#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
-#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
-#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
-#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
-#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
-#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
-#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
-#define DPFC_RECOMP_CTL _MMIO(0x320c)
-#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
-#define DPFC_RECOMP_STALL_EN REG_BIT(27)
-#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
-#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
-#define DPFC_STATUS _MMIO(0x3210)
-#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
-#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
-#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
-#define DPFC_STATUS2 _MMIO(0x3214)
-#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
-#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
-#define DPFC_FENCE_YOFF _MMIO(0x3218)
-#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
-#define DPFC_CHICKEN _MMIO(0x3224)
-#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
-#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
-#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
-#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
-#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
-#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
-
-#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
-#define FBC_STRIDE_OVERRIDE REG_BIT(15)
-#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
-#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
-
-#define ILK_FBC_RT_BASE _MMIO(0x2128)
-#define ILK_FBC_RT_VALID REG_BIT(0)
-#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
-
-#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
-#define ILK_FBCQ_DIS REG_BIT(22)
-#define ILK_PABSTRETCH_DIS REG_BIT(21)
-#define ILK_SABSTRETCH_DIS REG_BIT(20)
-#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
-#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
-#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
-#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
-#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
-#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
-#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
-#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
-#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
-#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
-
-
-/*
- * Framebuffer compression for Sandybridge
- *
- * The following two registers are of type GTTMMADR
- */
-#define SNB_DPFC_CTL_SA _MMIO(0x100100)
-#define SNB_DPFC_FENCE_EN REG_BIT(29)
-#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
-#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
-#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
-
-/* Framebuffer compression for Ivybridge */
-#define IVB_FBC_RT_BASE _MMIO(0x7020)
-#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE REG_BIT(31)
#define IPS_FALSE_COLOR REG_BIT(4)
-#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
-#define FBC_REND_NUKE REG_BIT(2)
-#define FBC_REND_CACHE_CLEAN REG_BIT(1)
-
/*
* Clock control & power management
*/
@@ -4526,11 +4389,6 @@
#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
-#define CHICKEN_MISC_4 _MMIO(0x4208c)
-#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
-#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
-#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
-
#define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7e70ee4fbd84..1dc5281b2ade 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -28,6 +28,7 @@
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "display/intel_display_trace.h"
+#include "display/intel_fbc_regs.h"
#include "display/skl_watermark.h"
#include "gt/intel_engine_regs.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 87ecc5104fd9..70d661bffcc2 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -10,6 +10,7 @@
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
#include "display/intel_dpio_phy.h"
+#include "display/intel_fbc_regs.h"
#include "display/intel_fdi_regs.h"
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (2 preceding siblings ...)
2024-04-12 14:52 ` [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-12 15:22 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h " Jani Nikula
` (4 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
Clean up i915_reg.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
.../gpu/drm/i915/display/intel_sprite_regs.h | 349 ++++++++++++++++++
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 340 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
8 files changed, 358 insertions(+), 341 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d7b440c8caef..36a253a19c74 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -47,6 +47,7 @@
#include "intel_fb.h"
#include "intel_frontbuffer.h"
#include "intel_sprite.h"
+#include "intel_sprite_regs.h"
static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
{
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
new file mode 100644
index 000000000000..caf4b58e9a27
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __INTEL_SPRITE_REGS__
+#define __INTEL_SPRITE_REGS__
+
+#include "intel_display_reg_defs.h"
+
+/* Sprite A control */
+#define _DVSACNTR 0x72180
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILED REG_BIT(10)
+#define DVS_DEST_KEY REG_BIT(2)
+#define _DVSALINOFF 0x72184
+#define _DVSASTRIDE 0x72188
+#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
+#define _DVSASIZE 0x72190
+#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
+#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
+#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
+#define _DVSAKEYVAL 0x72194
+#define _DVSAKEYMSK 0x72198
+#define _DVSASURF 0x7219c
+#define DVS_ADDR_MASK REG_GENMASK(31, 12)
+#define _DVSAKEYMAXVAL 0x721a0
+#define _DVSATILEOFF 0x721a4
+#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
+#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
+#define _DVSASURFLIVE 0x721ac
+#define _DVSAGAMC_G4X 0x721e0 /* g4x */
+#define _DVSASCALE 0x72204
+#define DVS_SCALE_ENABLE REG_BIT(31)
+#define DVS_FILTER_MASK REG_GENMASK(30, 29)
+#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
+#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
+#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
+#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
+#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
+#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
+#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
+
+#define _DVSBCNTR 0x73180
+#define _DVSBLINOFF 0x73184
+#define _DVSBSTRIDE 0x73188
+#define _DVSBPOS 0x7318c
+#define _DVSBSIZE 0x73190
+#define _DVSBKEYVAL 0x73194
+#define _DVSBKEYMSK 0x73198
+#define _DVSBSURF 0x7319c
+#define _DVSBKEYMAXVAL 0x731a0
+#define _DVSBTILEOFF 0x731a4
+#define _DVSBSURFLIVE 0x731ac
+#define _DVSBGAMC_G4X 0x731e0 /* g4x */
+#define _DVSBSCALE 0x73204
+#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
+#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
+
+#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
+#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
+#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
+#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
+#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
+#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
+
+#define _SPRA_CTL 0x70280
+#define SPRITE_ENABLE REG_BIT(31)
+#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
+#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
+#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
+#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
+#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
+#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
+#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
+#define SPRITE_SOURCE_KEY REG_BIT(22)
+#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
+#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
+#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
+#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
+#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
+#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
+#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
+#define SPRITE_ROTATE_180 REG_BIT(15)
+#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define SPRITE_TILED REG_BIT(10)
+#define SPRITE_DEST_KEY REG_BIT(2)
+#define _SPRA_LINOFF 0x70284
+#define _SPRA_STRIDE 0x70288
+#define _SPRA_POS 0x7028c
+#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
+#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
+#define _SPRA_SIZE 0x70290
+#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
+#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
+#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
+#define _SPRA_KEYVAL 0x70294
+#define _SPRA_KEYMSK 0x70298
+#define _SPRA_SURF 0x7029c
+#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
+#define _SPRA_KEYMAX 0x702a0
+#define _SPRA_TILEOFF 0x702a4
+#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
+#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
+#define _SPRA_OFFSET 0x702a4
+#define _SPRA_SURFLIVE 0x702ac
+#define _SPRA_SCALE 0x70304
+#define SPRITE_SCALE_ENABLE REG_BIT(31)
+#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
+#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
+#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
+#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
+#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
+#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
+#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
+#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
+#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
+#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
+#define _SPRA_GAMC 0x70400
+#define _SPRA_GAMC16 0x70440
+#define _SPRA_GAMC17 0x7044c
+
+#define _SPRB_CTL 0x71280
+#define _SPRB_LINOFF 0x71284
+#define _SPRB_STRIDE 0x71288
+#define _SPRB_POS 0x7128c
+#define _SPRB_SIZE 0x71290
+#define _SPRB_KEYVAL 0x71294
+#define _SPRB_KEYMSK 0x71298
+#define _SPRB_SURF 0x7129c
+#define _SPRB_KEYMAX 0x712a0
+#define _SPRB_TILEOFF 0x712a4
+#define _SPRB_OFFSET 0x712a4
+#define _SPRB_SURFLIVE 0x712ac
+#define _SPRB_SCALE 0x71304
+#define _SPRB_GAMC 0x71400
+#define _SPRB_GAMC16 0x71440
+#define _SPRB_GAMC17 0x7144c
+
+#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
+#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
+#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
+#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
+#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
+#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
+#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
+#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
+#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
+#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
+#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
+#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
+#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
+#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
+#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
+#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+
+#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
+#define SP_ENABLE REG_BIT(31)
+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
+#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
+#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
+#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
+#define SP_SOURCE_KEY REG_BIT(22)
+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
+#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
+#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
+#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
+#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
+#define SP_ROTATE_180 REG_BIT(15)
+#define SP_TILED REG_BIT(10)
+#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
+#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
+#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
+#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
+#define SP_POS_Y_MASK REG_GENMASK(31, 16)
+#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
+#define SP_POS_X_MASK REG_GENMASK(15, 0)
+#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
+#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
+#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
+#define SP_WIDTH_MASK REG_GENMASK(15, 0)
+#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
+#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
+#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
+#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
+#define SP_ADDR_MASK REG_GENMASK(31, 12)
+#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
+#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
+#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
+#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
+#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
+#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
+#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
+#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
+#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
+#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
+#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
+#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
+#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
+#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
+#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
+#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
+#define SP_SH_COS_MASK REG_GENMASK(9, 0)
+#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
+#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
+
+#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
+#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
+#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
+#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
+#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
+#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
+#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
+#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
+#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
+#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
+#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
+#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
+#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
+#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
+
+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
+#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
+
+#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
+#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
+#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
+#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
+#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
+#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
+#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
+#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
+#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
+#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
+
+/*
+ * CHV pipe B sprite CSC
+ *
+ * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
+ * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
+ * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
+ */
+#define _MMIO_CHV_SPCSC(plane_id, reg) \
+ _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
+
+#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
+#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
+#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
+#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
+#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
+#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
+
+#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
+#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
+#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
+#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
+#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
+#define SPCSC_C1_MASK REG_GENMASK(30, 16)
+#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
+#define SPCSC_C0_MASK REG_GENMASK(14, 0)
+#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
+
+#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
+#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
+#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
+#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
+#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
+#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
+#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
+
+#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
+#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
+#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
+#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
+#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
+#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
+#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
+
+#endif /* __INTEL_SPRITE_REGS__ */
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index d4a3f3e093b0..4be8cb65fb7e 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -50,6 +50,7 @@
#include "trace.h"
#include "display/intel_display.h"
+#include "display/intel_sprite_regs.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_context.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index e0c5dfb788eb..498698482d59 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -38,6 +38,7 @@
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
+#include "display/intel_sprite_regs.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 313efdabee57..4140da68aabb 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -34,11 +34,14 @@
*/
#include <uapi/drm/drm_fourcc.h>
-#include "i915_drv.h"
+
#include "gvt.h"
+#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/intel_sprite_regs.h"
+
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
int drm_format; /* Pixel format in DRM definition */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index efcb00472be2..7d749995c7a7 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -49,6 +49,7 @@
#include "display/intel_fdi_regs.h"
#include "display/intel_pps_regs.h"
#include "display/intel_psr_regs.h"
+#include "display/intel_sprite_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c44a21977a4..bb63c7214e12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3070,346 +3070,6 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
-/* Sprite A control */
-#define _DVSACNTR 0x72180
-#define DVS_ENABLE REG_BIT(31)
-#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
-#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
-#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
-#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
-#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
-#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
-#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
-#define DVS_SOURCE_KEY REG_BIT(22)
-#define DVS_RGB_ORDER_XBGR REG_BIT(20)
-#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
-#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
-#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
-#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
-#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
-#define DVS_ROTATE_180 REG_BIT(15)
-#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define DVS_TILED REG_BIT(10)
-#define DVS_DEST_KEY REG_BIT(2)
-#define _DVSALINOFF 0x72184
-#define _DVSASTRIDE 0x72188
-#define _DVSAPOS 0x7218c
-#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
-#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
-#define DVS_POS_X_MASK REG_GENMASK(15, 0)
-#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
-#define _DVSASIZE 0x72190
-#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
-#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
-#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
-#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
-#define _DVSAKEYVAL 0x72194
-#define _DVSAKEYMSK 0x72198
-#define _DVSASURF 0x7219c
-#define DVS_ADDR_MASK REG_GENMASK(31, 12)
-#define _DVSAKEYMAXVAL 0x721a0
-#define _DVSATILEOFF 0x721a4
-#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
-#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
-#define _DVSASURFLIVE 0x721ac
-#define _DVSAGAMC_G4X 0x721e0 /* g4x */
-#define _DVSASCALE 0x72204
-#define DVS_SCALE_ENABLE REG_BIT(31)
-#define DVS_FILTER_MASK REG_GENMASK(30, 29)
-#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
-#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
-#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
-#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
-#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
-#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
-#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
-#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
-#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
-#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
-#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
-
-#define _DVSBCNTR 0x73180
-#define _DVSBLINOFF 0x73184
-#define _DVSBSTRIDE 0x73188
-#define _DVSBPOS 0x7318c
-#define _DVSBSIZE 0x73190
-#define _DVSBKEYVAL 0x73194
-#define _DVSBKEYMSK 0x73198
-#define _DVSBSURF 0x7319c
-#define _DVSBKEYMAXVAL 0x731a0
-#define _DVSBTILEOFF 0x731a4
-#define _DVSBSURFLIVE 0x731ac
-#define _DVSBGAMC_G4X 0x731e0 /* g4x */
-#define _DVSBSCALE 0x73204
-#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
-#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
-
-#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
-#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
-#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
-#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
-#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
-#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
-#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
-#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
-#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
-#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
-#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
-#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
-#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
-#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
-
-#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE REG_BIT(31)
-#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
-#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
-#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
-#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
-#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
-#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
-#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
-#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
-#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
-#define SPRITE_SOURCE_KEY REG_BIT(22)
-#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
-#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
-#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
-#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
-#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
-#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
-#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
-#define SPRITE_ROTATE_180 REG_BIT(15)
-#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
-#define SPRITE_TILED REG_BIT(10)
-#define SPRITE_DEST_KEY REG_BIT(2)
-#define _SPRA_LINOFF 0x70284
-#define _SPRA_STRIDE 0x70288
-#define _SPRA_POS 0x7028c
-#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
-#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
-#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
-#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
-#define _SPRA_SIZE 0x70290
-#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
-#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
-#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
-#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
-#define _SPRA_KEYVAL 0x70294
-#define _SPRA_KEYMSK 0x70298
-#define _SPRA_SURF 0x7029c
-#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
-#define _SPRA_KEYMAX 0x702a0
-#define _SPRA_TILEOFF 0x702a4
-#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
-#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
-#define _SPRA_OFFSET 0x702a4
-#define _SPRA_SURFLIVE 0x702ac
-#define _SPRA_SCALE 0x70304
-#define SPRITE_SCALE_ENABLE REG_BIT(31)
-#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
-#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
-#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
-#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
-#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
-#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
-#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
-#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
-#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
-#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
-#define _SPRA_GAMC 0x70400
-#define _SPRA_GAMC16 0x70440
-#define _SPRA_GAMC17 0x7044c
-
-#define _SPRB_CTL 0x71280
-#define _SPRB_LINOFF 0x71284
-#define _SPRB_STRIDE 0x71288
-#define _SPRB_POS 0x7128c
-#define _SPRB_SIZE 0x71290
-#define _SPRB_KEYVAL 0x71294
-#define _SPRB_KEYMSK 0x71298
-#define _SPRB_SURF 0x7129c
-#define _SPRB_KEYMAX 0x712a0
-#define _SPRB_TILEOFF 0x712a4
-#define _SPRB_OFFSET 0x712a4
-#define _SPRB_SURFLIVE 0x712ac
-#define _SPRB_SCALE 0x71304
-#define _SPRB_GAMC 0x71400
-#define _SPRB_GAMC16 0x71440
-#define _SPRB_GAMC17 0x7144c
-
-#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
-#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
-#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
-#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
-#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
-#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
-#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
-#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
-#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
-#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
-#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
-#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
-#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
-#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
-#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
-#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
-
-#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
-#define SP_ENABLE REG_BIT(31)
-#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define SP_FORMAT_MASK REG_GENMASK(29, 26)
-#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
-#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
-#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
-#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
-#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
-#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
-#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
-#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
-#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
-#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
-#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
-#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
-#define SP_SOURCE_KEY REG_BIT(22)
-#define SP_YUV_FORMAT_BT709 REG_BIT(18)
-#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
-#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
-#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
-#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
-#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
-#define SP_ROTATE_180 REG_BIT(15)
-#define SP_TILED REG_BIT(10)
-#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
-#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
-#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
-#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
-#define SP_POS_Y_MASK REG_GENMASK(31, 16)
-#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
-#define SP_POS_X_MASK REG_GENMASK(15, 0)
-#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
-#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
-#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
-#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
-#define SP_WIDTH_MASK REG_GENMASK(15, 0)
-#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
-#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
-#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
-#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
-#define SP_ADDR_MASK REG_GENMASK(31, 12)
-#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
-#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
-#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
-#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
-#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
-#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
-#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
-#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
-#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
-#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
-#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
-#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
-#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
-#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
-#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
-#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
-#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
-#define SP_SH_COS_MASK REG_GENMASK(9, 0)
-#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
-#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
-
-#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
-#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
-#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
-#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
-#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
-#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
-#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
-#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
-#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
-#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
-#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
-#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
-#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
-#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
-#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
-
-#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
-#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
-
-#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
-#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
-#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
-#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
-
-/*
- * CHV pipe B sprite CSC
- *
- * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
- * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
- * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
- */
-#define _MMIO_CHV_SPCSC(plane_id, reg) \
- _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
-
-#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
-#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
-#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
-#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
-#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
-#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
-#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
-
-#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
-#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
-#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
-#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
-#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
-#define SPCSC_C1_MASK REG_GENMASK(30, 16)
-#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
-#define SPCSC_C0_MASK REG_GENMASK(14, 0)
-#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
-
-#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
-#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
-#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
-#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
-#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
-#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
-#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
-
-#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
-#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
-#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
-#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
-#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
-#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
-#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
-
/* Skylake plane registers */
#define _PLANE_CTL_1_A 0x70180
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 70d661bffcc2..442ffc0c79fe 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -14,6 +14,7 @@
#include "display/intel_fdi_regs.h"
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
+#include "display/intel_sprite_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_engine_regs.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (3 preceding siblings ...)
2024-04-12 14:52 ` [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-12 15:31 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 6/6] drm/i915/display: split out bxt_phy_regs.h " Jani Nikula
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
Clean up i915_reg.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_well.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
drivers/gpu/drm/i915/display/vlv_dpio_regs.h | 352 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 343 -----------------
5 files changed, 355 insertions(+), 343 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e4de40228997..0b356ff0e319 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -26,6 +26,7 @@
#include "intel_tc.h"
#include "intel_vga.h"
#include "skl_watermark.h"
+#include "vlv_dpio_regs.h"
#include "vlv_sideband.h"
#include "vlv_sideband_reg.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 2d7a71c8c69c..8d99e00ea326 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -29,6 +29,7 @@
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
+#include "vlv_dpio_regs.h"
#include "vlv_sideband.h"
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 3038655377ea..5c14bbd6ca82 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,7 @@
#include "intel_panel.h"
#include "intel_pps.h"
#include "intel_snps_phy.h"
+#include "vlv_dpio_regs.h"
#include "vlv_sideband.h"
struct intel_dpll_funcs {
diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
new file mode 100644
index 000000000000..0982682c269f
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
@@ -0,0 +1,352 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __VLV_DPIO_REGS_H__
+#define __VLV_DPIO_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/*
+ * Per pipe/PLL DPIO regs
+ */
+#define _VLV_PLL_DW3_CH0 0x800c
+#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
+#define DPIO_POST_DIV_DAC 0
+#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
+#define DPIO_POST_DIV_LVDS1 2
+#define DPIO_POST_DIV_LVDS2 3
+#define DPIO_K_SHIFT (24) /* 4 bits */
+#define DPIO_P1_SHIFT (21) /* 3 bits */
+#define DPIO_P2_SHIFT (16) /* 5 bits */
+#define DPIO_N_SHIFT (12) /* 4 bits */
+#define DPIO_ENABLE_CALIBRATION (1 << 11)
+#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
+#define DPIO_M2DIV_MASK 0xff
+#define _VLV_PLL_DW3_CH1 0x802c
+#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
+
+#define _VLV_PLL_DW5_CH0 0x8014
+#define DPIO_REFSEL_OVERRIDE 27
+#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
+#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
+#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
+#define DPIO_PLL_REFCLK_SEL_MASK 3
+#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
+#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
+#define _VLV_PLL_DW5_CH1 0x8034
+#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
+
+#define _VLV_PLL_DW7_CH0 0x801c
+#define _VLV_PLL_DW7_CH1 0x803c
+#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
+
+#define _VLV_PLL_DW8_CH0 0x8040
+#define _VLV_PLL_DW8_CH1 0x8060
+#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
+
+#define VLV_PLL_DW9_BCAST 0xc044
+#define _VLV_PLL_DW9_CH0 0x8044
+#define _VLV_PLL_DW9_CH1 0x8064
+#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
+
+#define _VLV_PLL_DW10_CH0 0x8048
+#define _VLV_PLL_DW10_CH1 0x8068
+#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
+
+#define _VLV_PLL_DW11_CH0 0x804c
+#define _VLV_PLL_DW11_CH1 0x806c
+#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
+
+/* Spec for ref block start counts at DW10 */
+#define VLV_REF_DW13 0x80ac
+
+#define VLV_CMN_DW0 0x8100
+
+/*
+ * Per DDI channel DPIO regs
+ */
+
+#define _VLV_PCS_DW0_CH0 0x8200
+#define _VLV_PCS_DW0_CH1 0x8400
+#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
+#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
+#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
+#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
+#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
+
+#define _VLV_PCS01_DW0_CH0 0x200
+#define _VLV_PCS23_DW0_CH0 0x400
+#define _VLV_PCS01_DW0_CH1 0x2600
+#define _VLV_PCS23_DW0_CH1 0x2800
+#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
+#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
+
+#define _VLV_PCS_DW1_CH0 0x8204
+#define _VLV_PCS_DW1_CH1 0x8404
+#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
+#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
+#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
+#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
+#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
+#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
+
+#define _VLV_PCS01_DW1_CH0 0x204
+#define _VLV_PCS23_DW1_CH0 0x404
+#define _VLV_PCS01_DW1_CH1 0x2604
+#define _VLV_PCS23_DW1_CH1 0x2804
+#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
+#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
+
+#define _VLV_PCS_DW8_CH0 0x8220
+#define _VLV_PCS_DW8_CH1 0x8420
+#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
+#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
+#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
+
+#define _VLV_PCS01_DW8_CH0 0x0220
+#define _VLV_PCS23_DW8_CH0 0x0420
+#define _VLV_PCS01_DW8_CH1 0x2620
+#define _VLV_PCS23_DW8_CH1 0x2820
+#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
+#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
+
+#define _VLV_PCS_DW9_CH0 0x8224
+#define _VLV_PCS_DW9_CH1 0x8424
+#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
+#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
+#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
+#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
+#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
+#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
+#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
+
+#define _VLV_PCS01_DW9_CH0 0x224
+#define _VLV_PCS23_DW9_CH0 0x424
+#define _VLV_PCS01_DW9_CH1 0x2624
+#define _VLV_PCS23_DW9_CH1 0x2824
+#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
+#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
+
+#define _CHV_PCS_DW10_CH0 0x8228
+#define _CHV_PCS_DW10_CH1 0x8428
+#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
+#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
+#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
+#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
+#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
+#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
+#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
+#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
+#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
+
+#define _VLV_PCS01_DW10_CH0 0x0228
+#define _VLV_PCS23_DW10_CH0 0x0428
+#define _VLV_PCS01_DW10_CH1 0x2628
+#define _VLV_PCS23_DW10_CH1 0x2828
+#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
+#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
+
+#define _VLV_PCS_DW11_CH0 0x822c
+#define _VLV_PCS_DW11_CH1 0x842c
+#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
+#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
+#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
+#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
+#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
+
+#define _VLV_PCS01_DW11_CH0 0x022c
+#define _VLV_PCS23_DW11_CH0 0x042c
+#define _VLV_PCS01_DW11_CH1 0x262c
+#define _VLV_PCS23_DW11_CH1 0x282c
+#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
+#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
+
+#define _VLV_PCS01_DW12_CH0 0x0230
+#define _VLV_PCS23_DW12_CH0 0x0430
+#define _VLV_PCS01_DW12_CH1 0x2630
+#define _VLV_PCS23_DW12_CH1 0x2830
+#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
+#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
+
+#define _VLV_PCS_DW12_CH0 0x8230
+#define _VLV_PCS_DW12_CH1 0x8430
+#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
+#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
+#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
+#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
+#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
+#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
+
+#define _VLV_PCS_DW14_CH0 0x8238
+#define _VLV_PCS_DW14_CH1 0x8438
+#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
+
+#define _VLV_PCS_DW23_CH0 0x825c
+#define _VLV_PCS_DW23_CH1 0x845c
+#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
+
+#define _VLV_TX_DW2_CH0 0x8288
+#define _VLV_TX_DW2_CH1 0x8488
+#define DPIO_SWING_MARGIN000_SHIFT 16
+#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
+#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
+#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
+
+#define _VLV_TX_DW3_CH0 0x828c
+#define _VLV_TX_DW3_CH1 0x848c
+/* The following bit for CHV phy */
+#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
+#define DPIO_SWING_MARGIN101_SHIFT 16
+#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
+#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
+
+#define _VLV_TX_DW4_CH0 0x8290
+#define _VLV_TX_DW4_CH1 0x8490
+#define DPIO_SWING_DEEMPH9P5_SHIFT 24
+#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
+#define DPIO_SWING_DEEMPH6P0_SHIFT 16
+#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
+#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
+
+#define _VLV_TX3_DW4_CH0 0x690
+#define _VLV_TX3_DW4_CH1 0x2a90
+#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
+
+#define _VLV_TX_DW5_CH0 0x8294
+#define _VLV_TX_DW5_CH1 0x8494
+#define DPIO_TX_OCALINIT_EN (1 << 31)
+#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
+
+#define _VLV_TX_DW11_CH0 0x82ac
+#define _VLV_TX_DW11_CH1 0x84ac
+#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
+
+#define _VLV_TX_DW14_CH0 0x82b8
+#define _VLV_TX_DW14_CH1 0x84b8
+#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
+
+/* CHV dpPhy registers */
+#define _CHV_PLL_DW0_CH0 0x8000
+#define _CHV_PLL_DW0_CH1 0x8180
+#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
+
+#define _CHV_PLL_DW1_CH0 0x8004
+#define _CHV_PLL_DW1_CH1 0x8184
+#define DPIO_CHV_N_DIV_SHIFT 8
+#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
+#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
+
+#define _CHV_PLL_DW2_CH0 0x8008
+#define _CHV_PLL_DW2_CH1 0x8188
+#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
+
+#define _CHV_PLL_DW3_CH0 0x800c
+#define _CHV_PLL_DW3_CH1 0x818c
+#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
+#define DPIO_CHV_FIRST_MOD (0 << 8)
+#define DPIO_CHV_SECOND_MOD (1 << 8)
+#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
+#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
+
+#define _CHV_PLL_DW6_CH0 0x8018
+#define _CHV_PLL_DW6_CH1 0x8198
+#define DPIO_CHV_GAIN_CTRL_SHIFT 16
+#define DPIO_CHV_INT_COEFF_SHIFT 8
+#define DPIO_CHV_PROP_COEFF_SHIFT 0
+#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
+
+#define _CHV_PLL_DW8_CH0 0x8020
+#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0 0x8024
+#define _CHV_PLL_DW9_CH1 0x81A4
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
+#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
+#define _CHV_CMN_DW0_CH0 0x8100
+#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
+#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
+#define DPIO_ALLDL_POWERDOWN (1 << 1)
+#define DPIO_ANYDL_POWERDOWN (1 << 0)
+
+#define _CHV_CMN_DW5_CH0 0x8114
+#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
+#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
+#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
+#define CHV_BUFRIGHTENA1_MASK (3 << 20)
+#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
+#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
+#define CHV_BUFLEFTENA1_FORCE (3 << 22)
+#define CHV_BUFLEFTENA1_MASK (3 << 22)
+
+#define _CHV_CMN_DW13_CH0 0x8134
+#define _CHV_CMN_DW0_CH1 0x8080
+#define DPIO_CHV_S1_DIV_SHIFT 21
+#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
+#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
+#define DPIO_CHV_K_DIV_SHIFT 4
+#define DPIO_PLL_FREQLOCK (1 << 1)
+#define DPIO_PLL_LOCK (1 << 0)
+#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
+
+#define _CHV_CMN_DW14_CH0 0x8138
+#define _CHV_CMN_DW1_CH1 0x8084
+#define DPIO_AFC_RECAL (1 << 14)
+#define DPIO_DCLKP_EN (1 << 13)
+#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
+#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
+#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
+#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
+#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
+#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
+#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
+#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
+#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
+
+#define _CHV_CMN_DW19_CH0 0x814c
+#define _CHV_CMN_DW6_CH1 0x8098
+#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
+#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
+#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
+#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
+
+#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
+
+#define CHV_CMN_DW28 0x8170
+#define DPIO_CL1POWERDOWNEN (1 << 23)
+#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
+#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
+#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
+#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
+#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
+
+#define CHV_CMN_DW30 0x8178
+#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
+#define DPIO_LRC_BYPASS (1 << 3)
+
+#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
+ (lane) * 0x200 + (offset))
+
+#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
+#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
+#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
+#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
+#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
+#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
+#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
+#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
+#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
+#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
+#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
+#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
+#define DPIO_FRC_LATENCY_SHFIT 8
+#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
+#define DPIO_UPAR_SHIFT 30
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb63c7214e12..86700c6caa27 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -195,349 +195,6 @@
#define DPIO_SFR_BYPASS (1 << 1)
#define DPIO_CMNRST (1 << 0)
-/*
- * Per pipe/PLL DPIO regs
- */
-#define _VLV_PLL_DW3_CH0 0x800c
-#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
-#define DPIO_POST_DIV_DAC 0
-#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
-#define DPIO_POST_DIV_LVDS1 2
-#define DPIO_POST_DIV_LVDS2 3
-#define DPIO_K_SHIFT (24) /* 4 bits */
-#define DPIO_P1_SHIFT (21) /* 3 bits */
-#define DPIO_P2_SHIFT (16) /* 5 bits */
-#define DPIO_N_SHIFT (12) /* 4 bits */
-#define DPIO_ENABLE_CALIBRATION (1 << 11)
-#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
-#define DPIO_M2DIV_MASK 0xff
-#define _VLV_PLL_DW3_CH1 0x802c
-#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
-
-#define _VLV_PLL_DW5_CH0 0x8014
-#define DPIO_REFSEL_OVERRIDE 27
-#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
-#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
-#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
-#define DPIO_PLL_REFCLK_SEL_MASK 3
-#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
-#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
-#define _VLV_PLL_DW5_CH1 0x8034
-#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
-
-#define _VLV_PLL_DW7_CH0 0x801c
-#define _VLV_PLL_DW7_CH1 0x803c
-#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
-
-#define _VLV_PLL_DW8_CH0 0x8040
-#define _VLV_PLL_DW8_CH1 0x8060
-#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
-
-#define VLV_PLL_DW9_BCAST 0xc044
-#define _VLV_PLL_DW9_CH0 0x8044
-#define _VLV_PLL_DW9_CH1 0x8064
-#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
-
-#define _VLV_PLL_DW10_CH0 0x8048
-#define _VLV_PLL_DW10_CH1 0x8068
-#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
-
-#define _VLV_PLL_DW11_CH0 0x804c
-#define _VLV_PLL_DW11_CH1 0x806c
-#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
-
-/* Spec for ref block start counts at DW10 */
-#define VLV_REF_DW13 0x80ac
-
-#define VLV_CMN_DW0 0x8100
-
-/*
- * Per DDI channel DPIO regs
- */
-
-#define _VLV_PCS_DW0_CH0 0x8200
-#define _VLV_PCS_DW0_CH1 0x8400
-#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
-#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
-#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
-#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
-#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
-
-#define _VLV_PCS01_DW0_CH0 0x200
-#define _VLV_PCS23_DW0_CH0 0x400
-#define _VLV_PCS01_DW0_CH1 0x2600
-#define _VLV_PCS23_DW0_CH1 0x2800
-#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
-#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
-
-#define _VLV_PCS_DW1_CH0 0x8204
-#define _VLV_PCS_DW1_CH1 0x8404
-#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
-#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
-#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
-#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
-#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
-#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
-
-#define _VLV_PCS01_DW1_CH0 0x204
-#define _VLV_PCS23_DW1_CH0 0x404
-#define _VLV_PCS01_DW1_CH1 0x2604
-#define _VLV_PCS23_DW1_CH1 0x2804
-#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
-#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
-
-#define _VLV_PCS_DW8_CH0 0x8220
-#define _VLV_PCS_DW8_CH1 0x8420
-#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
-#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
-#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
-
-#define _VLV_PCS01_DW8_CH0 0x0220
-#define _VLV_PCS23_DW8_CH0 0x0420
-#define _VLV_PCS01_DW8_CH1 0x2620
-#define _VLV_PCS23_DW8_CH1 0x2820
-#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
-#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
-
-#define _VLV_PCS_DW9_CH0 0x8224
-#define _VLV_PCS_DW9_CH1 0x8424
-#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
-#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
-#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
-#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
-#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
-#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
-#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
-
-#define _VLV_PCS01_DW9_CH0 0x224
-#define _VLV_PCS23_DW9_CH0 0x424
-#define _VLV_PCS01_DW9_CH1 0x2624
-#define _VLV_PCS23_DW9_CH1 0x2824
-#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
-#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
-
-#define _CHV_PCS_DW10_CH0 0x8228
-#define _CHV_PCS_DW10_CH1 0x8428
-#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
-#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
-#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
-#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
-#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
-#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
-#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
-#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
-#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
-
-#define _VLV_PCS01_DW10_CH0 0x0228
-#define _VLV_PCS23_DW10_CH0 0x0428
-#define _VLV_PCS01_DW10_CH1 0x2628
-#define _VLV_PCS23_DW10_CH1 0x2828
-#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
-#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
-
-#define _VLV_PCS_DW11_CH0 0x822c
-#define _VLV_PCS_DW11_CH1 0x842c
-#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
-#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
-#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
-#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
-#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
-
-#define _VLV_PCS01_DW11_CH0 0x022c
-#define _VLV_PCS23_DW11_CH0 0x042c
-#define _VLV_PCS01_DW11_CH1 0x262c
-#define _VLV_PCS23_DW11_CH1 0x282c
-#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
-#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
-
-#define _VLV_PCS01_DW12_CH0 0x0230
-#define _VLV_PCS23_DW12_CH0 0x0430
-#define _VLV_PCS01_DW12_CH1 0x2630
-#define _VLV_PCS23_DW12_CH1 0x2830
-#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
-#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
-
-#define _VLV_PCS_DW12_CH0 0x8230
-#define _VLV_PCS_DW12_CH1 0x8430
-#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
-#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
-#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
-#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
-#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
-#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
-
-#define _VLV_PCS_DW14_CH0 0x8238
-#define _VLV_PCS_DW14_CH1 0x8438
-#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
-
-#define _VLV_PCS_DW23_CH0 0x825c
-#define _VLV_PCS_DW23_CH1 0x845c
-#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
-
-#define _VLV_TX_DW2_CH0 0x8288
-#define _VLV_TX_DW2_CH1 0x8488
-#define DPIO_SWING_MARGIN000_SHIFT 16
-#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
-#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
-#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
-
-#define _VLV_TX_DW3_CH0 0x828c
-#define _VLV_TX_DW3_CH1 0x848c
-/* The following bit for CHV phy */
-#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
-#define DPIO_SWING_MARGIN101_SHIFT 16
-#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
-#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
-
-#define _VLV_TX_DW4_CH0 0x8290
-#define _VLV_TX_DW4_CH1 0x8490
-#define DPIO_SWING_DEEMPH9P5_SHIFT 24
-#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
-#define DPIO_SWING_DEEMPH6P0_SHIFT 16
-#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
-#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
-
-#define _VLV_TX3_DW4_CH0 0x690
-#define _VLV_TX3_DW4_CH1 0x2a90
-#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
-
-#define _VLV_TX_DW5_CH0 0x8294
-#define _VLV_TX_DW5_CH1 0x8494
-#define DPIO_TX_OCALINIT_EN (1 << 31)
-#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
-
-#define _VLV_TX_DW11_CH0 0x82ac
-#define _VLV_TX_DW11_CH1 0x84ac
-#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
-
-#define _VLV_TX_DW14_CH0 0x82b8
-#define _VLV_TX_DW14_CH1 0x84b8
-#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
-
-/* CHV dpPhy registers */
-#define _CHV_PLL_DW0_CH0 0x8000
-#define _CHV_PLL_DW0_CH1 0x8180
-#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
-
-#define _CHV_PLL_DW1_CH0 0x8004
-#define _CHV_PLL_DW1_CH1 0x8184
-#define DPIO_CHV_N_DIV_SHIFT 8
-#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
-#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
-
-#define _CHV_PLL_DW2_CH0 0x8008
-#define _CHV_PLL_DW2_CH1 0x8188
-#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
-
-#define _CHV_PLL_DW3_CH0 0x800c
-#define _CHV_PLL_DW3_CH1 0x818c
-#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
-#define DPIO_CHV_FIRST_MOD (0 << 8)
-#define DPIO_CHV_SECOND_MOD (1 << 8)
-#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
-#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
-#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
-
-#define _CHV_PLL_DW6_CH0 0x8018
-#define _CHV_PLL_DW6_CH1 0x8198
-#define DPIO_CHV_GAIN_CTRL_SHIFT 16
-#define DPIO_CHV_INT_COEFF_SHIFT 8
-#define DPIO_CHV_PROP_COEFF_SHIFT 0
-#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
-
-#define _CHV_PLL_DW8_CH0 0x8020
-#define _CHV_PLL_DW8_CH1 0x81A0
-#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
-#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
-#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
-
-#define _CHV_PLL_DW9_CH0 0x8024
-#define _CHV_PLL_DW9_CH1 0x81A4
-#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
-#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
-#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
-#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
-
-#define _CHV_CMN_DW0_CH0 0x8100
-#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
-#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
-#define DPIO_ALLDL_POWERDOWN (1 << 1)
-#define DPIO_ANYDL_POWERDOWN (1 << 0)
-
-#define _CHV_CMN_DW5_CH0 0x8114
-#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
-#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
-#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
-#define CHV_BUFRIGHTENA1_MASK (3 << 20)
-#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
-#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
-#define CHV_BUFLEFTENA1_FORCE (3 << 22)
-#define CHV_BUFLEFTENA1_MASK (3 << 22)
-
-#define _CHV_CMN_DW13_CH0 0x8134
-#define _CHV_CMN_DW0_CH1 0x8080
-#define DPIO_CHV_S1_DIV_SHIFT 21
-#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
-#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
-#define DPIO_CHV_K_DIV_SHIFT 4
-#define DPIO_PLL_FREQLOCK (1 << 1)
-#define DPIO_PLL_LOCK (1 << 0)
-#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
-
-#define _CHV_CMN_DW14_CH0 0x8138
-#define _CHV_CMN_DW1_CH1 0x8084
-#define DPIO_AFC_RECAL (1 << 14)
-#define DPIO_DCLKP_EN (1 << 13)
-#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
-#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
-#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
-#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
-#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
-#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
-#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
-#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
-#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
-
-#define _CHV_CMN_DW19_CH0 0x814c
-#define _CHV_CMN_DW6_CH1 0x8098
-#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
-#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
-#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
-#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
-
-#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
-
-#define CHV_CMN_DW28 0x8170
-#define DPIO_CL1POWERDOWNEN (1 << 23)
-#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
-#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
-#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
-#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
-#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
-
-#define CHV_CMN_DW30 0x8178
-#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
-#define DPIO_LRC_BYPASS (1 << 3)
-
-#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
- (lane) * 0x200 + (offset))
-
-#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
-#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
-#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
-#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
-#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
-#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
-#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
-#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
-#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
-#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
-#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
-#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
-#define DPIO_FRC_LATENCY_SHFIT 8
-#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
-#define DPIO_UPAR_SHIFT 30
-
/* BXT PHY registers */
#define _BXT_PHY0_BASE 0x6C000
#define _BXT_PHY1_BASE 0x162000
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 6/6] drm/i915/display: split out bxt_phy_regs.h from i915_reg.h
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (4 preceding siblings ...)
2024-04-12 14:52 ` [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h " Jani Nikula
@ 2024-04-12 14:52 ` Jani Nikula
2024-04-15 12:23 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_reg.h cleanups Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 14:52 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula
Clean up i915_reg.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/bxt_phy_regs.h | 292 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 283 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
10 files changed, 300 insertions(+), 283 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/bxt_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/bxt_phy_regs.h b/drivers/gpu/drm/i915/display/bxt_phy_regs.h
new file mode 100644
index 000000000000..73a3e545f5b6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/bxt_phy_regs.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __BXT_PHY_REGS__
+#define __BXT_PHY_REGS__
+
+#include "intel_display_reg_defs.h"
+
+/* BXT PHY registers */
+#define _BXT_PHY0_BASE 0x6C000
+#define _BXT_PHY1_BASE 0x162000
+#define _BXT_PHY2_BASE 0x163000
+#define BXT_PHY_BASE(phy) \
+ _PICK_EVEN_2RANGES(phy, 1, \
+ _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
+ _BXT_PHY1_BASE, _BXT_PHY2_BASE)
+
+#define _BXT_PHY(phy, reg) \
+ _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
+
+#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
+ (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
+ (reg_ch1) - _BXT_PHY0_BASE))
+#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
+ _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
+
+#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
+#define MIPIO_RST_CTRL (1 << 2)
+
+#define _BXT_PHY_CTL_DDI_A 0x64C00
+#define _BXT_PHY_CTL_DDI_B 0x64C10
+#define _BXT_PHY_CTL_DDI_C 0x64C20
+#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
+#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
+#define BXT_PHY_LANE_ENABLED (1 << 8)
+#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
+ _BXT_PHY_CTL_DDI_B)
+
+#define _PHY_CTL_FAMILY_DDI 0x64C90
+#define _PHY_CTL_FAMILY_EDP 0x64C80
+#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
+#define COMMON_RESET_DIS (1 << 31)
+#define BXT_PHY_CTL_FAMILY(phy) \
+ _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
+ _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
+ _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
+
+/* BXT PHY PLL registers */
+#define _PORT_PLL_A 0x46074
+#define _PORT_PLL_B 0x46078
+#define _PORT_PLL_C 0x4607c
+#define PORT_PLL_ENABLE REG_BIT(31)
+#define PORT_PLL_LOCK REG_BIT(30)
+#define PORT_PLL_REF_SEL REG_BIT(27)
+#define PORT_PLL_POWER_ENABLE REG_BIT(26)
+#define PORT_PLL_POWER_STATE REG_BIT(25)
+#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
+
+#define _PORT_PLL_EBB_0_A 0x162034
+#define _PORT_PLL_EBB_0_B 0x6C034
+#define _PORT_PLL_EBB_0_C 0x6C340
+#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
+#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
+#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
+#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
+#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PLL_EBB_0_B, \
+ _PORT_PLL_EBB_0_C)
+
+#define _PORT_PLL_EBB_4_A 0x162038
+#define _PORT_PLL_EBB_4_B 0x6C038
+#define _PORT_PLL_EBB_4_C 0x6C344
+#define PORT_PLL_RECALIBRATE REG_BIT(14)
+#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
+#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PLL_EBB_4_B, \
+ _PORT_PLL_EBB_4_C)
+
+#define _PORT_PLL_0_A 0x162100
+#define _PORT_PLL_0_B 0x6C100
+#define _PORT_PLL_0_C 0x6C380
+/* PORT_PLL_0_A */
+#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
+#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
+/* PORT_PLL_1_A */
+#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
+#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
+/* PORT_PLL_2_A */
+#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
+#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
+/* PORT_PLL_3_A */
+#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
+/* PORT_PLL_6_A */
+#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
+#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
+#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
+#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
+#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
+#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
+/* PORT_PLL_8_A */
+#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
+#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
+/* PORT_PLL_9_A */
+#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
+#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
+/* PORT_PLL_10_A */
+#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
+#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
+#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
+#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
+ _PORT_PLL_0_B, \
+ _PORT_PLL_0_C)
+#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
+ (idx) * 4)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A 0x162000
+#define _PORT_CL1CM_DW0_BC 0x6C000
+#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
+#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
+
+#define _PORT_CL1CM_DW9_A 0x162024
+#define _PORT_CL1CM_DW9_BC 0x6C024
+#define IREF0RC_OFFSET_SHIFT 8
+#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
+
+#define _PORT_CL1CM_DW10_A 0x162028
+#define _PORT_CL1CM_DW10_BC 0x6C028
+#define IREF1RC_OFFSET_SHIFT 8
+#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
+
+#define _PORT_CL1CM_DW28_A 0x162070
+#define _PORT_CL1CM_DW28_BC 0x6C070
+#define OCL1_POWER_DOWN_EN (1 << 23)
+#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
+#define SUS_CLK_CONFIG 0x3
+#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
+
+#define _PORT_CL1CM_DW30_A 0x162078
+#define _PORT_CL1CM_DW30_BC 0x6C078
+#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
+
+/* The spec defines this only for BXT PHY0, but lets assume that this
+ * would exist for PHY1 too if it had a second channel.
+ */
+#define _PORT_CL2CM_DW6_A 0x162358
+#define _PORT_CL2CM_DW6_BC 0x6C358
+#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
+#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+
+/* BXT PHY Ref registers */
+#define _PORT_REF_DW3_A 0x16218C
+#define _PORT_REF_DW3_BC 0x6C18C
+#define GRC_DONE (1 << 22)
+#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
+
+#define _PORT_REF_DW6_A 0x162198
+#define _PORT_REF_DW6_BC 0x6C198
+#define GRC_CODE_SHIFT 24
+#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
+#define GRC_CODE_FAST_SHIFT 16
+#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
+#define GRC_CODE_SLOW_SHIFT 8
+#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
+#define GRC_CODE_NOM_MASK 0xFF
+#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
+
+#define _PORT_REF_DW8_A 0x1621A0
+#define _PORT_REF_DW8_BC 0x6C1A0
+#define GRC_DIS (1 << 15)
+#define GRC_RDY_OVRD (1 << 1)
+#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
+
+/* BXT PHY PCS registers */
+#define _PORT_PCS_DW10_LN01_A 0x162428
+#define _PORT_PCS_DW10_LN01_B 0x6C428
+#define _PORT_PCS_DW10_LN01_C 0x6C828
+#define _PORT_PCS_DW10_GRP_A 0x162C28
+#define _PORT_PCS_DW10_GRP_B 0x6CC28
+#define _PORT_PCS_DW10_GRP_C 0x6CE28
+#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PCS_DW10_LN01_B, \
+ _PORT_PCS_DW10_LN01_C)
+#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PCS_DW10_GRP_B, \
+ _PORT_PCS_DW10_GRP_C)
+
+#define TX2_SWING_CALC_INIT (1 << 31)
+#define TX1_SWING_CALC_INIT (1 << 30)
+
+#define _PORT_PCS_DW12_LN01_A 0x162430
+#define _PORT_PCS_DW12_LN01_B 0x6C430
+#define _PORT_PCS_DW12_LN01_C 0x6C830
+#define _PORT_PCS_DW12_LN23_A 0x162630
+#define _PORT_PCS_DW12_LN23_B 0x6C630
+#define _PORT_PCS_DW12_LN23_C 0x6CA30
+#define _PORT_PCS_DW12_GRP_A 0x162c30
+#define _PORT_PCS_DW12_GRP_B 0x6CC30
+#define _PORT_PCS_DW12_GRP_C 0x6CE30
+#define LANESTAGGER_STRAP_OVRD (1 << 6)
+#define LANE_STAGGER_MASK 0x1F
+#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PCS_DW12_LN01_B, \
+ _PORT_PCS_DW12_LN01_C)
+#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PCS_DW12_LN23_B, \
+ _PORT_PCS_DW12_LN23_C)
+#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_PCS_DW12_GRP_B, \
+ _PORT_PCS_DW12_GRP_C)
+
+/* BXT PHY TX registers */
+#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)
+
+#define _PORT_TX_DW2_LN0_A 0x162508
+#define _PORT_TX_DW2_LN0_B 0x6C508
+#define _PORT_TX_DW2_LN0_C 0x6C908
+#define _PORT_TX_DW2_GRP_A 0x162D08
+#define _PORT_TX_DW2_GRP_B 0x6CD08
+#define _PORT_TX_DW2_GRP_C 0x6CF08
+#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW2_LN0_B, \
+ _PORT_TX_DW2_LN0_C)
+#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW2_GRP_B, \
+ _PORT_TX_DW2_GRP_C)
+#define MARGIN_000_SHIFT 16
+#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
+#define UNIQ_TRANS_SCALE_SHIFT 8
+#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
+
+#define _PORT_TX_DW3_LN0_A 0x16250C
+#define _PORT_TX_DW3_LN0_B 0x6C50C
+#define _PORT_TX_DW3_LN0_C 0x6C90C
+#define _PORT_TX_DW3_GRP_A 0x162D0C
+#define _PORT_TX_DW3_GRP_B 0x6CD0C
+#define _PORT_TX_DW3_GRP_C 0x6CF0C
+#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW3_LN0_B, \
+ _PORT_TX_DW3_LN0_C)
+#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW3_GRP_B, \
+ _PORT_TX_DW3_GRP_C)
+#define SCALE_DCOMP_METHOD (1 << 26)
+#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
+
+#define _PORT_TX_DW4_LN0_A 0x162510
+#define _PORT_TX_DW4_LN0_B 0x6C510
+#define _PORT_TX_DW4_LN0_C 0x6C910
+#define _PORT_TX_DW4_GRP_A 0x162D10
+#define _PORT_TX_DW4_GRP_B 0x6CD10
+#define _PORT_TX_DW4_GRP_C 0x6CF10
+#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW4_LN0_B, \
+ _PORT_TX_DW4_LN0_C)
+#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW4_GRP_B, \
+ _PORT_TX_DW4_GRP_C)
+#define DEEMPH_SHIFT 24
+#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
+
+#define _PORT_TX_DW5_LN0_A 0x162514
+#define _PORT_TX_DW5_LN0_B 0x6C514
+#define _PORT_TX_DW5_LN0_C 0x6C914
+#define _PORT_TX_DW5_GRP_A 0x162D14
+#define _PORT_TX_DW5_GRP_B 0x6CD14
+#define _PORT_TX_DW5_GRP_C 0x6CF14
+#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_LN0_B, \
+ _PORT_TX_DW5_LN0_C)
+#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_GRP_B, \
+ _PORT_TX_DW5_GRP_C)
+#define DCC_DELAY_RANGE_1 (1 << 9)
+#define DCC_DELAY_RANGE_2 (1 << 8)
+
+#define _PORT_TX_DW14_LN0_A 0x162538
+#define _PORT_TX_DW14_LN0_B 0x6C538
+#define _PORT_TX_DW14_LN0_C 0x6C938
+#define LATENCY_OPTIM_SHIFT 30
+#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
+#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
+ _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
+ _PORT_TX_DW14_LN0_C) + \
+ _BXT_LANE_OFFSET(lane))
+
+#endif /* __BXT_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3255d4e375af..2ad6e221cf67 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -31,6 +31,7 @@
#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_privacy_screen_consumer.h>
+#include "bxt_phy_regs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "icl_dsi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 8d99e00ea326..bf1897bec9ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "bxt_phy_regs.h"
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9ff6c4cc2e4b..c0255b0b3279 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -24,6 +24,7 @@
#include <linux/math.h>
#include <linux/string_helpers.h>
+#include "bxt_phy_regs.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 63f4af601d15..27d9d15852fc 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -31,6 +31,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_mipi_dsi.h>
+#include "bxt_phy_regs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 498698482d59..c8ee15f4ea34 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -36,6 +36,7 @@
#include "i915_reg.h"
#include "gvt.h"
+#include "display/bxt_phy_regs.h"
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
#include "display/intel_sprite_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7d749995c7a7..daa83f0c1d5f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -41,6 +41,7 @@
#include "gvt.h"
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
+#include "display/bxt_phy_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 5b5def6ddef7..1b75eda56c02 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -37,6 +37,7 @@
#include "i915_reg.h"
#include "gvt.h"
+#include "display/bxt_phy_regs.h"
#include "display/intel_dpio_phy.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86700c6caa27..f456153335c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -195,289 +195,6 @@
#define DPIO_SFR_BYPASS (1 << 1)
#define DPIO_CMNRST (1 << 0)
-/* BXT PHY registers */
-#define _BXT_PHY0_BASE 0x6C000
-#define _BXT_PHY1_BASE 0x162000
-#define _BXT_PHY2_BASE 0x163000
-#define BXT_PHY_BASE(phy) \
- _PICK_EVEN_2RANGES(phy, 1, \
- _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
- _BXT_PHY1_BASE, _BXT_PHY2_BASE)
-
-#define _BXT_PHY(phy, reg) \
- _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
-
-#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
- (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
- (reg_ch1) - _BXT_PHY0_BASE))
-#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
- _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
-
-#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
-#define MIPIO_RST_CTRL (1 << 2)
-
-#define _BXT_PHY_CTL_DDI_A 0x64C00
-#define _BXT_PHY_CTL_DDI_B 0x64C10
-#define _BXT_PHY_CTL_DDI_C 0x64C20
-#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
-#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
-#define BXT_PHY_LANE_ENABLED (1 << 8)
-#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
- _BXT_PHY_CTL_DDI_B)
-
-#define _PHY_CTL_FAMILY_DDI 0x64C90
-#define _PHY_CTL_FAMILY_EDP 0x64C80
-#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
-#define COMMON_RESET_DIS (1 << 31)
-#define BXT_PHY_CTL_FAMILY(phy) \
- _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
- _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
- _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
-
-/* BXT PHY PLL registers */
-#define _PORT_PLL_A 0x46074
-#define _PORT_PLL_B 0x46078
-#define _PORT_PLL_C 0x4607c
-#define PORT_PLL_ENABLE REG_BIT(31)
-#define PORT_PLL_LOCK REG_BIT(30)
-#define PORT_PLL_REF_SEL REG_BIT(27)
-#define PORT_PLL_POWER_ENABLE REG_BIT(26)
-#define PORT_PLL_POWER_STATE REG_BIT(25)
-#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
-
-#define _PORT_PLL_EBB_0_A 0x162034
-#define _PORT_PLL_EBB_0_B 0x6C034
-#define _PORT_PLL_EBB_0_C 0x6C340
-#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
-#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
-#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
-#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
-#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PLL_EBB_0_B, \
- _PORT_PLL_EBB_0_C)
-
-#define _PORT_PLL_EBB_4_A 0x162038
-#define _PORT_PLL_EBB_4_B 0x6C038
-#define _PORT_PLL_EBB_4_C 0x6C344
-#define PORT_PLL_RECALIBRATE REG_BIT(14)
-#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
-#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PLL_EBB_4_B, \
- _PORT_PLL_EBB_4_C)
-
-#define _PORT_PLL_0_A 0x162100
-#define _PORT_PLL_0_B 0x6C100
-#define _PORT_PLL_0_C 0x6C380
-/* PORT_PLL_0_A */
-#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
-#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
-/* PORT_PLL_1_A */
-#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
-#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
-/* PORT_PLL_2_A */
-#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
-#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
-/* PORT_PLL_3_A */
-#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
-/* PORT_PLL_6_A */
-#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
-#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
-#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
-#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
-#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
-#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
-/* PORT_PLL_8_A */
-#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
-#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
-/* PORT_PLL_9_A */
-#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
-#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
-/* PORT_PLL_10_A */
-#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
-#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
-#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
-#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
- _PORT_PLL_0_B, \
- _PORT_PLL_0_C)
-#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
- (idx) * 4)
-
-/* BXT PHY common lane registers */
-#define _PORT_CL1CM_DW0_A 0x162000
-#define _PORT_CL1CM_DW0_BC 0x6C000
-#define PHY_POWER_GOOD (1 << 16)
-#define PHY_RESERVED (1 << 7)
-#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
-
-#define _PORT_CL1CM_DW9_A 0x162024
-#define _PORT_CL1CM_DW9_BC 0x6C024
-#define IREF0RC_OFFSET_SHIFT 8
-#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
-
-#define _PORT_CL1CM_DW10_A 0x162028
-#define _PORT_CL1CM_DW10_BC 0x6C028
-#define IREF1RC_OFFSET_SHIFT 8
-#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
-
-#define _PORT_CL1CM_DW28_A 0x162070
-#define _PORT_CL1CM_DW28_BC 0x6C070
-#define OCL1_POWER_DOWN_EN (1 << 23)
-#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
-#define SUS_CLK_CONFIG 0x3
-#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
-
-#define _PORT_CL1CM_DW30_A 0x162078
-#define _PORT_CL1CM_DW30_BC 0x6C078
-#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
-#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
-
-/* The spec defines this only for BXT PHY0, but lets assume that this
- * would exist for PHY1 too if it had a second channel.
- */
-#define _PORT_CL2CM_DW6_A 0x162358
-#define _PORT_CL2CM_DW6_BC 0x6C358
-#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
-#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
-
-/* BXT PHY Ref registers */
-#define _PORT_REF_DW3_A 0x16218C
-#define _PORT_REF_DW3_BC 0x6C18C
-#define GRC_DONE (1 << 22)
-#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
-
-#define _PORT_REF_DW6_A 0x162198
-#define _PORT_REF_DW6_BC 0x6C198
-#define GRC_CODE_SHIFT 24
-#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
-#define GRC_CODE_FAST_SHIFT 16
-#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
-#define GRC_CODE_SLOW_SHIFT 8
-#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
-#define GRC_CODE_NOM_MASK 0xFF
-#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
-
-#define _PORT_REF_DW8_A 0x1621A0
-#define _PORT_REF_DW8_BC 0x6C1A0
-#define GRC_DIS (1 << 15)
-#define GRC_RDY_OVRD (1 << 1)
-#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
-
-/* BXT PHY PCS registers */
-#define _PORT_PCS_DW10_LN01_A 0x162428
-#define _PORT_PCS_DW10_LN01_B 0x6C428
-#define _PORT_PCS_DW10_LN01_C 0x6C828
-#define _PORT_PCS_DW10_GRP_A 0x162C28
-#define _PORT_PCS_DW10_GRP_B 0x6CC28
-#define _PORT_PCS_DW10_GRP_C 0x6CE28
-#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PCS_DW10_LN01_B, \
- _PORT_PCS_DW10_LN01_C)
-#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PCS_DW10_GRP_B, \
- _PORT_PCS_DW10_GRP_C)
-
-#define TX2_SWING_CALC_INIT (1 << 31)
-#define TX1_SWING_CALC_INIT (1 << 30)
-
-#define _PORT_PCS_DW12_LN01_A 0x162430
-#define _PORT_PCS_DW12_LN01_B 0x6C430
-#define _PORT_PCS_DW12_LN01_C 0x6C830
-#define _PORT_PCS_DW12_LN23_A 0x162630
-#define _PORT_PCS_DW12_LN23_B 0x6C630
-#define _PORT_PCS_DW12_LN23_C 0x6CA30
-#define _PORT_PCS_DW12_GRP_A 0x162c30
-#define _PORT_PCS_DW12_GRP_B 0x6CC30
-#define _PORT_PCS_DW12_GRP_C 0x6CE30
-#define LANESTAGGER_STRAP_OVRD (1 << 6)
-#define LANE_STAGGER_MASK 0x1F
-#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PCS_DW12_LN01_B, \
- _PORT_PCS_DW12_LN01_C)
-#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PCS_DW12_LN23_B, \
- _PORT_PCS_DW12_LN23_C)
-#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_PCS_DW12_GRP_B, \
- _PORT_PCS_DW12_GRP_C)
-
-/* BXT PHY TX registers */
-#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
- ((lane) & 1) * 0x80)
-
-#define _PORT_TX_DW2_LN0_A 0x162508
-#define _PORT_TX_DW2_LN0_B 0x6C508
-#define _PORT_TX_DW2_LN0_C 0x6C908
-#define _PORT_TX_DW2_GRP_A 0x162D08
-#define _PORT_TX_DW2_GRP_B 0x6CD08
-#define _PORT_TX_DW2_GRP_C 0x6CF08
-#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW2_LN0_B, \
- _PORT_TX_DW2_LN0_C)
-#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW2_GRP_B, \
- _PORT_TX_DW2_GRP_C)
-#define MARGIN_000_SHIFT 16
-#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
-#define UNIQ_TRANS_SCALE_SHIFT 8
-#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
-
-#define _PORT_TX_DW3_LN0_A 0x16250C
-#define _PORT_TX_DW3_LN0_B 0x6C50C
-#define _PORT_TX_DW3_LN0_C 0x6C90C
-#define _PORT_TX_DW3_GRP_A 0x162D0C
-#define _PORT_TX_DW3_GRP_B 0x6CD0C
-#define _PORT_TX_DW3_GRP_C 0x6CF0C
-#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW3_LN0_B, \
- _PORT_TX_DW3_LN0_C)
-#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW3_GRP_B, \
- _PORT_TX_DW3_GRP_C)
-#define SCALE_DCOMP_METHOD (1 << 26)
-#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
-
-#define _PORT_TX_DW4_LN0_A 0x162510
-#define _PORT_TX_DW4_LN0_B 0x6C510
-#define _PORT_TX_DW4_LN0_C 0x6C910
-#define _PORT_TX_DW4_GRP_A 0x162D10
-#define _PORT_TX_DW4_GRP_B 0x6CD10
-#define _PORT_TX_DW4_GRP_C 0x6CF10
-#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW4_LN0_B, \
- _PORT_TX_DW4_LN0_C)
-#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW4_GRP_B, \
- _PORT_TX_DW4_GRP_C)
-#define DEEMPH_SHIFT 24
-#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
-
-#define _PORT_TX_DW5_LN0_A 0x162514
-#define _PORT_TX_DW5_LN0_B 0x6C514
-#define _PORT_TX_DW5_LN0_C 0x6C914
-#define _PORT_TX_DW5_GRP_A 0x162D14
-#define _PORT_TX_DW5_GRP_B 0x6CD14
-#define _PORT_TX_DW5_GRP_C 0x6CF14
-#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW5_LN0_B, \
- _PORT_TX_DW5_LN0_C)
-#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
- _PORT_TX_DW5_GRP_B, \
- _PORT_TX_DW5_GRP_C)
-#define DCC_DELAY_RANGE_1 (1 << 9)
-#define DCC_DELAY_RANGE_2 (1 << 8)
-
-#define _PORT_TX_DW14_LN0_A 0x162538
-#define _PORT_TX_DW14_LN0_B 0x6C538
-#define _PORT_TX_DW14_LN0_C 0x6C938
-#define LATENCY_OPTIM_SHIFT 30
-#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
-#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
- _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
- _PORT_TX_DW14_LN0_C) + \
- _BXT_LANE_OFFSET(lane))
-
/* UAIMI scratch pad register 1 */
#define UAIMI_SPR1 _MMIO(0x4F074)
/* SKL VccIO mask */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 442ffc0c79fe..80e7a5aa584b 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,6 +3,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include "display/bxt_phy_regs.h"
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_color_regs.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-12 14:52 ` [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
@ 2024-04-12 15:14 ` Ville Syrjälä
2024-04-12 15:50 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 15:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 05:52:55PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc_regs.h | 152 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 142 ----------------
> drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 6 files changed, 157 insertions(+), 142 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7c4d2b2bf20b..151dcd0c45b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -54,6 +54,7 @@
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> +#include "intel_fbc_regs.h"
> #include "intel_frontbuffer.h"
>
> #define for_each_fbc_id(__dev_priv, __fbc_id) \
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> new file mode 100644
> index 000000000000..d454d599a22c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2024 Intel Corporation */
> +
> +#ifndef __INTEL_FBC_REGS__
> +#define __INTEL_FBC_REGS__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/*
> + * Framebuffer compression (915+ only)
> + */
Outdated comment. Looks like pretty much all the comments
in this file are misleading/outdated. Maybe just nuke them
all while at it.
> +
> +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
> +#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
> +#define FBC_CONTROL _MMIO(0x3208)
> +#define FBC_CTL_EN REG_BIT(31)
> +#define FBC_CTL_PERIODIC REG_BIT(30)
> +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
> +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
> +#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
> +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
> +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
> +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
> +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
> +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
> +#define FBC_COMMAND _MMIO(0x320c)
> +#define FBC_CMD_COMPRESS REG_BIT(0)
> +#define FBC_STATUS _MMIO(0x3210)
> +#define FBC_STAT_COMPRESSING REG_BIT(31)
> +#define FBC_STAT_COMPRESSED REG_BIT(30)
> +#define FBC_STAT_MODIFIED REG_BIT(29)
> +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
> +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
> +#define FBC_CTL_FENCE_DBL REG_BIT(4)
> +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
> +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
> +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
> +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
> +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
> +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
> +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
> +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
> +#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
> +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
> +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
> +#define FBC_MOD_NUM_VALID REG_BIT(0)
> +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
> +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
> +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
> +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
> +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
> +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
> +
> +#define FBC_LL_SIZE (1536)
> +
> +/* Framebuffer compression for GM45+ */
> +#define DPFC_CB_BASE _MMIO(0x3200)
> +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> +#define DPFC_CONTROL _MMIO(0x3208)
> +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> +#define DPFC_CTL_EN REG_BIT(31)
> +#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
> +#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> +#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
> +#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
> +#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
> +#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
> +#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
> +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
> +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
> +#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
> +#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
> +#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
> +#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
> +#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
> +#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
> +#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
> +#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> +#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
> +#define DPFC_RECOMP_CTL _MMIO(0x320c)
> +#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
> +#define DPFC_RECOMP_STALL_EN REG_BIT(27)
> +#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
> +#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
> +#define DPFC_STATUS _MMIO(0x3210)
> +#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
> +#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
> +#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
> +#define DPFC_STATUS2 _MMIO(0x3214)
> +#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
> +#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
> +#define DPFC_FENCE_YOFF _MMIO(0x3218)
> +#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> +#define DPFC_CHICKEN _MMIO(0x3224)
> +#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> +#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
> +#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
> +#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
> +#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
> +#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
> +
> +#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> +#define FBC_STRIDE_OVERRIDE REG_BIT(15)
> +#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> +#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> +
> +#define ILK_FBC_RT_BASE _MMIO(0x2128)
> +#define ILK_FBC_RT_VALID REG_BIT(0)
> +#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
> +
> +#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
Not an FBC register.
> +#define ILK_FBCQ_DIS REG_BIT(22)
> +#define ILK_PABSTRETCH_DIS REG_BIT(21)
> +#define ILK_SABSTRETCH_DIS REG_BIT(20)
> +#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
> +#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
> +#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
> +#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
> +#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
> +#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
> +#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
> +#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
> +#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
> +#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
> +
> +
> +/*
> + * Framebuffer compression for Sandybridge
> + *
> + * The following two registers are of type GTTMMADR
> + */
> +#define SNB_DPFC_CTL_SA _MMIO(0x100100)
> +#define SNB_DPFC_FENCE_EN REG_BIT(29)
> +#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
> +#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
> +#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
> +
> +/* Framebuffer compression for Ivybridge */
> +#define IVB_FBC_RT_BASE _MMIO(0x7020)
> +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
> +
> +#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
> +#define FBC_REND_NUKE REG_BIT(2)
> +#define FBC_REND_CACHE_CLEAN REG_BIT(1)
> +
> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
Also not an FBC register.
> +#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> +#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> +#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
> +
> +#endif /* __INTEL_FBC_REGS__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 68b6aa11bcf7..40e79f0dc257 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -17,6 +17,8 @@
> #include "intel_ring.h"
> #include "intel_workarounds.h"
>
> +#include "display/intel_fbc_regs.h"
> +
> /**
> * DOC: Hardware workarounds
> *
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74965383a56..8c44a21977a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1248,148 +1248,11 @@
> #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
> #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
>
> -/*
> - * Framebuffer compression (915+ only)
> - */
> -
> -#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
> -#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
> -#define FBC_CONTROL _MMIO(0x3208)
> -#define FBC_CTL_EN REG_BIT(31)
> -#define FBC_CTL_PERIODIC REG_BIT(30)
> -#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
> -#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
> -#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
> -#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
> -#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
> -#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
> -#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
> -#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> -#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
> -#define FBC_COMMAND _MMIO(0x320c)
> -#define FBC_CMD_COMPRESS REG_BIT(0)
> -#define FBC_STATUS _MMIO(0x3210)
> -#define FBC_STAT_COMPRESSING REG_BIT(31)
> -#define FBC_STAT_COMPRESSED REG_BIT(30)
> -#define FBC_STAT_MODIFIED REG_BIT(29)
> -#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
> -#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
> -#define FBC_CTL_FENCE_DBL REG_BIT(4)
> -#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
> -#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
> -#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
> -#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
> -#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
> -#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
> -#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
> -#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
> -#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
> -#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
> -#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
> -#define FBC_MOD_NUM_VALID REG_BIT(0)
> -#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
> -#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
> -#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
> -#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
> -#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
> -#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
> -
> -#define FBC_LL_SIZE (1536)
> -
> -/* Framebuffer compression for GM45+ */
> -#define DPFC_CB_BASE _MMIO(0x3200)
> -#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> -#define DPFC_CONTROL _MMIO(0x3208)
> -#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> -#define DPFC_CTL_EN REG_BIT(31)
> -#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
> -#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> -#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
> -#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
> -#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
> -#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
> -#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
> -#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
> -#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
> -#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
> -#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
> -#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
> -#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
> -#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
> -#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
> -#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
> -#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> -#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
> -#define DPFC_RECOMP_CTL _MMIO(0x320c)
> -#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
> -#define DPFC_RECOMP_STALL_EN REG_BIT(27)
> -#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
> -#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
> -#define DPFC_STATUS _MMIO(0x3210)
> -#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
> -#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
> -#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
> -#define DPFC_STATUS2 _MMIO(0x3214)
> -#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
> -#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
> -#define DPFC_FENCE_YOFF _MMIO(0x3218)
> -#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> -#define DPFC_CHICKEN _MMIO(0x3224)
> -#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> -#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
> -#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
> -#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
> -#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
> -#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
> -
> -#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> -#define FBC_STRIDE_OVERRIDE REG_BIT(15)
> -#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> -#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> -
> -#define ILK_FBC_RT_BASE _MMIO(0x2128)
> -#define ILK_FBC_RT_VALID REG_BIT(0)
> -#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
> -
> -#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
> -#define ILK_FBCQ_DIS REG_BIT(22)
> -#define ILK_PABSTRETCH_DIS REG_BIT(21)
> -#define ILK_SABSTRETCH_DIS REG_BIT(20)
> -#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
> -#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
> -#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
> -#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
> -#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
> -#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
> -#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
> -#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
> -#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
> -#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
> -
> -
> -/*
> - * Framebuffer compression for Sandybridge
> - *
> - * The following two registers are of type GTTMMADR
> - */
> -#define SNB_DPFC_CTL_SA _MMIO(0x100100)
> -#define SNB_DPFC_FENCE_EN REG_BIT(29)
> -#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
> -#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
> -#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
> -
> -/* Framebuffer compression for Ivybridge */
> -#define IVB_FBC_RT_BASE _MMIO(0x7020)
> -#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
>
> #define IPS_CTL _MMIO(0x43408)
> #define IPS_ENABLE REG_BIT(31)
> #define IPS_FALSE_COLOR REG_BIT(4)
>
> -#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
> -#define FBC_REND_NUKE REG_BIT(2)
> -#define FBC_REND_CACHE_CLEAN REG_BIT(1)
> -
> /*
> * Clock control & power management
> */
> @@ -4526,11 +4389,6 @@
> #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
> #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
>
> -#define CHICKEN_MISC_4 _MMIO(0x4208c)
> -#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> -#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> -#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
> -
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 7e70ee4fbd84..1dc5281b2ade 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -28,6 +28,7 @@
> #include "display/intel_de.h"
> #include "display/intel_display.h"
> #include "display/intel_display_trace.h"
> +#include "display/intel_fbc_regs.h"
> #include "display/skl_watermark.h"
>
> #include "gt/intel_engine_regs.h"
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 87ecc5104fd9..70d661bffcc2 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -10,6 +10,7 @@
> #include "display/intel_dmc_regs.h"
> #include "display/intel_dp_aux_regs.h"
> #include "display/intel_dpio_phy.h"
> +#include "display/intel_fbc_regs.h"
> #include "display/intel_fdi_regs.h"
> #include "display/intel_lvds_regs.h"
> #include "display/intel_psr_regs.h"
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
@ 2024-04-12 15:15 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 15:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 05:52:53PM +0300, Jani Nikula wrote:
> There are too few registers to warrant a dedicated file for LPE audio
> regs, but the audio reg file is better than i915_reg.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio_regs.h | 16 ++++++++++++++++
> drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 16 ----------------
> 3 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> index 616e7b1275c4..7a6d919481fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> @@ -148,4 +148,20 @@
> #define HBLANK_START_COUNT_96 4
> #define HBLANK_START_COUNT_128 5
>
> +/* LPE Audio */
> +#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
> +#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
> +
> +#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62f38)
> +#define VLV_CHICKEN_BIT_DBG_ENABLE REG_BIT(0)
> +
> +#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62f20)
> +#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62f30)
> +#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62f34)
> +#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
> + _VLV_AUD_PORT_EN_B_DBG, \
> + _VLV_AUD_PORT_EN_C_DBG, \
> + _VLV_AUD_PORT_EN_D_DBG)
> +#define VLV_AMP_MUTE REG_BIT(1)
> +
> #endif /* __INTEL_AUDIO_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> index 5863763de530..93e6cac9a4ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> @@ -72,7 +72,7 @@
>
> #include "i915_drv.h"
> #include "i915_irq.h"
> -#include "i915_reg.h"
> +#include "intel_audio_regs.h"
> #include "intel_de.h"
> #include "intel_lpe_audio.h"
> #include "intel_pci_config.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f34efcd7d6c..c689bc7e2867 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1228,22 +1228,6 @@
> #define I915_ASLE_INTERRUPT (1 << 0)
> #define I915_BSD_USER_INTERRUPT (1 << 25)
>
> -#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
> -#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
> -
> -/* DisplayPort Audio w/ LPE */
> -#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
> -#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
> -
> -#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
> -#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
> -#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
> -#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
> - _VLV_AUD_PORT_EN_B_DBG, \
> - _VLV_AUD_PORT_EN_C_DBG, \
> - _VLV_AUD_PORT_EN_D_DBG)
> -#define VLV_AMP_MUTE (1 << 1)
> -
> #define GEN6_BSD_RNCID _MMIO(0x12198)
>
> #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h
2024-04-12 14:52 ` [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
@ 2024-04-12 15:19 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 15:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 05:52:54PM +0300, Jani Nikula wrote:
> For some reason the paletter registers were missed when adding
> intel_color_regs.h. Finish the job.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_color_regs.h | 30 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 30 -------------------
> 2 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
> index 9f4ae58f3e7e..969745821172 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
> @@ -8,6 +8,36 @@
>
> #include "intel_display_reg_defs.h"
>
> +/*
> + * Palette regs
> + */
Quite redundant. If we want to keep a comment then it
should be adjusted to say these are for gmch platforms.
> +#define _PALETTE_A 0xa000
> +#define _PALETTE_B 0xa800
> +#define _CHV_PALETTE_C 0xc000
> +/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
> +#define PALETTE_RED_MASK REG_GENMASK(23, 16)
> +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> +/* pre-i965 10bit interpolated mode ldw */
> +#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
> +#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
> +#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
> +/* pre-i965 10bit interpolated mode udw */
> +#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
> +#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
> +#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
> +#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
> +#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
> +#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
> +#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
> +#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
> +#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
> +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PICK_EVEN_2RANGES(pipe, 2, \
> + _PALETTE_A, _PALETTE_B, \
> + _CHV_PALETTE_C, _CHV_PALETTE_C) + \
> + (i) * 4)
> +
> /* legacy palette */
and then this should be adjusted to indicate ilk+
Otherwise
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c689bc7e2867..b74965383a56 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1700,36 +1700,6 @@
>
> #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
>
> -/*
> - * Palette regs
> - */
> -#define _PALETTE_A 0xa000
> -#define _PALETTE_B 0xa800
> -#define _CHV_PALETTE_C 0xc000
> -/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
> -#define PALETTE_RED_MASK REG_GENMASK(23, 16)
> -#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> -#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> -/* pre-i965 10bit interpolated mode ldw */
> -#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
> -#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
> -#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
> -/* pre-i965 10bit interpolated mode udw */
> -#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
> -#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
> -#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
> -#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
> -#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
> -#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
> -#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
> -#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
> -#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
> -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> - _PICK_EVEN_2RANGES(pipe, 2, \
> - _PALETTE_A, _PALETTE_B, \
> - _CHV_PALETTE_C, _CHV_PALETTE_C) + \
> - (i) * 4)
> -
> #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
>
> #define BXT_RP_STATE_CAP _MMIO(0x138170)
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
2024-04-12 14:52 ` [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
@ 2024-04-12 15:22 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 15:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 05:52:56PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
> .../gpu/drm/i915/display/intel_sprite_regs.h | 349 ++++++++++++++++++
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
> drivers/gpu/drm/i915/gvt/display.c | 1 +
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 5 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 340 -----------------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 8 files changed, 358 insertions(+), 341 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index d7b440c8caef..36a253a19c74 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -47,6 +47,7 @@
> #include "intel_fb.h"
> #include "intel_frontbuffer.h"
> #include "intel_sprite.h"
> +#include "intel_sprite_regs.h"
>
> static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> new file mode 100644
> index 000000000000..caf4b58e9a27
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> @@ -0,0 +1,349 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2024 Intel Corporation */
> +
> +#ifndef __INTEL_SPRITE_REGS__
> +#define __INTEL_SPRITE_REGS__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* Sprite A control */
Redundant comment.
Otherwise
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
We should perhaps indicate which sprite registers are for
which platforms, but doesn't look like we have any
comments like that. So probably material for a potential
followup.
> +#define _DVSACNTR 0x72180
> +#define DVS_ENABLE REG_BIT(31)
> +#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
> +#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
> +#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
> +#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
> +#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
> +#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
> +#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
> +#define DVS_SOURCE_KEY REG_BIT(22)
> +#define DVS_RGB_ORDER_XBGR REG_BIT(20)
> +#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
> +#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
> +#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
> +#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
> +#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
> +#define DVS_ROTATE_180 REG_BIT(15)
> +#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define DVS_TILED REG_BIT(10)
> +#define DVS_DEST_KEY REG_BIT(2)
> +#define _DVSALINOFF 0x72184
> +#define _DVSASTRIDE 0x72188
> +#define _DVSAPOS 0x7218c
> +#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
> +#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
> +#define DVS_POS_X_MASK REG_GENMASK(15, 0)
> +#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
> +#define _DVSASIZE 0x72190
> +#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
> +#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
> +#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
> +#define _DVSAKEYVAL 0x72194
> +#define _DVSAKEYMSK 0x72198
> +#define _DVSASURF 0x7219c
> +#define DVS_ADDR_MASK REG_GENMASK(31, 12)
> +#define _DVSAKEYMAXVAL 0x721a0
> +#define _DVSATILEOFF 0x721a4
> +#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
> +#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
> +#define _DVSASURFLIVE 0x721ac
> +#define _DVSAGAMC_G4X 0x721e0 /* g4x */
> +#define _DVSASCALE 0x72204
> +#define DVS_SCALE_ENABLE REG_BIT(31)
> +#define DVS_FILTER_MASK REG_GENMASK(30, 29)
> +#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
> +#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
> +#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
> +#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> +#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> +#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> +#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
> +#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> +#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
> +#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
> +#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
> +
> +#define _DVSBCNTR 0x73180
> +#define _DVSBLINOFF 0x73184
> +#define _DVSBSTRIDE 0x73188
> +#define _DVSBPOS 0x7318c
> +#define _DVSBSIZE 0x73190
> +#define _DVSBKEYVAL 0x73194
> +#define _DVSBKEYMSK 0x73198
> +#define _DVSBSURF 0x7319c
> +#define _DVSBKEYMAXVAL 0x731a0
> +#define _DVSBTILEOFF 0x731a4
> +#define _DVSBSURFLIVE 0x731ac
> +#define _DVSBGAMC_G4X 0x731e0 /* g4x */
> +#define _DVSBSCALE 0x73204
> +#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
> +#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
> +
> +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
> +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
> +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
> +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
> +#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
> +#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
> +
> +#define _SPRA_CTL 0x70280
> +#define SPRITE_ENABLE REG_BIT(31)
> +#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
> +#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
> +#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
> +#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
> +#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
> +#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
> +#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
> +#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
> +#define SPRITE_SOURCE_KEY REG_BIT(22)
> +#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
> +#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
> +#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
> +#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
> +#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
> +#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
> +#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
> +#define SPRITE_ROTATE_180 REG_BIT(15)
> +#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
> +#define SPRITE_TILED REG_BIT(10)
> +#define SPRITE_DEST_KEY REG_BIT(2)
> +#define _SPRA_LINOFF 0x70284
> +#define _SPRA_STRIDE 0x70288
> +#define _SPRA_POS 0x7028c
> +#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
> +#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
> +#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
> +#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
> +#define _SPRA_SIZE 0x70290
> +#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
> +#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
> +#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
> +#define _SPRA_KEYVAL 0x70294
> +#define _SPRA_KEYMSK 0x70298
> +#define _SPRA_SURF 0x7029c
> +#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
> +#define _SPRA_KEYMAX 0x702a0
> +#define _SPRA_TILEOFF 0x702a4
> +#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
> +#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
> +#define _SPRA_OFFSET 0x702a4
> +#define _SPRA_SURFLIVE 0x702ac
> +#define _SPRA_SCALE 0x70304
> +#define SPRITE_SCALE_ENABLE REG_BIT(31)
> +#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
> +#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
> +#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
> +#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
> +#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> +#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> +#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> +#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
> +#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> +#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
> +#define _SPRA_GAMC 0x70400
> +#define _SPRA_GAMC16 0x70440
> +#define _SPRA_GAMC17 0x7044c
> +
> +#define _SPRB_CTL 0x71280
> +#define _SPRB_LINOFF 0x71284
> +#define _SPRB_STRIDE 0x71288
> +#define _SPRB_POS 0x7128c
> +#define _SPRB_SIZE 0x71290
> +#define _SPRB_KEYVAL 0x71294
> +#define _SPRB_KEYMSK 0x71298
> +#define _SPRB_SURF 0x7129c
> +#define _SPRB_KEYMAX 0x712a0
> +#define _SPRB_TILEOFF 0x712a4
> +#define _SPRB_OFFSET 0x712a4
> +#define _SPRB_SURFLIVE 0x712ac
> +#define _SPRB_SCALE 0x71304
> +#define _SPRB_GAMC 0x71400
> +#define _SPRB_GAMC16 0x71440
> +#define _SPRB_GAMC17 0x7144c
> +
> +#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> +#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> +#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> +#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
> +#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> +#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> +#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> +#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> +#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> +#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> +#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> +#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> +#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
> +#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
> +#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
> +#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> +
> +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
> +#define SP_ENABLE REG_BIT(31)
> +#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define SP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
> +#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
> +#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
> +#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
> +#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
> +#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
> +#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
> +#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
> +#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
> +#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
> +#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
> +#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
> +#define SP_SOURCE_KEY REG_BIT(22)
> +#define SP_YUV_FORMAT_BT709 REG_BIT(18)
> +#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
> +#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
> +#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
> +#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
> +#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
> +#define SP_ROTATE_180 REG_BIT(15)
> +#define SP_TILED REG_BIT(10)
> +#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
> +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> +#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
> +#define SP_POS_Y_MASK REG_GENMASK(31, 16)
> +#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
> +#define SP_POS_X_MASK REG_GENMASK(15, 0)
> +#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
> +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
> +#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
> +#define SP_WIDTH_MASK REG_GENMASK(15, 0)
> +#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
> +#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
> +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
> +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
> +#define SP_ADDR_MASK REG_GENMASK(31, 12)
> +#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
> +#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
> +#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
> +#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
> +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
> +#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> +#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> +#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
> +#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
> +#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> +#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> +#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
> +#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
> +#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
> +#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
> +#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
> +#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
> +#define SP_SH_COS_MASK REG_GENMASK(9, 0)
> +#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
> +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
> +
> +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
> +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
> +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
> +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
> +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
> +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
> +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
> +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
> +
> +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> + _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> +#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> + _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
> +
> +#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
> +#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
> +#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
> +#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
> +#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
> +#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
> +#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
> +#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
> +#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> +#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
> +#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
> +#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
> +
> +/*
> + * CHV pipe B sprite CSC
> + *
> + * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
> + * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
> + * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
> + */
> +#define _MMIO_CHV_SPCSC(plane_id, reg) \
> + _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
> +
> +#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
> +#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
> +#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
> +#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
> +#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
> +#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
> +#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
> +
> +#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
> +#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
> +#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
> +#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
> +#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
> +#define SPCSC_C1_MASK REG_GENMASK(30, 16)
> +#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
> +#define SPCSC_C0_MASK REG_GENMASK(14, 0)
> +#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
> +
> +#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
> +#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
> +#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
> +#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
> +#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
> +#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
> +#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
> +
> +#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
> +#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
> +#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
> +#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
> +#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
> +#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
> +#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
> +
> +#endif /* __INTEL_SPRITE_REGS__ */
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index d4a3f3e093b0..4be8cb65fb7e 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -50,6 +50,7 @@
> #include "trace.h"
>
> #include "display/intel_display.h"
> +#include "display/intel_sprite_regs.h"
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_pm.h"
> #include "gt/intel_context.h"
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index e0c5dfb788eb..498698482d59 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -38,6 +38,7 @@
>
> #include "display/intel_display.h"
> #include "display/intel_dpio_phy.h"
> +#include "display/intel_sprite_regs.h"
>
> static int get_edp_pipe(struct intel_vgpu *vgpu)
> {
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 313efdabee57..4140da68aabb 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -34,11 +34,14 @@
> */
>
> #include <uapi/drm/drm_fourcc.h>
> -#include "i915_drv.h"
> +
> #include "gvt.h"
> +#include "i915_drv.h"
> #include "i915_pvinfo.h"
> #include "i915_reg.h"
>
> +#include "display/intel_sprite_regs.h"
> +
> #define PRIMARY_FORMAT_NUM 16
> struct pixel_format {
> int drm_format; /* Pixel format in DRM definition */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index efcb00472be2..7d749995c7a7 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -49,6 +49,7 @@
> #include "display/intel_fdi_regs.h"
> #include "display/intel_pps_regs.h"
> #include "display/intel_psr_regs.h"
> +#include "display/intel_sprite_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
> #include "gt/intel_gt_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c44a21977a4..bb63c7214e12 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3070,346 +3070,6 @@
> #define _PIPEDSI0CONF 0x7b008
> #define _PIPEDSI1CONF 0x7b808
>
> -/* Sprite A control */
> -#define _DVSACNTR 0x72180
> -#define DVS_ENABLE REG_BIT(31)
> -#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
> -#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
> -#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
> -#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
> -#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
> -#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
> -#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
> -#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
> -#define DVS_SOURCE_KEY REG_BIT(22)
> -#define DVS_RGB_ORDER_XBGR REG_BIT(20)
> -#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
> -#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
> -#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
> -#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
> -#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
> -#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
> -#define DVS_ROTATE_180 REG_BIT(15)
> -#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
> -#define DVS_TILED REG_BIT(10)
> -#define DVS_DEST_KEY REG_BIT(2)
> -#define _DVSALINOFF 0x72184
> -#define _DVSASTRIDE 0x72188
> -#define _DVSAPOS 0x7218c
> -#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
> -#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
> -#define DVS_POS_X_MASK REG_GENMASK(15, 0)
> -#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
> -#define _DVSASIZE 0x72190
> -#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
> -#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
> -#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
> -#define _DVSAKEYVAL 0x72194
> -#define _DVSAKEYMSK 0x72198
> -#define _DVSASURF 0x7219c
> -#define DVS_ADDR_MASK REG_GENMASK(31, 12)
> -#define _DVSAKEYMAXVAL 0x721a0
> -#define _DVSATILEOFF 0x721a4
> -#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
> -#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
> -#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
> -#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
> -#define _DVSASURFLIVE 0x721ac
> -#define _DVSAGAMC_G4X 0x721e0 /* g4x */
> -#define _DVSASCALE 0x72204
> -#define DVS_SCALE_ENABLE REG_BIT(31)
> -#define DVS_FILTER_MASK REG_GENMASK(30, 29)
> -#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
> -#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
> -#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
> -#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> -#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> -#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> -#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
> -#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> -#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
> -#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
> -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
> -
> -#define _DVSBCNTR 0x73180
> -#define _DVSBLINOFF 0x73184
> -#define _DVSBSTRIDE 0x73188
> -#define _DVSBPOS 0x7318c
> -#define _DVSBSIZE 0x73190
> -#define _DVSBKEYVAL 0x73194
> -#define _DVSBKEYMSK 0x73198
> -#define _DVSBSURF 0x7319c
> -#define _DVSBKEYMAXVAL 0x731a0
> -#define _DVSBTILEOFF 0x731a4
> -#define _DVSBSURFLIVE 0x731ac
> -#define _DVSBGAMC_G4X 0x731e0 /* g4x */
> -#define _DVSBSCALE 0x73204
> -#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
> -#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
> -
> -#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> -#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> -#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> -#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
> -#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
> -#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> -#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> -#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> -#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> -#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> -#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> -#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
> -#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
> -#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
> -#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
> -
> -#define _SPRA_CTL 0x70280
> -#define SPRITE_ENABLE REG_BIT(31)
> -#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
> -#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> -#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
> -#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
> -#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
> -#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
> -#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
> -#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
> -#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
> -#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
> -#define SPRITE_SOURCE_KEY REG_BIT(22)
> -#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
> -#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
> -#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
> -#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
> -#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
> -#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
> -#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
> -#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
> -#define SPRITE_ROTATE_180 REG_BIT(15)
> -#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
> -#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
> -#define SPRITE_TILED REG_BIT(10)
> -#define SPRITE_DEST_KEY REG_BIT(2)
> -#define _SPRA_LINOFF 0x70284
> -#define _SPRA_STRIDE 0x70288
> -#define _SPRA_POS 0x7028c
> -#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
> -#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
> -#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
> -#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
> -#define _SPRA_SIZE 0x70290
> -#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
> -#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
> -#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
> -#define _SPRA_KEYVAL 0x70294
> -#define _SPRA_KEYMSK 0x70298
> -#define _SPRA_SURF 0x7029c
> -#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
> -#define _SPRA_KEYMAX 0x702a0
> -#define _SPRA_TILEOFF 0x702a4
> -#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> -#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
> -#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
> -#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
> -#define _SPRA_OFFSET 0x702a4
> -#define _SPRA_SURFLIVE 0x702ac
> -#define _SPRA_SCALE 0x70304
> -#define SPRITE_SCALE_ENABLE REG_BIT(31)
> -#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
> -#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
> -#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
> -#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
> -#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
> -#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
> -#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
> -#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
> -#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> -#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
> -#define _SPRA_GAMC 0x70400
> -#define _SPRA_GAMC16 0x70440
> -#define _SPRA_GAMC17 0x7044c
> -
> -#define _SPRB_CTL 0x71280
> -#define _SPRB_LINOFF 0x71284
> -#define _SPRB_STRIDE 0x71288
> -#define _SPRB_POS 0x7128c
> -#define _SPRB_SIZE 0x71290
> -#define _SPRB_KEYVAL 0x71294
> -#define _SPRB_KEYMSK 0x71298
> -#define _SPRB_SURF 0x7129c
> -#define _SPRB_KEYMAX 0x712a0
> -#define _SPRB_TILEOFF 0x712a4
> -#define _SPRB_OFFSET 0x712a4
> -#define _SPRB_SURFLIVE 0x712ac
> -#define _SPRB_SCALE 0x71304
> -#define _SPRB_GAMC 0x71400
> -#define _SPRB_GAMC16 0x71440
> -#define _SPRB_GAMC17 0x7144c
> -
> -#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> -#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> -#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> -#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
> -#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> -#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> -#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> -#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> -#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> -#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> -#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> -#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> -#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
> -#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
> -#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
> -#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> -
> -#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
> -#define SP_ENABLE REG_BIT(31)
> -#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
> -#define SP_FORMAT_MASK REG_GENMASK(29, 26)
> -#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
> -#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
> -#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
> -#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
> -#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
> -#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
> -#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
> -#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
> -#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
> -#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
> -#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
> -#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
> -#define SP_SOURCE_KEY REG_BIT(22)
> -#define SP_YUV_FORMAT_BT709 REG_BIT(18)
> -#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
> -#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
> -#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
> -#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
> -#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
> -#define SP_ROTATE_180 REG_BIT(15)
> -#define SP_TILED REG_BIT(10)
> -#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
> -#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> -#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> -#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
> -#define SP_POS_Y_MASK REG_GENMASK(31, 16)
> -#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
> -#define SP_POS_X_MASK REG_GENMASK(15, 0)
> -#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
> -#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
> -#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
> -#define SP_WIDTH_MASK REG_GENMASK(15, 0)
> -#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
> -#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
> -#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
> -#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
> -#define SP_ADDR_MASK REG_GENMASK(31, 12)
> -#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
> -#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
> -#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> -#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
> -#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
> -#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
> -#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
> -#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> -#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> -#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
> -#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
> -#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> -#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> -#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
> -#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
> -#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
> -#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
> -#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
> -#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
> -#define SP_SH_COS_MASK REG_GENMASK(9, 0)
> -#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
> -#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
> -
> -#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> -#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
> -#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
> -#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
> -#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
> -#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
> -#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
> -#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
> -#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> -#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> -#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> -#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> -#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> -#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> -#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
> -
> -#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> - _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> -#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> - _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
> -
> -#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> -#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
> -#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
> -#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
> -
> -/*
> - * CHV pipe B sprite CSC
> - *
> - * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
> - * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
> - * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
> - */
> -#define _MMIO_CHV_SPCSC(plane_id, reg) \
> - _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
> -
> -#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
> -#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
> -#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
> -#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
> -#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
> -#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
> -#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
> -
> -#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
> -#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
> -#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
> -#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
> -#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
> -#define SPCSC_C1_MASK REG_GENMASK(30, 16)
> -#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
> -#define SPCSC_C0_MASK REG_GENMASK(14, 0)
> -#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
> -
> -#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
> -#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
> -#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
> -#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
> -#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
> -#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
> -#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
> -
> -#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
> -#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
> -#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
> -#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
> -#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
> -#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
> -#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
> -
> /* Skylake plane registers */
>
> #define _PLANE_CTL_1_A 0x70180
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 70d661bffcc2..442ffc0c79fe 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -14,6 +14,7 @@
> #include "display/intel_fdi_regs.h"
> #include "display/intel_lvds_regs.h"
> #include "display/intel_psr_regs.h"
> +#include "display/intel_sprite_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
> #include "gt/intel_engine_regs.h"
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
2024-04-12 14:52 ` [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h " Jani Nikula
@ 2024-04-12 15:31 ` Ville Syrjälä
2024-04-12 15:52 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 15:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 05:52:57PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../i915/display/intel_display_power_well.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
> drivers/gpu/drm/i915/display/vlv_dpio_regs.h | 352 ++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 343 -----------------
> 5 files changed, 355 insertions(+), 343 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_regs.h
I have pretty much the same thing, but IIRC I did a bunch of
changes to the definitons first, and then extracted them.
So the rebase could be somewhat painful.
I suppose I should actually post my stuff and then we can
figure out what to do with these...
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e4de40228997..0b356ff0e319 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -26,6 +26,7 @@
> #include "intel_tc.h"
> #include "intel_vga.h"
> #include "skl_watermark.h"
> +#include "vlv_dpio_regs.h"
> #include "vlv_sideband.h"
> #include "vlv_sideband_reg.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 2d7a71c8c69c..8d99e00ea326 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -29,6 +29,7 @@
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dpio_phy.h"
> +#include "vlv_dpio_regs.h"
> #include "vlv_sideband.h"
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 3038655377ea..5c14bbd6ca82 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,7 @@
> #include "intel_panel.h"
> #include "intel_pps.h"
> #include "intel_snps_phy.h"
> +#include "vlv_dpio_regs.h"
> #include "vlv_sideband.h"
>
> struct intel_dpll_funcs {
> diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
> new file mode 100644
> index 000000000000..0982682c269f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
> @@ -0,0 +1,352 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2024 Intel Corporation */
> +
> +#ifndef __VLV_DPIO_REGS_H__
> +#define __VLV_DPIO_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/*
> + * Per pipe/PLL DPIO regs
> + */
> +#define _VLV_PLL_DW3_CH0 0x800c
> +#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
> +#define DPIO_POST_DIV_DAC 0
> +#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
> +#define DPIO_POST_DIV_LVDS1 2
> +#define DPIO_POST_DIV_LVDS2 3
> +#define DPIO_K_SHIFT (24) /* 4 bits */
> +#define DPIO_P1_SHIFT (21) /* 3 bits */
> +#define DPIO_P2_SHIFT (16) /* 5 bits */
> +#define DPIO_N_SHIFT (12) /* 4 bits */
> +#define DPIO_ENABLE_CALIBRATION (1 << 11)
> +#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> +#define DPIO_M2DIV_MASK 0xff
> +#define _VLV_PLL_DW3_CH1 0x802c
> +#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
> +
> +#define _VLV_PLL_DW5_CH0 0x8014
> +#define DPIO_REFSEL_OVERRIDE 27
> +#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> +#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
> +#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
> +#define DPIO_PLL_REFCLK_SEL_MASK 3
> +#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> +#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
> +#define _VLV_PLL_DW5_CH1 0x8034
> +#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
> +
> +#define _VLV_PLL_DW7_CH0 0x801c
> +#define _VLV_PLL_DW7_CH1 0x803c
> +#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
> +
> +#define _VLV_PLL_DW8_CH0 0x8040
> +#define _VLV_PLL_DW8_CH1 0x8060
> +#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
> +
> +#define VLV_PLL_DW9_BCAST 0xc044
> +#define _VLV_PLL_DW9_CH0 0x8044
> +#define _VLV_PLL_DW9_CH1 0x8064
> +#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> +
> +#define _VLV_PLL_DW10_CH0 0x8048
> +#define _VLV_PLL_DW10_CH1 0x8068
> +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
> +
> +#define _VLV_PLL_DW11_CH0 0x804c
> +#define _VLV_PLL_DW11_CH1 0x806c
> +#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
> +
> +/* Spec for ref block start counts at DW10 */
> +#define VLV_REF_DW13 0x80ac
> +
> +#define VLV_CMN_DW0 0x8100
> +
> +/*
> + * Per DDI channel DPIO regs
> + */
> +
> +#define _VLV_PCS_DW0_CH0 0x8200
> +#define _VLV_PCS_DW0_CH1 0x8400
> +#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
> +#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
> +#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
> +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
> +#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> +
> +#define _VLV_PCS01_DW0_CH0 0x200
> +#define _VLV_PCS23_DW0_CH0 0x400
> +#define _VLV_PCS01_DW0_CH1 0x2600
> +#define _VLV_PCS23_DW0_CH1 0x2800
> +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> +
> +#define _VLV_PCS_DW1_CH0 0x8204
> +#define _VLV_PCS_DW1_CH1 0x8404
> +#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
> +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
> +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
> +#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
> +#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
> +#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> +
> +#define _VLV_PCS01_DW1_CH0 0x204
> +#define _VLV_PCS23_DW1_CH0 0x404
> +#define _VLV_PCS01_DW1_CH1 0x2604
> +#define _VLV_PCS23_DW1_CH1 0x2804
> +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> +
> +#define _VLV_PCS_DW8_CH0 0x8220
> +#define _VLV_PCS_DW8_CH1 0x8420
> +#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
> +#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
> +#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> +
> +#define _VLV_PCS01_DW8_CH0 0x0220
> +#define _VLV_PCS23_DW8_CH0 0x0420
> +#define _VLV_PCS01_DW8_CH1 0x2620
> +#define _VLV_PCS23_DW8_CH1 0x2820
> +#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
> +#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
> +
> +#define _VLV_PCS_DW9_CH0 0x8224
> +#define _VLV_PCS_DW9_CH1 0x8424
> +#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
> +#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
> +#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
> +#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
> +#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
> +#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
> +#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
> +
> +#define _VLV_PCS01_DW9_CH0 0x224
> +#define _VLV_PCS23_DW9_CH0 0x424
> +#define _VLV_PCS01_DW9_CH1 0x2624
> +#define _VLV_PCS23_DW9_CH1 0x2824
> +#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
> +#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
> +
> +#define _CHV_PCS_DW10_CH0 0x8228
> +#define _CHV_PCS_DW10_CH1 0x8428
> +#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
> +#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
> +#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
> +#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
> +#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
> +#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
> +#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
> +#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
> +#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
> +
> +#define _VLV_PCS01_DW10_CH0 0x0228
> +#define _VLV_PCS23_DW10_CH0 0x0428
> +#define _VLV_PCS01_DW10_CH1 0x2628
> +#define _VLV_PCS23_DW10_CH1 0x2828
> +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> +
> +#define _VLV_PCS_DW11_CH0 0x822c
> +#define _VLV_PCS_DW11_CH1 0x842c
> +#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
> +#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
> +#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
> +#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
> +#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> +
> +#define _VLV_PCS01_DW11_CH0 0x022c
> +#define _VLV_PCS23_DW11_CH0 0x042c
> +#define _VLV_PCS01_DW11_CH1 0x262c
> +#define _VLV_PCS23_DW11_CH1 0x282c
> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
> +
> +#define _VLV_PCS01_DW12_CH0 0x0230
> +#define _VLV_PCS23_DW12_CH0 0x0430
> +#define _VLV_PCS01_DW12_CH1 0x2630
> +#define _VLV_PCS23_DW12_CH1 0x2830
> +#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
> +#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
> +
> +#define _VLV_PCS_DW12_CH0 0x8230
> +#define _VLV_PCS_DW12_CH1 0x8430
> +#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
> +#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
> +#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
> +#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
> +#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
> +#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> +
> +#define _VLV_PCS_DW14_CH0 0x8238
> +#define _VLV_PCS_DW14_CH1 0x8438
> +#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
> +
> +#define _VLV_PCS_DW23_CH0 0x825c
> +#define _VLV_PCS_DW23_CH1 0x845c
> +#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
> +
> +#define _VLV_TX_DW2_CH0 0x8288
> +#define _VLV_TX_DW2_CH1 0x8488
> +#define DPIO_SWING_MARGIN000_SHIFT 16
> +#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
> +#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
> +#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
> +
> +#define _VLV_TX_DW3_CH0 0x828c
> +#define _VLV_TX_DW3_CH1 0x848c
> +/* The following bit for CHV phy */
> +#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
> +#define DPIO_SWING_MARGIN101_SHIFT 16
> +#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
> +#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
> +
> +#define _VLV_TX_DW4_CH0 0x8290
> +#define _VLV_TX_DW4_CH1 0x8490
> +#define DPIO_SWING_DEEMPH9P5_SHIFT 24
> +#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> +#define DPIO_SWING_DEEMPH6P0_SHIFT 16
> +#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> +#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
> +
> +#define _VLV_TX3_DW4_CH0 0x690
> +#define _VLV_TX3_DW4_CH1 0x2a90
> +#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
> +
> +#define _VLV_TX_DW5_CH0 0x8294
> +#define _VLV_TX_DW5_CH1 0x8494
> +#define DPIO_TX_OCALINIT_EN (1 << 31)
> +#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
> +
> +#define _VLV_TX_DW11_CH0 0x82ac
> +#define _VLV_TX_DW11_CH1 0x84ac
> +#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
> +
> +#define _VLV_TX_DW14_CH0 0x82b8
> +#define _VLV_TX_DW14_CH1 0x84b8
> +#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
> +
> +/* CHV dpPhy registers */
> +#define _CHV_PLL_DW0_CH0 0x8000
> +#define _CHV_PLL_DW0_CH1 0x8180
> +#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
> +
> +#define _CHV_PLL_DW1_CH0 0x8004
> +#define _CHV_PLL_DW1_CH1 0x8184
> +#define DPIO_CHV_N_DIV_SHIFT 8
> +#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
> +#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
> +
> +#define _CHV_PLL_DW2_CH0 0x8008
> +#define _CHV_PLL_DW2_CH1 0x8188
> +#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
> +
> +#define _CHV_PLL_DW3_CH0 0x800c
> +#define _CHV_PLL_DW3_CH1 0x818c
> +#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
> +#define DPIO_CHV_FIRST_MOD (0 << 8)
> +#define DPIO_CHV_SECOND_MOD (1 << 8)
> +#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
> +#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
> +#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
> +
> +#define _CHV_PLL_DW6_CH0 0x8018
> +#define _CHV_PLL_DW6_CH1 0x8198
> +#define DPIO_CHV_GAIN_CTRL_SHIFT 16
> +#define DPIO_CHV_INT_COEFF_SHIFT 8
> +#define DPIO_CHV_PROP_COEFF_SHIFT 0
> +#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
> +
> +#define _CHV_PLL_DW8_CH0 0x8020
> +#define _CHV_PLL_DW8_CH1 0x81A0
> +#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> +#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> +
> +#define _CHV_PLL_DW9_CH0 0x8024
> +#define _CHV_PLL_DW9_CH1 0x81A4
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> +
> +#define _CHV_CMN_DW0_CH0 0x8100
> +#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
> +#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
> +#define DPIO_ALLDL_POWERDOWN (1 << 1)
> +#define DPIO_ANYDL_POWERDOWN (1 << 0)
> +
> +#define _CHV_CMN_DW5_CH0 0x8114
> +#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
> +#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
> +#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
> +#define CHV_BUFRIGHTENA1_MASK (3 << 20)
> +#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
> +#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
> +#define CHV_BUFLEFTENA1_FORCE (3 << 22)
> +#define CHV_BUFLEFTENA1_MASK (3 << 22)
> +
> +#define _CHV_CMN_DW13_CH0 0x8134
> +#define _CHV_CMN_DW0_CH1 0x8080
> +#define DPIO_CHV_S1_DIV_SHIFT 21
> +#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
> +#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
> +#define DPIO_CHV_K_DIV_SHIFT 4
> +#define DPIO_PLL_FREQLOCK (1 << 1)
> +#define DPIO_PLL_LOCK (1 << 0)
> +#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
> +
> +#define _CHV_CMN_DW14_CH0 0x8138
> +#define _CHV_CMN_DW1_CH1 0x8084
> +#define DPIO_AFC_RECAL (1 << 14)
> +#define DPIO_DCLKP_EN (1 << 13)
> +#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
> +#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
> +#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
> +#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
> +#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
> +#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
> +#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
> +#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
> +#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
> +
> +#define _CHV_CMN_DW19_CH0 0x814c
> +#define _CHV_CMN_DW6_CH1 0x8098
> +#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
> +#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
> +#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
> +#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
> +
> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
> +
> +#define CHV_CMN_DW28 0x8170
> +#define DPIO_CL1POWERDOWNEN (1 << 23)
> +#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
> +#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
> +#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
> +#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
> +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
> +
> +#define CHV_CMN_DW30 0x8178
> +#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
> +#define DPIO_LRC_BYPASS (1 << 3)
> +
> +#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
> + (lane) * 0x200 + (offset))
> +
> +#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
> +#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
> +#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
> +#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
> +#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
> +#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
> +#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
> +#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
> +#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
> +#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
> +#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
> +#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
> +#define DPIO_FRC_LATENCY_SHFIT 8
> +#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
> +#define DPIO_UPAR_SHIFT 30
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb63c7214e12..86700c6caa27 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -195,349 +195,6 @@
> #define DPIO_SFR_BYPASS (1 << 1)
> #define DPIO_CMNRST (1 << 0)
>
> -/*
> - * Per pipe/PLL DPIO regs
> - */
> -#define _VLV_PLL_DW3_CH0 0x800c
> -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
> -#define DPIO_POST_DIV_DAC 0
> -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
> -#define DPIO_POST_DIV_LVDS1 2
> -#define DPIO_POST_DIV_LVDS2 3
> -#define DPIO_K_SHIFT (24) /* 4 bits */
> -#define DPIO_P1_SHIFT (21) /* 3 bits */
> -#define DPIO_P2_SHIFT (16) /* 5 bits */
> -#define DPIO_N_SHIFT (12) /* 4 bits */
> -#define DPIO_ENABLE_CALIBRATION (1 << 11)
> -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> -#define DPIO_M2DIV_MASK 0xff
> -#define _VLV_PLL_DW3_CH1 0x802c
> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
> -
> -#define _VLV_PLL_DW5_CH0 0x8014
> -#define DPIO_REFSEL_OVERRIDE 27
> -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
> -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
> -#define DPIO_PLL_REFCLK_SEL_MASK 3
> -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
> -#define _VLV_PLL_DW5_CH1 0x8034
> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
> -
> -#define _VLV_PLL_DW7_CH0 0x801c
> -#define _VLV_PLL_DW7_CH1 0x803c
> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
> -
> -#define _VLV_PLL_DW8_CH0 0x8040
> -#define _VLV_PLL_DW8_CH1 0x8060
> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
> -
> -#define VLV_PLL_DW9_BCAST 0xc044
> -#define _VLV_PLL_DW9_CH0 0x8044
> -#define _VLV_PLL_DW9_CH1 0x8064
> -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> -
> -#define _VLV_PLL_DW10_CH0 0x8048
> -#define _VLV_PLL_DW10_CH1 0x8068
> -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
> -
> -#define _VLV_PLL_DW11_CH0 0x804c
> -#define _VLV_PLL_DW11_CH1 0x806c
> -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
> -
> -/* Spec for ref block start counts at DW10 */
> -#define VLV_REF_DW13 0x80ac
> -
> -#define VLV_CMN_DW0 0x8100
> -
> -/*
> - * Per DDI channel DPIO regs
> - */
> -
> -#define _VLV_PCS_DW0_CH0 0x8200
> -#define _VLV_PCS_DW0_CH1 0x8400
> -#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
> -#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
> -#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
> -#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
> -#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> -
> -#define _VLV_PCS01_DW0_CH0 0x200
> -#define _VLV_PCS23_DW0_CH0 0x400
> -#define _VLV_PCS01_DW0_CH1 0x2600
> -#define _VLV_PCS23_DW0_CH1 0x2800
> -#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> -#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> -
> -#define _VLV_PCS_DW1_CH0 0x8204
> -#define _VLV_PCS_DW1_CH1 0x8404
> -#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
> -#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
> -#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
> -#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
> -#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
> -#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> -
> -#define _VLV_PCS01_DW1_CH0 0x204
> -#define _VLV_PCS23_DW1_CH0 0x404
> -#define _VLV_PCS01_DW1_CH1 0x2604
> -#define _VLV_PCS23_DW1_CH1 0x2804
> -#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> -#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> -
> -#define _VLV_PCS_DW8_CH0 0x8220
> -#define _VLV_PCS_DW8_CH1 0x8420
> -#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
> -#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
> -#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> -
> -#define _VLV_PCS01_DW8_CH0 0x0220
> -#define _VLV_PCS23_DW8_CH0 0x0420
> -#define _VLV_PCS01_DW8_CH1 0x2620
> -#define _VLV_PCS23_DW8_CH1 0x2820
> -#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
> -#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
> -
> -#define _VLV_PCS_DW9_CH0 0x8224
> -#define _VLV_PCS_DW9_CH1 0x8424
> -#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
> -#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
> -#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
> -#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
> -#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
> -#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
> -#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
> -
> -#define _VLV_PCS01_DW9_CH0 0x224
> -#define _VLV_PCS23_DW9_CH0 0x424
> -#define _VLV_PCS01_DW9_CH1 0x2624
> -#define _VLV_PCS23_DW9_CH1 0x2824
> -#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
> -#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
> -
> -#define _CHV_PCS_DW10_CH0 0x8228
> -#define _CHV_PCS_DW10_CH1 0x8428
> -#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
> -#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
> -#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
> -#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
> -#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
> -#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
> -#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
> -#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
> -#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
> -
> -#define _VLV_PCS01_DW10_CH0 0x0228
> -#define _VLV_PCS23_DW10_CH0 0x0428
> -#define _VLV_PCS01_DW10_CH1 0x2628
> -#define _VLV_PCS23_DW10_CH1 0x2828
> -#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> -#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> -
> -#define _VLV_PCS_DW11_CH0 0x822c
> -#define _VLV_PCS_DW11_CH1 0x842c
> -#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
> -#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
> -#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
> -#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
> -#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> -
> -#define _VLV_PCS01_DW11_CH0 0x022c
> -#define _VLV_PCS23_DW11_CH0 0x042c
> -#define _VLV_PCS01_DW11_CH1 0x262c
> -#define _VLV_PCS23_DW11_CH1 0x282c
> -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
> -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
> -
> -#define _VLV_PCS01_DW12_CH0 0x0230
> -#define _VLV_PCS23_DW12_CH0 0x0430
> -#define _VLV_PCS01_DW12_CH1 0x2630
> -#define _VLV_PCS23_DW12_CH1 0x2830
> -#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
> -#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
> -
> -#define _VLV_PCS_DW12_CH0 0x8230
> -#define _VLV_PCS_DW12_CH1 0x8430
> -#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
> -#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
> -#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
> -#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
> -#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
> -#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> -
> -#define _VLV_PCS_DW14_CH0 0x8238
> -#define _VLV_PCS_DW14_CH1 0x8438
> -#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
> -
> -#define _VLV_PCS_DW23_CH0 0x825c
> -#define _VLV_PCS_DW23_CH1 0x845c
> -#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
> -
> -#define _VLV_TX_DW2_CH0 0x8288
> -#define _VLV_TX_DW2_CH1 0x8488
> -#define DPIO_SWING_MARGIN000_SHIFT 16
> -#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
> -#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
> -#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
> -
> -#define _VLV_TX_DW3_CH0 0x828c
> -#define _VLV_TX_DW3_CH1 0x848c
> -/* The following bit for CHV phy */
> -#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
> -#define DPIO_SWING_MARGIN101_SHIFT 16
> -#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
> -#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
> -
> -#define _VLV_TX_DW4_CH0 0x8290
> -#define _VLV_TX_DW4_CH1 0x8490
> -#define DPIO_SWING_DEEMPH9P5_SHIFT 24
> -#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> -#define DPIO_SWING_DEEMPH6P0_SHIFT 16
> -#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> -#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
> -
> -#define _VLV_TX3_DW4_CH0 0x690
> -#define _VLV_TX3_DW4_CH1 0x2a90
> -#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
> -
> -#define _VLV_TX_DW5_CH0 0x8294
> -#define _VLV_TX_DW5_CH1 0x8494
> -#define DPIO_TX_OCALINIT_EN (1 << 31)
> -#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
> -
> -#define _VLV_TX_DW11_CH0 0x82ac
> -#define _VLV_TX_DW11_CH1 0x84ac
> -#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
> -
> -#define _VLV_TX_DW14_CH0 0x82b8
> -#define _VLV_TX_DW14_CH1 0x84b8
> -#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
> -
> -/* CHV dpPhy registers */
> -#define _CHV_PLL_DW0_CH0 0x8000
> -#define _CHV_PLL_DW0_CH1 0x8180
> -#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
> -
> -#define _CHV_PLL_DW1_CH0 0x8004
> -#define _CHV_PLL_DW1_CH1 0x8184
> -#define DPIO_CHV_N_DIV_SHIFT 8
> -#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
> -#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
> -
> -#define _CHV_PLL_DW2_CH0 0x8008
> -#define _CHV_PLL_DW2_CH1 0x8188
> -#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
> -
> -#define _CHV_PLL_DW3_CH0 0x800c
> -#define _CHV_PLL_DW3_CH1 0x818c
> -#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
> -#define DPIO_CHV_FIRST_MOD (0 << 8)
> -#define DPIO_CHV_SECOND_MOD (1 << 8)
> -#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
> -#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
> -#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
> -
> -#define _CHV_PLL_DW6_CH0 0x8018
> -#define _CHV_PLL_DW6_CH1 0x8198
> -#define DPIO_CHV_GAIN_CTRL_SHIFT 16
> -#define DPIO_CHV_INT_COEFF_SHIFT 8
> -#define DPIO_CHV_PROP_COEFF_SHIFT 0
> -#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
> -
> -#define _CHV_PLL_DW8_CH0 0x8020
> -#define _CHV_PLL_DW8_CH1 0x81A0
> -#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> -#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
> -#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> -
> -#define _CHV_PLL_DW9_CH0 0x8024
> -#define _CHV_PLL_DW9_CH1 0x81A4
> -#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
> -#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
> -#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
> -#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> -
> -#define _CHV_CMN_DW0_CH0 0x8100
> -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
> -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
> -#define DPIO_ALLDL_POWERDOWN (1 << 1)
> -#define DPIO_ANYDL_POWERDOWN (1 << 0)
> -
> -#define _CHV_CMN_DW5_CH0 0x8114
> -#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
> -#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
> -#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
> -#define CHV_BUFRIGHTENA1_MASK (3 << 20)
> -#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
> -#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
> -#define CHV_BUFLEFTENA1_FORCE (3 << 22)
> -#define CHV_BUFLEFTENA1_MASK (3 << 22)
> -
> -#define _CHV_CMN_DW13_CH0 0x8134
> -#define _CHV_CMN_DW0_CH1 0x8080
> -#define DPIO_CHV_S1_DIV_SHIFT 21
> -#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
> -#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
> -#define DPIO_CHV_K_DIV_SHIFT 4
> -#define DPIO_PLL_FREQLOCK (1 << 1)
> -#define DPIO_PLL_LOCK (1 << 0)
> -#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
> -
> -#define _CHV_CMN_DW14_CH0 0x8138
> -#define _CHV_CMN_DW1_CH1 0x8084
> -#define DPIO_AFC_RECAL (1 << 14)
> -#define DPIO_DCLKP_EN (1 << 13)
> -#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
> -#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
> -#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
> -#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
> -#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
> -#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
> -#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
> -#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
> -#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
> -
> -#define _CHV_CMN_DW19_CH0 0x814c
> -#define _CHV_CMN_DW6_CH1 0x8098
> -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
> -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
> -#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
> -#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
> -
> -#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
> -
> -#define CHV_CMN_DW28 0x8170
> -#define DPIO_CL1POWERDOWNEN (1 << 23)
> -#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
> -#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
> -#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
> -#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
> -#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
> -
> -#define CHV_CMN_DW30 0x8178
> -#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
> -#define DPIO_LRC_BYPASS (1 << 3)
> -
> -#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
> - (lane) * 0x200 + (offset))
> -
> -#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
> -#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
> -#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
> -#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
> -#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
> -#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
> -#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
> -#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
> -#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
> -#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
> -#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
> -#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
> -#define DPIO_FRC_LATENCY_SHFIT 8
> -#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
> -#define DPIO_UPAR_SHIFT 30
> -
> /* BXT PHY registers */
> #define _BXT_PHY0_BASE 0x6C000
> #define _BXT_PHY1_BASE 0x162000
> --
> 2.39.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-12 15:14 ` Ville Syrjälä
@ 2024-04-12 15:50 ` Jani Nikula
2024-04-12 16:26 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 15:50 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On Fri, 12 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Apr 12, 2024 at 05:52:55PM +0300, Jani Nikula wrote:
>> +/*
>> + * Framebuffer compression (915+ only)
>> + */
>
> Outdated comment. Looks like pretty much all the comments
> in this file are misleading/outdated. Maybe just nuke them
> all while at it.
Ack.
>> +#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
>
> Not an FBC register.
Whoops, this one was an accident.
>> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
>
> Also not an FBC register.
However this one was intentional. So the register isn't "an fbc
register", but the contents are all about fbc, and it's only used in
intel_fbc.c.
I guess after all reasonable topical things have been split out from
i915_reg.h, whatever display stuff is left will need to be put to a new
intel_display_regs.h or something. Things like this would then end up
there. Better or worse that way, I don't know.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
2024-04-12 15:31 ` Ville Syrjälä
@ 2024-04-12 15:52 ` Jani Nikula
0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2024-04-12 15:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On Fri, 12 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Apr 12, 2024 at 05:52:57PM +0300, Jani Nikula wrote:
>> Clean up i915_reg.h.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../i915/display/intel_display_power_well.c | 1 +
>> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
>> drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
>> drivers/gpu/drm/i915/display/vlv_dpio_regs.h | 352 ++++++++++++++++++
>> drivers/gpu/drm/i915/i915_reg.h | 343 -----------------
>> 5 files changed, 355 insertions(+), 343 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_regs.h
>
> I have pretty much the same thing, but IIRC I did a bunch of
> changes to the definitons first, and then extracted them.
> So the rebase could be somewhat painful.
>
> I suppose I should actually post my stuff and then we can
> figure out what to do with these...
Let's not waste the cleanups, the movement is the easy part.
BR,
Jani.
>
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index e4de40228997..0b356ff0e319 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -26,6 +26,7 @@
>> #include "intel_tc.h"
>> #include "intel_vga.h"
>> #include "skl_watermark.h"
>> +#include "vlv_dpio_regs.h"
>> #include "vlv_sideband.h"
>> #include "vlv_sideband_reg.h"
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
>> index 2d7a71c8c69c..8d99e00ea326 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
>> @@ -29,6 +29,7 @@
>> #include "intel_display_types.h"
>> #include "intel_dp.h"
>> #include "intel_dpio_phy.h"
>> +#include "vlv_dpio_regs.h"
>> #include "vlv_sideband.h"
>>
>> /**
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
>> index 3038655377ea..5c14bbd6ca82 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
>> @@ -20,6 +20,7 @@
>> #include "intel_panel.h"
>> #include "intel_pps.h"
>> #include "intel_snps_phy.h"
>> +#include "vlv_dpio_regs.h"
>> #include "vlv_sideband.h"
>>
>> struct intel_dpll_funcs {
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
>> new file mode 100644
>> index 000000000000..0982682c269f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/vlv_dpio_regs.h
>> @@ -0,0 +1,352 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/* Copyright © 2024 Intel Corporation */
>> +
>> +#ifndef __VLV_DPIO_REGS_H__
>> +#define __VLV_DPIO_REGS_H__
>> +
>> +#include "intel_display_reg_defs.h"
>> +
>> +/*
>> + * Per pipe/PLL DPIO regs
>> + */
>> +#define _VLV_PLL_DW3_CH0 0x800c
>> +#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
>> +#define DPIO_POST_DIV_DAC 0
>> +#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
>> +#define DPIO_POST_DIV_LVDS1 2
>> +#define DPIO_POST_DIV_LVDS2 3
>> +#define DPIO_K_SHIFT (24) /* 4 bits */
>> +#define DPIO_P1_SHIFT (21) /* 3 bits */
>> +#define DPIO_P2_SHIFT (16) /* 5 bits */
>> +#define DPIO_N_SHIFT (12) /* 4 bits */
>> +#define DPIO_ENABLE_CALIBRATION (1 << 11)
>> +#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
>> +#define DPIO_M2DIV_MASK 0xff
>> +#define _VLV_PLL_DW3_CH1 0x802c
>> +#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>> +
>> +#define _VLV_PLL_DW5_CH0 0x8014
>> +#define DPIO_REFSEL_OVERRIDE 27
>> +#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
>> +#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
>> +#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
>> +#define DPIO_PLL_REFCLK_SEL_MASK 3
>> +#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
>> +#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
>> +#define _VLV_PLL_DW5_CH1 0x8034
>> +#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>> +
>> +#define _VLV_PLL_DW7_CH0 0x801c
>> +#define _VLV_PLL_DW7_CH1 0x803c
>> +#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>> +
>> +#define _VLV_PLL_DW8_CH0 0x8040
>> +#define _VLV_PLL_DW8_CH1 0x8060
>> +#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>> +
>> +#define VLV_PLL_DW9_BCAST 0xc044
>> +#define _VLV_PLL_DW9_CH0 0x8044
>> +#define _VLV_PLL_DW9_CH1 0x8064
>> +#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
>> +
>> +#define _VLV_PLL_DW10_CH0 0x8048
>> +#define _VLV_PLL_DW10_CH1 0x8068
>> +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
>> +
>> +#define _VLV_PLL_DW11_CH0 0x804c
>> +#define _VLV_PLL_DW11_CH1 0x806c
>> +#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
>> +
>> +/* Spec for ref block start counts at DW10 */
>> +#define VLV_REF_DW13 0x80ac
>> +
>> +#define VLV_CMN_DW0 0x8100
>> +
>> +/*
>> + * Per DDI channel DPIO regs
>> + */
>> +
>> +#define _VLV_PCS_DW0_CH0 0x8200
>> +#define _VLV_PCS_DW0_CH1 0x8400
>> +#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
>> +#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
>> +#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
>> +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
>> +#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>> +
>> +#define _VLV_PCS01_DW0_CH0 0x200
>> +#define _VLV_PCS23_DW0_CH0 0x400
>> +#define _VLV_PCS01_DW0_CH1 0x2600
>> +#define _VLV_PCS23_DW0_CH1 0x2800
>> +#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
>> +#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
>> +
>> +#define _VLV_PCS_DW1_CH0 0x8204
>> +#define _VLV_PCS_DW1_CH1 0x8404
>> +#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
>> +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
>> +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
>> +#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
>> +#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
>> +#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
>> +
>> +#define _VLV_PCS01_DW1_CH0 0x204
>> +#define _VLV_PCS23_DW1_CH0 0x404
>> +#define _VLV_PCS01_DW1_CH1 0x2604
>> +#define _VLV_PCS23_DW1_CH1 0x2804
>> +#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
>> +#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
>> +
>> +#define _VLV_PCS_DW8_CH0 0x8220
>> +#define _VLV_PCS_DW8_CH1 0x8420
>> +#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
>> +#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
>> +#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>> +
>> +#define _VLV_PCS01_DW8_CH0 0x0220
>> +#define _VLV_PCS23_DW8_CH0 0x0420
>> +#define _VLV_PCS01_DW8_CH1 0x2620
>> +#define _VLV_PCS23_DW8_CH1 0x2820
>> +#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
>> +#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
>> +
>> +#define _VLV_PCS_DW9_CH0 0x8224
>> +#define _VLV_PCS_DW9_CH1 0x8424
>> +#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
>> +#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
>> +#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
>> +#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
>> +#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
>> +#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
>> +#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
>> +
>> +#define _VLV_PCS01_DW9_CH0 0x224
>> +#define _VLV_PCS23_DW9_CH0 0x424
>> +#define _VLV_PCS01_DW9_CH1 0x2624
>> +#define _VLV_PCS23_DW9_CH1 0x2824
>> +#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
>> +#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
>> +
>> +#define _CHV_PCS_DW10_CH0 0x8228
>> +#define _CHV_PCS_DW10_CH1 0x8428
>> +#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
>> +#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
>> +#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
>> +#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
>> +#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
>> +#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
>> +#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
>> +#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
>> +#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>> +
>> +#define _VLV_PCS01_DW10_CH0 0x0228
>> +#define _VLV_PCS23_DW10_CH0 0x0428
>> +#define _VLV_PCS01_DW10_CH1 0x2628
>> +#define _VLV_PCS23_DW10_CH1 0x2828
>> +#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
>> +#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
>> +
>> +#define _VLV_PCS_DW11_CH0 0x822c
>> +#define _VLV_PCS_DW11_CH1 0x842c
>> +#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
>> +#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
>> +#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
>> +#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
>> +#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
>> +
>> +#define _VLV_PCS01_DW11_CH0 0x022c
>> +#define _VLV_PCS23_DW11_CH0 0x042c
>> +#define _VLV_PCS01_DW11_CH1 0x262c
>> +#define _VLV_PCS23_DW11_CH1 0x282c
>> +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
>> +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
>> +
>> +#define _VLV_PCS01_DW12_CH0 0x0230
>> +#define _VLV_PCS23_DW12_CH0 0x0430
>> +#define _VLV_PCS01_DW12_CH1 0x2630
>> +#define _VLV_PCS23_DW12_CH1 0x2830
>> +#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
>> +#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
>> +
>> +#define _VLV_PCS_DW12_CH0 0x8230
>> +#define _VLV_PCS_DW12_CH1 0x8430
>> +#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
>> +#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
>> +#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
>> +#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
>> +#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
>> +#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
>> +
>> +#define _VLV_PCS_DW14_CH0 0x8238
>> +#define _VLV_PCS_DW14_CH1 0x8438
>> +#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
>> +
>> +#define _VLV_PCS_DW23_CH0 0x825c
>> +#define _VLV_PCS_DW23_CH1 0x845c
>> +#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
>> +
>> +#define _VLV_TX_DW2_CH0 0x8288
>> +#define _VLV_TX_DW2_CH1 0x8488
>> +#define DPIO_SWING_MARGIN000_SHIFT 16
>> +#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
>> +#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
>> +#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
>> +
>> +#define _VLV_TX_DW3_CH0 0x828c
>> +#define _VLV_TX_DW3_CH1 0x848c
>> +/* The following bit for CHV phy */
>> +#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
>> +#define DPIO_SWING_MARGIN101_SHIFT 16
>> +#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
>> +#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
>> +
>> +#define _VLV_TX_DW4_CH0 0x8290
>> +#define _VLV_TX_DW4_CH1 0x8490
>> +#define DPIO_SWING_DEEMPH9P5_SHIFT 24
>> +#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
>> +#define DPIO_SWING_DEEMPH6P0_SHIFT 16
>> +#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
>> +#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
>> +
>> +#define _VLV_TX3_DW4_CH0 0x690
>> +#define _VLV_TX3_DW4_CH1 0x2a90
>> +#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
>> +
>> +#define _VLV_TX_DW5_CH0 0x8294
>> +#define _VLV_TX_DW5_CH1 0x8494
>> +#define DPIO_TX_OCALINIT_EN (1 << 31)
>> +#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
>> +
>> +#define _VLV_TX_DW11_CH0 0x82ac
>> +#define _VLV_TX_DW11_CH1 0x84ac
>> +#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
>> +
>> +#define _VLV_TX_DW14_CH0 0x82b8
>> +#define _VLV_TX_DW14_CH1 0x84b8
>> +#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
>> +
>> +/* CHV dpPhy registers */
>> +#define _CHV_PLL_DW0_CH0 0x8000
>> +#define _CHV_PLL_DW0_CH1 0x8180
>> +#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
>> +
>> +#define _CHV_PLL_DW1_CH0 0x8004
>> +#define _CHV_PLL_DW1_CH1 0x8184
>> +#define DPIO_CHV_N_DIV_SHIFT 8
>> +#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
>> +#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
>> +
>> +#define _CHV_PLL_DW2_CH0 0x8008
>> +#define _CHV_PLL_DW2_CH1 0x8188
>> +#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
>> +
>> +#define _CHV_PLL_DW3_CH0 0x800c
>> +#define _CHV_PLL_DW3_CH1 0x818c
>> +#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
>> +#define DPIO_CHV_FIRST_MOD (0 << 8)
>> +#define DPIO_CHV_SECOND_MOD (1 << 8)
>> +#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
>> +#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
>> +#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>> +
>> +#define _CHV_PLL_DW6_CH0 0x8018
>> +#define _CHV_PLL_DW6_CH1 0x8198
>> +#define DPIO_CHV_GAIN_CTRL_SHIFT 16
>> +#define DPIO_CHV_INT_COEFF_SHIFT 8
>> +#define DPIO_CHV_PROP_COEFF_SHIFT 0
>> +#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>> +
>> +#define _CHV_PLL_DW8_CH0 0x8020
>> +#define _CHV_PLL_DW8_CH1 0x81A0
>> +#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
>> +#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
>> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>> +
>> +#define _CHV_PLL_DW9_CH0 0x8024
>> +#define _CHV_PLL_DW9_CH1 0x81A4
>> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
>> +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
>> +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
>> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>> +
>> +#define _CHV_CMN_DW0_CH0 0x8100
>> +#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
>> +#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
>> +#define DPIO_ALLDL_POWERDOWN (1 << 1)
>> +#define DPIO_ANYDL_POWERDOWN (1 << 0)
>> +
>> +#define _CHV_CMN_DW5_CH0 0x8114
>> +#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
>> +#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
>> +#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
>> +#define CHV_BUFRIGHTENA1_MASK (3 << 20)
>> +#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
>> +#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
>> +#define CHV_BUFLEFTENA1_FORCE (3 << 22)
>> +#define CHV_BUFLEFTENA1_MASK (3 << 22)
>> +
>> +#define _CHV_CMN_DW13_CH0 0x8134
>> +#define _CHV_CMN_DW0_CH1 0x8080
>> +#define DPIO_CHV_S1_DIV_SHIFT 21
>> +#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
>> +#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
>> +#define DPIO_CHV_K_DIV_SHIFT 4
>> +#define DPIO_PLL_FREQLOCK (1 << 1)
>> +#define DPIO_PLL_LOCK (1 << 0)
>> +#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
>> +
>> +#define _CHV_CMN_DW14_CH0 0x8138
>> +#define _CHV_CMN_DW1_CH1 0x8084
>> +#define DPIO_AFC_RECAL (1 << 14)
>> +#define DPIO_DCLKP_EN (1 << 13)
>> +#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
>> +#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
>> +#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
>> +#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
>> +#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
>> +#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
>> +#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
>> +#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
>> +#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>> +
>> +#define _CHV_CMN_DW19_CH0 0x814c
>> +#define _CHV_CMN_DW6_CH1 0x8098
>> +#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
>> +#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
>> +#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
>> +#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
>> +
>> +#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
>> +
>> +#define CHV_CMN_DW28 0x8170
>> +#define DPIO_CL1POWERDOWNEN (1 << 23)
>> +#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
>> +#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
>> +#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
>> +#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
>> +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
>> +
>> +#define CHV_CMN_DW30 0x8178
>> +#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
>> +#define DPIO_LRC_BYPASS (1 << 3)
>> +
>> +#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
>> + (lane) * 0x200 + (offset))
>> +
>> +#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
>> +#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
>> +#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
>> +#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
>> +#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
>> +#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
>> +#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
>> +#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
>> +#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
>> +#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
>> +#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
>> +#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
>> +#define DPIO_FRC_LATENCY_SHFIT 8
>> +#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>> +#define DPIO_UPAR_SHIFT 30
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index bb63c7214e12..86700c6caa27 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -195,349 +195,6 @@
>> #define DPIO_SFR_BYPASS (1 << 1)
>> #define DPIO_CMNRST (1 << 0)
>>
>> -/*
>> - * Per pipe/PLL DPIO regs
>> - */
>> -#define _VLV_PLL_DW3_CH0 0x800c
>> -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
>> -#define DPIO_POST_DIV_DAC 0
>> -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
>> -#define DPIO_POST_DIV_LVDS1 2
>> -#define DPIO_POST_DIV_LVDS2 3
>> -#define DPIO_K_SHIFT (24) /* 4 bits */
>> -#define DPIO_P1_SHIFT (21) /* 3 bits */
>> -#define DPIO_P2_SHIFT (16) /* 5 bits */
>> -#define DPIO_N_SHIFT (12) /* 4 bits */
>> -#define DPIO_ENABLE_CALIBRATION (1 << 11)
>> -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
>> -#define DPIO_M2DIV_MASK 0xff
>> -#define _VLV_PLL_DW3_CH1 0x802c
>> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>> -
>> -#define _VLV_PLL_DW5_CH0 0x8014
>> -#define DPIO_REFSEL_OVERRIDE 27
>> -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
>> -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
>> -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
>> -#define DPIO_PLL_REFCLK_SEL_MASK 3
>> -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
>> -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
>> -#define _VLV_PLL_DW5_CH1 0x8034
>> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>> -
>> -#define _VLV_PLL_DW7_CH0 0x801c
>> -#define _VLV_PLL_DW7_CH1 0x803c
>> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>> -
>> -#define _VLV_PLL_DW8_CH0 0x8040
>> -#define _VLV_PLL_DW8_CH1 0x8060
>> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>> -
>> -#define VLV_PLL_DW9_BCAST 0xc044
>> -#define _VLV_PLL_DW9_CH0 0x8044
>> -#define _VLV_PLL_DW9_CH1 0x8064
>> -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
>> -
>> -#define _VLV_PLL_DW10_CH0 0x8048
>> -#define _VLV_PLL_DW10_CH1 0x8068
>> -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
>> -
>> -#define _VLV_PLL_DW11_CH0 0x804c
>> -#define _VLV_PLL_DW11_CH1 0x806c
>> -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
>> -
>> -/* Spec for ref block start counts at DW10 */
>> -#define VLV_REF_DW13 0x80ac
>> -
>> -#define VLV_CMN_DW0 0x8100
>> -
>> -/*
>> - * Per DDI channel DPIO regs
>> - */
>> -
>> -#define _VLV_PCS_DW0_CH0 0x8200
>> -#define _VLV_PCS_DW0_CH1 0x8400
>> -#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
>> -#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
>> -#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
>> -#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
>> -#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
>> -
>> -#define _VLV_PCS01_DW0_CH0 0x200
>> -#define _VLV_PCS23_DW0_CH0 0x400
>> -#define _VLV_PCS01_DW0_CH1 0x2600
>> -#define _VLV_PCS23_DW0_CH1 0x2800
>> -#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
>> -#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
>> -
>> -#define _VLV_PCS_DW1_CH0 0x8204
>> -#define _VLV_PCS_DW1_CH1 0x8404
>> -#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
>> -#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
>> -#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
>> -#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
>> -#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
>> -#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
>> -
>> -#define _VLV_PCS01_DW1_CH0 0x204
>> -#define _VLV_PCS23_DW1_CH0 0x404
>> -#define _VLV_PCS01_DW1_CH1 0x2604
>> -#define _VLV_PCS23_DW1_CH1 0x2804
>> -#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
>> -#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
>> -
>> -#define _VLV_PCS_DW8_CH0 0x8220
>> -#define _VLV_PCS_DW8_CH1 0x8420
>> -#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
>> -#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
>> -#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
>> -
>> -#define _VLV_PCS01_DW8_CH0 0x0220
>> -#define _VLV_PCS23_DW8_CH0 0x0420
>> -#define _VLV_PCS01_DW8_CH1 0x2620
>> -#define _VLV_PCS23_DW8_CH1 0x2820
>> -#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
>> -#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
>> -
>> -#define _VLV_PCS_DW9_CH0 0x8224
>> -#define _VLV_PCS_DW9_CH1 0x8424
>> -#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
>> -#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
>> -#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
>> -#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
>> -#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
>> -#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
>> -#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
>> -
>> -#define _VLV_PCS01_DW9_CH0 0x224
>> -#define _VLV_PCS23_DW9_CH0 0x424
>> -#define _VLV_PCS01_DW9_CH1 0x2624
>> -#define _VLV_PCS23_DW9_CH1 0x2824
>> -#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
>> -#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
>> -
>> -#define _CHV_PCS_DW10_CH0 0x8228
>> -#define _CHV_PCS_DW10_CH1 0x8428
>> -#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
>> -#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
>> -#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
>> -#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
>> -#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
>> -#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
>> -#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
>> -#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
>> -#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
>> -
>> -#define _VLV_PCS01_DW10_CH0 0x0228
>> -#define _VLV_PCS23_DW10_CH0 0x0428
>> -#define _VLV_PCS01_DW10_CH1 0x2628
>> -#define _VLV_PCS23_DW10_CH1 0x2828
>> -#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
>> -#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
>> -
>> -#define _VLV_PCS_DW11_CH0 0x822c
>> -#define _VLV_PCS_DW11_CH1 0x842c
>> -#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
>> -#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
>> -#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
>> -#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
>> -#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
>> -
>> -#define _VLV_PCS01_DW11_CH0 0x022c
>> -#define _VLV_PCS23_DW11_CH0 0x042c
>> -#define _VLV_PCS01_DW11_CH1 0x262c
>> -#define _VLV_PCS23_DW11_CH1 0x282c
>> -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
>> -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
>> -
>> -#define _VLV_PCS01_DW12_CH0 0x0230
>> -#define _VLV_PCS23_DW12_CH0 0x0430
>> -#define _VLV_PCS01_DW12_CH1 0x2630
>> -#define _VLV_PCS23_DW12_CH1 0x2830
>> -#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
>> -#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
>> -
>> -#define _VLV_PCS_DW12_CH0 0x8230
>> -#define _VLV_PCS_DW12_CH1 0x8430
>> -#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
>> -#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
>> -#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
>> -#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
>> -#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
>> -#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
>> -
>> -#define _VLV_PCS_DW14_CH0 0x8238
>> -#define _VLV_PCS_DW14_CH1 0x8438
>> -#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
>> -
>> -#define _VLV_PCS_DW23_CH0 0x825c
>> -#define _VLV_PCS_DW23_CH1 0x845c
>> -#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
>> -
>> -#define _VLV_TX_DW2_CH0 0x8288
>> -#define _VLV_TX_DW2_CH1 0x8488
>> -#define DPIO_SWING_MARGIN000_SHIFT 16
>> -#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
>> -#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
>> -#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
>> -
>> -#define _VLV_TX_DW3_CH0 0x828c
>> -#define _VLV_TX_DW3_CH1 0x848c
>> -/* The following bit for CHV phy */
>> -#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
>> -#define DPIO_SWING_MARGIN101_SHIFT 16
>> -#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
>> -#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
>> -
>> -#define _VLV_TX_DW4_CH0 0x8290
>> -#define _VLV_TX_DW4_CH1 0x8490
>> -#define DPIO_SWING_DEEMPH9P5_SHIFT 24
>> -#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
>> -#define DPIO_SWING_DEEMPH6P0_SHIFT 16
>> -#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
>> -#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
>> -
>> -#define _VLV_TX3_DW4_CH0 0x690
>> -#define _VLV_TX3_DW4_CH1 0x2a90
>> -#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
>> -
>> -#define _VLV_TX_DW5_CH0 0x8294
>> -#define _VLV_TX_DW5_CH1 0x8494
>> -#define DPIO_TX_OCALINIT_EN (1 << 31)
>> -#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
>> -
>> -#define _VLV_TX_DW11_CH0 0x82ac
>> -#define _VLV_TX_DW11_CH1 0x84ac
>> -#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
>> -
>> -#define _VLV_TX_DW14_CH0 0x82b8
>> -#define _VLV_TX_DW14_CH1 0x84b8
>> -#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
>> -
>> -/* CHV dpPhy registers */
>> -#define _CHV_PLL_DW0_CH0 0x8000
>> -#define _CHV_PLL_DW0_CH1 0x8180
>> -#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
>> -
>> -#define _CHV_PLL_DW1_CH0 0x8004
>> -#define _CHV_PLL_DW1_CH1 0x8184
>> -#define DPIO_CHV_N_DIV_SHIFT 8
>> -#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
>> -#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
>> -
>> -#define _CHV_PLL_DW2_CH0 0x8008
>> -#define _CHV_PLL_DW2_CH1 0x8188
>> -#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
>> -
>> -#define _CHV_PLL_DW3_CH0 0x800c
>> -#define _CHV_PLL_DW3_CH1 0x818c
>> -#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
>> -#define DPIO_CHV_FIRST_MOD (0 << 8)
>> -#define DPIO_CHV_SECOND_MOD (1 << 8)
>> -#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
>> -#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
>> -#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>> -
>> -#define _CHV_PLL_DW6_CH0 0x8018
>> -#define _CHV_PLL_DW6_CH1 0x8198
>> -#define DPIO_CHV_GAIN_CTRL_SHIFT 16
>> -#define DPIO_CHV_INT_COEFF_SHIFT 8
>> -#define DPIO_CHV_PROP_COEFF_SHIFT 0
>> -#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>> -
>> -#define _CHV_PLL_DW8_CH0 0x8020
>> -#define _CHV_PLL_DW8_CH1 0x81A0
>> -#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
>> -#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
>> -#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>> -
>> -#define _CHV_PLL_DW9_CH0 0x8024
>> -#define _CHV_PLL_DW9_CH1 0x81A4
>> -#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
>> -#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
>> -#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
>> -#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>> -
>> -#define _CHV_CMN_DW0_CH0 0x8100
>> -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
>> -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
>> -#define DPIO_ALLDL_POWERDOWN (1 << 1)
>> -#define DPIO_ANYDL_POWERDOWN (1 << 0)
>> -
>> -#define _CHV_CMN_DW5_CH0 0x8114
>> -#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
>> -#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
>> -#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
>> -#define CHV_BUFRIGHTENA1_MASK (3 << 20)
>> -#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
>> -#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
>> -#define CHV_BUFLEFTENA1_FORCE (3 << 22)
>> -#define CHV_BUFLEFTENA1_MASK (3 << 22)
>> -
>> -#define _CHV_CMN_DW13_CH0 0x8134
>> -#define _CHV_CMN_DW0_CH1 0x8080
>> -#define DPIO_CHV_S1_DIV_SHIFT 21
>> -#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
>> -#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
>> -#define DPIO_CHV_K_DIV_SHIFT 4
>> -#define DPIO_PLL_FREQLOCK (1 << 1)
>> -#define DPIO_PLL_LOCK (1 << 0)
>> -#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
>> -
>> -#define _CHV_CMN_DW14_CH0 0x8138
>> -#define _CHV_CMN_DW1_CH1 0x8084
>> -#define DPIO_AFC_RECAL (1 << 14)
>> -#define DPIO_DCLKP_EN (1 << 13)
>> -#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
>> -#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
>> -#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
>> -#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
>> -#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
>> -#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
>> -#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
>> -#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
>> -#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
>> -
>> -#define _CHV_CMN_DW19_CH0 0x814c
>> -#define _CHV_CMN_DW6_CH1 0x8098
>> -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
>> -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
>> -#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
>> -#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
>> -
>> -#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
>> -
>> -#define CHV_CMN_DW28 0x8170
>> -#define DPIO_CL1POWERDOWNEN (1 << 23)
>> -#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
>> -#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
>> -#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
>> -#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
>> -#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
>> -
>> -#define CHV_CMN_DW30 0x8178
>> -#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
>> -#define DPIO_LRC_BYPASS (1 << 3)
>> -
>> -#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
>> - (lane) * 0x200 + (offset))
>> -
>> -#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
>> -#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
>> -#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
>> -#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
>> -#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
>> -#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
>> -#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
>> -#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
>> -#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
>> -#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
>> -#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
>> -#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
>> -#define DPIO_FRC_LATENCY_SHFIT 8
>> -#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
>> -#define DPIO_UPAR_SHIFT 30
>> -
>> /* BXT PHY registers */
>> #define _BXT_PHY0_BASE 0x6C000
>> #define _BXT_PHY1_BASE 0x162000
>> --
>> 2.39.2
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
2024-04-12 15:50 ` Jani Nikula
@ 2024-04-12 16:26 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2024-04-12 16:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Fri, Apr 12, 2024 at 06:50:57PM +0300, Jani Nikula wrote:
> On Fri, 12 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Apr 12, 2024 at 05:52:55PM +0300, Jani Nikula wrote:
> >> +/*
> >> + * Framebuffer compression (915+ only)
> >> + */
> >
> > Outdated comment. Looks like pretty much all the comments
> > in this file are misleading/outdated. Maybe just nuke them
> > all while at it.
>
> Ack.
>
> >> +#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
> >
> > Not an FBC register.
>
> Whoops, this one was an accident.
>
> >> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
> >
> > Also not an FBC register.
>
> However this one was intentional. So the register isn't "an fbc
> register", but the contents are all about fbc,
Only the bits we have thus far defined. There's other stuff
in there that we haven't bothered to name.
> and it's only used in
> intel_fbc.c.
I don't think we should place chicken register/etc definitons based
purely on where it might be currently used. That may change at any
point when we discover a new chicken bit that needs to be flipped.
At that point the defintion would have to be moved again, or what
seems rather likely to happen, people will overlook the existing
definiton and add a duplicate elsewhere.
>
> I guess after all reasonable topical things have been split out from
> i915_reg.h, whatever display stuff is left will need to be put to a new
> intel_display_regs.h or something. Things like this would then end up
> there. Better or worse that way, I don't know.
Yeah, there are a bunch of "these don't really belong anywhere"
registers. Though maybe this kind of non-specific chicken registers
could even live in the intel_chicken_regs.h file. Shrug.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_reg.h cleanups
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (5 preceding siblings ...)
2024-04-12 14:52 ` [PATCH 6/6] drm/i915/display: split out bxt_phy_regs.h " Jani Nikula
@ 2024-04-15 12:23 ` Patchwork
2024-04-15 12:37 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 15:53 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-04-15 12:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: i915_reg.h cleanups
URL : https://patchwork.freedesktop.org/series/132381/
State : warning
== Summary ==
Error: dim checkpatch failed
19e68395cec8 drm/i915/audio: move LPE audio regs to intel_audio_regs.h
dfbe99d107b3 drm/i915/color: move palette registers to intel_color_regs.h
abfc95490d07 drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:23: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#23:
new file mode 100644
-:91: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#91: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:64:
+#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
-:94: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:67:
+#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
-:98: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:71:
+#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
-:154: CHECK:LINE_SPACING: Please don't use multiple blank lines
#154: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:127:
+
+
total: 0 errors, 4 warnings, 1 checks, 340 lines checked
3a0f5dc85170 drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
-:131: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#131: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:99:
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-:132: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#132: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:100:
+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
-:133: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns
#133: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:101:
+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
-:145: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:113:
+#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
-:326: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#326: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:294:
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-:329: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#329: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:297:
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-:331: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#331: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:299:
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-:332: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#332: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:300:
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
-:335: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:303:
+#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
total: 0 errors, 10 warnings, 0 checks, 745 lines checked
08ff131d6a15 drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:47: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#47:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 722 lines checked
566b3d7419f6 drm/i915/display: split out bxt_phy_regs.h from i915_reg.h
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:11: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
-:232: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects?
#232: FILE: drivers/gpu/drm/i915/display/bxt_phy_regs.h:217:
+#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)
total: 0 errors, 1 warnings, 1 checks, 637 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: i915_reg.h cleanups
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (6 preceding siblings ...)
2024-04-15 12:23 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_reg.h cleanups Patchwork
@ 2024-04-15 12:37 ` Patchwork
2024-04-15 15:53 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-04-15 12:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4654 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h cleanups
URL : https://patchwork.freedesktop.org/series/132381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14572 -> Patchwork_132381v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/index.html
Participating hosts (40 -> 38)
------------------------------
Additional (2): bat-kbl-2 fi-cfl-8109u
Missing (4): fi-kbl-8809g fi-elk-e7500 fi-snb-2520m bat-arls-3
Known issues
------------
Here are the changes found in Patchwork_132381v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][1] ([i915#1849])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/bat-kbl-2/igt@fbdev@info.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][3] +39 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@gtt:
- bat-arls-2: [PASS][5] -> [ABORT][6] ([i915#10677])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/bat-arls-2/igt@i915_selftest@live@gtt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/bat-arls-2/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@hugepages:
- fi-apl-guc: [PASS][7] -> [ABORT][8] ([i915#10461])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/fi-apl-guc/igt@i915_selftest@live@hugepages.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/fi-apl-guc/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@perf:
- bat-dg2-8: [PASS][9] -> [ABORT][10] ([i915#10366])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/bat-dg2-8/igt@i915_selftest@live@perf.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/bat-dg2-8/igt@i915_selftest@live@perf.html
* igt@kms_pm_backlight@basic-brightness:
- fi-cfl-8109u: NOTRUN -> [SKIP][11] +11 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/fi-cfl-8109u/igt@kms_pm_backlight@basic-brightness.html
#### Possible fixes ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [FAIL][12] ([i915#10378]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
[i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10461]: https://gitlab.freedesktop.org/drm/intel/issues/10461
[i915#10677]: https://gitlab.freedesktop.org/drm/intel/issues/10677
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
Build changes
-------------
* Linux: CI_DRM_14572 -> Patchwork_132381v1
CI-20190529: 20190529
CI_DRM_14572: 85eef611f85be84edeabab83debdbb1fabeba066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7806: 849cd963ce7e8222dcf17cc872d355181fd2c2a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132381v1: 85eef611f85be84edeabab83debdbb1fabeba066 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a72891e8eab8 drm/i915/display: split out bxt_phy_regs.h from i915_reg.h
d1706507aa57 drm/i915/display: split out intel_dpio_regs.h from i915_reg.h
3252ba27c86b drm/i915/display: split out intel_sprite_regs.h from i915_reg.h
f20203ff0022 drm/i915/display: split out intel_fbc_regs.h from i915_reg.h
44475679c3a6 drm/i915/color: move palette registers to intel_color_regs.h
837e2cec47b2 drm/i915/audio: move LPE audio regs to intel_audio_regs.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/index.html
[-- Attachment #2: Type: text/html, Size: 5512 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: i915_reg.h cleanups
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
` (7 preceding siblings ...)
2024-04-15 12:37 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-04-15 15:53 ` Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2024-04-15 15:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 82179 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h cleanups
URL : https://patchwork.freedesktop.org/series/132381/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14572_full -> Patchwork_132381v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_132381v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_132381v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_132381v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@drm_fdinfo@context-close-stress:
- shard-dg1: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@drm_fdinfo@context-close-stress.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-2:
- shard-glk: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-2.html
Known issues
------------
Here are the changes found in Patchwork_132381v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-mtlp: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [FAIL][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-2/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-2/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-4/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-4/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-4/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-8/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-4/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-4/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-8/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#9318])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#7701])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#8414])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@drm_fdinfo@all-busy-idle-check-all.html
* igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8414]) +6 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@drm_fdinfo@busy-hang@rcs0.html
* igt@drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#8414])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@drm_fdinfo@virtual-busy-hang-all.html
* igt@gem_ccs@suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][55] ([i915#9323])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_ccs@suspend-resume.html
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#9323])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#7697])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#8555])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#280])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@mmap-args:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#280])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_ctx_sseu@mmap-args.html
- shard-tglu: NOTRUN -> [SKIP][61] ([i915#280])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4771])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#4036])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_exec_balancer@invalid-bonds.html
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#4036])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_capture@many-4k-zero:
- shard-mtlp: NOTRUN -> [FAIL][65] ([i915#9606])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none-share:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#3539] / [i915#4852])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_exec_fair@basic-none-share.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglu: [PASS][67] -> [FAIL][68] ([i915#2842]) +1 other test fail
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4473])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-pace-share:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#3539] / [i915#4852]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_exec_fair@basic-pace-share.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][71] -> [FAIL][72] ([i915#2842]) +1 other test fail
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-5/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#3539])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3281])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-scanout:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#3281])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#3281]) +5 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#3281]) +5 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#4812]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][79] ([i915#4860]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#4860]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4860]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#4613]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#4613])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][84] ([i915#10378])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][85] ([i915#4613]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk3/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][86] -> [TIMEOUT][87] ([i915#5493])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [PASS][88] -> [TIMEOUT][89] ([i915#5493])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#4613])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_mmap@bad-object:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#4083]) +6 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_mmap@bad-object.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#4077]) +8 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#4077]) +6 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#4077]) +4 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_wc@bad-offset:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#4083]) +3 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@gem_mmap_wc@bad-offset.html
* igt@gem_mmap_wc@set-cache-level:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4083])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#3282])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_partial_pwrite_pread@write-display.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][98] ([i915#2658])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk3/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-regular-buffer:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#4270])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-tglu: NOTRUN -> [SKIP][100] ([i915#4270])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#4270]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#4270]) +3 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#4270]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_readwrite@read-bad-handle:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#3282]) +3 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_readwrite@read-bad-handle.html
* igt@gem_readwrite@write-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#3282]) +6 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#8428]) +2 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#5190] / [i915#8428])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#3282] / [i915#3297])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#3297])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-rkl: NOTRUN -> [SKIP][110] ([i915#3297])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#3297]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_userptr_blits@unsync-unmap-cycles.html
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#3297]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglu: NOTRUN -> [SKIP][113] ([i915#2527] / [i915#2856])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@batch-without-end:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#2856])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-dg1: NOTRUN -> [SKIP][115] ([i915#2527]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@bb-large:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#2527])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#2856]) +1 other test skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_module_load@load:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#6227])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: NOTRUN -> [ABORT][119] ([i915#10131] / [i915#9820])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rps@basic-api:
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#6621]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#6621])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#8925])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@i915_pm_rps@thresholds-idle@gt1:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8925])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@i915_pm_rps@thresholds-idle@gt1.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#6188])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_selftest@live@gem:
- shard-dg2: [PASS][125] -> [ABORT][126] ([i915#10366])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-8/igt@i915_selftest@live@gem.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-6/igt@i915_selftest@live@gem.html
* igt@i915_selftest@mock@memory_region:
- shard-dg1: NOTRUN -> [DMESG-WARN][127] ([i915#9311])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][128] -> [FAIL][129] ([i915#10031])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#5190])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg1: NOTRUN -> [SKIP][131] ([i915#4212])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#4212])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][133] ([i915#10333])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_async_flips@test-cursor.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][134] ([i915#3555])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#5286]) +1 other test skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#5286])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#4538] / [i915#5286]) +2 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#5286])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#3638])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][140] +4 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: [PASS][141] -> [FAIL][142] ([i915#3743]) +1 other test fail
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-tglu-5/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#6187])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][144] +13 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#4538] / [i915#5190]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][146] +24 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#4538]) +5 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#10656])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_big_joiner@invalid-modeset.html
- shard-tglu: NOTRUN -> [SKIP][149] ([i915#10656])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-10/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#6095]) +59 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-14/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-4.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#10307] / [i915#6095]) +174 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-10/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][153] ([i915#6095]) +69 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][154] ([i915#10278]) +1 other test skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#6095]) +23 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-a-edp-1.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#6095]) +11 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][157] +231 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk4/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#4087]) +3 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-2/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-rkl: NOTRUN -> [SKIP][159] +9 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#7828]) +1 other test skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-dg1: NOTRUN -> [SKIP][161] ([i915#7828]) +5 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#7828]) +1 other test skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][163] ([i915#7828]) +5 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#7828]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@atomic-dpms:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#6944] / [i915#9424])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_content_protection@atomic-dpms.html
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#7116] / [i915#9424])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#7118] / [i915#7162] / [i915#9424])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-256x85:
- shard-mtlp: NOTRUN -> [SKIP][168] ([i915#8814])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8814]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#3359])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#3359])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#3359]) +1 other test skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#3359])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-tglu: NOTRUN -> [SKIP][174] ([i915#3555])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#4103])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#9809]) +3 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-snb: [PASS][177] -> [SKIP][178] +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-snb1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-snb2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#9067])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#4103] / [i915#4213])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#9833])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#9227])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-10/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#9723])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
* igt@kms_fbcon_fbt@psr:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#3469])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_fbcon_fbt@psr.html
- shard-tglu: NOTRUN -> [SKIP][185] ([i915#3469])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@display-2x:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#1839])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg1: NOTRUN -> [SKIP][187] ([i915#9337])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_feature_discovery@dp-mst.html
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#9337])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#658])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#3637]) +3 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#9934]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@blocking-wf_vblank@b-vga1:
- shard-snb: [PASS][192] -> [FAIL][193] ([i915#2122]) +1 other test fail
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-snb4/igt@kms_flip@blocking-wf_vblank@b-vga1.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-snb7/igt@kms_flip@blocking-wf_vblank@b-vga1.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [PASS][194] -> [FAIL][195] ([i915#79])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_flip@plain-flip-ts-check@b-hdmi-a4:
- shard-dg1: [PASS][196] -> [FAIL][197] ([i915#2122]) +3 other tests fail
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-16/igt@kms_flip@plain-flip-ts-check@b-hdmi-a4.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-15/igt@kms_flip@plain-flip-ts-check@b-hdmi-a4.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#8810])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#2672])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#2672])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][201] ([i915#2672]) +3 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#2587] / [i915#2672]) +3 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][203] ([i915#2587] / [i915#2672]) +1 other test skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#2672] / [i915#3555]) +1 other test skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#5354]) +8 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#3458]) +4 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][207] ([i915#1825]) +11 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#8708])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#1825]) +17 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#3458]) +10 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#9766])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#8708]) +11 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#3023]) +7 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][214] ([i915#8708]) +7 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#3555] / [i915#8228])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][216]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-snb6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][217] ([i915#10647]) +1 other test fail
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#3582]) +3 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html
* igt@kms_plane_multiple@tiling-4:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#3555]) +2 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_plane_multiple@tiling-4.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-mtlp: NOTRUN -> [SKIP][220] ([i915#6953])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][221] ([i915#8292])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#9423]) +7 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#9423]) +3 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][224] ([i915#9423]) +3 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#9423]) +11 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#5176] / [i915#9423]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-c-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-c-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#5235]) +9 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][229] ([i915#5235]) +7 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][230] ([i915#3555] / [i915#5235]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][231] ([i915#5235]) +9 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#5235] / [i915#9423]) +15 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg1: NOTRUN -> [SKIP][233] ([i915#9519])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2: [PASS][234] -> [SKIP][235] ([i915#9519]) +1 other test skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-1/igt@kms_pm_rpm@dpms-non-lpsp.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-10/igt@kms_pm_rpm@dpms-non-lpsp.html
- shard-rkl: [PASS][236] -> [SKIP][237] ([i915#9519]) +1 other test skip
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-1/igt@kms_pm_rpm@dpms-non-lpsp.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-2/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#9519])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-dg1: NOTRUN -> [SKIP][239] +37 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#9683])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#9683])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-dg1: NOTRUN -> [SKIP][242] ([i915#1072] / [i915#9732]) +15 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@fbc-pr-cursor-render:
- shard-mtlp: NOTRUN -> [SKIP][243] ([i915#9688]) +9 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_psr@fbc-pr-cursor-render.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@psr-primary-render:
- shard-tglu: NOTRUN -> [SKIP][245] ([i915#9732]) +4 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_psr@psr-primary-render.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][246] ([i915#1072] / [i915#9732]) +6 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#4235] / [i915#5190])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-mtlp: NOTRUN -> [SKIP][248] ([i915#5289])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg1: NOTRUN -> [SKIP][249] ([i915#5289])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
- shard-mtlp: NOTRUN -> [SKIP][250] ([i915#4235])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#5030]) +2 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][252] ([i915#5030] / [i915#9041])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html
* igt@kms_sysfs_edid_timing:
- shard-dg1: NOTRUN -> [FAIL][253] ([IGT#2] / [i915#6493])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][254] ([i915#8623])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
- shard-mtlp: [PASS][255] -> [FAIL][256] ([i915#9196]) +1 other test fail
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: NOTRUN -> [SKIP][257] ([i915#9906])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-fb-id:
- shard-mtlp: NOTRUN -> [SKIP][258] ([i915#2437])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][259] ([i915#2437] / [i915#9412])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-tglu: NOTRUN -> [SKIP][260] ([i915#2437] / [i915#9412])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-glk: NOTRUN -> [SKIP][261] ([i915#2437])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-rkl: NOTRUN -> [SKIP][262] ([i915#2437])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@global-sseu-config:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#7387])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@perf@global-sseu-config.html
* igt@perf@per-context-mode-unprivileged:
- shard-dg1: NOTRUN -> [SKIP][264] ([i915#2433])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-mtlp: NOTRUN -> [FAIL][265] ([i915#4349]) +1 other test fail
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-2/igt@perf_pmu@busy-double-start@rcs0.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][266] ([i915#9781])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@tools_test@sysfs_l3_parity:
- shard-dg2: NOTRUN -> [SKIP][267] ([i915#4818])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_get_bo_offset@create-get-offsets:
- shard-mtlp: NOTRUN -> [SKIP][268] ([i915#2575]) +5 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@v3d/v3d_get_bo_offset@create-get-offsets.html
* igt@v3d/v3d_submit_cl@bad-extension:
- shard-dg1: NOTRUN -> [SKIP][269] ([i915#2575]) +8 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@v3d/v3d_submit_cl@bad-extension.html
* igt@v3d/v3d_submit_csd@bad-in-sync:
- shard-dg2: NOTRUN -> [SKIP][270] ([i915#2575]) +1 other test skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@v3d/v3d_submit_csd@bad-in-sync.html
* igt@v3d/v3d_submit_csd@bad-pad:
- shard-tglu: NOTRUN -> [SKIP][271] ([i915#2575]) +4 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-4/igt@v3d/v3d_submit_csd@bad-pad.html
* igt@vc4/vc4_create_bo@create-bo-0:
- shard-mtlp: NOTRUN -> [SKIP][272] ([i915#7711]) +5 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-6/igt@vc4/vc4_create_bo@create-bo-0.html
* igt@vc4/vc4_perfmon@destroy-valid-perfmon:
- shard-dg2: NOTRUN -> [SKIP][273] ([i915#7711]) +1 other test skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@vc4/vc4_perfmon@destroy-valid-perfmon.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
- shard-dg1: NOTRUN -> [SKIP][274] ([i915#7711]) +4 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-17/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html
* igt@vc4/vc4_tiling@set-bad-modifier:
- shard-rkl: NOTRUN -> [SKIP][275] ([i915#7711]) +2 other tests skip
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@vc4/vc4_tiling@set-bad-modifier.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: [FAIL][276] ([i915#7742]) -> [PASS][277] +1 other test pass
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-3/igt@drm_fdinfo@idle@rcs0.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][278] ([i915#6268]) -> [PASS][279]
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@kms:
- shard-tglu: [INCOMPLETE][280] ([i915#10513]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-tglu-9/igt@gem_eio@kms.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-3/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][282] ([i915#2842]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [FAIL][284] ([i915#10378]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_pipe_control_store_loop@reused-buffer:
- shard-dg1: [DMESG-WARN][286] ([i915#4423]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-18/igt@gem_pipe_control_store_loop@reused-buffer.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@gem_pipe_control_store_loop@reused-buffer.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [INCOMPLETE][288] ([i915#9820] / [i915#9849]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][290] ([i915#3591]) -> [PASS][291]
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_power@sanity:
- shard-mtlp: [SKIP][292] ([i915#7984]) -> [PASS][293]
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-1/igt@i915_power@sanity.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-3/igt@i915_power@sanity.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-2:
- shard-glk: [FAIL][294] ([i915#2521]) -> [PASS][295]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-glk5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-2.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-2.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: [FAIL][296] ([i915#3743]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][298] ([i915#2122]) -> [PASS][299] +1 other test pass
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-snb6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][300] ([i915#9519]) -> [PASS][301] +2 other tests pass
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-3/igt@kms_pm_rpm@dpms-lpsp.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [FAIL][302] ([IGT#2]) -> [PASS][303]
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-10/igt@kms_sysfs_edid_timing.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_sysfs_edid_timing.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-mtlp: [FAIL][304] ([i915#9196]) -> [PASS][305]
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-rkl: [FAIL][306] ([i915#9196]) -> [PASS][307]
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][308] ([i915#9196]) -> [PASS][309]
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][310] ([i915#4349]) -> [PASS][311]
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-3/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-3/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [INCOMPLETE][312] ([i915#9364]) -> [ABORT][313] ([i915#9846])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [ABORT][314] ([i915#9820]) -> [INCOMPLETE][315] ([i915#9820] / [i915#9849])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-dg2: [SKIP][316] ([i915#10433] / [i915#3458]) -> [SKIP][317] ([i915#3458])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg1: [SKIP][318] ([i915#4423] / [i915#8708]) -> [SKIP][319] ([i915#8708])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][320] ([i915#4070] / [i915#4816]) -> [SKIP][321] ([i915#4816])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][322] ([i915#3361]) -> [SKIP][323] ([i915#4281])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: [SKIP][324] ([i915#1072] / [i915#9732]) -> [SKIP][325] ([i915#1072] / [i915#9673] / [i915#9732]) +6 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-4/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][326] ([i915#7484]) -> [FAIL][327] ([i915#9100])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14572/shard-dg2-6/igt@perf@non-zero-reason@0-rcs0.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10031]: https://gitlab.freedesktop.org/drm/intel/issues/10031
[i915#10131]: https://gitlab.freedesktop.org/drm/intel/issues/10131
[i915#10278]: https://gitlab.freedesktop.org/drm/intel/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#10333]: https://gitlab.freedesktop.org/drm/intel/issues/10333
[i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
[i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/intel/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/intel/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/intel/issues/10513
[i915#10647]: https://gitlab.freedesktop.org/drm/intel/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/intel/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9041]: https://gitlab.freedesktop.org/drm/intel/issues/9041
[i915#9067]: https://gitlab.freedesktop.org/drm/intel/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/intel/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/intel/issues/9227
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9364]: https://gitlab.freedesktop.org/drm/intel/issues/9364
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/intel/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/intel/issues/9766
[i915#9781]: https://gitlab.freedesktop.org/drm/intel/issues/9781
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9846]: https://gitlab.freedesktop.org/drm/intel/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14572 -> Patchwork_132381v1
CI-20190529: 20190529
CI_DRM_14572: 85eef611f85be84edeabab83debdbb1fabeba066 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7806: 849cd963ce7e8222dcf17cc872d355181fd2c2a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132381v1: 85eef611f85be84edeabab83debdbb1fabeba066 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132381v1/index.html
[-- Attachment #2: Type: text/html, Size: 99378 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-04-15 15:53 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
2024-04-12 15:15 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
2024-04-12 15:19 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
2024-04-12 15:14 ` Ville Syrjälä
2024-04-12 15:50 ` Jani Nikula
2024-04-12 16:26 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
2024-04-12 15:22 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h " Jani Nikula
2024-04-12 15:31 ` Ville Syrjälä
2024-04-12 15:52 ` Jani Nikula
2024-04-12 14:52 ` [PATCH 6/6] drm/i915/display: split out bxt_phy_regs.h " Jani Nikula
2024-04-15 12:23 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_reg.h cleanups Patchwork
2024-04-15 12:37 ` ✓ Fi.CI.BAT: success " Patchwork
2024-04-15 15:53 ` ✗ Fi.CI.IGT: failure " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox