* [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
@ 2024-05-15 16:56 ` Jani Nikula
2024-05-16 13:25 ` Rodrigo Vivi
2024-05-16 13:25 ` Rodrigo Vivi
2024-05-15 18:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Patchwork
` (5 subsequent siblings)
6 siblings, 2 replies; 11+ messages in thread
From: Jani Nikula @ 2024-05-15 16:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Lucas De Marchi, Rodrigo Vivi
Now that the PCI ID macros allow us to pass in the macro to use, stop
redefining INTEL_VGA_DEVICE.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_device.c | 87 +++++++++---------
drivers/gpu/drm/i915/intel_device_info.c | 91 +++++++++----------
2 files changed, 88 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 950e66cdba0a..cf093bc0cb28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
return pci_match_id(ids, pdev);
}
-#undef INTEL_VGA_DEVICE
-#define INTEL_VGA_DEVICE(id, info) { id, info }
+#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
static const struct {
u32 devid;
const struct intel_display_device_info *info;
} intel_display_ids[] = {
- INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display),
- INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display),
- INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display),
- INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display),
- INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display),
- INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display),
- INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display),
- INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display),
- INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display),
- INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display),
- INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display),
- INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display),
- INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display),
- INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display),
- INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display),
- INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display),
- INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display),
- INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display),
- INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display),
- INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display),
- INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display),
- INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display),
- INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display),
- INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display),
- INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display),
- INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display),
- INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display),
- INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display),
- INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display),
- INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display),
- INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
- INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
- INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display),
- INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display),
- INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display),
- INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
- INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
- INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
- INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
- INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
- INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
- INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display),
+ INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display),
+ INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display),
+ INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display),
+ INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display),
+ INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display),
+ INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display),
+ INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display),
+ INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display),
+ INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display),
+ INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display),
+ INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display),
+ INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display),
+ INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display),
+ INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display),
+ INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display),
+ INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display),
+ INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display),
+ INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display),
+ INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display),
+ INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display),
+ INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display),
+ INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display),
+ INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
+ INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display),
+ INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display),
+ INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
+ INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
+ INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
+ INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
+ INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display),
+ INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
+ INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
+ INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display),
+ INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display),
+ INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display),
+ INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
+ INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
+ INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
+ INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
+ INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
+ INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
+ INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display),
/*
* Do not add any GMD_ID-based platforms to this list. They will
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 82bb34416fb1..862f4b705227 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -127,81 +127,80 @@ void intel_device_info_print(const struct intel_device_info *info,
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
-#undef INTEL_VGA_DEVICE
-#define INTEL_VGA_DEVICE(id, info) (id)
+#define ID(id) (id)
static const u16 subplatform_ult_ids[] = {
- INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_HSW_ULT_GT1_IDS(ID),
+ INTEL_HSW_ULT_GT2_IDS(ID),
+ INTEL_HSW_ULT_GT3_IDS(ID),
+ INTEL_BDW_ULT_GT1_IDS(ID),
+ INTEL_BDW_ULT_GT2_IDS(ID),
+ INTEL_BDW_ULT_GT3_IDS(ID),
+ INTEL_BDW_ULT_RSVD_IDS(ID),
+ INTEL_SKL_ULT_GT1_IDS(ID),
+ INTEL_SKL_ULT_GT2_IDS(ID),
+ INTEL_SKL_ULT_GT3_IDS(ID),
+ INTEL_KBL_ULT_GT1_IDS(ID),
+ INTEL_KBL_ULT_GT2_IDS(ID),
+ INTEL_KBL_ULT_GT3_IDS(ID),
+ INTEL_CFL_U_GT2_IDS(ID),
+ INTEL_CFL_U_GT3_IDS(ID),
+ INTEL_WHL_U_GT1_IDS(ID),
+ INTEL_WHL_U_GT2_IDS(ID),
+ INTEL_WHL_U_GT3_IDS(ID),
+ INTEL_CML_U_GT1_IDS(ID),
+ INTEL_CML_U_GT2_IDS(ID),
};
static const u16 subplatform_ulx_ids[] = {
- INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_HSW_ULX_GT1_IDS(ID),
+ INTEL_HSW_ULX_GT2_IDS(ID),
+ INTEL_BDW_ULX_GT1_IDS(ID),
+ INTEL_BDW_ULX_GT2_IDS(ID),
+ INTEL_BDW_ULX_GT3_IDS(ID),
+ INTEL_BDW_ULX_RSVD_IDS(ID),
+ INTEL_SKL_ULX_GT1_IDS(ID),
+ INTEL_SKL_ULX_GT2_IDS(ID),
+ INTEL_KBL_ULX_GT1_IDS(ID),
+ INTEL_KBL_ULX_GT2_IDS(ID),
+ INTEL_AML_KBL_GT2_IDS(ID),
+ INTEL_AML_CFL_GT2_IDS(ID),
};
static const u16 subplatform_portf_ids[] = {
- INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_ICL_PORT_F_IDS(ID),
};
static const u16 subplatform_uy_ids[] = {
- INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_TGL_GT2_IDS(ID),
};
static const u16 subplatform_n_ids[] = {
- INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_ADLN_IDS(ID),
};
static const u16 subplatform_rpl_ids[] = {
- INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_RPLS_IDS(ID),
+ INTEL_RPLU_IDS(ID),
+ INTEL_RPLP_IDS(ID),
};
static const u16 subplatform_rplu_ids[] = {
- INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_RPLU_IDS(ID),
};
static const u16 subplatform_g10_ids[] = {
- INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_DG2_G10_IDS(ID),
+ INTEL_ATS_M150_IDS(ID),
};
static const u16 subplatform_g11_ids[] = {
- INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0),
- INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_DG2_G11_IDS(ID),
+ INTEL_ATS_M75_IDS(ID),
};
static const u16 subplatform_g12_ids[] = {
- INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0),
+ INTEL_DG2_G12_IDS(ID),
};
static bool find_devid(u16 id, const u16 *p, unsigned int num)
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
2024-05-15 16:56 ` [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE Jani Nikula
@ 2024-05-16 13:25 ` Rodrigo Vivi
2024-05-16 13:25 ` Rodrigo Vivi
1 sibling, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2024-05-16 13:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi
On Wed, May 15, 2024 at 07:56:51PM +0300, Jani Nikula wrote:
> Now that the PCI ID macros allow us to pass in the macro to use, stop
> redefining INTEL_VGA_DEVICE.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_device.c | 87 +++++++++---------
> drivers/gpu/drm/i915/intel_device_info.c | 91 +++++++++----------
> 2 files changed, 88 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 950e66cdba0a..cf093bc0cb28 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
> return pci_match_id(ids, pdev);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) { id, info }
> +#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
>
> static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display),
> - INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display),
> - INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display),
> - INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display),
> - INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display),
> - INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display),
> - INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display),
> - INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display),
> - INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display),
> - INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display),
> - INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display),
> - INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display),
> - INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display),
> - INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display),
> - INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display),
> - INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display),
> - INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display),
> - INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display),
> - INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display),
> - INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display),
> - INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display),
> - INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display),
> - INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display),
> - INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display),
> - INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display),
> - INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> - INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> - INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display),
> - INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display),
> - INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display),
> - INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> - INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display),
> + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display),
> + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display),
> + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display),
> + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display),
> + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display),
> + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display),
> + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display),
> + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display),
> + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display),
> + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display),
> + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display),
> + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display),
> + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display),
> + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display),
> + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display),
> + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display),
> + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display),
> + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display),
> + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display),
> + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display),
> + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display),
> + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display),
> + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display),
> + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display),
> + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display),
> + INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
> + INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
> + INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display),
> + INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display),
> + INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display),
> + INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
> + INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
> + INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display),
>
> /*
> * Do not add any GMD_ID-based platforms to this list. They will
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 82bb34416fb1..862f4b705227 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -127,81 +127,80 @@ void intel_device_info_print(const struct intel_device_info *info,
> drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) (id)
> +#define ID(id) (id)
>
> static const u16 subplatform_ult_ids[] = {
> - INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT1_IDS(ID),
> + INTEL_HSW_ULT_GT2_IDS(ID),
> + INTEL_HSW_ULT_GT3_IDS(ID),
> + INTEL_BDW_ULT_GT1_IDS(ID),
> + INTEL_BDW_ULT_GT2_IDS(ID),
> + INTEL_BDW_ULT_GT3_IDS(ID),
> + INTEL_BDW_ULT_RSVD_IDS(ID),
> + INTEL_SKL_ULT_GT1_IDS(ID),
> + INTEL_SKL_ULT_GT2_IDS(ID),
> + INTEL_SKL_ULT_GT3_IDS(ID),
> + INTEL_KBL_ULT_GT1_IDS(ID),
> + INTEL_KBL_ULT_GT2_IDS(ID),
> + INTEL_KBL_ULT_GT3_IDS(ID),
> + INTEL_CFL_U_GT2_IDS(ID),
> + INTEL_CFL_U_GT3_IDS(ID),
> + INTEL_WHL_U_GT1_IDS(ID),
> + INTEL_WHL_U_GT2_IDS(ID),
> + INTEL_WHL_U_GT3_IDS(ID),
> + INTEL_CML_U_GT1_IDS(ID),
> + INTEL_CML_U_GT2_IDS(ID),
> };
>
> static const u16 subplatform_ulx_ids[] = {
> - INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULX_GT1_IDS(ID),
> + INTEL_HSW_ULX_GT2_IDS(ID),
> + INTEL_BDW_ULX_GT1_IDS(ID),
> + INTEL_BDW_ULX_GT2_IDS(ID),
> + INTEL_BDW_ULX_GT3_IDS(ID),
> + INTEL_BDW_ULX_RSVD_IDS(ID),
> + INTEL_SKL_ULX_GT1_IDS(ID),
> + INTEL_SKL_ULX_GT2_IDS(ID),
> + INTEL_KBL_ULX_GT1_IDS(ID),
> + INTEL_KBL_ULX_GT2_IDS(ID),
> + INTEL_AML_KBL_GT2_IDS(ID),
> + INTEL_AML_CFL_GT2_IDS(ID),
> };
>
> static const u16 subplatform_portf_ids[] = {
> - INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ICL_PORT_F_IDS(ID),
> };
>
> static const u16 subplatform_uy_ids[] = {
> - INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_TGL_GT2_IDS(ID),
> };
>
> static const u16 subplatform_n_ids[] = {
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ADLN_IDS(ID),
> };
>
> static const u16 subplatform_rpl_ids[] = {
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLS_IDS(ID),
> + INTEL_RPLU_IDS(ID),
> + INTEL_RPLP_IDS(ID),
> };
>
> static const u16 subplatform_rplu_ids[] = {
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLU_IDS(ID),
> };
>
> static const u16 subplatform_g10_ids[] = {
> - INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G10_IDS(ID),
> + INTEL_ATS_M150_IDS(ID),
> };
>
> static const u16 subplatform_g11_ids[] = {
> - INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G11_IDS(ID),
> + INTEL_ATS_M75_IDS(ID),
> };
>
> static const u16 subplatform_g12_ids[] = {
> - INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G12_IDS(ID),
> };
>
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
2024-05-15 16:56 ` [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE Jani Nikula
2024-05-16 13:25 ` Rodrigo Vivi
@ 2024-05-16 13:25 ` Rodrigo Vivi
1 sibling, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2024-05-16 13:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi
On Wed, May 15, 2024 at 07:56:51PM +0300, Jani Nikula wrote:
> Now that the PCI ID macros allow us to pass in the macro to use, stop
> redefining INTEL_VGA_DEVICE.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_device.c | 87 +++++++++---------
> drivers/gpu/drm/i915/intel_device_info.c | 91 +++++++++----------
> 2 files changed, 88 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 950e66cdba0a..cf093bc0cb28 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
> return pci_match_id(ids, pdev);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) { id, info }
> +#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
>
> static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display),
> - INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display),
> - INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display),
> - INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display),
> - INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display),
> - INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display),
> - INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display),
> - INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display),
> - INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display),
> - INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display),
> - INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display),
> - INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display),
> - INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display),
> - INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display),
> - INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display),
> - INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display),
> - INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display),
> - INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display),
> - INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display),
> - INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display),
> - INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display),
> - INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display),
> - INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display),
> - INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display),
> - INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display),
> - INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display),
> - INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> - INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> - INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display),
> - INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display),
> - INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display),
> - INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> - INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> - INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display),
> + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display),
> + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display),
> + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display),
> + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display),
> + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display),
> + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display),
> + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display),
> + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display),
> + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display),
> + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display),
> + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display),
> + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display),
> + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display),
> + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display),
> + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display),
> + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display),
> + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display),
> + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display),
> + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display),
> + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display),
> + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display),
> + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display),
> + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display),
> + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display),
> + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display),
> + INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display),
> + INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
> + INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display),
> + INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display),
> + INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display),
> + INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display),
> + INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
> + INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display),
> + INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display),
> + INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display),
>
> /*
> * Do not add any GMD_ID-based platforms to this list. They will
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 82bb34416fb1..862f4b705227 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -127,81 +127,80 @@ void intel_device_info_print(const struct intel_device_info *info,
> drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
> }
>
> -#undef INTEL_VGA_DEVICE
> -#define INTEL_VGA_DEVICE(id, info) (id)
> +#define ID(id) (id)
>
> static const u16 subplatform_ult_ids[] = {
> - INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT1_IDS(ID),
> + INTEL_HSW_ULT_GT2_IDS(ID),
> + INTEL_HSW_ULT_GT3_IDS(ID),
> + INTEL_BDW_ULT_GT1_IDS(ID),
> + INTEL_BDW_ULT_GT2_IDS(ID),
> + INTEL_BDW_ULT_GT3_IDS(ID),
> + INTEL_BDW_ULT_RSVD_IDS(ID),
> + INTEL_SKL_ULT_GT1_IDS(ID),
> + INTEL_SKL_ULT_GT2_IDS(ID),
> + INTEL_SKL_ULT_GT3_IDS(ID),
> + INTEL_KBL_ULT_GT1_IDS(ID),
> + INTEL_KBL_ULT_GT2_IDS(ID),
> + INTEL_KBL_ULT_GT3_IDS(ID),
> + INTEL_CFL_U_GT2_IDS(ID),
> + INTEL_CFL_U_GT3_IDS(ID),
> + INTEL_WHL_U_GT1_IDS(ID),
> + INTEL_WHL_U_GT2_IDS(ID),
> + INTEL_WHL_U_GT3_IDS(ID),
> + INTEL_CML_U_GT1_IDS(ID),
> + INTEL_CML_U_GT2_IDS(ID),
> };
>
> static const u16 subplatform_ulx_ids[] = {
> - INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULX_GT1_IDS(ID),
> + INTEL_HSW_ULX_GT2_IDS(ID),
> + INTEL_BDW_ULX_GT1_IDS(ID),
> + INTEL_BDW_ULX_GT2_IDS(ID),
> + INTEL_BDW_ULX_GT3_IDS(ID),
> + INTEL_BDW_ULX_RSVD_IDS(ID),
> + INTEL_SKL_ULX_GT1_IDS(ID),
> + INTEL_SKL_ULX_GT2_IDS(ID),
> + INTEL_KBL_ULX_GT1_IDS(ID),
> + INTEL_KBL_ULX_GT2_IDS(ID),
> + INTEL_AML_KBL_GT2_IDS(ID),
> + INTEL_AML_CFL_GT2_IDS(ID),
> };
>
> static const u16 subplatform_portf_ids[] = {
> - INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ICL_PORT_F_IDS(ID),
> };
>
> static const u16 subplatform_uy_ids[] = {
> - INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_TGL_GT2_IDS(ID),
> };
>
> static const u16 subplatform_n_ids[] = {
> - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ADLN_IDS(ID),
> };
>
> static const u16 subplatform_rpl_ids[] = {
> - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLS_IDS(ID),
> + INTEL_RPLU_IDS(ID),
> + INTEL_RPLP_IDS(ID),
> };
>
> static const u16 subplatform_rplu_ids[] = {
> - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLU_IDS(ID),
> };
>
> static const u16 subplatform_g10_ids[] = {
> - INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G10_IDS(ID),
> + INTEL_ATS_M150_IDS(ID),
> };
>
> static const u16 subplatform_g11_ids[] = {
> - INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0),
> - INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G11_IDS(ID),
> + INTEL_ATS_M75_IDS(ID),
> };
>
> static const u16 subplatform_g12_ids[] = {
> - INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_DG2_G12_IDS(ID),
> };
>
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
2024-05-15 16:56 ` [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE Jani Nikula
@ 2024-05-15 18:09 ` Patchwork
2024-05-15 18:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-05-15 18:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3356 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
URL : https://patchwork.freedesktop.org/series/133664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14768 -> Patchwork_133664v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/index.html
Participating hosts (43 -> 43)
------------------------------
Additional (1): fi-kbl-8809g
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_133664v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][2] -> [FAIL][3] ([i915#10378])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] +30 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
#### Possible fixes ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [FAIL][6] ([i915#10378]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/bat-dg2-11/igt@gem_lmem_swapping@basic@lmem0.html
* igt@kms_flip@basic-flip-vs-dpms@a-dp7:
- {bat-mtlp-9}: [DMESG-WARN][8] ([i915#10435]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@a-dp7.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@a-dp7.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
Build changes
-------------
* Linux: CI_DRM_14768 -> Patchwork_133664v1
CI-20190529: 20190529
CI_DRM_14768: 26a52a7b24c1f334d92f5deac9f3eaf3224f3864 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7855: 7855
Patchwork_133664v1: 26a52a7b24c1f334d92f5deac9f3eaf3224f3864 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/index.html
[-- Attachment #2: Type: text/html, Size: 4193 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
2024-05-15 16:56 ` [PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE Jani Nikula
2024-05-15 18:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Patchwork
@ 2024-05-15 18:10 ` Patchwork
2024-05-15 18:10 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-05-15 18:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
URL : https://patchwork.freedesktop.org/series/133664/
State : warning
== Summary ==
Error: dim checkpatch failed
527339fb7437 drm/i915/pciids: switch to xe driver style PCI ID macros
-:533: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#533: FILE: include/drm/i915_pciids.h:50:
+#define INTEL_I810_IDS(MACRO__, ...) \
+ MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
+ MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
+ MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
-:533: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#533: FILE: include/drm/i915_pciids.h:50:
+#define INTEL_I810_IDS(MACRO__, ...) \
+ MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
+ MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
+ MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
-:556: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#556: FILE: include/drm/i915_pciids.h:64:
+#define INTEL_I85X_IDS(MACRO__, ...) \
+ MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
+ MACRO__(0x358e, ## __VA_ARGS__)
-:556: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#556: FILE: include/drm/i915_pciids.h:64:
+#define INTEL_I85X_IDS(MACRO__, ...) \
+ MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
+ MACRO__(0x358e, ## __VA_ARGS__)
-:568: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#568: FILE: include/drm/i915_pciids.h:71:
+#define INTEL_I915G_IDS(MACRO__, ...) \
+ MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
+ MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
-:568: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#568: FILE: include/drm/i915_pciids.h:71:
+#define INTEL_I915G_IDS(MACRO__, ...) \
+ MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
+ MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
-:585: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#585: FILE: include/drm/i915_pciids.h:81:
+#define INTEL_I945GM_IDS(MACRO__, ...) \
+ MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
+ MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
-:585: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#585: FILE: include/drm/i915_pciids.h:81:
+#define INTEL_I945GM_IDS(MACRO__, ...) \
+ MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
+ MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
-:594: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#594: FILE: include/drm/i915_pciids.h:85:
+#define INTEL_I965G_IDS(MACRO__, ...) \
+ MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
+ MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
+ MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
+ MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
-:594: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#594: FILE: include/drm/i915_pciids.h:85:
+#define INTEL_I965G_IDS(MACRO__, ...) \
+ MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
+ MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
+ MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
+ MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
-:604: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#604: FILE: include/drm/i915_pciids.h:91:
+#define INTEL_G33_IDS(MACRO__, ...) \
+ MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
+ MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
+ MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
-:604: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#604: FILE: include/drm/i915_pciids.h:91:
+#define INTEL_G33_IDS(MACRO__, ...) \
+ MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
+ MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
+ MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
-:612: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#612: FILE: include/drm/i915_pciids.h:96:
+#define INTEL_I965GM_IDS(MACRO__, ...) \
+ MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
+ MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
-:612: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#612: FILE: include/drm/i915_pciids.h:96:
+#define INTEL_I965GM_IDS(MACRO__, ...) \
+ MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
+ MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
-:972: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#972: FILE: include/drm/i915_pciids.h:103:
+#define INTEL_G45_IDS(MACRO__, ...) \
+ MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
+ MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
+ MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
+ MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
+ MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
+ MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
-:972: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#972: FILE: include/drm/i915_pciids.h:103:
+#define INTEL_G45_IDS(MACRO__, ...) \
+ MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
+ MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
+ MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
+ MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
+ MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
+ MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
-:986: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#986: FILE: include/drm/i915_pciids.h:117:
+#define INTEL_PNV_IDS(MACRO__, ...) \
+ INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
-:986: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#986: FILE: include/drm/i915_pciids.h:117:
+#define INTEL_PNV_IDS(MACRO__, ...) \
+ INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
-:996: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#996: FILE: include/drm/i915_pciids.h:127:
+#define INTEL_ILK_IDS(MACRO__, ...) \
+ INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
-:996: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#996: FILE: include/drm/i915_pciids.h:127:
+#define INTEL_ILK_IDS(MACRO__, ...) \
+ INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
-:1000: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1000: FILE: include/drm/i915_pciids.h:131:
+#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0102, ## __VA_ARGS__), \
+ MACRO__(0x010A, ## __VA_ARGS__)
-:1000: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1000: FILE: include/drm/i915_pciids.h:131:
+#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0102, ## __VA_ARGS__), \
+ MACRO__(0x010A, ## __VA_ARGS__)
-:1004: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1004: FILE: include/drm/i915_pciids.h:135:
+#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0112, ## __VA_ARGS__), \
+ MACRO__(0x0122, ## __VA_ARGS__)
-:1004: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1004: FILE: include/drm/i915_pciids.h:135:
+#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0112, ## __VA_ARGS__), \
+ MACRO__(0x0122, ## __VA_ARGS__)
-:1008: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1008: FILE: include/drm/i915_pciids.h:139:
+#define INTEL_SNB_D_IDS(MACRO__, ...) \
+ INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1008: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1008: FILE: include/drm/i915_pciids.h:139:
+#define INTEL_SNB_D_IDS(MACRO__, ...) \
+ INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1015: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1015: FILE: include/drm/i915_pciids.h:146:
+#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0116, ## __VA_ARGS__), \
+ MACRO__(0x0126, ## __VA_ARGS__)
-:1015: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1015: FILE: include/drm/i915_pciids.h:146:
+#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0116, ## __VA_ARGS__), \
+ MACRO__(0x0126, ## __VA_ARGS__)
-:1019: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1019: FILE: include/drm/i915_pciids.h:150:
+#define INTEL_SNB_M_IDS(MACRO__, ...) \
+ INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1019: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1019: FILE: include/drm/i915_pciids.h:150:
+#define INTEL_SNB_M_IDS(MACRO__, ...) \
+ INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1023: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1023: FILE: include/drm/i915_pciids.h:154:
+#define INTEL_SNB_IDS(MACRO__, ...) \
+ INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
-:1023: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1023: FILE: include/drm/i915_pciids.h:154:
+#define INTEL_SNB_IDS(MACRO__, ...) \
+ INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
-:1033: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1033: FILE: include/drm/i915_pciids.h:164:
+#define INTEL_IVB_M_IDS(MACRO__, ...) \
+ INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1033: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1033: FILE: include/drm/i915_pciids.h:164:
+#define INTEL_IVB_M_IDS(MACRO__, ...) \
+ INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1037: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1037: FILE: include/drm/i915_pciids.h:168:
+#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
+ MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
-:1037: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1037: FILE: include/drm/i915_pciids.h:168:
+#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
+ MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
-:1041: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1041: FILE: include/drm/i915_pciids.h:172:
+#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
+ MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
-:1041: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1041: FILE: include/drm/i915_pciids.h:172:
+#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
+ MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
-:1045: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1045: FILE: include/drm/i915_pciids.h:176:
+#define INTEL_IVB_D_IDS(MACRO__, ...) \
+ INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1045: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1045: FILE: include/drm/i915_pciids.h:176:
+#define INTEL_IVB_D_IDS(MACRO__, ...) \
+ INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1049: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1049: FILE: include/drm/i915_pciids.h:180:
+#define INTEL_IVB_IDS(MACRO__, ...) \
+ INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
-:1049: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1049: FILE: include/drm/i915_pciids.h:180:
+#define INTEL_IVB_IDS(MACRO__, ...) \
+ INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
-:1056: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1056: FILE: include/drm/i915_pciids.h:187:
+#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
+ MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
+ MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
+ MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
-:1056: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1056: FILE: include/drm/i915_pciids.h:187:
+#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
+ MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
+ MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
+ MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
-:1065: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1065: FILE: include/drm/i915_pciids.h:196:
+#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
+ MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
+ MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
+ MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
+ MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
+ MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
+ MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
+ MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
+ MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
+ MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
+ MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
+ MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
+ MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
+ MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
+ MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
-:1065: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1065: FILE: include/drm/i915_pciids.h:196:
+#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
+ MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
+ MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
+ MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
+ MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
+ MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
+ MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
+ MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
+ MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
+ MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
+ MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
+ MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
+ MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
+ MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
+ MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
-:1084: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1084: FILE: include/drm/i915_pciids.h:215:
+#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
+ MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
+ MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
+ MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
+
-:1084: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1084: FILE: include/drm/i915_pciids.h:215:
+#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
+ MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
+ MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
+ MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
+
-:1093: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1093: FILE: include/drm/i915_pciids.h:224:
+#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
+ MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
+ MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
+ MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
+ MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
+ MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
+ MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
+ MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
+ MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
+ MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
+ MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
+ MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
+ MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
+ MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
+ MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
-:1093: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1093: FILE: include/drm/i915_pciids.h:224:
+#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
+ MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
+ MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
+ MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
+ MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
+ MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
+ MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
+ MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
+ MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
+ MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
+ MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
+ MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
+ MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
+ MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
+ MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
-:1112: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1112: FILE: include/drm/i915_pciids.h:243:
+#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
+ MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
+ MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
+ MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
+ MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
-:1112: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1112: FILE: include/drm/i915_pciids.h:243:
+#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
+ MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
+ MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
+ MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
+ MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
-:1119: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1119: FILE: include/drm/i915_pciids.h:250:
+#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
+ MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
+ MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
+ MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
+ MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
+ MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
+ MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
+ MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
+ MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
+ MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
+ MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
+ MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
+ MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
+ MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
+ MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
-:1119: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1119: FILE: include/drm/i915_pciids.h:250:
+#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
+ INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
+ MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
+ MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
+ MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
+ MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
+ MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
+ MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
+ MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
+ MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
+ MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
+ MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
+ MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
+ MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
+ MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
+ MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
-:1137: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1137: FILE: include/drm/i915_pciids.h:268:
+#define INTEL_HSW_IDS(MACRO__, ...) \
+ INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
-:1137: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1137: FILE: include/drm/i915_pciids.h:268:
+#define INTEL_HSW_IDS(MACRO__, ...) \
+ INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
-:1142: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1142: FILE: include/drm/i915_pciids.h:273:
+#define INTEL_VLV_IDS(MACRO__, ...) \
+ MACRO__(0x0f30, ## __VA_ARGS__), \
+ MACRO__(0x0f31, ## __VA_ARGS__), \
+ MACRO__(0x0f32, ## __VA_ARGS__), \
+ MACRO__(0x0f33, ## __VA_ARGS__)
-:1142: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1142: FILE: include/drm/i915_pciids.h:273:
+#define INTEL_VLV_IDS(MACRO__, ...) \
+ MACRO__(0x0f30, ## __VA_ARGS__), \
+ MACRO__(0x0f31, ## __VA_ARGS__), \
+ MACRO__(0x0f32, ## __VA_ARGS__), \
+ MACRO__(0x0f33, ## __VA_ARGS__)
-:1148: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1148: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
+ MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
-:1148: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1148: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
+ MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
-:1155: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1155: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
+ MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
+ MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
-:1155: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1155: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
+ MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
+ MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
-:1162: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1162: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
+ MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
-:1162: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1162: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
+ MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
-:1169: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1169: FILE: include/drm/i915_pciids.h:300:
+#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
+ MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
+ MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
-:1169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1169: FILE: include/drm/i915_pciids.h:300:
+#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
+ MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
+ MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
-:1176: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1176: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
+
-:1176: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1176: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
+
-:1183: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1183: FILE: include/drm/i915_pciids.h:314:
+#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
+ MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
-:1183: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1183: FILE: include/drm/i915_pciids.h:314:
+#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
+ MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
-:1190: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1190: FILE: include/drm/i915_pciids.h:321:
+#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
+ MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
-:1190: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1190: FILE: include/drm/i915_pciids.h:321:
+#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
+ MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
-:1197: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1197: FILE: include/drm/i915_pciids.h:328:
+#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
+ MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
-:1197: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1197: FILE: include/drm/i915_pciids.h:328:
+#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
+ INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
+ MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
+ MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
-:1204: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1204: FILE: include/drm/i915_pciids.h:335:
+#define INTEL_BDW_IDS(MACRO__, ...) \
+ INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
-:1204: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1204: FILE: include/drm/i915_pciids.h:335:
+#define INTEL_BDW_IDS(MACRO__, ...) \
+ INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
-:1210: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1210: FILE: include/drm/i915_pciids.h:341:
+#define INTEL_CHV_IDS(MACRO__, ...) \
+ MACRO__(0x22b0, ## __VA_ARGS__), \
+ MACRO__(0x22b1, ## __VA_ARGS__), \
+ MACRO__(0x22b2, ## __VA_ARGS__), \
+ MACRO__(0x22b3, ## __VA_ARGS__)
-:1210: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1210: FILE: include/drm/i915_pciids.h:341:
+#define INTEL_CHV_IDS(MACRO__, ...) \
+ MACRO__(0x22b0, ## __VA_ARGS__), \
+ MACRO__(0x22b1, ## __VA_ARGS__), \
+ MACRO__(0x22b2, ## __VA_ARGS__), \
+ MACRO__(0x22b3, ## __VA_ARGS__)
-:1216: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1216: FILE: include/drm/i915_pciids.h:347:
+#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
+ MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
-:1216: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1216: FILE: include/drm/i915_pciids.h:347:
+#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
+ MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
-:1220: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1220: FILE: include/drm/i915_pciids.h:351:
+#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
+ MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
-:1220: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1220: FILE: include/drm/i915_pciids.h:351:
+#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
+ MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
-:1224: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1224: FILE: include/drm/i915_pciids.h:355:
+#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
+ MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
+ MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
-:1224: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1224: FILE: include/drm/i915_pciids.h:355:
+#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
+ MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
+ MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
-:1232: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1232: FILE: include/drm/i915_pciids.h:363:
+#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
+ MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
-:1232: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1232: FILE: include/drm/i915_pciids.h:363:
+#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
+ MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
-:1239: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1239: FILE: include/drm/i915_pciids.h:370:
+#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
+ MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
-:1239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1239: FILE: include/drm/i915_pciids.h:370:
+#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
+ MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
-:1247: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1247: FILE: include/drm/i915_pciids.h:378:
+#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
+ MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
-:1247: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1247: FILE: include/drm/i915_pciids.h:378:
+#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
+ MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
-:1252: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1252: FILE: include/drm/i915_pciids.h:383:
+#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
+ MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
+ MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
-:1252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1252: FILE: include/drm/i915_pciids.h:383:
+#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
+ INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
+ MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
+ MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
-:1258: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1258: FILE: include/drm/i915_pciids.h:389:
+#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
+ MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
+ MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
+ MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
+ MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
-:1258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1258: FILE: include/drm/i915_pciids.h:389:
+#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
+ MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
+ MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
+ MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
+ MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
-:1264: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1264: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_SKL_IDS(MACRO__, ...) \
+ INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
-:1264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1264: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_SKL_IDS(MACRO__, ...) \
+ INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
-:1270: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1270: FILE: include/drm/i915_pciids.h:401:
+#define INTEL_BXT_IDS(MACRO__, ...) \
+ MACRO__(0x0A84, ## __VA_ARGS__), \
+ MACRO__(0x1A84, ## __VA_ARGS__), \
+ MACRO__(0x1A85, ## __VA_ARGS__), \
+ MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
+ MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
-:1270: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1270: FILE: include/drm/i915_pciids.h:401:
+#define INTEL_BXT_IDS(MACRO__, ...) \
+ MACRO__(0x0A84, ## __VA_ARGS__), \
+ MACRO__(0x1A84, ## __VA_ARGS__), \
+ MACRO__(0x1A85, ## __VA_ARGS__), \
+ MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
+ MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
-:1277: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1277: FILE: include/drm/i915_pciids.h:408:
+#define INTEL_GLK_IDS(MACRO__, ...) \
+ MACRO__(0x3184, ## __VA_ARGS__), \
+ MACRO__(0x3185, ## __VA_ARGS__)
-:1277: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1277: FILE: include/drm/i915_pciids.h:408:
+#define INTEL_GLK_IDS(MACRO__, ...) \
+ MACRO__(0x3184, ## __VA_ARGS__), \
+ MACRO__(0x3185, ## __VA_ARGS__)
-:1281: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1281: FILE: include/drm/i915_pciids.h:412:
+#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
+ MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
-:1281: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1281: FILE: include/drm/i915_pciids.h:412:
+#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
+ MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
-:1285: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1285: FILE: include/drm/i915_pciids.h:416:
+#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
+ MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
-:1285: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1285: FILE: include/drm/i915_pciids.h:416:
+#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
+ MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
-:1289: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1289: FILE: include/drm/i915_pciids.h:420:
+#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
+ MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
+ MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
-:1289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1289: FILE: include/drm/i915_pciids.h:420:
+#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
+ MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
+ MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
-:1297: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1297: FILE: include/drm/i915_pciids.h:428:
+#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
+ MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
-:1297: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1297: FILE: include/drm/i915_pciids.h:428:
+#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
+ MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
-:1304: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1304: FILE: include/drm/i915_pciids.h:435:
+#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
+ MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
+ MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
-:1304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1304: FILE: include/drm/i915_pciids.h:435:
+#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
+ MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
+ MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
-:1316: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1316: FILE: include/drm/i915_pciids.h:447:
+#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
-:1316: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1316: FILE: include/drm/i915_pciids.h:447:
+#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
+ INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
-:1328: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1328: FILE: include/drm/i915_pciids.h:456:
+#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
+ MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
-:1328: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1328: FILE: include/drm/i915_pciids.h:456:
+#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
+ MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
-:1344: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1344: FILE: include/drm/i915_pciids.h:465:
+#define INTEL_CML_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9BA2, ## __VA_ARGS__), \
+ MACRO__(0x9BA4, ## __VA_ARGS__), \
+ MACRO__(0x9BA5, ## __VA_ARGS__), \
+ MACRO__(0x9BA8, ## __VA_ARGS__)
-:1344: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1344: FILE: include/drm/i915_pciids.h:465:
+#define INTEL_CML_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9BA2, ## __VA_ARGS__), \
+ MACRO__(0x9BA4, ## __VA_ARGS__), \
+ MACRO__(0x9BA5, ## __VA_ARGS__), \
+ MACRO__(0x9BA8, ## __VA_ARGS__)
-:1354: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1354: FILE: include/drm/i915_pciids.h:471:
+#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9B21, ## __VA_ARGS__), \
+ MACRO__(0x9BAA, ## __VA_ARGS__), \
+ MACRO__(0x9BAC, ## __VA_ARGS__)
-:1354: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1354: FILE: include/drm/i915_pciids.h:471:
+#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9B21, ## __VA_ARGS__), \
+ MACRO__(0x9BAA, ## __VA_ARGS__), \
+ MACRO__(0x9BAC, ## __VA_ARGS__)
-:1386: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1386: FILE: include/drm/i915_pciids.h:477:
+#define INTEL_CML_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9BC2, ## __VA_ARGS__), \
+ MACRO__(0x9BC4, ## __VA_ARGS__), \
+ MACRO__(0x9BC5, ## __VA_ARGS__), \
+ MACRO__(0x9BC6, ## __VA_ARGS__), \
+ MACRO__(0x9BC8, ## __VA_ARGS__), \
+ MACRO__(0x9BE6, ## __VA_ARGS__), \
+ MACRO__(0x9BF6, ## __VA_ARGS__)
-:1386: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1386: FILE: include/drm/i915_pciids.h:477:
+#define INTEL_CML_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9BC2, ## __VA_ARGS__), \
+ MACRO__(0x9BC4, ## __VA_ARGS__), \
+ MACRO__(0x9BC5, ## __VA_ARGS__), \
+ MACRO__(0x9BC6, ## __VA_ARGS__), \
+ MACRO__(0x9BC8, ## __VA_ARGS__), \
+ MACRO__(0x9BE6, ## __VA_ARGS__), \
+ MACRO__(0x9BF6, ## __VA_ARGS__)
-:1395: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1395: FILE: include/drm/i915_pciids.h:486:
+#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9B41, ## __VA_ARGS__), \
+ MACRO__(0x9BCA, ## __VA_ARGS__), \
+ MACRO__(0x9BCC, ## __VA_ARGS__)
-:1395: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1395: FILE: include/drm/i915_pciids.h:486:
+#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9B41, ## __VA_ARGS__), \
+ MACRO__(0x9BCA, ## __VA_ARGS__), \
+ MACRO__(0x9BCC, ## __VA_ARGS__)
-:1400: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1400: FILE: include/drm/i915_pciids.h:491:
+#define INTEL_CML_IDS(MACRO__, ...) \
+ INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1400: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1400: FILE: include/drm/i915_pciids.h:491:
+#define INTEL_CML_IDS(MACRO__, ...) \
+ INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1406: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1406: FILE: include/drm/i915_pciids.h:497:
+#define INTEL_KBL_IDS(MACRO__, ...) \
+ INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1406: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1406: FILE: include/drm/i915_pciids.h:497:
+#define INTEL_KBL_IDS(MACRO__, ...) \
+ INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1425: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1425: FILE: include/drm/i915_pciids.h:505:
+#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
-:1425: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1425: FILE: include/drm/i915_pciids.h:505:
+#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
+ MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
-:1430: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1430: FILE: include/drm/i915_pciids.h:510:
+#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
-:1430: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1430: FILE: include/drm/i915_pciids.h:510:
+#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
+ MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
-:1446: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1446: FILE: include/drm/i915_pciids.h:521:
+#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
-:1446: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1446: FILE: include/drm/i915_pciids.h:521:
+#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
+ MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
-:1471: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1471: FILE: include/drm/i915_pciids.h:530:
+#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
-:1471: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1471: FILE: include/drm/i915_pciids.h:530:
+#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
+ MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
+ MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
-:1477: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1477: FILE: include/drm/i915_pciids.h:536:
+#define INTEL_CFL_IDS(MACRO__, ...) \
+ INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1477: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1477: FILE: include/drm/i915_pciids.h:536:
+#define INTEL_CFL_IDS(MACRO__, ...) \
+ INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1490: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1490: FILE: include/drm/i915_pciids.h:546:
+#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x3EA1, ## __VA_ARGS__), \
+ MACRO__(0x3EA4, ## __VA_ARGS__)
-:1490: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1490: FILE: include/drm/i915_pciids.h:546:
+#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x3EA1, ## __VA_ARGS__), \
+ MACRO__(0x3EA4, ## __VA_ARGS__)
-:1498: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1498: FILE: include/drm/i915_pciids.h:551:
+#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3EA0, ## __VA_ARGS__), \
+ MACRO__(0x3EA3, ## __VA_ARGS__)
-:1498: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1498: FILE: include/drm/i915_pciids.h:551:
+#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x3EA0, ## __VA_ARGS__), \
+ MACRO__(0x3EA3, ## __VA_ARGS__)
-:1512: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1512: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_WHL_IDS(MACRO__, ...) \
+ INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
-:1512: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1512: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_WHL_IDS(MACRO__, ...) \
+ INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
-:1536: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1536: FILE: include/drm/i915_pciids.h:565:
+#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
+ MACRO__(0x5A44, ## __VA_ARGS__), \
+ MACRO__(0x5A4C, ## __VA_ARGS__), \
+ MACRO__(0x5A54, ## __VA_ARGS__), \
+ MACRO__(0x5A5C, ## __VA_ARGS__)
-:1536: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1536: FILE: include/drm/i915_pciids.h:565:
+#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
+ MACRO__(0x5A44, ## __VA_ARGS__), \
+ MACRO__(0x5A4C, ## __VA_ARGS__), \
+ MACRO__(0x5A54, ## __VA_ARGS__), \
+ MACRO__(0x5A5C, ## __VA_ARGS__)
-:1542: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1542: FILE: include/drm/i915_pciids.h:571:
+#define INTEL_CNL_IDS(MACRO__, ...) \
+ INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5A40, ## __VA_ARGS__), \
+ MACRO__(0x5A41, ## __VA_ARGS__), \
+ MACRO__(0x5A42, ## __VA_ARGS__), \
+ MACRO__(0x5A49, ## __VA_ARGS__), \
+ MACRO__(0x5A4A, ## __VA_ARGS__), \
+ MACRO__(0x5A50, ## __VA_ARGS__), \
+ MACRO__(0x5A51, ## __VA_ARGS__), \
+ MACRO__(0x5A52, ## __VA_ARGS__), \
+ MACRO__(0x5A59, ## __VA_ARGS__), \
+ MACRO__(0x5A5A, ## __VA_ARGS__)
-:1542: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1542: FILE: include/drm/i915_pciids.h:571:
+#define INTEL_CNL_IDS(MACRO__, ...) \
+ INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x5A40, ## __VA_ARGS__), \
+ MACRO__(0x5A41, ## __VA_ARGS__), \
+ MACRO__(0x5A42, ## __VA_ARGS__), \
+ MACRO__(0x5A49, ## __VA_ARGS__), \
+ MACRO__(0x5A4A, ## __VA_ARGS__), \
+ MACRO__(0x5A50, ## __VA_ARGS__), \
+ MACRO__(0x5A51, ## __VA_ARGS__), \
+ MACRO__(0x5A52, ## __VA_ARGS__), \
+ MACRO__(0x5A59, ## __VA_ARGS__), \
+ MACRO__(0x5A5A, ## __VA_ARGS__)
-:1575: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1575: FILE: include/drm/i915_pciids.h:585:
+#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
+ MACRO__(0x8A50, ## __VA_ARGS__), \
+ MACRO__(0x8A52, ## __VA_ARGS__), \
+ MACRO__(0x8A53, ## __VA_ARGS__), \
+ MACRO__(0x8A54, ## __VA_ARGS__), \
+ MACRO__(0x8A56, ## __VA_ARGS__), \
+ MACRO__(0x8A57, ## __VA_ARGS__), \
+ MACRO__(0x8A58, ## __VA_ARGS__), \
+ MACRO__(0x8A59, ## __VA_ARGS__), \
+ MACRO__(0x8A5A, ## __VA_ARGS__), \
+ MACRO__(0x8A5B, ## __VA_ARGS__), \
+ MACRO__(0x8A5C, ## __VA_ARGS__), \
+ MACRO__(0x8A70, ## __VA_ARGS__), \
+ MACRO__(0x8A71, ## __VA_ARGS__)
-:1575: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1575: FILE: include/drm/i915_pciids.h:585:
+#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
+ MACRO__(0x8A50, ## __VA_ARGS__), \
+ MACRO__(0x8A52, ## __VA_ARGS__), \
+ MACRO__(0x8A53, ## __VA_ARGS__), \
+ MACRO__(0x8A54, ## __VA_ARGS__), \
+ MACRO__(0x8A56, ## __VA_ARGS__), \
+ MACRO__(0x8A57, ## __VA_ARGS__), \
+ MACRO__(0x8A58, ## __VA_ARGS__), \
+ MACRO__(0x8A59, ## __VA_ARGS__), \
+ MACRO__(0x8A5A, ## __VA_ARGS__), \
+ MACRO__(0x8A5B, ## __VA_ARGS__), \
+ MACRO__(0x8A5C, ## __VA_ARGS__), \
+ MACRO__(0x8A70, ## __VA_ARGS__), \
+ MACRO__(0x8A71, ## __VA_ARGS__)
-:1590: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1590: FILE: include/drm/i915_pciids.h:600:
+#define INTEL_ICL_IDS(MACRO__, ...) \
+ INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x8A51, ## __VA_ARGS__), \
+ MACRO__(0x8A5D, ## __VA_ARGS__)
-:1590: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1590: FILE: include/drm/i915_pciids.h:600:
+#define INTEL_ICL_IDS(MACRO__, ...) \
+ INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
+ MACRO__(0x8A51, ## __VA_ARGS__), \
+ MACRO__(0x8A5D, ## __VA_ARGS__)
-:1603: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1603: FILE: include/drm/i915_pciids.h:606:
+#define INTEL_EHL_IDS(MACRO__, ...) \
+ MACRO__(0x4541, ## __VA_ARGS__), \
+ MACRO__(0x4551, ## __VA_ARGS__), \
+ MACRO__(0x4555, ## __VA_ARGS__), \
+ MACRO__(0x4557, ## __VA_ARGS__), \
+ MACRO__(0x4570, ## __VA_ARGS__), \
+ MACRO__(0x4571, ## __VA_ARGS__)
-:1603: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1603: FILE: include/drm/i915_pciids.h:606:
+#define INTEL_EHL_IDS(MACRO__, ...) \
+ MACRO__(0x4541, ## __VA_ARGS__), \
+ MACRO__(0x4551, ## __VA_ARGS__), \
+ MACRO__(0x4555, ## __VA_ARGS__), \
+ MACRO__(0x4557, ## __VA_ARGS__), \
+ MACRO__(0x4570, ## __VA_ARGS__), \
+ MACRO__(0x4571, ## __VA_ARGS__)
-:1618: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1618: FILE: include/drm/i915_pciids.h:615:
+#define INTEL_JSL_IDS(MACRO__, ...) \
+ MACRO__(0x4E51, ## __VA_ARGS__), \
+ MACRO__(0x4E55, ## __VA_ARGS__), \
+ MACRO__(0x4E57, ## __VA_ARGS__), \
+ MACRO__(0x4E61, ## __VA_ARGS__), \
+ MACRO__(0x4E71, ## __VA_ARGS__)
-:1618: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1618: FILE: include/drm/i915_pciids.h:615:
+#define INTEL_JSL_IDS(MACRO__, ...) \
+ MACRO__(0x4E51, ## __VA_ARGS__), \
+ MACRO__(0x4E55, ## __VA_ARGS__), \
+ MACRO__(0x4E57, ## __VA_ARGS__), \
+ MACRO__(0x4E61, ## __VA_ARGS__), \
+ MACRO__(0x4E71, ## __VA_ARGS__)
-:1644: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1644: FILE: include/drm/i915_pciids.h:623:
+#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9A60, ## __VA_ARGS__), \
+ MACRO__(0x9A68, ## __VA_ARGS__), \
+ MACRO__(0x9A70, ## __VA_ARGS__)
-:1644: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1644: FILE: include/drm/i915_pciids.h:623:
+#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9A60, ## __VA_ARGS__), \
+ MACRO__(0x9A68, ## __VA_ARGS__), \
+ MACRO__(0x9A70, ## __VA_ARGS__)
-:1649: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1649: FILE: include/drm/i915_pciids.h:628:
+#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9A40, ## __VA_ARGS__), \
+ MACRO__(0x9A49, ## __VA_ARGS__), \
+ MACRO__(0x9A59, ## __VA_ARGS__), \
+ MACRO__(0x9A78, ## __VA_ARGS__), \
+ MACRO__(0x9AC0, ## __VA_ARGS__), \
+ MACRO__(0x9AC9, ## __VA_ARGS__), \
+ MACRO__(0x9AD9, ## __VA_ARGS__), \
+ MACRO__(0x9AF8, ## __VA_ARGS__)
-:1649: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1649: FILE: include/drm/i915_pciids.h:628:
+#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9A40, ## __VA_ARGS__), \
+ MACRO__(0x9A49, ## __VA_ARGS__), \
+ MACRO__(0x9A59, ## __VA_ARGS__), \
+ MACRO__(0x9A78, ## __VA_ARGS__), \
+ MACRO__(0x9AC0, ## __VA_ARGS__), \
+ MACRO__(0x9AC9, ## __VA_ARGS__), \
+ MACRO__(0x9AD9, ## __VA_ARGS__), \
+ MACRO__(0x9AF8, ## __VA_ARGS__)
-:1659: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1659: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_TGL_IDS(MACRO__, ...) \
+ INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1659: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1659: FILE: include/drm/i915_pciids.h:638:
+#define INTEL_TGL_IDS(MACRO__, ...) \
+ INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
-:1671: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1671: FILE: include/drm/i915_pciids.h:643:
+#define INTEL_RKL_IDS(MACRO__, ...) \
+ MACRO__(0x4C80, ## __VA_ARGS__), \
+ MACRO__(0x4C8A, ## __VA_ARGS__), \
+ MACRO__(0x4C8B, ## __VA_ARGS__), \
+ MACRO__(0x4C8C, ## __VA_ARGS__), \
+ MACRO__(0x4C90, ## __VA_ARGS__), \
+ MACRO__(0x4C9A, ## __VA_ARGS__)
-:1671: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1671: FILE: include/drm/i915_pciids.h:643:
+#define INTEL_RKL_IDS(MACRO__, ...) \
+ MACRO__(0x4C80, ## __VA_ARGS__), \
+ MACRO__(0x4C8A, ## __VA_ARGS__), \
+ MACRO__(0x4C8B, ## __VA_ARGS__), \
+ MACRO__(0x4C8C, ## __VA_ARGS__), \
+ MACRO__(0x4C90, ## __VA_ARGS__), \
+ MACRO__(0x4C9A, ## __VA_ARGS__)
-:1686: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1686: FILE: include/drm/i915_pciids.h:652:
+#define INTEL_DG1_IDS(MACRO__, ...) \
+ MACRO__(0x4905, ## __VA_ARGS__), \
+ MACRO__(0x4906, ## __VA_ARGS__), \
+ MACRO__(0x4907, ## __VA_ARGS__), \
+ MACRO__(0x4908, ## __VA_ARGS__), \
+ MACRO__(0x4909, ## __VA_ARGS__)
-:1686: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1686: FILE: include/drm/i915_pciids.h:652:
+#define INTEL_DG1_IDS(MACRO__, ...) \
+ MACRO__(0x4905, ## __VA_ARGS__), \
+ MACRO__(0x4906, ## __VA_ARGS__), \
+ MACRO__(0x4907, ## __VA_ARGS__), \
+ MACRO__(0x4908, ## __VA_ARGS__), \
+ MACRO__(0x4909, ## __VA_ARGS__)
-:1703: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1703: FILE: include/drm/i915_pciids.h:660:
+#define INTEL_ADLS_IDS(MACRO__, ...) \
+ MACRO__(0x4680, ## __VA_ARGS__), \
+ MACRO__(0x4682, ## __VA_ARGS__), \
+ MACRO__(0x4688, ## __VA_ARGS__), \
+ MACRO__(0x468A, ## __VA_ARGS__), \
+ MACRO__(0x468B, ## __VA_ARGS__), \
+ MACRO__(0x4690, ## __VA_ARGS__), \
+ MACRO__(0x4692, ## __VA_ARGS__), \
+ MACRO__(0x4693, ## __VA_ARGS__)
-:1703: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1703: FILE: include/drm/i915_pciids.h:660:
+#define INTEL_ADLS_IDS(MACRO__, ...) \
+ MACRO__(0x4680, ## __VA_ARGS__), \
+ MACRO__(0x4682, ## __VA_ARGS__), \
+ MACRO__(0x4688, ## __VA_ARGS__), \
+ MACRO__(0x468A, ## __VA_ARGS__), \
+ MACRO__(0x468B, ## __VA_ARGS__), \
+ MACRO__(0x4690, ## __VA_ARGS__), \
+ MACRO__(0x4692, ## __VA_ARGS__), \
+ MACRO__(0x4693, ## __VA_ARGS__)
-:1733: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1733: FILE: include/drm/i915_pciids.h:671:
+#define INTEL_ADLP_IDS(MACRO__, ...) \
+ MACRO__(0x46A0, ## __VA_ARGS__), \
+ MACRO__(0x46A1, ## __VA_ARGS__), \
+ MACRO__(0x46A2, ## __VA_ARGS__), \
+ MACRO__(0x46A3, ## __VA_ARGS__), \
+ MACRO__(0x46A6, ## __VA_ARGS__), \
+ MACRO__(0x46A8, ## __VA_ARGS__), \
+ MACRO__(0x46AA, ## __VA_ARGS__), \
+ MACRO__(0x462A, ## __VA_ARGS__), \
+ MACRO__(0x4626, ## __VA_ARGS__), \
+ MACRO__(0x4628, ## __VA_ARGS__), \
+ MACRO__(0x46B0, ## __VA_ARGS__), \
+ MACRO__(0x46B1, ## __VA_ARGS__), \
+ MACRO__(0x46B2, ## __VA_ARGS__), \
+ MACRO__(0x46B3, ## __VA_ARGS__), \
+ MACRO__(0x46C0, ## __VA_ARGS__), \
+ MACRO__(0x46C1, ## __VA_ARGS__), \
+ MACRO__(0x46C2, ## __VA_ARGS__), \
+ MACRO__(0x46C3, ## __VA_ARGS__)
-:1733: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1733: FILE: include/drm/i915_pciids.h:671:
+#define INTEL_ADLP_IDS(MACRO__, ...) \
+ MACRO__(0x46A0, ## __VA_ARGS__), \
+ MACRO__(0x46A1, ## __VA_ARGS__), \
+ MACRO__(0x46A2, ## __VA_ARGS__), \
+ MACRO__(0x46A3, ## __VA_ARGS__), \
+ MACRO__(0x46A6, ## __VA_ARGS__), \
+ MACRO__(0x46A8, ## __VA_ARGS__), \
+ MACRO__(0x46AA, ## __VA_ARGS__), \
+ MACRO__(0x462A, ## __VA_ARGS__), \
+ MACRO__(0x4626, ## __VA_ARGS__), \
+ MACRO__(0x4628, ## __VA_ARGS__), \
+ MACRO__(0x46B0, ## __VA_ARGS__), \
+ MACRO__(0x46B1, ## __VA_ARGS__), \
+ MACRO__(0x46B2, ## __VA_ARGS__), \
+ MACRO__(0x46B3, ## __VA_ARGS__), \
+ MACRO__(0x46C0, ## __VA_ARGS__), \
+ MACRO__(0x46C1, ## __VA_ARGS__), \
+ MACRO__(0x46C2, ## __VA_ARGS__), \
+ MACRO__(0x46C3, ## __VA_ARGS__)
-:1760: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1760: FILE: include/drm/i915_pciids.h:692:
+#define INTEL_ADLN_IDS(MACRO__, ...) \
+ MACRO__(0x46D0, ## __VA_ARGS__), \
+ MACRO__(0x46D1, ## __VA_ARGS__), \
+ MACRO__(0x46D2, ## __VA_ARGS__), \
+ MACRO__(0x46D3, ## __VA_ARGS__), \
+ MACRO__(0x46D4, ## __VA_ARGS__)
-:1760: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1760: FILE: include/drm/i915_pciids.h:692:
+#define INTEL_ADLN_IDS(MACRO__, ...) \
+ MACRO__(0x46D0, ## __VA_ARGS__), \
+ MACRO__(0x46D1, ## __VA_ARGS__), \
+ MACRO__(0x46D2, ## __VA_ARGS__), \
+ MACRO__(0x46D3, ## __VA_ARGS__), \
+ MACRO__(0x46D4, ## __VA_ARGS__)
-:1777: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1777: FILE: include/drm/i915_pciids.h:700:
+#define INTEL_RPLS_IDS(MACRO__, ...) \
+ MACRO__(0xA780, ## __VA_ARGS__), \
+ MACRO__(0xA781, ## __VA_ARGS__), \
+ MACRO__(0xA782, ## __VA_ARGS__), \
+ MACRO__(0xA783, ## __VA_ARGS__), \
+ MACRO__(0xA788, ## __VA_ARGS__), \
+ MACRO__(0xA789, ## __VA_ARGS__), \
+ MACRO__(0xA78A, ## __VA_ARGS__), \
+ MACRO__(0xA78B, ## __VA_ARGS__)
-:1777: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1777: FILE: include/drm/i915_pciids.h:700:
+#define INTEL_RPLS_IDS(MACRO__, ...) \
+ MACRO__(0xA780, ## __VA_ARGS__), \
+ MACRO__(0xA781, ## __VA_ARGS__), \
+ MACRO__(0xA782, ## __VA_ARGS__), \
+ MACRO__(0xA783, ## __VA_ARGS__), \
+ MACRO__(0xA788, ## __VA_ARGS__), \
+ MACRO__(0xA789, ## __VA_ARGS__), \
+ MACRO__(0xA78A, ## __VA_ARGS__), \
+ MACRO__(0xA78B, ## __VA_ARGS__)
-:1794: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1794: FILE: include/drm/i915_pciids.h:711:
+#define INTEL_RPLU_IDS(MACRO__, ...) \
+ MACRO__(0xA721, ## __VA_ARGS__), \
+ MACRO__(0xA7A1, ## __VA_ARGS__), \
+ MACRO__(0xA7A9, ## __VA_ARGS__), \
+ MACRO__(0xA7AC, ## __VA_ARGS__), \
+ MACRO__(0xA7AD, ## __VA_ARGS__)
-:1794: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1794: FILE: include/drm/i915_pciids.h:711:
+#define INTEL_RPLU_IDS(MACRO__, ...) \
+ MACRO__(0xA721, ## __VA_ARGS__), \
+ MACRO__(0xA7A1, ## __VA_ARGS__), \
+ MACRO__(0xA7A9, ## __VA_ARGS__), \
+ MACRO__(0xA7AC, ## __VA_ARGS__), \
+ MACRO__(0xA7AD, ## __VA_ARGS__)
-:1808: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1808: FILE: include/drm/i915_pciids.h:719:
+#define INTEL_RPLP_IDS(MACRO__, ...) \
+ MACRO__(0xA720, ## __VA_ARGS__), \
+ MACRO__(0xA7A0, ## __VA_ARGS__), \
+ MACRO__(0xA7A8, ## __VA_ARGS__), \
+ MACRO__(0xA7AA, ## __VA_ARGS__), \
+ MACRO__(0xA7AB, ## __VA_ARGS__)
-:1808: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1808: FILE: include/drm/i915_pciids.h:719:
+#define INTEL_RPLP_IDS(MACRO__, ...) \
+ MACRO__(0xA720, ## __VA_ARGS__), \
+ MACRO__(0xA7A0, ## __VA_ARGS__), \
+ MACRO__(0xA7A8, ## __VA_ARGS__), \
+ MACRO__(0xA7AA, ## __VA_ARGS__), \
+ MACRO__(0xA7AB, ## __VA_ARGS__)
-:1862: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1862: FILE: include/drm/i915_pciids.h:727:
+#define INTEL_DG2_G10_IDS(MACRO__, ...) \
+ MACRO__(0x5690, ## __VA_ARGS__), \
+ MACRO__(0x5691, ## __VA_ARGS__), \
+ MACRO__(0x5692, ## __VA_ARGS__), \
+ MACRO__(0x56A0, ## __VA_ARGS__), \
+ MACRO__(0x56A1, ## __VA_ARGS__), \
+ MACRO__(0x56A2, ## __VA_ARGS__), \
+ MACRO__(0x56BE, ## __VA_ARGS__), \
+ MACRO__(0x56BF, ## __VA_ARGS__)
-:1862: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1862: FILE: include/drm/i915_pciids.h:727:
+#define INTEL_DG2_G10_IDS(MACRO__, ...) \
+ MACRO__(0x5690, ## __VA_ARGS__), \
+ MACRO__(0x5691, ## __VA_ARGS__), \
+ MACRO__(0x5692, ## __VA_ARGS__), \
+ MACRO__(0x56A0, ## __VA_ARGS__), \
+ MACRO__(0x56A1, ## __VA_ARGS__), \
+ MACRO__(0x56A2, ## __VA_ARGS__), \
+ MACRO__(0x56BE, ## __VA_ARGS__), \
+ MACRO__(0x56BF, ## __VA_ARGS__)
-:1872: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1872: FILE: include/drm/i915_pciids.h:737:
+#define INTEL_DG2_G11_IDS(MACRO__, ...) \
+ MACRO__(0x5693, ## __VA_ARGS__), \
+ MACRO__(0x5694, ## __VA_ARGS__), \
+ MACRO__(0x5695, ## __VA_ARGS__), \
+ MACRO__(0x56A5, ## __VA_ARGS__), \
+ MACRO__(0x56A6, ## __VA_ARGS__), \
+ MACRO__(0x56B0, ## __VA_ARGS__), \
+ MACRO__(0x56B1, ## __VA_ARGS__), \
+ MACRO__(0x56BA, ## __VA_ARGS__), \
+ MACRO__(0x56BB, ## __VA_ARGS__), \
+ MACRO__(0x56BC, ## __VA_ARGS__), \
+ MACRO__(0x56BD, ## __VA_ARGS__)
-:1872: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1872: FILE: include/drm/i915_pciids.h:737:
+#define INTEL_DG2_G11_IDS(MACRO__, ...) \
+ MACRO__(0x5693, ## __VA_ARGS__), \
+ MACRO__(0x5694, ## __VA_ARGS__), \
+ MACRO__(0x5695, ## __VA_ARGS__), \
+ MACRO__(0x56A5, ## __VA_ARGS__), \
+ MACRO__(0x56A6, ## __VA_ARGS__), \
+ MACRO__(0x56B0, ## __VA_ARGS__), \
+ MACRO__(0x56B1, ## __VA_ARGS__), \
+ MACRO__(0x56BA, ## __VA_ARGS__), \
+ MACRO__(0x56BB, ## __VA_ARGS__), \
+ MACRO__(0x56BC, ## __VA_ARGS__), \
+ MACRO__(0x56BD, ## __VA_ARGS__)
-:1885: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1885: FILE: include/drm/i915_pciids.h:750:
+#define INTEL_DG2_G12_IDS(MACRO__, ...) \
+ MACRO__(0x5696, ## __VA_ARGS__), \
+ MACRO__(0x5697, ## __VA_ARGS__), \
+ MACRO__(0x56A3, ## __VA_ARGS__), \
+ MACRO__(0x56A4, ## __VA_ARGS__), \
+ MACRO__(0x56B2, ## __VA_ARGS__), \
+ MACRO__(0x56B3, ## __VA_ARGS__)
-:1885: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1885: FILE: include/drm/i915_pciids.h:750:
+#define INTEL_DG2_G12_IDS(MACRO__, ...) \
+ MACRO__(0x5696, ## __VA_ARGS__), \
+ MACRO__(0x5697, ## __VA_ARGS__), \
+ MACRO__(0x56A3, ## __VA_ARGS__), \
+ MACRO__(0x56A4, ## __VA_ARGS__), \
+ MACRO__(0x56B2, ## __VA_ARGS__), \
+ MACRO__(0x56B3, ## __VA_ARGS__)
-:1893: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1893: FILE: include/drm/i915_pciids.h:758:
+#define INTEL_DG2_IDS(MACRO__, ...) \
+ INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
-:1893: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1893: FILE: include/drm/i915_pciids.h:758:
+#define INTEL_DG2_IDS(MACRO__, ...) \
+ INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
-:1898: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1898: FILE: include/drm/i915_pciids.h:763:
+#define INTEL_ATS_M150_IDS(MACRO__, ...) \
+ MACRO__(0x56C0, ## __VA_ARGS__), \
+ MACRO__(0x56C2, ## __VA_ARGS__)
-:1898: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1898: FILE: include/drm/i915_pciids.h:763:
+#define INTEL_ATS_M150_IDS(MACRO__, ...) \
+ MACRO__(0x56C0, ## __VA_ARGS__), \
+ MACRO__(0x56C2, ## __VA_ARGS__)
-:1905: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1905: FILE: include/drm/i915_pciids.h:770:
+#define INTEL_ATS_M_IDS(MACRO__, ...) \
+ INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
-:1905: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1905: FILE: include/drm/i915_pciids.h:770:
+#define INTEL_ATS_M_IDS(MACRO__, ...) \
+ INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
+ INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
-:1920: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1920: FILE: include/drm/i915_pciids.h:775:
+#define INTEL_MTL_IDS(MACRO__, ...) \
+ MACRO__(0x7D40, ## __VA_ARGS__), \
+ MACRO__(0x7D41, ## __VA_ARGS__), \
+ MACRO__(0x7D45, ## __VA_ARGS__), \
+ MACRO__(0x7D51, ## __VA_ARGS__), \
+ MACRO__(0x7D55, ## __VA_ARGS__), \
+ MACRO__(0x7D60, ## __VA_ARGS__), \
+ MACRO__(0x7D67, ## __VA_ARGS__), \
+ MACRO__(0x7DD1, ## __VA_ARGS__), \
+ MACRO__(0x7DD5, ## __VA_ARGS__)
-:1920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#1920: FILE: include/drm/i915_pciids.h:775:
+#define INTEL_MTL_IDS(MACRO__, ...) \
+ MACRO__(0x7D40, ## __VA_ARGS__), \
+ MACRO__(0x7D41, ## __VA_ARGS__), \
+ MACRO__(0x7D45, ## __VA_ARGS__), \
+ MACRO__(0x7D51, ## __VA_ARGS__), \
+ MACRO__(0x7D55, ## __VA_ARGS__), \
+ MACRO__(0x7D60, ## __VA_ARGS__), \
+ MACRO__(0x7D67, ## __VA_ARGS__), \
+ MACRO__(0x7DD1, ## __VA_ARGS__), \
+ MACRO__(0x7DD5, ## __VA_ARGS__)
total: 95 errors, 0 warnings, 95 checks, 1887 lines checked
16a88d9e58a0 drm/i915: stop redefining INTEL_VGA_DEVICE
^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
` (2 preceding siblings ...)
2024-05-15 18:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
@ 2024-05-15 18:10 ` Patchwork
2024-05-16 5:15 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-05-15 18:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
URL : https://patchwork.freedesktop.org/series/133664/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
^ permalink raw reply [flat|nested] 11+ messages in thread* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
` (3 preceding siblings ...)
2024-05-15 18:10 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-16 5:15 ` Patchwork
2024-05-16 13:25 ` [PATCH 1/2] " Rodrigo Vivi
2024-05-20 12:27 ` Jani Nikula
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2024-05-16 5:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 71044 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
URL : https://patchwork.freedesktop.org/series/133664/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14768_full -> Patchwork_133664v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133664v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133664v1_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133664v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_spin_batch@legacy@blt:
- shard-dg1: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg1-13/igt@gem_spin_batch@legacy@blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_spin_batch@legacy@blt.html
* igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk3/igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-c-hdmi-a-1.html
Known issues
------------
Here are the changes found in Patchwork_133664v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- shard-rkl: NOTRUN -> [SKIP][4] ([i915#9318])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@cold-reset-bound:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#11078])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@device_reset@cold-reset-bound.html
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#11078])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@device_reset@cold-reset-bound.html
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#11078])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-idle@vecs0:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8414]) +6 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@drm_fdinfo@busy-idle@vecs0.html
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: NOTRUN -> [FAIL][9] ([i915#7742]) +1 other test fail
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#8414]) +5 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8414])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][12] ([i915#9323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy.html
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#9323])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#7697])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#8562])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@gem_create@create-ext-set-pat.html
- shard-dg1: NOTRUN -> [SKIP][17] ([i915#8562])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@hang:
- shard-dg1: NOTRUN -> [SKIP][18] ([i915#8555])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][19] ([i915#1099])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_ctx_sseu@invalid-args:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#280])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@gem_ctx_sseu@invalid-args.html
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#280])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-tglu: NOTRUN -> [ABORT][22] ([i915#10030] / [i915#7975] / [i915#8213])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#4525])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@sliced:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#4812])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_exec_balancer@sliced.html
- shard-dg1: NOTRUN -> [SKIP][25] ([i915#4812])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglu: [PASS][26] -> [FAIL][27] ([i915#2842])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-tglu-3/igt@gem_exec_fair@basic-none-share@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-rkl: [PASS][28] -> [FAIL][29] ([i915#2842])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglu: NOTRUN -> [FAIL][30] ([i915#2842])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][31] ([i915#2842])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-sync:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#4473] / [i915#4771])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-gtt:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3281]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_exec_reloc@basic-cpu-gtt.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#3281]) +7 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#3281]) +8 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][38] ([i915#7975] / [i915#8213])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4860])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#4860])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4860])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_lmem_swapping@basic@lmem0:
- shard-dg2: [PASS][42] -> [FAIL][43] ([i915#10378])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-6/igt@gem_lmem_swapping@basic@lmem0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg1: NOTRUN -> [FAIL][44] ([i915#10378])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#4613]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk: NOTRUN -> [SKIP][46] ([i915#4613]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk3/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_mmap_gtt@basic-write-read:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#4077]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@gem_mmap_gtt@basic-write-read.html
* igt@gem_mmap_gtt@big-copy:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4077]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@medium-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#4077]) +9 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_mmap_gtt@medium-copy-odd.html
* igt@gem_mmap_wc@bad-size:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4083]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_mmap_wc@bad-size.html
* igt@gem_mmap_wc@read-write-distinct:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4083]) +4 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_mmap_wc@read-write-distinct.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#3282]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#3282])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#3282])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4270])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#4270]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@gem_pxp@protected-raw-src-copy-not-readible.html
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#4270]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#4270])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#8428]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#8411])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4079])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#3297])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-tglu: NOTRUN -> [SKIP][63] ([i915#3297])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen9_exec_parse@bb-start-out:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#2527]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@gen9_exec_parse@bb-start-out.html
- shard-dg1: NOTRUN -> [SKIP][65] ([i915#2527]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@gen9_exec_parse@bb-start-out.html
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#2856])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [PASS][67] -> [INCOMPLETE][68] ([i915#1982] / [i915#9820] / [i915#9849])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg1-15/igt@i915_module_load@reload-with-fault-injection.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: [PASS][69] -> [INCOMPLETE][70] ([i915#10047] / [i915#10887] / [i915#9820])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-tglu-4/igt@i915_module_load@reload-with-fault-injection.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-mtlp: NOTRUN -> [SKIP][71] +3 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#8925])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#7707])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-dg1: NOTRUN -> [SKIP][74] ([i915#4212]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_addfb_basic@tile-pitch-mismatch.html
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4212])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-glk: NOTRUN -> [SKIP][76] ([i915#1769]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][77] ([i915#4538] / [i915#5286]) +4 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][78] ([i915#5286])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#5286]) +3 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3638])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#3638]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4538] / [i915#5190]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][83] ([i915#4538]) +3 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_joiner@invalid-modeset-force-joiner:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#10656])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-5/igt@kms_big_joiner@invalid-modeset-force-joiner.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-10/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#6095]) +51 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#6095]) +53 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#10307] / [i915#6095]) +161 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
- shard-snb: NOTRUN -> [SKIP][89] +112 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#6095]) +15 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-edp-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][91] ([i915#6095]) +3 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#4087]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_edid@dp-edid-read:
- shard-tglu: NOTRUN -> [SKIP][93] ([i915#7828])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#7828]) +6 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#7828]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_hpd@dp-hpd-storm-disable:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#7828]) +5 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
* igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#7828]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
* igt@kms_content_protection@content-type-change:
- shard-rkl: NOTRUN -> [SKIP][98] ([i915#9424])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#3299])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#3116]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_content_protection@dp-mst-type-1.html
- shard-dg1: NOTRUN -> [SKIP][101] ([i915#3299]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#7118] / [i915#9424])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-5/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@uevent:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#7118] / [i915#9424])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#3359])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#8814])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#3359])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-rkl: NOTRUN -> [SKIP][108] ([i915#4103])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#4103] / [i915#4213]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-rkl: NOTRUN -> [SKIP][110] +30 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-snb: [PASS][111] -> [SKIP][112] +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#9723])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#9227])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_feature_discovery@display-3x:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#1839])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#9337])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_feature_discovery@dp-mst.html
- shard-rkl: NOTRUN -> [SKIP][117] ([i915#9337])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_feature_discovery@dp-mst.html
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#9337])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][119] -> [FAIL][120] ([i915#79])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#3637])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#9934]) +2 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1:
- shard-snb: NOTRUN -> [FAIL][123] ([i915#2122])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@kms_flip@2x-plain-flip-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1:
- shard-snb: [PASS][124] -> [FAIL][125] ([i915#2122])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb6/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#2672]) +3 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#2587] / [i915#2672]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#2672])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-dg2: [PASS][129] -> [FAIL][130] ([i915#6880]) +2 other tests fail
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#1825]) +10 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#5354]) +3 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#8708]) +13 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#3023]) +13 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][135] +9 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#1825]) +23 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#10070])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#10070])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#10070])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#10433] / [i915#3458]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#3458]) +13 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#3458]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#8708]) +7 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle-suspend:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#8228])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#3555]) +4 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_plane_multiple@tiling-yf.html
- shard-dg1: NOTRUN -> [SKIP][146] ([i915#3555]) +6 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_plane_multiple@tiling-yf.html
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#3555] / [i915#8806])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-tglu: NOTRUN -> [SKIP][148] ([i915#6953])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-3/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][149] ([i915#8292])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#9423]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#9423]) +7 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#9423]) +3 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-13/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#5235]) +7 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#5235] / [i915#9423]) +7 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#5235]) +3 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_pm_backlight@fade:
- shard-rkl: NOTRUN -> [SKIP][157] ([i915#5354])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_pm_backlight@fade.html
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#5354])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#9685])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#3361])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html
- shard-dg1: NOTRUN -> [SKIP][161] ([i915#3361])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_pm_dc@dc6-dpms.html
- shard-tglu: [PASS][162] -> [FAIL][163] ([i915#9295])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-7/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#9340])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#9519])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][166] -> [SKIP][167] ([i915#9519])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-10/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#9519])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][169] -> [SKIP][170] ([i915#9519])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#9519])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2: NOTRUN -> [SKIP][172] +4 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_psr2_sf@fbc-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][173] +34 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-pr-cursor-render:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#9688]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_psr@fbc-pr-cursor-render.html
* igt@kms_psr@fbc-pr-sprite-blt:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#1072] / [i915#9732]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_psr@fbc-pr-sprite-blt.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#9732]) +1 other test skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-psr2-cursor-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][177] +172 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk8/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#1072] / [i915#9732]) +13 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#1072] / [i915#9732]) +14 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-17/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#5190])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#5289])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#5289]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#4235])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-tglu: NOTRUN -> [SKIP][184] ([i915#3555])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [PASS][185] -> [FAIL][186] ([i915#9196])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [PASS][187] -> [FAIL][188] ([i915#9196])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [PASS][189] -> [FAIL][190] ([i915#9196])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#2437] / [i915#9412])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-10/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-glk: NOTRUN -> [SKIP][192] ([i915#2437])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][193] ([i915#2436] / [i915#7387])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@perf@gen8-unprivileged-single-ctx-counters.html
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#2436])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#7387])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@perf@global-sseu-config.html
* igt@perf@mi-rpc:
- shard-dg1: NOTRUN -> [SKIP][196] ([i915#2434])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][197] ([i915#2435])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@perf@per-context-mode-unprivileged.html
- shard-dg1: NOTRUN -> [SKIP][198] ([i915#2433])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@perf@per-context-mode-unprivileged.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#9917])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-4/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#9917])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-glk: NOTRUN -> [FAIL][201] ([i915#9781])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk7/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-glk: NOTRUN -> [FAIL][202] ([i915#9779])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk7/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_submit_cl@bad-extension:
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#2575]) +8 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@v3d/v3d_submit_cl@bad-extension.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#2575]) +3 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_csd@bad-bo:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#2575]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@v3d/v3d_submit_csd@bad-bo.html
* igt@vc4/vc4_label_bo@set-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][206] ([i915#7711]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@vc4/vc4_label_bo@set-bad-handle.html
* igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#7711]) +5 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-16/igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem.html
* igt@vc4/vc4_tiling@get-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#7711]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@vc4/vc4_tiling@get-bad-handle.html
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#7711]) +3 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-1/igt@vc4/vc4_tiling@get-bad-handle.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-tglu: [INCOMPLETE][210] ([i915#10513]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-tglu-9/igt@gem_eio@kms.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-tglu-3/igt@gem_eio@kms.html
- shard-dg2: [INCOMPLETE][212] ([i915#10513]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-10/igt@gem_eio@kms.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [FAIL][214] ([i915#2842]) -> [PASS][215] +3 other tests pass
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-4/igt@gem_exec_fair@basic-none@vecs0.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][216] ([i915#2842]) -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@heavy-multi@lmem0:
- shard-dg2: [FAIL][218] ([i915#10378]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-11/igt@gem_lmem_swapping@heavy-multi@lmem0.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-3/igt@gem_lmem_swapping@heavy-multi@lmem0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][220] ([i915#5493]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [INCOMPLETE][222] ([i915#9849]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-dg1: [INCOMPLETE][224] -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg1-14/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg1-18/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][226] ([i915#10031]) -> [PASS][227]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@torture-bo@all-pipes:
- shard-snb: [ABORT][228] -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb6/igt@kms_cursor_legacy@torture-bo@all-pipes.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb4/igt@kms_cursor_legacy@torture-bo@all-pipes.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][230] ([i915#2122]) -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb4/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
- shard-snb: [DMESG-WARN][232] -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-snb: [INCOMPLETE][234] ([i915#4839]) -> [PASS][235]
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-snb: [SKIP][236] -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][238] ([i915#9519]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg2: [FAIL][240] ([i915#8717]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-2/igt@kms_pm_rpm@i2c.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-10/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][242] ([i915#9519]) -> [PASS][243] +4 other tests pass
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-11/igt@kms_pm_rpm@modeset-lpsp.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2:
- shard-rkl: [FAIL][244] ([i915#9196]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-3/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][246] ([i915#4349]) -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-rkl-5/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][248] ([i915#9846]) -> [INCOMPLETE][249] ([i915#9364])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-5/igt@gem_create@create-ext-cpu-access-big.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][250] ([i915#10131] / [i915#10887] / [i915#9820]) -> [ABORT][251] ([i915#10131] / [i915#9697])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-mtlp: [ABORT][252] -> [SKIP][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-mtlp-3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-mtlp-1/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][254] ([i915#10826]) -> [FAIL][255] ([i915#2122])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-dg2: [SKIP][256] ([i915#10433] / [i915#3458]) -> [SKIP][257] ([i915#3458])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg2: [SKIP][258] ([i915#3458]) -> [SKIP][259] ([i915#10433] / [i915#3458]) +2 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-dg2: [SKIP][260] ([i915#1072] / [i915#9732]) -> [SKIP][261] ([i915#1072] / [i915#9673] / [i915#9732]) +3 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-8/igt@kms_psr@fbc-pr-primary-render.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-11/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: [SKIP][262] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][263] ([i915#1072] / [i915#9732]) +17 other tests skip
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14768/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/shard-dg2-8/igt@kms_psr@psr-cursor-render.html
[i915#10030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10030
[i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
[i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
[i915#10070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10070
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8717
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9697
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14768 -> Patchwork_133664v1
CI-20190529: 20190529
CI_DRM_14768: 26a52a7b24c1f334d92f5deac9f3eaf3224f3864 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7855: 7855
Patchwork_133664v1: 26a52a7b24c1f334d92f5deac9f3eaf3224f3864 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133664v1/index.html
[-- Attachment #2: Type: text/html, Size: 86240 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
` (4 preceding siblings ...)
2024-05-16 5:15 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-05-16 13:25 ` Rodrigo Vivi
2024-05-20 12:27 ` Jani Nikula
6 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2024-05-16 13:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Bjorn Helgaas, linux-pci, Lucas De Marchi
On Wed, May 15, 2024 at 07:56:50PM +0300, Jani Nikula wrote:
> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
> same pattern.
>
> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Tip: It's probably easiest to apply and use 'git show --color-words' for
> review.
>
> This transformation is completely scripted:
>
> | #!/bin/bash
> |
> | FILE=include/drm/i915_pciids.h
> |
> | sed -i 's/[\t ]*\\/ \\/' $FILE
> |
> | sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
> |
> | sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
> |
> | sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ## __VA_ARGS__)/' $FILE
> |
> | # Special case: IVB Q transcode
> | sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
> |
> | # Change all users
> | for file in $(git grep -l "#include <drm/i915_pciids.h>"); do
> | for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed 's/#define //'); do
> | sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
> | done
> | done
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 80 +-
> .../drm/i915/display/intel_display_device.c | 86 +-
> drivers/gpu/drm/i915/i915_pci.c | 150 +-
> drivers/gpu/drm/i915/intel_device_info.c | 88 +-
> include/drm/i915_pciids.h | 1348 ++++++++---------
> 5 files changed, 876 insertions(+), 876 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fd74d7f26f01..1c137771c5d2 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops __initconst = {
>
> /* Intel integrated GPUs for which we need to reserve "stolen memory" */
> static const struct pci_device_id intel_early_ids[] __initconst = {
> - INTEL_I830_IDS(&i830_early_ops),
> - INTEL_I845G_IDS(&i845_early_ops),
> - INTEL_I85X_IDS(&i85x_early_ops),
> - INTEL_I865G_IDS(&i865_early_ops),
> - INTEL_I915G_IDS(&gen3_early_ops),
> - INTEL_I915GM_IDS(&gen3_early_ops),
> - INTEL_I945G_IDS(&gen3_early_ops),
> - INTEL_I945GM_IDS(&gen3_early_ops),
> - INTEL_VLV_IDS(&gen6_early_ops),
> - INTEL_PNV_IDS(&gen3_early_ops),
> - INTEL_I965G_IDS(&gen3_early_ops),
> - INTEL_G33_IDS(&gen3_early_ops),
> - INTEL_I965GM_IDS(&gen3_early_ops),
> - INTEL_GM45_IDS(&gen3_early_ops),
> - INTEL_G45_IDS(&gen3_early_ops),
> - INTEL_ILK_IDS(&gen3_early_ops),
> - INTEL_SNB_IDS(&gen6_early_ops),
> - INTEL_IVB_IDS(&gen6_early_ops),
> - INTEL_HSW_IDS(&gen6_early_ops),
> - INTEL_BDW_IDS(&gen8_early_ops),
> - INTEL_CHV_IDS(&chv_early_ops),
> - INTEL_SKL_IDS(&gen9_early_ops),
> - INTEL_BXT_IDS(&gen9_early_ops),
> - INTEL_KBL_IDS(&gen9_early_ops),
> - INTEL_CFL_IDS(&gen9_early_ops),
> - INTEL_WHL_IDS(&gen9_early_ops),
> - INTEL_CML_IDS(&gen9_early_ops),
> - INTEL_GLK_IDS(&gen9_early_ops),
> - INTEL_CNL_IDS(&gen9_early_ops),
> - INTEL_ICL_IDS(&gen11_early_ops),
> - INTEL_EHL_IDS(&gen11_early_ops),
> - INTEL_JSL_IDS(&gen11_early_ops),
> - INTEL_TGL_IDS(&gen11_early_ops),
> - INTEL_RKL_IDS(&gen11_early_ops),
> - INTEL_ADLS_IDS(&gen11_early_ops),
> - INTEL_ADLP_IDS(&gen11_early_ops),
> - INTEL_ADLN_IDS(&gen11_early_ops),
> - INTEL_RPLS_IDS(&gen11_early_ops),
> - INTEL_RPLU_IDS(&gen11_early_ops),
> - INTEL_RPLP_IDS(&gen11_early_ops),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &gen8_early_ops),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_early_ops),
> + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CML_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CNL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 89069cff06b4..950e66cdba0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -788,7 +788,7 @@ __diag_pop();
> static bool has_no_display(struct pci_dev *pdev)
> {
> static const struct pci_device_id ids[] = {
> - INTEL_IVB_Q_IDS(0),
> + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0),
> {}
> };
>
> @@ -802,48 +802,48 @@ static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(&i830_display),
> - INTEL_I845G_IDS(&i845_display),
> - INTEL_I85X_IDS(&i85x_display),
> - INTEL_I865G_IDS(&i865g_display),
> - INTEL_I915G_IDS(&i915g_display),
> - INTEL_I915GM_IDS(&i915gm_display),
> - INTEL_I945G_IDS(&i945g_display),
> - INTEL_I945GM_IDS(&i945gm_display),
> - INTEL_I965G_IDS(&i965g_display),
> - INTEL_G33_IDS(&g33_display),
> - INTEL_I965GM_IDS(&i965gm_display),
> - INTEL_GM45_IDS(&gm45_display),
> - INTEL_G45_IDS(&g45_display),
> - INTEL_PNV_IDS(&pnv_display),
> - INTEL_ILK_D_IDS(&ilk_d_display),
> - INTEL_ILK_M_IDS(&ilk_m_display),
> - INTEL_SNB_IDS(&snb_display),
> - INTEL_IVB_IDS(&ivb_display),
> - INTEL_HSW_IDS(&hsw_display),
> - INTEL_VLV_IDS(&vlv_display),
> - INTEL_BDW_IDS(&bdw_display),
> - INTEL_CHV_IDS(&chv_display),
> - INTEL_SKL_IDS(&skl_display),
> - INTEL_BXT_IDS(&bxt_display),
> - INTEL_GLK_IDS(&glk_display),
> - INTEL_KBL_IDS(&skl_display),
> - INTEL_CFL_IDS(&skl_display),
> - INTEL_WHL_IDS(&skl_display),
> - INTEL_CML_IDS(&skl_display),
> - INTEL_ICL_IDS(&icl_display),
> - INTEL_EHL_IDS(&jsl_ehl_display),
> - INTEL_JSL_IDS(&jsl_ehl_display),
> - INTEL_TGL_IDS(&tgl_display),
> - INTEL_DG1_IDS(&dg1_display),
> - INTEL_RKL_IDS(&rkl_display),
> - INTEL_ADLS_IDS(&adl_s_display),
> - INTEL_RPLS_IDS(&adl_s_display),
> - INTEL_ADLP_IDS(&xe_lpd_display),
> - INTEL_ADLN_IDS(&xe_lpd_display),
> - INTEL_RPLU_IDS(&xe_lpd_display),
> - INTEL_RPLP_IDS(&xe_lpd_display),
> - INTEL_DG2_IDS(&xe_hpd_display),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display),
> + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display),
> + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display),
> + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display),
> + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display),
> + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display),
> + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display),
> + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display),
>
> /*
> * Do not add any GMD_ID-based platforms to this list. They will
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 74202925d13f..84cd2f0343a2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -797,81 +797,81 @@ __diag_pop();
> * PCI ID matches, otherwise we'll use the wrong info struct above.
> */
> static const struct pci_device_id pciidlist[] = {
> - INTEL_I830_IDS(&i830_info),
> - INTEL_I845G_IDS(&i845g_info),
> - INTEL_I85X_IDS(&i85x_info),
> - INTEL_I865G_IDS(&i865g_info),
> - INTEL_I915G_IDS(&i915g_info),
> - INTEL_I915GM_IDS(&i915gm_info),
> - INTEL_I945G_IDS(&i945g_info),
> - INTEL_I945GM_IDS(&i945gm_info),
> - INTEL_I965G_IDS(&i965g_info),
> - INTEL_G33_IDS(&g33_info),
> - INTEL_I965GM_IDS(&i965gm_info),
> - INTEL_GM45_IDS(&gm45_info),
> - INTEL_G45_IDS(&g45_info),
> - INTEL_PNV_G_IDS(&pnv_g_info),
> - INTEL_PNV_M_IDS(&pnv_m_info),
> - INTEL_ILK_D_IDS(&ilk_d_info),
> - INTEL_ILK_M_IDS(&ilk_m_info),
> - INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
> - INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
> - INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
> - INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
> - INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
> - INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
> - INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
> - INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
> - INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
> - INTEL_HSW_GT1_IDS(&hsw_gt1_info),
> - INTEL_HSW_GT2_IDS(&hsw_gt2_info),
> - INTEL_HSW_GT3_IDS(&hsw_gt3_info),
> - INTEL_VLV_IDS(&vlv_info),
> - INTEL_BDW_GT1_IDS(&bdw_gt1_info),
> - INTEL_BDW_GT2_IDS(&bdw_gt2_info),
> - INTEL_BDW_GT3_IDS(&bdw_gt3_info),
> - INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
> - INTEL_CHV_IDS(&chv_info),
> - INTEL_SKL_GT1_IDS(&skl_gt1_info),
> - INTEL_SKL_GT2_IDS(&skl_gt2_info),
> - INTEL_SKL_GT3_IDS(&skl_gt3_info),
> - INTEL_SKL_GT4_IDS(&skl_gt4_info),
> - INTEL_BXT_IDS(&bxt_info),
> - INTEL_GLK_IDS(&glk_info),
> - INTEL_KBL_GT1_IDS(&kbl_gt1_info),
> - INTEL_KBL_GT2_IDS(&kbl_gt2_info),
> - INTEL_KBL_GT3_IDS(&kbl_gt3_info),
> - INTEL_KBL_GT4_IDS(&kbl_gt3_info),
> - INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
> - INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
> - INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
> - INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
> - INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
> - INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
> - INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
> - INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
> - INTEL_CML_GT1_IDS(&cml_gt1_info),
> - INTEL_CML_GT2_IDS(&cml_gt2_info),
> - INTEL_CML_U_GT1_IDS(&cml_gt1_info),
> - INTEL_CML_U_GT2_IDS(&cml_gt2_info),
> - INTEL_ICL_IDS(&icl_info),
> - INTEL_EHL_IDS(&ehl_info),
> - INTEL_JSL_IDS(&jsl_info),
> - INTEL_TGL_IDS(&tgl_info),
> - INTEL_RKL_IDS(&rkl_info),
> - INTEL_ADLS_IDS(&adl_s_info),
> - INTEL_ADLP_IDS(&adl_p_info),
> - INTEL_ADLN_IDS(&adl_p_info),
> - INTEL_DG1_IDS(&dg1_info),
> - INTEL_RPLS_IDS(&adl_s_info),
> - INTEL_RPLU_IDS(&adl_p_info),
> - INTEL_RPLP_IDS(&adl_p_info),
> - INTEL_DG2_IDS(&dg2_info),
> - INTEL_ATS_M_IDS(&ats_m_info),
> - INTEL_MTL_IDS(&mtl_info),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info),
> + INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info),
> + INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info),
> + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info),
> + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info),
> + INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info),
> + INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info),
> + INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info),
> + INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info),
> + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */
> + INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info),
> + INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info),
> + INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info),
> + INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info),
> + INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info),
> + INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info),
> + INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info),
> + INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info),
> + INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info),
> + INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info),
> + INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info),
> + INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info),
> + INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info),
> + INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info),
> + INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info),
> + INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info),
> + INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
> + INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
> + INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
> + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
> + INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
> + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
> + INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
> + INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
> + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
> + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info),
> + INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info),
> + INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info),
> {}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a39497971994..82bb34416fb1 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -131,77 +131,77 @@ void intel_device_info_print(const struct intel_device_info *info,
> #define INTEL_VGA_DEVICE(id, info) (id)
>
> static const u16 subplatform_ult_ids[] = {
> - INTEL_HSW_ULT_GT1_IDS(0),
> - INTEL_HSW_ULT_GT2_IDS(0),
> - INTEL_HSW_ULT_GT3_IDS(0),
> - INTEL_BDW_ULT_GT1_IDS(0),
> - INTEL_BDW_ULT_GT2_IDS(0),
> - INTEL_BDW_ULT_GT3_IDS(0),
> - INTEL_BDW_ULT_RSVD_IDS(0),
> - INTEL_SKL_ULT_GT1_IDS(0),
> - INTEL_SKL_ULT_GT2_IDS(0),
> - INTEL_SKL_ULT_GT3_IDS(0),
> - INTEL_KBL_ULT_GT1_IDS(0),
> - INTEL_KBL_ULT_GT2_IDS(0),
> - INTEL_KBL_ULT_GT3_IDS(0),
> - INTEL_CFL_U_GT2_IDS(0),
> - INTEL_CFL_U_GT3_IDS(0),
> - INTEL_WHL_U_GT1_IDS(0),
> - INTEL_WHL_U_GT2_IDS(0),
> - INTEL_WHL_U_GT3_IDS(0),
> - INTEL_CML_U_GT1_IDS(0),
> - INTEL_CML_U_GT2_IDS(0),
> + INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_ulx_ids[] = {
> - INTEL_HSW_ULX_GT1_IDS(0),
> - INTEL_HSW_ULX_GT2_IDS(0),
> - INTEL_BDW_ULX_GT1_IDS(0),
> - INTEL_BDW_ULX_GT2_IDS(0),
> - INTEL_BDW_ULX_GT3_IDS(0),
> - INTEL_BDW_ULX_RSVD_IDS(0),
> - INTEL_SKL_ULX_GT1_IDS(0),
> - INTEL_SKL_ULX_GT2_IDS(0),
> - INTEL_KBL_ULX_GT1_IDS(0),
> - INTEL_KBL_ULX_GT2_IDS(0),
> - INTEL_AML_KBL_GT2_IDS(0),
> - INTEL_AML_CFL_GT2_IDS(0),
> + INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_portf_ids[] = {
> - INTEL_ICL_PORT_F_IDS(0),
> + INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_uy_ids[] = {
> - INTEL_TGL_GT2_IDS(0),
> + INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_n_ids[] = {
> - INTEL_ADLN_IDS(0),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_rpl_ids[] = {
> - INTEL_RPLS_IDS(0),
> - INTEL_RPLU_IDS(0),
> - INTEL_RPLP_IDS(0),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_rplu_ids[] = {
> - INTEL_RPLU_IDS(0),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g10_ids[] = {
> - INTEL_DG2_G10_IDS(0),
> - INTEL_ATS_M150_IDS(0),
> + INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g11_ids[] = {
> - INTEL_DG2_G11_IDS(0),
> - INTEL_ATS_M75_IDS(0),
> + INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g12_ids[] = {
> - INTEL_DG2_G12_IDS(0),
> + INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 04f6ca3dc5c1..3e39d644ebaa 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -35,752 +35,752 @@
> * Don't use C99 here because "class" is reserved and we want to
> * give userspace flexibility.
> */
> -#define INTEL_VGA_DEVICE(id, info) { \
> - 0x8086, id, \
> - ~0, ~0, \
> - 0x030000, 0xff0000, \
> +#define INTEL_VGA_DEVICE(id, info) { \
> + 0x8086, id, \
> + ~0, ~0, \
> + 0x030000, 0xff0000, \
> (unsigned long) info }
>
> -#define INTEL_QUANTA_VGA_DEVICE(info) { \
> - 0x8086, 0x16a, \
> - 0x152d, 0x8990, \
> - 0x030000, 0xff0000, \
> +#define INTEL_QUANTA_VGA_DEVICE(info) { \
> + 0x8086, 0x16a, \
> + 0x152d, 0x8990, \
> + 0x030000, 0xff0000, \
> (unsigned long) info }
>
> -#define INTEL_I810_IDS(info) \
> - INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
> - INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
> - INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
> +#define INTEL_I810_IDS(MACRO__, ...) \
> + MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
> + MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
> + MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
>
> -#define INTEL_I815_IDS(info) \
> - INTEL_VGA_DEVICE(0x1132, info) /* I815*/
> +#define INTEL_I815_IDS(MACRO__, ...) \
> + MACRO__(0x1132, ## __VA_ARGS__) /* I815*/
>
> -#define INTEL_I830_IDS(info) \
> - INTEL_VGA_DEVICE(0x3577, info)
> +#define INTEL_I830_IDS(MACRO__, ...) \
> + MACRO__(0x3577, ## __VA_ARGS__)
>
> -#define INTEL_I845G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2562, info)
> +#define INTEL_I845G_IDS(MACRO__, ...) \
> + MACRO__(0x2562, ## __VA_ARGS__)
>
> -#define INTEL_I85X_IDS(info) \
> - INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
> - INTEL_VGA_DEVICE(0x358e, info)
> +#define INTEL_I85X_IDS(MACRO__, ...) \
> + MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
> + MACRO__(0x358e, ## __VA_ARGS__)
>
> -#define INTEL_I865G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
> +#define INTEL_I865G_IDS(MACRO__, ...) \
> + MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */
>
> -#define INTEL_I915G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
> - INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
> +#define INTEL_I915G_IDS(MACRO__, ...) \
> + MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
> + MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
>
> -#define INTEL_I915GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
> +#define INTEL_I915GM_IDS(MACRO__, ...) \
> + MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */
>
> -#define INTEL_I945G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
> +#define INTEL_I945G_IDS(MACRO__, ...) \
> + MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */
>
> -#define INTEL_I945GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
> - INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
> +#define INTEL_I945GM_IDS(MACRO__, ...) \
> + MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
> + MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
>
> -#define INTEL_I965G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
> - INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
> - INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
> - INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
> +#define INTEL_I965G_IDS(MACRO__, ...) \
> + MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
> + MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
> + MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
> + MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
>
> -#define INTEL_G33_IDS(info) \
> - INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
> - INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
> - INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
> +#define INTEL_G33_IDS(MACRO__, ...) \
> + MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
> + MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
> + MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
>
> -#define INTEL_I965GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
> - INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
> +#define INTEL_I965GM_IDS(MACRO__, ...) \
> + MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
> + MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
>
> -#define INTEL_GM45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
> +#define INTEL_GM45_IDS(MACRO__, ...) \
> + MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */
>
> -#define INTEL_G45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
> - INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
> - INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
> - INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
> - INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> - INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
> -
> -#define INTEL_PNV_G_IDS(info) \
> - INTEL_VGA_DEVICE(0xa001, info)
> -
> -#define INTEL_PNV_M_IDS(info) \
> - INTEL_VGA_DEVICE(0xa011, info)
> -
> -#define INTEL_PNV_IDS(info) \
> - INTEL_PNV_G_IDS(info), \
> - INTEL_PNV_M_IDS(info)
> -
> -#define INTEL_ILK_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0042, info)
> -
> -#define INTEL_ILK_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0046, info)
> -
> -#define INTEL_ILK_IDS(info) \
> - INTEL_ILK_D_IDS(info), \
> - INTEL_ILK_M_IDS(info)
> -
> -#define INTEL_SNB_D_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0102, info), \
> - INTEL_VGA_DEVICE(0x010A, info)
> -
> -#define INTEL_SNB_D_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0112, info), \
> - INTEL_VGA_DEVICE(0x0122, info)
> -
> -#define INTEL_SNB_D_IDS(info) \
> - INTEL_SNB_D_GT1_IDS(info), \
> - INTEL_SNB_D_GT2_IDS(info)
> -
> -#define INTEL_SNB_M_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0106, info)
> -
> -#define INTEL_SNB_M_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0116, info), \
> - INTEL_VGA_DEVICE(0x0126, info)
> -
> -#define INTEL_SNB_M_IDS(info) \
> - INTEL_SNB_M_GT1_IDS(info), \
> - INTEL_SNB_M_GT2_IDS(info)
> -
> -#define INTEL_SNB_IDS(info) \
> - INTEL_SNB_D_IDS(info), \
> - INTEL_SNB_M_IDS(info)
> -
> -#define INTEL_IVB_M_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
> -
> -#define INTEL_IVB_M_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
> -
> -#define INTEL_IVB_M_IDS(info) \
> - INTEL_IVB_M_GT1_IDS(info), \
> - INTEL_IVB_M_GT2_IDS(info)
> -
> -#define INTEL_IVB_D_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
> -
> -#define INTEL_IVB_D_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
> -
> -#define INTEL_IVB_D_IDS(info) \
> - INTEL_IVB_D_GT1_IDS(info), \
> - INTEL_IVB_D_GT2_IDS(info)
> -
> -#define INTEL_IVB_IDS(info) \
> - INTEL_IVB_M_IDS(info), \
> - INTEL_IVB_D_IDS(info)
> -
> -#define INTEL_IVB_Q_IDS(info) \
> - INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> -
> -#define INTEL_HSW_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
> -
> -#define INTEL_HSW_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
> -
> -#define INTEL_HSW_GT1_IDS(info) \
> - INTEL_HSW_ULT_GT1_IDS(info), \
> - INTEL_HSW_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> - INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> - INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
> -
> -#define INTEL_HSW_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
> -
> -#define INTEL_HSW_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
> -
> -#define INTEL_HSW_GT2_IDS(info) \
> - INTEL_HSW_ULT_GT2_IDS(info), \
> - INTEL_HSW_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
> - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
> -
> -#define INTEL_HSW_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
> -
> -#define INTEL_HSW_GT3_IDS(info) \
> - INTEL_HSW_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
> - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
> -
> -#define INTEL_HSW_IDS(info) \
> - INTEL_HSW_GT1_IDS(info), \
> - INTEL_HSW_GT2_IDS(info), \
> - INTEL_HSW_GT3_IDS(info)
> -
> -#define INTEL_VLV_IDS(info) \
> - INTEL_VGA_DEVICE(0x0f30, info), \
> - INTEL_VGA_DEVICE(0x0f31, info), \
> - INTEL_VGA_DEVICE(0x0f32, info), \
> - INTEL_VGA_DEVICE(0x0f33, info)
> -
> -#define INTEL_BDW_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
> -
> -#define INTEL_BDW_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
> -
> -#define INTEL_BDW_GT1_IDS(info) \
> - INTEL_BDW_ULT_GT1_IDS(info), \
> - INTEL_BDW_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> - INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
> -
> -#define INTEL_BDW_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
> -
> -#define INTEL_BDW_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> -
> -#define INTEL_BDW_GT2_IDS(info) \
> - INTEL_BDW_ULT_GT2_IDS(info), \
> - INTEL_BDW_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> - INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> - INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> -
> -#define INTEL_BDW_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
> -
> -#define INTEL_BDW_ULX_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> -
> -#define INTEL_BDW_GT3_IDS(info) \
> - INTEL_BDW_ULT_GT3_IDS(info), \
> - INTEL_BDW_ULX_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> -
> -#define INTEL_BDW_ULT_RSVD_IDS(info) \
> - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163B, info) /* Iris */
> -
> -#define INTEL_BDW_ULX_RSVD_IDS(info) \
> - INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> -
> -#define INTEL_BDW_RSVD_IDS(info) \
> - INTEL_BDW_ULT_RSVD_IDS(info), \
> - INTEL_BDW_ULX_RSVD_IDS(info), \
> - INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> -
> -#define INTEL_BDW_IDS(info) \
> - INTEL_BDW_GT1_IDS(info), \
> - INTEL_BDW_GT2_IDS(info), \
> - INTEL_BDW_GT3_IDS(info), \
> - INTEL_BDW_RSVD_IDS(info)
> -
> -#define INTEL_CHV_IDS(info) \
> - INTEL_VGA_DEVICE(0x22b0, info), \
> - INTEL_VGA_DEVICE(0x22b1, info), \
> - INTEL_VGA_DEVICE(0x22b2, info), \
> - INTEL_VGA_DEVICE(0x22b3, info)
> -
> -#define INTEL_SKL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
> -
> -#define INTEL_SKL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
> -
> -#define INTEL_SKL_GT1_IDS(info) \
> - INTEL_SKL_ULT_GT1_IDS(info), \
> - INTEL_SKL_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */
> -
> -#define INTEL_SKL_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
> -
> -#define INTEL_SKL_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
> -
> -#define INTEL_SKL_GT2_IDS(info) \
> - INTEL_SKL_ULT_GT2_IDS(info), \
> - INTEL_SKL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> -
> -#define INTEL_SKL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
> - INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */
> -
> -#define INTEL_SKL_GT3_IDS(info) \
> - INTEL_SKL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
> - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */
> -
> -#define INTEL_SKL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> - INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
> -
> -#define INTEL_SKL_IDS(info) \
> - INTEL_SKL_GT1_IDS(info), \
> - INTEL_SKL_GT2_IDS(info), \
> - INTEL_SKL_GT3_IDS(info), \
> - INTEL_SKL_GT4_IDS(info)
> -
> -#define INTEL_BXT_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A84, info), \
> - INTEL_VGA_DEVICE(0x1A84, info), \
> - INTEL_VGA_DEVICE(0x1A85, info), \
> - INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> - INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> -
> -#define INTEL_GLK_IDS(info) \
> - INTEL_VGA_DEVICE(0x3184, info), \
> - INTEL_VGA_DEVICE(0x3185, info)
> -
> -#define INTEL_KBL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
> -
> -#define INTEL_KBL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
> -
> -#define INTEL_KBL_GT1_IDS(info) \
> - INTEL_KBL_ULT_GT1_IDS(info), \
> - INTEL_KBL_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
> -
> -#define INTEL_KBL_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
> -
> -#define INTEL_KBL_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
> -
> -#define INTEL_KBL_GT2_IDS(info) \
> - INTEL_KBL_ULT_GT2_IDS(info), \
> - INTEL_KBL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> -
> -#define INTEL_KBL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT3_IDS(info) \
> - INTEL_KBL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> +#define INTEL_G45_IDS(MACRO__, ...) \
> + MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
> + MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
> + MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
> + MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
> + MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
> + MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
> +
> +#define INTEL_PNV_G_IDS(MACRO__, ...) \
> + MACRO__(0xa001, ## __VA_ARGS__)
> +
> +#define INTEL_PNV_M_IDS(MACRO__, ...) \
> + MACRO__(0xa011, ## __VA_ARGS__)
> +
> +#define INTEL_PNV_IDS(MACRO__, ...) \
> + INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_D_IDS(MACRO__, ...) \
> + MACRO__(0x0042, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_M_IDS(MACRO__, ...) \
> + MACRO__(0x0046, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_IDS(MACRO__, ...) \
> + INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0102, ## __VA_ARGS__), \
> + MACRO__(0x010A, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0112, ## __VA_ARGS__), \
> + MACRO__(0x0122, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_IDS(MACRO__, ...) \
> + INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0106, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0116, ## __VA_ARGS__), \
> + MACRO__(0x0126, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_IDS(MACRO__, ...) \
> + INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_IDS(MACRO__, ...) \
> + INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */
> +
> +#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */
> +
> +#define INTEL_IVB_M_IDS(MACRO__, ...) \
> + INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
> + MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
> +
> +#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
> + MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
> +
> +#define INTEL_IVB_D_IDS(MACRO__, ...) \
> + INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_IDS(MACRO__, ...) \
> + INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_Q_IDS(MACRO__, ...) \
> + INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */
> +
> +#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
> + MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
> + MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
> + MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
> +
> +#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */
> +
> +#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
> + MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
> + MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
> + MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
> + MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
> + MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
> + MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
> + MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
> + MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
> + MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
> + MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
> + MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
> + MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
> + MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
> + MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
> +
> +#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
> + MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
> + MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
> + MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
> +
> +#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \
> +
> +#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
> + MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
> + MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
> + MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
> + MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
> + MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
> + MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
> + MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
> + MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
> + MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
> + MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
> + MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
> + MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
> + MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
> + MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
> +
> +#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
> + MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
> + MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
> + MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
> + MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
> +
> +#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
> + MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
> + MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
> + MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
> + MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
> + MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
> + MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
> + MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
> + MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
> + MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
> + MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
> + MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
> + MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
> + MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
> + MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
> +
> +#define INTEL_HSW_IDS(MACRO__, ...) \
> + INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_VLV_IDS(MACRO__, ...) \
> + MACRO__(0x0f30, ## __VA_ARGS__), \
> + MACRO__(0x0f31, ## __VA_ARGS__), \
> + MACRO__(0x0f32, ## __VA_ARGS__), \
> + MACRO__(0x0f33, ## __VA_ARGS__)
> +
> +#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
> + MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
> +
> +#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */
> +
> +#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
> + MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
> + MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
> +
> +#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
> + MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
> +
> +#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */
> +
> +#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
> + MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
> + MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
> +
> +#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
> +
> +#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x162E, ## __VA_ARGS__) /* ULX */
> +
> +#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
> + MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
> +
> +#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
> + MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
> +
> +#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \
> + MACRO__(0x163E, ## __VA_ARGS__) /* ULX */
> +
> +#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
> + MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
> +
> +#define INTEL_BDW_IDS(MACRO__, ...) \
> + INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_CHV_IDS(MACRO__, ...) \
> + MACRO__(0x22b0, ## __VA_ARGS__), \
> + MACRO__(0x22b1, ## __VA_ARGS__), \
> + MACRO__(0x22b2, ## __VA_ARGS__), \
> + MACRO__(0x22b3, ## __VA_ARGS__)
> +
> +#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
> + MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
> +
> +#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
> + MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
> +
> +#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
> + MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
> + MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
> +
> +#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
> + MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
> +
> +#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */
> +
> +#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
> + MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
> +
> +#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
> + MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
> +
> +#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
> + MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
> + MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
> +
> +#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
> + MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
> + MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
> + MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
> + MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
> +
> +#define INTEL_SKL_IDS(MACRO__, ...) \
> + INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_BXT_IDS(MACRO__, ...) \
> + MACRO__(0x0A84, ## __VA_ARGS__), \
> + MACRO__(0x1A84, ## __VA_ARGS__), \
> + MACRO__(0x1A85, ## __VA_ARGS__), \
> + MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
> + MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
> +
> +#define INTEL_GLK_IDS(MACRO__, ...) \
> + MACRO__(0x3184, ## __VA_ARGS__), \
> + MACRO__(0x3185, ## __VA_ARGS__)
> +
> +#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
> + MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
> +
> +#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
> + MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
> +
> +#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
> + MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
> + MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
> +
> +#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
> + MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
> +
> +#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */
> +
> +#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
> + MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
> + MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
> +
> +#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT4_IDS(MACRO__, ...) \
> + MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */
>
> /* AML/KBL Y GT2 */
> -#define INTEL_AML_KBL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
> +#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
> + MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
>
> /* AML/CFL Y GT2 */
> -#define INTEL_AML_CFL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x87CA, info)
> +#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x87CA, ## __VA_ARGS__)
>
> /* CML GT1 */
> -#define INTEL_CML_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BA2, info), \
> - INTEL_VGA_DEVICE(0x9BA4, info), \
> - INTEL_VGA_DEVICE(0x9BA5, info), \
> - INTEL_VGA_DEVICE(0x9BA8, info)
> +#define INTEL_CML_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9BA2, ## __VA_ARGS__), \
> + MACRO__(0x9BA4, ## __VA_ARGS__), \
> + MACRO__(0x9BA5, ## __VA_ARGS__), \
> + MACRO__(0x9BA8, ## __VA_ARGS__)
>
> -#define INTEL_CML_U_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B21, info), \
> - INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAC, info)
> +#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9B21, ## __VA_ARGS__), \
> + MACRO__(0x9BAA, ## __VA_ARGS__), \
> + MACRO__(0x9BAC, ## __VA_ARGS__)
>
> /* CML GT2 */
> -#define INTEL_CML_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BC2, info), \
> - INTEL_VGA_DEVICE(0x9BC4, info), \
> - INTEL_VGA_DEVICE(0x9BC5, info), \
> - INTEL_VGA_DEVICE(0x9BC6, info), \
> - INTEL_VGA_DEVICE(0x9BC8, info), \
> - INTEL_VGA_DEVICE(0x9BE6, info), \
> - INTEL_VGA_DEVICE(0x9BF6, info)
> -
> -#define INTEL_CML_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B41, info), \
> - INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCC, info)
> -
> -#define INTEL_CML_IDS(info) \
> - INTEL_CML_GT1_IDS(info), \
> - INTEL_CML_GT2_IDS(info), \
> - INTEL_CML_U_GT1_IDS(info), \
> - INTEL_CML_U_GT2_IDS(info)
> -
> -#define INTEL_KBL_IDS(info) \
> - INTEL_KBL_GT1_IDS(info), \
> - INTEL_KBL_GT2_IDS(info), \
> - INTEL_KBL_GT3_IDS(info), \
> - INTEL_KBL_GT4_IDS(info), \
> - INTEL_AML_KBL_GT2_IDS(info)
> +#define INTEL_CML_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9BC2, ## __VA_ARGS__), \
> + MACRO__(0x9BC4, ## __VA_ARGS__), \
> + MACRO__(0x9BC5, ## __VA_ARGS__), \
> + MACRO__(0x9BC6, ## __VA_ARGS__), \
> + MACRO__(0x9BC8, ## __VA_ARGS__), \
> + MACRO__(0x9BE6, ## __VA_ARGS__), \
> + MACRO__(0x9BF6, ## __VA_ARGS__)
> +
> +#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9B41, ## __VA_ARGS__), \
> + MACRO__(0x9BCA, ## __VA_ARGS__), \
> + MACRO__(0x9BCC, ## __VA_ARGS__)
> +
> +#define INTEL_CML_IDS(MACRO__, ...) \
> + INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_KBL_IDS(MACRO__, ...) \
> + INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* CFL S */
> -#define INTEL_CFL_S_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
> -
> -#define INTEL_CFL_S_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
> +#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
> +
> +#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
>
> /* CFL H */
> -#define INTEL_CFL_H_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E9C, info)
> +#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3E9C, ## __VA_ARGS__)
>
> -#define INTEL_CFL_H_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
> +#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
>
> /* CFL U GT2 */
> -#define INTEL_CFL_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA9, info)
> +#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3EA9, ## __VA_ARGS__)
>
> /* CFL U GT3 */
> -#define INTEL_CFL_U_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
> -
> -#define INTEL_CFL_IDS(info) \
> - INTEL_CFL_S_GT1_IDS(info), \
> - INTEL_CFL_S_GT2_IDS(info), \
> - INTEL_CFL_H_GT1_IDS(info), \
> - INTEL_CFL_H_GT2_IDS(info), \
> - INTEL_CFL_U_GT2_IDS(info), \
> - INTEL_CFL_U_GT3_IDS(info), \
> - INTEL_AML_CFL_GT2_IDS(info)
> +#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_CFL_IDS(MACRO__, ...) \
> + INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* WHL/CFL U GT1 */
> -#define INTEL_WHL_U_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA1, info), \
> - INTEL_VGA_DEVICE(0x3EA4, info)
> +#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3EA1, ## __VA_ARGS__), \
> + MACRO__(0x3EA4, ## __VA_ARGS__)
>
> /* WHL/CFL U GT2 */
> -#define INTEL_WHL_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA0, info), \
> - INTEL_VGA_DEVICE(0x3EA3, info)
> +#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3EA0, ## __VA_ARGS__), \
> + MACRO__(0x3EA3, ## __VA_ARGS__)
>
> /* WHL/CFL U GT3 */
> -#define INTEL_WHL_U_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA2, info)
> +#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x3EA2, ## __VA_ARGS__)
>
> -#define INTEL_WHL_IDS(info) \
> - INTEL_WHL_U_GT1_IDS(info), \
> - INTEL_WHL_U_GT2_IDS(info), \
> - INTEL_WHL_U_GT3_IDS(info)
> +#define INTEL_WHL_IDS(MACRO__, ...) \
> + INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
>
> /* CNL */
> -#define INTEL_CNL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A44, info), \
> - INTEL_VGA_DEVICE(0x5A4C, info), \
> - INTEL_VGA_DEVICE(0x5A54, info), \
> - INTEL_VGA_DEVICE(0x5A5C, info)
> -
> -#define INTEL_CNL_IDS(info) \
> - INTEL_CNL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x5A40, info), \
> - INTEL_VGA_DEVICE(0x5A41, info), \
> - INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info), \
> - INTEL_VGA_DEVICE(0x5A50, info), \
> - INTEL_VGA_DEVICE(0x5A51, info), \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A59, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info)
> +#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
> + MACRO__(0x5A44, ## __VA_ARGS__), \
> + MACRO__(0x5A4C, ## __VA_ARGS__), \
> + MACRO__(0x5A54, ## __VA_ARGS__), \
> + MACRO__(0x5A5C, ## __VA_ARGS__)
> +
> +#define INTEL_CNL_IDS(MACRO__, ...) \
> + INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5A40, ## __VA_ARGS__), \
> + MACRO__(0x5A41, ## __VA_ARGS__), \
> + MACRO__(0x5A42, ## __VA_ARGS__), \
> + MACRO__(0x5A49, ## __VA_ARGS__), \
> + MACRO__(0x5A4A, ## __VA_ARGS__), \
> + MACRO__(0x5A50, ## __VA_ARGS__), \
> + MACRO__(0x5A51, ## __VA_ARGS__), \
> + MACRO__(0x5A52, ## __VA_ARGS__), \
> + MACRO__(0x5A59, ## __VA_ARGS__), \
> + MACRO__(0x5A5A, ## __VA_ARGS__)
>
> /* ICL */
> -#define INTEL_ICL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x8A50, info), \
> - INTEL_VGA_DEVICE(0x8A52, info), \
> - INTEL_VGA_DEVICE(0x8A53, info), \
> - INTEL_VGA_DEVICE(0x8A54, info), \
> - INTEL_VGA_DEVICE(0x8A56, info), \
> - INTEL_VGA_DEVICE(0x8A57, info), \
> - INTEL_VGA_DEVICE(0x8A58, info), \
> - INTEL_VGA_DEVICE(0x8A59, info), \
> - INTEL_VGA_DEVICE(0x8A5A, info), \
> - INTEL_VGA_DEVICE(0x8A5B, info), \
> - INTEL_VGA_DEVICE(0x8A5C, info), \
> - INTEL_VGA_DEVICE(0x8A70, info), \
> - INTEL_VGA_DEVICE(0x8A71, info)
> -
> -#define INTEL_ICL_IDS(info) \
> - INTEL_ICL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x8A51, info), \
> - INTEL_VGA_DEVICE(0x8A5D, info)
> +#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
> + MACRO__(0x8A50, ## __VA_ARGS__), \
> + MACRO__(0x8A52, ## __VA_ARGS__), \
> + MACRO__(0x8A53, ## __VA_ARGS__), \
> + MACRO__(0x8A54, ## __VA_ARGS__), \
> + MACRO__(0x8A56, ## __VA_ARGS__), \
> + MACRO__(0x8A57, ## __VA_ARGS__), \
> + MACRO__(0x8A58, ## __VA_ARGS__), \
> + MACRO__(0x8A59, ## __VA_ARGS__), \
> + MACRO__(0x8A5A, ## __VA_ARGS__), \
> + MACRO__(0x8A5B, ## __VA_ARGS__), \
> + MACRO__(0x8A5C, ## __VA_ARGS__), \
> + MACRO__(0x8A70, ## __VA_ARGS__), \
> + MACRO__(0x8A71, ## __VA_ARGS__)
> +
> +#define INTEL_ICL_IDS(MACRO__, ...) \
> + INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x8A51, ## __VA_ARGS__), \
> + MACRO__(0x8A5D, ## __VA_ARGS__)
>
> /* EHL */
> -#define INTEL_EHL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4541, info), \
> - INTEL_VGA_DEVICE(0x4551, info), \
> - INTEL_VGA_DEVICE(0x4555, info), \
> - INTEL_VGA_DEVICE(0x4557, info), \
> - INTEL_VGA_DEVICE(0x4570, info), \
> - INTEL_VGA_DEVICE(0x4571, info)
> +#define INTEL_EHL_IDS(MACRO__, ...) \
> + MACRO__(0x4541, ## __VA_ARGS__), \
> + MACRO__(0x4551, ## __VA_ARGS__), \
> + MACRO__(0x4555, ## __VA_ARGS__), \
> + MACRO__(0x4557, ## __VA_ARGS__), \
> + MACRO__(0x4570, ## __VA_ARGS__), \
> + MACRO__(0x4571, ## __VA_ARGS__)
>
> /* JSL */
> -#define INTEL_JSL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4E51, info), \
> - INTEL_VGA_DEVICE(0x4E55, info), \
> - INTEL_VGA_DEVICE(0x4E57, info), \
> - INTEL_VGA_DEVICE(0x4E61, info), \
> - INTEL_VGA_DEVICE(0x4E71, info)
> +#define INTEL_JSL_IDS(MACRO__, ...) \
> + MACRO__(0x4E51, ## __VA_ARGS__), \
> + MACRO__(0x4E55, ## __VA_ARGS__), \
> + MACRO__(0x4E57, ## __VA_ARGS__), \
> + MACRO__(0x4E61, ## __VA_ARGS__), \
> + MACRO__(0x4E71, ## __VA_ARGS__)
>
> /* TGL */
> -#define INTEL_TGL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9A60, info), \
> - INTEL_VGA_DEVICE(0x9A68, info), \
> - INTEL_VGA_DEVICE(0x9A70, info)
> -
> -#define INTEL_TGL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9A40, info), \
> - INTEL_VGA_DEVICE(0x9A49, info), \
> - INTEL_VGA_DEVICE(0x9A59, info), \
> - INTEL_VGA_DEVICE(0x9A78, info), \
> - INTEL_VGA_DEVICE(0x9AC0, info), \
> - INTEL_VGA_DEVICE(0x9AC9, info), \
> - INTEL_VGA_DEVICE(0x9AD9, info), \
> - INTEL_VGA_DEVICE(0x9AF8, info)
> -
> -#define INTEL_TGL_IDS(info) \
> - INTEL_TGL_GT1_IDS(info), \
> - INTEL_TGL_GT2_IDS(info)
> +#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9A60, ## __VA_ARGS__), \
> + MACRO__(0x9A68, ## __VA_ARGS__), \
> + MACRO__(0x9A70, ## __VA_ARGS__)
> +
> +#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9A40, ## __VA_ARGS__), \
> + MACRO__(0x9A49, ## __VA_ARGS__), \
> + MACRO__(0x9A59, ## __VA_ARGS__), \
> + MACRO__(0x9A78, ## __VA_ARGS__), \
> + MACRO__(0x9AC0, ## __VA_ARGS__), \
> + MACRO__(0x9AC9, ## __VA_ARGS__), \
> + MACRO__(0x9AD9, ## __VA_ARGS__), \
> + MACRO__(0x9AF8, ## __VA_ARGS__)
> +
> +#define INTEL_TGL_IDS(MACRO__, ...) \
> + INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* RKL */
> -#define INTEL_RKL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4C80, info), \
> - INTEL_VGA_DEVICE(0x4C8A, info), \
> - INTEL_VGA_DEVICE(0x4C8B, info), \
> - INTEL_VGA_DEVICE(0x4C8C, info), \
> - INTEL_VGA_DEVICE(0x4C90, info), \
> - INTEL_VGA_DEVICE(0x4C9A, info)
> +#define INTEL_RKL_IDS(MACRO__, ...) \
> + MACRO__(0x4C80, ## __VA_ARGS__), \
> + MACRO__(0x4C8A, ## __VA_ARGS__), \
> + MACRO__(0x4C8B, ## __VA_ARGS__), \
> + MACRO__(0x4C8C, ## __VA_ARGS__), \
> + MACRO__(0x4C90, ## __VA_ARGS__), \
> + MACRO__(0x4C9A, ## __VA_ARGS__)
>
> /* DG1 */
> -#define INTEL_DG1_IDS(info) \
> - INTEL_VGA_DEVICE(0x4905, info), \
> - INTEL_VGA_DEVICE(0x4906, info), \
> - INTEL_VGA_DEVICE(0x4907, info), \
> - INTEL_VGA_DEVICE(0x4908, info), \
> - INTEL_VGA_DEVICE(0x4909, info)
> +#define INTEL_DG1_IDS(MACRO__, ...) \
> + MACRO__(0x4905, ## __VA_ARGS__), \
> + MACRO__(0x4906, ## __VA_ARGS__), \
> + MACRO__(0x4907, ## __VA_ARGS__), \
> + MACRO__(0x4908, ## __VA_ARGS__), \
> + MACRO__(0x4909, ## __VA_ARGS__)
>
> /* ADL-S */
> -#define INTEL_ADLS_IDS(info) \
> - INTEL_VGA_DEVICE(0x4680, info), \
> - INTEL_VGA_DEVICE(0x4682, info), \
> - INTEL_VGA_DEVICE(0x4688, info), \
> - INTEL_VGA_DEVICE(0x468A, info), \
> - INTEL_VGA_DEVICE(0x468B, info), \
> - INTEL_VGA_DEVICE(0x4690, info), \
> - INTEL_VGA_DEVICE(0x4692, info), \
> - INTEL_VGA_DEVICE(0x4693, info)
> +#define INTEL_ADLS_IDS(MACRO__, ...) \
> + MACRO__(0x4680, ## __VA_ARGS__), \
> + MACRO__(0x4682, ## __VA_ARGS__), \
> + MACRO__(0x4688, ## __VA_ARGS__), \
> + MACRO__(0x468A, ## __VA_ARGS__), \
> + MACRO__(0x468B, ## __VA_ARGS__), \
> + MACRO__(0x4690, ## __VA_ARGS__), \
> + MACRO__(0x4692, ## __VA_ARGS__), \
> + MACRO__(0x4693, ## __VA_ARGS__)
>
> /* ADL-P */
> -#define INTEL_ADLP_IDS(info) \
> - INTEL_VGA_DEVICE(0x46A0, info), \
> - INTEL_VGA_DEVICE(0x46A1, info), \
> - INTEL_VGA_DEVICE(0x46A2, info), \
> - INTEL_VGA_DEVICE(0x46A3, info), \
> - INTEL_VGA_DEVICE(0x46A6, info), \
> - INTEL_VGA_DEVICE(0x46A8, info), \
> - INTEL_VGA_DEVICE(0x46AA, info), \
> - INTEL_VGA_DEVICE(0x462A, info), \
> - INTEL_VGA_DEVICE(0x4626, info), \
> - INTEL_VGA_DEVICE(0x4628, info), \
> - INTEL_VGA_DEVICE(0x46B0, info), \
> - INTEL_VGA_DEVICE(0x46B1, info), \
> - INTEL_VGA_DEVICE(0x46B2, info), \
> - INTEL_VGA_DEVICE(0x46B3, info), \
> - INTEL_VGA_DEVICE(0x46C0, info), \
> - INTEL_VGA_DEVICE(0x46C1, info), \
> - INTEL_VGA_DEVICE(0x46C2, info), \
> - INTEL_VGA_DEVICE(0x46C3, info)
> +#define INTEL_ADLP_IDS(MACRO__, ...) \
> + MACRO__(0x46A0, ## __VA_ARGS__), \
> + MACRO__(0x46A1, ## __VA_ARGS__), \
> + MACRO__(0x46A2, ## __VA_ARGS__), \
> + MACRO__(0x46A3, ## __VA_ARGS__), \
> + MACRO__(0x46A6, ## __VA_ARGS__), \
> + MACRO__(0x46A8, ## __VA_ARGS__), \
> + MACRO__(0x46AA, ## __VA_ARGS__), \
> + MACRO__(0x462A, ## __VA_ARGS__), \
> + MACRO__(0x4626, ## __VA_ARGS__), \
> + MACRO__(0x4628, ## __VA_ARGS__), \
> + MACRO__(0x46B0, ## __VA_ARGS__), \
> + MACRO__(0x46B1, ## __VA_ARGS__), \
> + MACRO__(0x46B2, ## __VA_ARGS__), \
> + MACRO__(0x46B3, ## __VA_ARGS__), \
> + MACRO__(0x46C0, ## __VA_ARGS__), \
> + MACRO__(0x46C1, ## __VA_ARGS__), \
> + MACRO__(0x46C2, ## __VA_ARGS__), \
> + MACRO__(0x46C3, ## __VA_ARGS__)
>
> /* ADL-N */
> -#define INTEL_ADLN_IDS(info) \
> - INTEL_VGA_DEVICE(0x46D0, info), \
> - INTEL_VGA_DEVICE(0x46D1, info), \
> - INTEL_VGA_DEVICE(0x46D2, info), \
> - INTEL_VGA_DEVICE(0x46D3, info), \
> - INTEL_VGA_DEVICE(0x46D4, info)
> +#define INTEL_ADLN_IDS(MACRO__, ...) \
> + MACRO__(0x46D0, ## __VA_ARGS__), \
> + MACRO__(0x46D1, ## __VA_ARGS__), \
> + MACRO__(0x46D2, ## __VA_ARGS__), \
> + MACRO__(0x46D3, ## __VA_ARGS__), \
> + MACRO__(0x46D4, ## __VA_ARGS__)
>
> /* RPL-S */
> -#define INTEL_RPLS_IDS(info) \
> - INTEL_VGA_DEVICE(0xA780, info), \
> - INTEL_VGA_DEVICE(0xA781, info), \
> - INTEL_VGA_DEVICE(0xA782, info), \
> - INTEL_VGA_DEVICE(0xA783, info), \
> - INTEL_VGA_DEVICE(0xA788, info), \
> - INTEL_VGA_DEVICE(0xA789, info), \
> - INTEL_VGA_DEVICE(0xA78A, info), \
> - INTEL_VGA_DEVICE(0xA78B, info)
> +#define INTEL_RPLS_IDS(MACRO__, ...) \
> + MACRO__(0xA780, ## __VA_ARGS__), \
> + MACRO__(0xA781, ## __VA_ARGS__), \
> + MACRO__(0xA782, ## __VA_ARGS__), \
> + MACRO__(0xA783, ## __VA_ARGS__), \
> + MACRO__(0xA788, ## __VA_ARGS__), \
> + MACRO__(0xA789, ## __VA_ARGS__), \
> + MACRO__(0xA78A, ## __VA_ARGS__), \
> + MACRO__(0xA78B, ## __VA_ARGS__)
>
> /* RPL-U */
> -#define INTEL_RPLU_IDS(info) \
> - INTEL_VGA_DEVICE(0xA721, info), \
> - INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A9, info), \
> - INTEL_VGA_DEVICE(0xA7AC, info), \
> - INTEL_VGA_DEVICE(0xA7AD, info)
> +#define INTEL_RPLU_IDS(MACRO__, ...) \
> + MACRO__(0xA721, ## __VA_ARGS__), \
> + MACRO__(0xA7A1, ## __VA_ARGS__), \
> + MACRO__(0xA7A9, ## __VA_ARGS__), \
> + MACRO__(0xA7AC, ## __VA_ARGS__), \
> + MACRO__(0xA7AD, ## __VA_ARGS__)
>
> /* RPL-P */
> -#define INTEL_RPLP_IDS(info) \
> - INTEL_VGA_DEVICE(0xA720, info), \
> - INTEL_VGA_DEVICE(0xA7A0, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> - INTEL_VGA_DEVICE(0xA7AA, info), \
> - INTEL_VGA_DEVICE(0xA7AB, info)
> +#define INTEL_RPLP_IDS(MACRO__, ...) \
> + MACRO__(0xA720, ## __VA_ARGS__), \
> + MACRO__(0xA7A0, ## __VA_ARGS__), \
> + MACRO__(0xA7A8, ## __VA_ARGS__), \
> + MACRO__(0xA7AA, ## __VA_ARGS__), \
> + MACRO__(0xA7AB, ## __VA_ARGS__)
>
> /* DG2 */
> -#define INTEL_DG2_G10_IDS(info) \
> - INTEL_VGA_DEVICE(0x5690, info), \
> - INTEL_VGA_DEVICE(0x5691, info), \
> - INTEL_VGA_DEVICE(0x5692, info), \
> - INTEL_VGA_DEVICE(0x56A0, info), \
> - INTEL_VGA_DEVICE(0x56A1, info), \
> - INTEL_VGA_DEVICE(0x56A2, info), \
> - INTEL_VGA_DEVICE(0x56BE, info), \
> - INTEL_VGA_DEVICE(0x56BF, info)
> -
> -#define INTEL_DG2_G11_IDS(info) \
> - INTEL_VGA_DEVICE(0x5693, info), \
> - INTEL_VGA_DEVICE(0x5694, info), \
> - INTEL_VGA_DEVICE(0x5695, info), \
> - INTEL_VGA_DEVICE(0x56A5, info), \
> - INTEL_VGA_DEVICE(0x56A6, info), \
> - INTEL_VGA_DEVICE(0x56B0, info), \
> - INTEL_VGA_DEVICE(0x56B1, info), \
> - INTEL_VGA_DEVICE(0x56BA, info), \
> - INTEL_VGA_DEVICE(0x56BB, info), \
> - INTEL_VGA_DEVICE(0x56BC, info), \
> - INTEL_VGA_DEVICE(0x56BD, info)
> -
> -#define INTEL_DG2_G12_IDS(info) \
> - INTEL_VGA_DEVICE(0x5696, info), \
> - INTEL_VGA_DEVICE(0x5697, info), \
> - INTEL_VGA_DEVICE(0x56A3, info), \
> - INTEL_VGA_DEVICE(0x56A4, info), \
> - INTEL_VGA_DEVICE(0x56B2, info), \
> - INTEL_VGA_DEVICE(0x56B3, info)
> -
> -#define INTEL_DG2_IDS(info) \
> - INTEL_DG2_G10_IDS(info), \
> - INTEL_DG2_G11_IDS(info), \
> - INTEL_DG2_G12_IDS(info)
> -
> -#define INTEL_ATS_M150_IDS(info) \
> - INTEL_VGA_DEVICE(0x56C0, info), \
> - INTEL_VGA_DEVICE(0x56C2, info)
> -
> -#define INTEL_ATS_M75_IDS(info) \
> - INTEL_VGA_DEVICE(0x56C1, info)
> -
> -#define INTEL_ATS_M_IDS(info) \
> - INTEL_ATS_M150_IDS(info), \
> - INTEL_ATS_M75_IDS(info)
> +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__), \
> + MACRO__(0x56A0, ## __VA_ARGS__), \
> + MACRO__(0x56A1, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__), \
> + MACRO__(0x56BE, ## __VA_ARGS__), \
> + MACRO__(0x56BF, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__), \
> + MACRO__(0x56A5, ## __VA_ARGS__), \
> + MACRO__(0x56A6, ## __VA_ARGS__), \
> + MACRO__(0x56B0, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__), \
> + MACRO__(0x56BA, ## __VA_ARGS__), \
> + MACRO__(0x56BB, ## __VA_ARGS__), \
> + MACRO__(0x56BC, ## __VA_ARGS__), \
> + MACRO__(0x56BD, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__), \
> + MACRO__(0x56A3, ## __VA_ARGS__), \
> + MACRO__(0x56A4, ## __VA_ARGS__), \
> + MACRO__(0x56B2, ## __VA_ARGS__), \
> + MACRO__(0x56B3, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M150_IDS(MACRO__, ...) \
> + MACRO__(0x56C0, ## __VA_ARGS__), \
> + MACRO__(0x56C2, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M75_IDS(MACRO__, ...) \
> + MACRO__(0x56C1, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M_IDS(MACRO__, ...) \
> + INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
>
> /* MTL */
> -#define INTEL_MTL_IDS(info) \
> - INTEL_VGA_DEVICE(0x7D40, info), \
> - INTEL_VGA_DEVICE(0x7D41, info), \
> - INTEL_VGA_DEVICE(0x7D45, info), \
> - INTEL_VGA_DEVICE(0x7D51, info), \
> - INTEL_VGA_DEVICE(0x7D55, info), \
> - INTEL_VGA_DEVICE(0x7D60, info), \
> - INTEL_VGA_DEVICE(0x7D67, info), \
> - INTEL_VGA_DEVICE(0x7DD1, info), \
> - INTEL_VGA_DEVICE(0x7DD5, info)
> +#define INTEL_MTL_IDS(MACRO__, ...) \
> + MACRO__(0x7D40, ## __VA_ARGS__), \
> + MACRO__(0x7D41, ## __VA_ARGS__), \
> + MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D51, ## __VA_ARGS__), \
> + MACRO__(0x7D55, ## __VA_ARGS__), \
> + MACRO__(0x7D60, ## __VA_ARGS__), \
> + MACRO__(0x7D67, ## __VA_ARGS__), \
> + MACRO__(0x7DD1, ## __VA_ARGS__), \
> + MACRO__(0x7DD5, ## __VA_ARGS__)
>
> #endif /* _I915_PCIIDS_H */
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-15 16:56 [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros Jani Nikula
` (5 preceding siblings ...)
2024-05-16 13:25 ` [PATCH 1/2] " Rodrigo Vivi
@ 2024-05-20 12:27 ` Jani Nikula
2024-05-22 9:43 ` Jani Nikula
6 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2024-05-20 12:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Bjorn Helgaas, linux-pci, Lucas De Marchi, Rodrigo Vivi
On Wed, 15 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
> same pattern.
>
> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org
Bjorn, since I asked for acks on the last ones, I probably should here
too. :)
I'm hoping to stop mucking with the macros after this.
BR,
Jani.
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Tip: It's probably easiest to apply and use 'git show --color-words' for
> review.
>
> This transformation is completely scripted:
>
> | #!/bin/bash
> |
> | FILE=include/drm/i915_pciids.h
> |
> | sed -i 's/[\t ]*\\/ \\/' $FILE
> |
> | sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
> |
> | sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
> |
> | sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ## __VA_ARGS__)/' $FILE
> |
> | # Special case: IVB Q transcode
> | sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
> |
> | # Change all users
> | for file in $(git grep -l "#include <drm/i915_pciids.h>"); do
> | for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed 's/#define //'); do
> | sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
> | done
> | done
> ---
> arch/x86/kernel/early-quirks.c | 80 +-
> .../drm/i915/display/intel_display_device.c | 86 +-
> drivers/gpu/drm/i915/i915_pci.c | 150 +-
> drivers/gpu/drm/i915/intel_device_info.c | 88 +-
> include/drm/i915_pciids.h | 1348 ++++++++---------
> 5 files changed, 876 insertions(+), 876 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fd74d7f26f01..1c137771c5d2 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops __initconst = {
>
> /* Intel integrated GPUs for which we need to reserve "stolen memory" */
> static const struct pci_device_id intel_early_ids[] __initconst = {
> - INTEL_I830_IDS(&i830_early_ops),
> - INTEL_I845G_IDS(&i845_early_ops),
> - INTEL_I85X_IDS(&i85x_early_ops),
> - INTEL_I865G_IDS(&i865_early_ops),
> - INTEL_I915G_IDS(&gen3_early_ops),
> - INTEL_I915GM_IDS(&gen3_early_ops),
> - INTEL_I945G_IDS(&gen3_early_ops),
> - INTEL_I945GM_IDS(&gen3_early_ops),
> - INTEL_VLV_IDS(&gen6_early_ops),
> - INTEL_PNV_IDS(&gen3_early_ops),
> - INTEL_I965G_IDS(&gen3_early_ops),
> - INTEL_G33_IDS(&gen3_early_ops),
> - INTEL_I965GM_IDS(&gen3_early_ops),
> - INTEL_GM45_IDS(&gen3_early_ops),
> - INTEL_G45_IDS(&gen3_early_ops),
> - INTEL_ILK_IDS(&gen3_early_ops),
> - INTEL_SNB_IDS(&gen6_early_ops),
> - INTEL_IVB_IDS(&gen6_early_ops),
> - INTEL_HSW_IDS(&gen6_early_ops),
> - INTEL_BDW_IDS(&gen8_early_ops),
> - INTEL_CHV_IDS(&chv_early_ops),
> - INTEL_SKL_IDS(&gen9_early_ops),
> - INTEL_BXT_IDS(&gen9_early_ops),
> - INTEL_KBL_IDS(&gen9_early_ops),
> - INTEL_CFL_IDS(&gen9_early_ops),
> - INTEL_WHL_IDS(&gen9_early_ops),
> - INTEL_CML_IDS(&gen9_early_ops),
> - INTEL_GLK_IDS(&gen9_early_ops),
> - INTEL_CNL_IDS(&gen9_early_ops),
> - INTEL_ICL_IDS(&gen11_early_ops),
> - INTEL_EHL_IDS(&gen11_early_ops),
> - INTEL_JSL_IDS(&gen11_early_ops),
> - INTEL_TGL_IDS(&gen11_early_ops),
> - INTEL_RKL_IDS(&gen11_early_ops),
> - INTEL_ADLS_IDS(&gen11_early_ops),
> - INTEL_ADLP_IDS(&gen11_early_ops),
> - INTEL_ADLN_IDS(&gen11_early_ops),
> - INTEL_RPLS_IDS(&gen11_early_ops),
> - INTEL_RPLU_IDS(&gen11_early_ops),
> - INTEL_RPLP_IDS(&gen11_early_ops),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &gen6_early_ops),
> + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &gen8_early_ops),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_early_ops),
> + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CML_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_CNL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 89069cff06b4..950e66cdba0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -788,7 +788,7 @@ __diag_pop();
> static bool has_no_display(struct pci_dev *pdev)
> {
> static const struct pci_device_id ids[] = {
> - INTEL_IVB_Q_IDS(0),
> + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0),
> {}
> };
>
> @@ -802,48 +802,48 @@ static const struct {
> u32 devid;
> const struct intel_display_device_info *info;
> } intel_display_ids[] = {
> - INTEL_I830_IDS(&i830_display),
> - INTEL_I845G_IDS(&i845_display),
> - INTEL_I85X_IDS(&i85x_display),
> - INTEL_I865G_IDS(&i865g_display),
> - INTEL_I915G_IDS(&i915g_display),
> - INTEL_I915GM_IDS(&i915gm_display),
> - INTEL_I945G_IDS(&i945g_display),
> - INTEL_I945GM_IDS(&i945gm_display),
> - INTEL_I965G_IDS(&i965g_display),
> - INTEL_G33_IDS(&g33_display),
> - INTEL_I965GM_IDS(&i965gm_display),
> - INTEL_GM45_IDS(&gm45_display),
> - INTEL_G45_IDS(&g45_display),
> - INTEL_PNV_IDS(&pnv_display),
> - INTEL_ILK_D_IDS(&ilk_d_display),
> - INTEL_ILK_M_IDS(&ilk_m_display),
> - INTEL_SNB_IDS(&snb_display),
> - INTEL_IVB_IDS(&ivb_display),
> - INTEL_HSW_IDS(&hsw_display),
> - INTEL_VLV_IDS(&vlv_display),
> - INTEL_BDW_IDS(&bdw_display),
> - INTEL_CHV_IDS(&chv_display),
> - INTEL_SKL_IDS(&skl_display),
> - INTEL_BXT_IDS(&bxt_display),
> - INTEL_GLK_IDS(&glk_display),
> - INTEL_KBL_IDS(&skl_display),
> - INTEL_CFL_IDS(&skl_display),
> - INTEL_WHL_IDS(&skl_display),
> - INTEL_CML_IDS(&skl_display),
> - INTEL_ICL_IDS(&icl_display),
> - INTEL_EHL_IDS(&jsl_ehl_display),
> - INTEL_JSL_IDS(&jsl_ehl_display),
> - INTEL_TGL_IDS(&tgl_display),
> - INTEL_DG1_IDS(&dg1_display),
> - INTEL_RKL_IDS(&rkl_display),
> - INTEL_ADLS_IDS(&adl_s_display),
> - INTEL_RPLS_IDS(&adl_s_display),
> - INTEL_ADLP_IDS(&xe_lpd_display),
> - INTEL_ADLN_IDS(&xe_lpd_display),
> - INTEL_RPLU_IDS(&xe_lpd_display),
> - INTEL_RPLP_IDS(&xe_lpd_display),
> - INTEL_DG2_IDS(&xe_hpd_display),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display),
> + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display),
> + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display),
> + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display),
> + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display),
> + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display),
> + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display),
> + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display),
> + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display),
> + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display),
> + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display),
>
> /*
> * Do not add any GMD_ID-based platforms to this list. They will
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 74202925d13f..84cd2f0343a2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -797,81 +797,81 @@ __diag_pop();
> * PCI ID matches, otherwise we'll use the wrong info struct above.
> */
> static const struct pci_device_id pciidlist[] = {
> - INTEL_I830_IDS(&i830_info),
> - INTEL_I845G_IDS(&i845g_info),
> - INTEL_I85X_IDS(&i85x_info),
> - INTEL_I865G_IDS(&i865g_info),
> - INTEL_I915G_IDS(&i915g_info),
> - INTEL_I915GM_IDS(&i915gm_info),
> - INTEL_I945G_IDS(&i945g_info),
> - INTEL_I945GM_IDS(&i945gm_info),
> - INTEL_I965G_IDS(&i965g_info),
> - INTEL_G33_IDS(&g33_info),
> - INTEL_I965GM_IDS(&i965gm_info),
> - INTEL_GM45_IDS(&gm45_info),
> - INTEL_G45_IDS(&g45_info),
> - INTEL_PNV_G_IDS(&pnv_g_info),
> - INTEL_PNV_M_IDS(&pnv_m_info),
> - INTEL_ILK_D_IDS(&ilk_d_info),
> - INTEL_ILK_M_IDS(&ilk_m_info),
> - INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
> - INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
> - INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
> - INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
> - INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
> - INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
> - INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
> - INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
> - INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
> - INTEL_HSW_GT1_IDS(&hsw_gt1_info),
> - INTEL_HSW_GT2_IDS(&hsw_gt2_info),
> - INTEL_HSW_GT3_IDS(&hsw_gt3_info),
> - INTEL_VLV_IDS(&vlv_info),
> - INTEL_BDW_GT1_IDS(&bdw_gt1_info),
> - INTEL_BDW_GT2_IDS(&bdw_gt2_info),
> - INTEL_BDW_GT3_IDS(&bdw_gt3_info),
> - INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
> - INTEL_CHV_IDS(&chv_info),
> - INTEL_SKL_GT1_IDS(&skl_gt1_info),
> - INTEL_SKL_GT2_IDS(&skl_gt2_info),
> - INTEL_SKL_GT3_IDS(&skl_gt3_info),
> - INTEL_SKL_GT4_IDS(&skl_gt4_info),
> - INTEL_BXT_IDS(&bxt_info),
> - INTEL_GLK_IDS(&glk_info),
> - INTEL_KBL_GT1_IDS(&kbl_gt1_info),
> - INTEL_KBL_GT2_IDS(&kbl_gt2_info),
> - INTEL_KBL_GT3_IDS(&kbl_gt3_info),
> - INTEL_KBL_GT4_IDS(&kbl_gt3_info),
> - INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
> - INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
> - INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
> - INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
> - INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
> - INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
> - INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
> - INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
> - INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
> - INTEL_CML_GT1_IDS(&cml_gt1_info),
> - INTEL_CML_GT2_IDS(&cml_gt2_info),
> - INTEL_CML_U_GT1_IDS(&cml_gt1_info),
> - INTEL_CML_U_GT2_IDS(&cml_gt2_info),
> - INTEL_ICL_IDS(&icl_info),
> - INTEL_EHL_IDS(&ehl_info),
> - INTEL_JSL_IDS(&jsl_info),
> - INTEL_TGL_IDS(&tgl_info),
> - INTEL_RKL_IDS(&rkl_info),
> - INTEL_ADLS_IDS(&adl_s_info),
> - INTEL_ADLP_IDS(&adl_p_info),
> - INTEL_ADLN_IDS(&adl_p_info),
> - INTEL_DG1_IDS(&dg1_info),
> - INTEL_RPLS_IDS(&adl_s_info),
> - INTEL_RPLU_IDS(&adl_p_info),
> - INTEL_RPLP_IDS(&adl_p_info),
> - INTEL_DG2_IDS(&dg2_info),
> - INTEL_ATS_M_IDS(&ats_m_info),
> - INTEL_MTL_IDS(&mtl_info),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info),
> + INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info),
> + INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info),
> + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info),
> + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info),
> + INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info),
> + INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info),
> + INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info),
> + INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info),
> + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */
> + INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info),
> + INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info),
> + INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info),
> + INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info),
> + INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info),
> + INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info),
> + INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info),
> + INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info),
> + INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info),
> + INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info),
> + INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info),
> + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info),
> + INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info),
> + INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info),
> + INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info),
> + INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info),
> + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info),
> + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info),
> + INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info),
> + INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
> + INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
> + INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
> + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
> + INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
> + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
> + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
> + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
> + INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
> + INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
> + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
> + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
> + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info),
> + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info),
> + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info),
> + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info),
> + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info),
> + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
> + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
> + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info),
> + INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info),
> + INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info),
> {}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a39497971994..82bb34416fb1 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -131,77 +131,77 @@ void intel_device_info_print(const struct intel_device_info *info,
> #define INTEL_VGA_DEVICE(id, info) (id)
>
> static const u16 subplatform_ult_ids[] = {
> - INTEL_HSW_ULT_GT1_IDS(0),
> - INTEL_HSW_ULT_GT2_IDS(0),
> - INTEL_HSW_ULT_GT3_IDS(0),
> - INTEL_BDW_ULT_GT1_IDS(0),
> - INTEL_BDW_ULT_GT2_IDS(0),
> - INTEL_BDW_ULT_GT3_IDS(0),
> - INTEL_BDW_ULT_RSVD_IDS(0),
> - INTEL_SKL_ULT_GT1_IDS(0),
> - INTEL_SKL_ULT_GT2_IDS(0),
> - INTEL_SKL_ULT_GT3_IDS(0),
> - INTEL_KBL_ULT_GT1_IDS(0),
> - INTEL_KBL_ULT_GT2_IDS(0),
> - INTEL_KBL_ULT_GT3_IDS(0),
> - INTEL_CFL_U_GT2_IDS(0),
> - INTEL_CFL_U_GT3_IDS(0),
> - INTEL_WHL_U_GT1_IDS(0),
> - INTEL_WHL_U_GT2_IDS(0),
> - INTEL_WHL_U_GT3_IDS(0),
> - INTEL_CML_U_GT1_IDS(0),
> - INTEL_CML_U_GT2_IDS(0),
> + INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_ulx_ids[] = {
> - INTEL_HSW_ULX_GT1_IDS(0),
> - INTEL_HSW_ULX_GT2_IDS(0),
> - INTEL_BDW_ULX_GT1_IDS(0),
> - INTEL_BDW_ULX_GT2_IDS(0),
> - INTEL_BDW_ULX_GT3_IDS(0),
> - INTEL_BDW_ULX_RSVD_IDS(0),
> - INTEL_SKL_ULX_GT1_IDS(0),
> - INTEL_SKL_ULX_GT2_IDS(0),
> - INTEL_KBL_ULX_GT1_IDS(0),
> - INTEL_KBL_ULX_GT2_IDS(0),
> - INTEL_AML_KBL_GT2_IDS(0),
> - INTEL_AML_CFL_GT2_IDS(0),
> + INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_portf_ids[] = {
> - INTEL_ICL_PORT_F_IDS(0),
> + INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_uy_ids[] = {
> - INTEL_TGL_GT2_IDS(0),
> + INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_n_ids[] = {
> - INTEL_ADLN_IDS(0),
> + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_rpl_ids[] = {
> - INTEL_RPLS_IDS(0),
> - INTEL_RPLU_IDS(0),
> - INTEL_RPLP_IDS(0),
> + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_rplu_ids[] = {
> - INTEL_RPLU_IDS(0),
> + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g10_ids[] = {
> - INTEL_DG2_G10_IDS(0),
> - INTEL_ATS_M150_IDS(0),
> + INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g11_ids[] = {
> - INTEL_DG2_G11_IDS(0),
> - INTEL_ATS_M75_IDS(0),
> + INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0),
> + INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static const u16 subplatform_g12_ids[] = {
> - INTEL_DG2_G12_IDS(0),
> + INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0),
> };
>
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 04f6ca3dc5c1..3e39d644ebaa 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -35,752 +35,752 @@
> * Don't use C99 here because "class" is reserved and we want to
> * give userspace flexibility.
> */
> -#define INTEL_VGA_DEVICE(id, info) { \
> - 0x8086, id, \
> - ~0, ~0, \
> - 0x030000, 0xff0000, \
> +#define INTEL_VGA_DEVICE(id, info) { \
> + 0x8086, id, \
> + ~0, ~0, \
> + 0x030000, 0xff0000, \
> (unsigned long) info }
>
> -#define INTEL_QUANTA_VGA_DEVICE(info) { \
> - 0x8086, 0x16a, \
> - 0x152d, 0x8990, \
> - 0x030000, 0xff0000, \
> +#define INTEL_QUANTA_VGA_DEVICE(info) { \
> + 0x8086, 0x16a, \
> + 0x152d, 0x8990, \
> + 0x030000, 0xff0000, \
> (unsigned long) info }
>
> -#define INTEL_I810_IDS(info) \
> - INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
> - INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
> - INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
> +#define INTEL_I810_IDS(MACRO__, ...) \
> + MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
> + MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
> + MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
>
> -#define INTEL_I815_IDS(info) \
> - INTEL_VGA_DEVICE(0x1132, info) /* I815*/
> +#define INTEL_I815_IDS(MACRO__, ...) \
> + MACRO__(0x1132, ## __VA_ARGS__) /* I815*/
>
> -#define INTEL_I830_IDS(info) \
> - INTEL_VGA_DEVICE(0x3577, info)
> +#define INTEL_I830_IDS(MACRO__, ...) \
> + MACRO__(0x3577, ## __VA_ARGS__)
>
> -#define INTEL_I845G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2562, info)
> +#define INTEL_I845G_IDS(MACRO__, ...) \
> + MACRO__(0x2562, ## __VA_ARGS__)
>
> -#define INTEL_I85X_IDS(info) \
> - INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
> - INTEL_VGA_DEVICE(0x358e, info)
> +#define INTEL_I85X_IDS(MACRO__, ...) \
> + MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
> + MACRO__(0x358e, ## __VA_ARGS__)
>
> -#define INTEL_I865G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
> +#define INTEL_I865G_IDS(MACRO__, ...) \
> + MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */
>
> -#define INTEL_I915G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
> - INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
> +#define INTEL_I915G_IDS(MACRO__, ...) \
> + MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
> + MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
>
> -#define INTEL_I915GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
> +#define INTEL_I915GM_IDS(MACRO__, ...) \
> + MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */
>
> -#define INTEL_I945G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
> +#define INTEL_I945G_IDS(MACRO__, ...) \
> + MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */
>
> -#define INTEL_I945GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
> - INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
> +#define INTEL_I945GM_IDS(MACRO__, ...) \
> + MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
> + MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
>
> -#define INTEL_I965G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
> - INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
> - INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
> - INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
> +#define INTEL_I965G_IDS(MACRO__, ...) \
> + MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
> + MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
> + MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
> + MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
>
> -#define INTEL_G33_IDS(info) \
> - INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
> - INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
> - INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
> +#define INTEL_G33_IDS(MACRO__, ...) \
> + MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
> + MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
> + MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
>
> -#define INTEL_I965GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
> - INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
> +#define INTEL_I965GM_IDS(MACRO__, ...) \
> + MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
> + MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
>
> -#define INTEL_GM45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
> +#define INTEL_GM45_IDS(MACRO__, ...) \
> + MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */
>
> -#define INTEL_G45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
> - INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
> - INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
> - INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
> - INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> - INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
> -
> -#define INTEL_PNV_G_IDS(info) \
> - INTEL_VGA_DEVICE(0xa001, info)
> -
> -#define INTEL_PNV_M_IDS(info) \
> - INTEL_VGA_DEVICE(0xa011, info)
> -
> -#define INTEL_PNV_IDS(info) \
> - INTEL_PNV_G_IDS(info), \
> - INTEL_PNV_M_IDS(info)
> -
> -#define INTEL_ILK_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0042, info)
> -
> -#define INTEL_ILK_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0046, info)
> -
> -#define INTEL_ILK_IDS(info) \
> - INTEL_ILK_D_IDS(info), \
> - INTEL_ILK_M_IDS(info)
> -
> -#define INTEL_SNB_D_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0102, info), \
> - INTEL_VGA_DEVICE(0x010A, info)
> -
> -#define INTEL_SNB_D_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0112, info), \
> - INTEL_VGA_DEVICE(0x0122, info)
> -
> -#define INTEL_SNB_D_IDS(info) \
> - INTEL_SNB_D_GT1_IDS(info), \
> - INTEL_SNB_D_GT2_IDS(info)
> -
> -#define INTEL_SNB_M_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0106, info)
> -
> -#define INTEL_SNB_M_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0116, info), \
> - INTEL_VGA_DEVICE(0x0126, info)
> -
> -#define INTEL_SNB_M_IDS(info) \
> - INTEL_SNB_M_GT1_IDS(info), \
> - INTEL_SNB_M_GT2_IDS(info)
> -
> -#define INTEL_SNB_IDS(info) \
> - INTEL_SNB_D_IDS(info), \
> - INTEL_SNB_M_IDS(info)
> -
> -#define INTEL_IVB_M_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
> -
> -#define INTEL_IVB_M_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
> -
> -#define INTEL_IVB_M_IDS(info) \
> - INTEL_IVB_M_GT1_IDS(info), \
> - INTEL_IVB_M_GT2_IDS(info)
> -
> -#define INTEL_IVB_D_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
> -
> -#define INTEL_IVB_D_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
> -
> -#define INTEL_IVB_D_IDS(info) \
> - INTEL_IVB_D_GT1_IDS(info), \
> - INTEL_IVB_D_GT2_IDS(info)
> -
> -#define INTEL_IVB_IDS(info) \
> - INTEL_IVB_M_IDS(info), \
> - INTEL_IVB_D_IDS(info)
> -
> -#define INTEL_IVB_Q_IDS(info) \
> - INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> -
> -#define INTEL_HSW_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
> -
> -#define INTEL_HSW_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
> -
> -#define INTEL_HSW_GT1_IDS(info) \
> - INTEL_HSW_ULT_GT1_IDS(info), \
> - INTEL_HSW_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> - INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> - INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
> -
> -#define INTEL_HSW_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
> -
> -#define INTEL_HSW_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
> -
> -#define INTEL_HSW_GT2_IDS(info) \
> - INTEL_HSW_ULT_GT2_IDS(info), \
> - INTEL_HSW_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
> - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
> -
> -#define INTEL_HSW_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
> -
> -#define INTEL_HSW_GT3_IDS(info) \
> - INTEL_HSW_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
> - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
> -
> -#define INTEL_HSW_IDS(info) \
> - INTEL_HSW_GT1_IDS(info), \
> - INTEL_HSW_GT2_IDS(info), \
> - INTEL_HSW_GT3_IDS(info)
> -
> -#define INTEL_VLV_IDS(info) \
> - INTEL_VGA_DEVICE(0x0f30, info), \
> - INTEL_VGA_DEVICE(0x0f31, info), \
> - INTEL_VGA_DEVICE(0x0f32, info), \
> - INTEL_VGA_DEVICE(0x0f33, info)
> -
> -#define INTEL_BDW_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */
> -
> -#define INTEL_BDW_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
> -
> -#define INTEL_BDW_GT1_IDS(info) \
> - INTEL_BDW_ULT_GT1_IDS(info), \
> - INTEL_BDW_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> - INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
> -
> -#define INTEL_BDW_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */
> -
> -#define INTEL_BDW_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> -
> -#define INTEL_BDW_GT2_IDS(info) \
> - INTEL_BDW_ULT_GT2_IDS(info), \
> - INTEL_BDW_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> - INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> - INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> -
> -#define INTEL_BDW_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \
> -
> -#define INTEL_BDW_ULX_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> -
> -#define INTEL_BDW_GT3_IDS(info) \
> - INTEL_BDW_ULT_GT3_IDS(info), \
> - INTEL_BDW_ULX_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> -
> -#define INTEL_BDW_ULT_RSVD_IDS(info) \
> - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163B, info) /* Iris */
> -
> -#define INTEL_BDW_ULX_RSVD_IDS(info) \
> - INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> -
> -#define INTEL_BDW_RSVD_IDS(info) \
> - INTEL_BDW_ULT_RSVD_IDS(info), \
> - INTEL_BDW_ULX_RSVD_IDS(info), \
> - INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> -
> -#define INTEL_BDW_IDS(info) \
> - INTEL_BDW_GT1_IDS(info), \
> - INTEL_BDW_GT2_IDS(info), \
> - INTEL_BDW_GT3_IDS(info), \
> - INTEL_BDW_RSVD_IDS(info)
> -
> -#define INTEL_CHV_IDS(info) \
> - INTEL_VGA_DEVICE(0x22b0, info), \
> - INTEL_VGA_DEVICE(0x22b1, info), \
> - INTEL_VGA_DEVICE(0x22b2, info), \
> - INTEL_VGA_DEVICE(0x22b3, info)
> -
> -#define INTEL_SKL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */
> -
> -#define INTEL_SKL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */
> -
> -#define INTEL_SKL_GT1_IDS(info) \
> - INTEL_SKL_ULT_GT1_IDS(info), \
> - INTEL_SKL_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */
> -
> -#define INTEL_SKL_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */
> -
> -#define INTEL_SKL_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
> -
> -#define INTEL_SKL_GT2_IDS(info) \
> - INTEL_SKL_ULT_GT2_IDS(info), \
> - INTEL_SKL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> -
> -#define INTEL_SKL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
> - INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */
> -
> -#define INTEL_SKL_GT3_IDS(info) \
> - INTEL_SKL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
> - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */
> -
> -#define INTEL_SKL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> - INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
> -
> -#define INTEL_SKL_IDS(info) \
> - INTEL_SKL_GT1_IDS(info), \
> - INTEL_SKL_GT2_IDS(info), \
> - INTEL_SKL_GT3_IDS(info), \
> - INTEL_SKL_GT4_IDS(info)
> -
> -#define INTEL_BXT_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A84, info), \
> - INTEL_VGA_DEVICE(0x1A84, info), \
> - INTEL_VGA_DEVICE(0x1A85, info), \
> - INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> - INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> -
> -#define INTEL_GLK_IDS(info) \
> - INTEL_VGA_DEVICE(0x3184, info), \
> - INTEL_VGA_DEVICE(0x3185, info)
> -
> -#define INTEL_KBL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */
> -
> -#define INTEL_KBL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */
> -
> -#define INTEL_KBL_GT1_IDS(info) \
> - INTEL_KBL_ULT_GT1_IDS(info), \
> - INTEL_KBL_ULX_GT1_IDS(info), \
> - INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
> -
> -#define INTEL_KBL_ULT_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */
> -
> -#define INTEL_KBL_ULX_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */
> -
> -#define INTEL_KBL_GT2_IDS(info) \
> - INTEL_KBL_ULT_GT2_IDS(info), \
> - INTEL_KBL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
> - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> -
> -#define INTEL_KBL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT3_IDS(info) \
> - INTEL_KBL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> +#define INTEL_G45_IDS(MACRO__, ...) \
> + MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
> + MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
> + MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
> + MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
> + MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
> + MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
> +
> +#define INTEL_PNV_G_IDS(MACRO__, ...) \
> + MACRO__(0xa001, ## __VA_ARGS__)
> +
> +#define INTEL_PNV_M_IDS(MACRO__, ...) \
> + MACRO__(0xa011, ## __VA_ARGS__)
> +
> +#define INTEL_PNV_IDS(MACRO__, ...) \
> + INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_D_IDS(MACRO__, ...) \
> + MACRO__(0x0042, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_M_IDS(MACRO__, ...) \
> + MACRO__(0x0046, ## __VA_ARGS__)
> +
> +#define INTEL_ILK_IDS(MACRO__, ...) \
> + INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0102, ## __VA_ARGS__), \
> + MACRO__(0x010A, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0112, ## __VA_ARGS__), \
> + MACRO__(0x0122, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_D_IDS(MACRO__, ...) \
> + INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0106, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0116, ## __VA_ARGS__), \
> + MACRO__(0x0126, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_M_IDS(MACRO__, ...) \
> + INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_SNB_IDS(MACRO__, ...) \
> + INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */
> +
> +#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */
> +
> +#define INTEL_IVB_M_IDS(MACRO__, ...) \
> + INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
> + MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
> +
> +#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
> + MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
> +
> +#define INTEL_IVB_D_IDS(MACRO__, ...) \
> + INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_IDS(MACRO__, ...) \
> + INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_IVB_Q_IDS(MACRO__, ...) \
> + INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */
> +
> +#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
> + MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
> + MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
> + MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
> +
> +#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */
> +
> +#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
> + MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
> + MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
> + MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
> + MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
> + MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
> + MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
> + MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
> + MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
> + MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
> + MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
> + MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
> + MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
> + MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
> + MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
> +
> +#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
> + MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
> + MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
> + MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
> +
> +#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \
> +
> +#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
> + MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
> + MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
> + MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
> + MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
> + MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
> + MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
> + MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
> + MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
> + MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
> + MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
> + MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
> + MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
> + MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
> + MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
> +
> +#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
> + MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
> + MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
> + MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
> + MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
> +
> +#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
> + INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
> + MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
> + MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
> + MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
> + MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
> + MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
> + MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
> + MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
> + MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
> + MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
> + MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
> + MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
> + MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
> + MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
> + MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
> +
> +#define INTEL_HSW_IDS(MACRO__, ...) \
> + INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_VLV_IDS(MACRO__, ...) \
> + MACRO__(0x0f30, ## __VA_ARGS__), \
> + MACRO__(0x0f31, ## __VA_ARGS__), \
> + MACRO__(0x0f32, ## __VA_ARGS__), \
> + MACRO__(0x0f33, ## __VA_ARGS__)
> +
> +#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
> + MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
> +
> +#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */
> +
> +#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
> + MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
> + MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
> +
> +#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
> + MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
> +
> +#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */
> +
> +#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
> + MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
> + MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
> +
> +#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
> +
> +#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x162E, ## __VA_ARGS__) /* ULX */
> +
> +#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
> + MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
> +
> +#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
> + MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
> +
> +#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \
> + MACRO__(0x163E, ## __VA_ARGS__) /* ULX */
> +
> +#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
> + INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
> + MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
> + MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
> +
> +#define INTEL_BDW_IDS(MACRO__, ...) \
> + INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_CHV_IDS(MACRO__, ...) \
> + MACRO__(0x22b0, ## __VA_ARGS__), \
> + MACRO__(0x22b1, ## __VA_ARGS__), \
> + MACRO__(0x22b2, ## __VA_ARGS__), \
> + MACRO__(0x22b3, ## __VA_ARGS__)
> +
> +#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
> + MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
> +
> +#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
> + MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
> +
> +#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
> + MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
> + MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
> +
> +#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
> + MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
> +
> +#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */
> +
> +#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
> + MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
> +
> +#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
> + MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
> +
> +#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
> + INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
> + MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
> + MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
> +
> +#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
> + MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
> + MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
> + MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
> + MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
> +
> +#define INTEL_SKL_IDS(MACRO__, ...) \
> + INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_BXT_IDS(MACRO__, ...) \
> + MACRO__(0x0A84, ## __VA_ARGS__), \
> + MACRO__(0x1A84, ## __VA_ARGS__), \
> + MACRO__(0x1A85, ## __VA_ARGS__), \
> + MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
> + MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
> +
> +#define INTEL_GLK_IDS(MACRO__, ...) \
> + MACRO__(0x3184, ## __VA_ARGS__), \
> + MACRO__(0x3185, ## __VA_ARGS__)
> +
> +#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
> + MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
> +
> +#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
> + MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
> +
> +#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
> + MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
> + MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
> +
> +#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
> + MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
> +
> +#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */
> +
> +#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
> + MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
> + MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
> +
> +#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
> + INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT4_IDS(MACRO__, ...) \
> + MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */
>
> /* AML/KBL Y GT2 */
> -#define INTEL_AML_KBL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
> +#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
> + MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
>
> /* AML/CFL Y GT2 */
> -#define INTEL_AML_CFL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x87CA, info)
> +#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x87CA, ## __VA_ARGS__)
>
> /* CML GT1 */
> -#define INTEL_CML_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BA2, info), \
> - INTEL_VGA_DEVICE(0x9BA4, info), \
> - INTEL_VGA_DEVICE(0x9BA5, info), \
> - INTEL_VGA_DEVICE(0x9BA8, info)
> +#define INTEL_CML_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9BA2, ## __VA_ARGS__), \
> + MACRO__(0x9BA4, ## __VA_ARGS__), \
> + MACRO__(0x9BA5, ## __VA_ARGS__), \
> + MACRO__(0x9BA8, ## __VA_ARGS__)
>
> -#define INTEL_CML_U_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B21, info), \
> - INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAC, info)
> +#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9B21, ## __VA_ARGS__), \
> + MACRO__(0x9BAA, ## __VA_ARGS__), \
> + MACRO__(0x9BAC, ## __VA_ARGS__)
>
> /* CML GT2 */
> -#define INTEL_CML_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9BC2, info), \
> - INTEL_VGA_DEVICE(0x9BC4, info), \
> - INTEL_VGA_DEVICE(0x9BC5, info), \
> - INTEL_VGA_DEVICE(0x9BC6, info), \
> - INTEL_VGA_DEVICE(0x9BC8, info), \
> - INTEL_VGA_DEVICE(0x9BE6, info), \
> - INTEL_VGA_DEVICE(0x9BF6, info)
> -
> -#define INTEL_CML_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B41, info), \
> - INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCC, info)
> -
> -#define INTEL_CML_IDS(info) \
> - INTEL_CML_GT1_IDS(info), \
> - INTEL_CML_GT2_IDS(info), \
> - INTEL_CML_U_GT1_IDS(info), \
> - INTEL_CML_U_GT2_IDS(info)
> -
> -#define INTEL_KBL_IDS(info) \
> - INTEL_KBL_GT1_IDS(info), \
> - INTEL_KBL_GT2_IDS(info), \
> - INTEL_KBL_GT3_IDS(info), \
> - INTEL_KBL_GT4_IDS(info), \
> - INTEL_AML_KBL_GT2_IDS(info)
> +#define INTEL_CML_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9BC2, ## __VA_ARGS__), \
> + MACRO__(0x9BC4, ## __VA_ARGS__), \
> + MACRO__(0x9BC5, ## __VA_ARGS__), \
> + MACRO__(0x9BC6, ## __VA_ARGS__), \
> + MACRO__(0x9BC8, ## __VA_ARGS__), \
> + MACRO__(0x9BE6, ## __VA_ARGS__), \
> + MACRO__(0x9BF6, ## __VA_ARGS__)
> +
> +#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9B41, ## __VA_ARGS__), \
> + MACRO__(0x9BCA, ## __VA_ARGS__), \
> + MACRO__(0x9BCC, ## __VA_ARGS__)
> +
> +#define INTEL_CML_IDS(MACRO__, ...) \
> + INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_KBL_IDS(MACRO__, ...) \
> + INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* CFL S */
> -#define INTEL_CFL_S_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
> - INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
> -
> -#define INTEL_CFL_S_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
> +#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
> + MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
> +
> +#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
> + MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
>
> /* CFL H */
> -#define INTEL_CFL_H_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E9C, info)
> +#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3E9C, ## __VA_ARGS__)
>
> -#define INTEL_CFL_H_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
> +#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
> + MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
>
> /* CFL U GT2 */
> -#define INTEL_CFL_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA9, info)
> +#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3EA9, ## __VA_ARGS__)
>
> /* CFL U GT3 */
> -#define INTEL_CFL_U_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
> -
> -#define INTEL_CFL_IDS(info) \
> - INTEL_CFL_S_GT1_IDS(info), \
> - INTEL_CFL_S_GT2_IDS(info), \
> - INTEL_CFL_H_GT1_IDS(info), \
> - INTEL_CFL_H_GT2_IDS(info), \
> - INTEL_CFL_U_GT2_IDS(info), \
> - INTEL_CFL_U_GT3_IDS(info), \
> - INTEL_AML_CFL_GT2_IDS(info)
> +#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
> + MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
> +
> +#define INTEL_CFL_IDS(MACRO__, ...) \
> + INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* WHL/CFL U GT1 */
> -#define INTEL_WHL_U_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA1, info), \
> - INTEL_VGA_DEVICE(0x3EA4, info)
> +#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x3EA1, ## __VA_ARGS__), \
> + MACRO__(0x3EA4, ## __VA_ARGS__)
>
> /* WHL/CFL U GT2 */
> -#define INTEL_WHL_U_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA0, info), \
> - INTEL_VGA_DEVICE(0x3EA3, info)
> +#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x3EA0, ## __VA_ARGS__), \
> + MACRO__(0x3EA3, ## __VA_ARGS__)
>
> /* WHL/CFL U GT3 */
> -#define INTEL_WHL_U_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x3EA2, info)
> +#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \
> + MACRO__(0x3EA2, ## __VA_ARGS__)
>
> -#define INTEL_WHL_IDS(info) \
> - INTEL_WHL_U_GT1_IDS(info), \
> - INTEL_WHL_U_GT2_IDS(info), \
> - INTEL_WHL_U_GT3_IDS(info)
> +#define INTEL_WHL_IDS(MACRO__, ...) \
> + INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
>
> /* CNL */
> -#define INTEL_CNL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A44, info), \
> - INTEL_VGA_DEVICE(0x5A4C, info), \
> - INTEL_VGA_DEVICE(0x5A54, info), \
> - INTEL_VGA_DEVICE(0x5A5C, info)
> -
> -#define INTEL_CNL_IDS(info) \
> - INTEL_CNL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x5A40, info), \
> - INTEL_VGA_DEVICE(0x5A41, info), \
> - INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info), \
> - INTEL_VGA_DEVICE(0x5A50, info), \
> - INTEL_VGA_DEVICE(0x5A51, info), \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A59, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info)
> +#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
> + MACRO__(0x5A44, ## __VA_ARGS__), \
> + MACRO__(0x5A4C, ## __VA_ARGS__), \
> + MACRO__(0x5A54, ## __VA_ARGS__), \
> + MACRO__(0x5A5C, ## __VA_ARGS__)
> +
> +#define INTEL_CNL_IDS(MACRO__, ...) \
> + INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x5A40, ## __VA_ARGS__), \
> + MACRO__(0x5A41, ## __VA_ARGS__), \
> + MACRO__(0x5A42, ## __VA_ARGS__), \
> + MACRO__(0x5A49, ## __VA_ARGS__), \
> + MACRO__(0x5A4A, ## __VA_ARGS__), \
> + MACRO__(0x5A50, ## __VA_ARGS__), \
> + MACRO__(0x5A51, ## __VA_ARGS__), \
> + MACRO__(0x5A52, ## __VA_ARGS__), \
> + MACRO__(0x5A59, ## __VA_ARGS__), \
> + MACRO__(0x5A5A, ## __VA_ARGS__)
>
> /* ICL */
> -#define INTEL_ICL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x8A50, info), \
> - INTEL_VGA_DEVICE(0x8A52, info), \
> - INTEL_VGA_DEVICE(0x8A53, info), \
> - INTEL_VGA_DEVICE(0x8A54, info), \
> - INTEL_VGA_DEVICE(0x8A56, info), \
> - INTEL_VGA_DEVICE(0x8A57, info), \
> - INTEL_VGA_DEVICE(0x8A58, info), \
> - INTEL_VGA_DEVICE(0x8A59, info), \
> - INTEL_VGA_DEVICE(0x8A5A, info), \
> - INTEL_VGA_DEVICE(0x8A5B, info), \
> - INTEL_VGA_DEVICE(0x8A5C, info), \
> - INTEL_VGA_DEVICE(0x8A70, info), \
> - INTEL_VGA_DEVICE(0x8A71, info)
> -
> -#define INTEL_ICL_IDS(info) \
> - INTEL_ICL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x8A51, info), \
> - INTEL_VGA_DEVICE(0x8A5D, info)
> +#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
> + MACRO__(0x8A50, ## __VA_ARGS__), \
> + MACRO__(0x8A52, ## __VA_ARGS__), \
> + MACRO__(0x8A53, ## __VA_ARGS__), \
> + MACRO__(0x8A54, ## __VA_ARGS__), \
> + MACRO__(0x8A56, ## __VA_ARGS__), \
> + MACRO__(0x8A57, ## __VA_ARGS__), \
> + MACRO__(0x8A58, ## __VA_ARGS__), \
> + MACRO__(0x8A59, ## __VA_ARGS__), \
> + MACRO__(0x8A5A, ## __VA_ARGS__), \
> + MACRO__(0x8A5B, ## __VA_ARGS__), \
> + MACRO__(0x8A5C, ## __VA_ARGS__), \
> + MACRO__(0x8A70, ## __VA_ARGS__), \
> + MACRO__(0x8A71, ## __VA_ARGS__)
> +
> +#define INTEL_ICL_IDS(MACRO__, ...) \
> + INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
> + MACRO__(0x8A51, ## __VA_ARGS__), \
> + MACRO__(0x8A5D, ## __VA_ARGS__)
>
> /* EHL */
> -#define INTEL_EHL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4541, info), \
> - INTEL_VGA_DEVICE(0x4551, info), \
> - INTEL_VGA_DEVICE(0x4555, info), \
> - INTEL_VGA_DEVICE(0x4557, info), \
> - INTEL_VGA_DEVICE(0x4570, info), \
> - INTEL_VGA_DEVICE(0x4571, info)
> +#define INTEL_EHL_IDS(MACRO__, ...) \
> + MACRO__(0x4541, ## __VA_ARGS__), \
> + MACRO__(0x4551, ## __VA_ARGS__), \
> + MACRO__(0x4555, ## __VA_ARGS__), \
> + MACRO__(0x4557, ## __VA_ARGS__), \
> + MACRO__(0x4570, ## __VA_ARGS__), \
> + MACRO__(0x4571, ## __VA_ARGS__)
>
> /* JSL */
> -#define INTEL_JSL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4E51, info), \
> - INTEL_VGA_DEVICE(0x4E55, info), \
> - INTEL_VGA_DEVICE(0x4E57, info), \
> - INTEL_VGA_DEVICE(0x4E61, info), \
> - INTEL_VGA_DEVICE(0x4E71, info)
> +#define INTEL_JSL_IDS(MACRO__, ...) \
> + MACRO__(0x4E51, ## __VA_ARGS__), \
> + MACRO__(0x4E55, ## __VA_ARGS__), \
> + MACRO__(0x4E57, ## __VA_ARGS__), \
> + MACRO__(0x4E61, ## __VA_ARGS__), \
> + MACRO__(0x4E71, ## __VA_ARGS__)
>
> /* TGL */
> -#define INTEL_TGL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9A60, info), \
> - INTEL_VGA_DEVICE(0x9A68, info), \
> - INTEL_VGA_DEVICE(0x9A70, info)
> -
> -#define INTEL_TGL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9A40, info), \
> - INTEL_VGA_DEVICE(0x9A49, info), \
> - INTEL_VGA_DEVICE(0x9A59, info), \
> - INTEL_VGA_DEVICE(0x9A78, info), \
> - INTEL_VGA_DEVICE(0x9AC0, info), \
> - INTEL_VGA_DEVICE(0x9AC9, info), \
> - INTEL_VGA_DEVICE(0x9AD9, info), \
> - INTEL_VGA_DEVICE(0x9AF8, info)
> -
> -#define INTEL_TGL_IDS(info) \
> - INTEL_TGL_GT1_IDS(info), \
> - INTEL_TGL_GT2_IDS(info)
> +#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9A60, ## __VA_ARGS__), \
> + MACRO__(0x9A68, ## __VA_ARGS__), \
> + MACRO__(0x9A70, ## __VA_ARGS__)
> +
> +#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9A40, ## __VA_ARGS__), \
> + MACRO__(0x9A49, ## __VA_ARGS__), \
> + MACRO__(0x9A59, ## __VA_ARGS__), \
> + MACRO__(0x9A78, ## __VA_ARGS__), \
> + MACRO__(0x9AC0, ## __VA_ARGS__), \
> + MACRO__(0x9AC9, ## __VA_ARGS__), \
> + MACRO__(0x9AD9, ## __VA_ARGS__), \
> + MACRO__(0x9AF8, ## __VA_ARGS__)
> +
> +#define INTEL_TGL_IDS(MACRO__, ...) \
> + INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
>
> /* RKL */
> -#define INTEL_RKL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4C80, info), \
> - INTEL_VGA_DEVICE(0x4C8A, info), \
> - INTEL_VGA_DEVICE(0x4C8B, info), \
> - INTEL_VGA_DEVICE(0x4C8C, info), \
> - INTEL_VGA_DEVICE(0x4C90, info), \
> - INTEL_VGA_DEVICE(0x4C9A, info)
> +#define INTEL_RKL_IDS(MACRO__, ...) \
> + MACRO__(0x4C80, ## __VA_ARGS__), \
> + MACRO__(0x4C8A, ## __VA_ARGS__), \
> + MACRO__(0x4C8B, ## __VA_ARGS__), \
> + MACRO__(0x4C8C, ## __VA_ARGS__), \
> + MACRO__(0x4C90, ## __VA_ARGS__), \
> + MACRO__(0x4C9A, ## __VA_ARGS__)
>
> /* DG1 */
> -#define INTEL_DG1_IDS(info) \
> - INTEL_VGA_DEVICE(0x4905, info), \
> - INTEL_VGA_DEVICE(0x4906, info), \
> - INTEL_VGA_DEVICE(0x4907, info), \
> - INTEL_VGA_DEVICE(0x4908, info), \
> - INTEL_VGA_DEVICE(0x4909, info)
> +#define INTEL_DG1_IDS(MACRO__, ...) \
> + MACRO__(0x4905, ## __VA_ARGS__), \
> + MACRO__(0x4906, ## __VA_ARGS__), \
> + MACRO__(0x4907, ## __VA_ARGS__), \
> + MACRO__(0x4908, ## __VA_ARGS__), \
> + MACRO__(0x4909, ## __VA_ARGS__)
>
> /* ADL-S */
> -#define INTEL_ADLS_IDS(info) \
> - INTEL_VGA_DEVICE(0x4680, info), \
> - INTEL_VGA_DEVICE(0x4682, info), \
> - INTEL_VGA_DEVICE(0x4688, info), \
> - INTEL_VGA_DEVICE(0x468A, info), \
> - INTEL_VGA_DEVICE(0x468B, info), \
> - INTEL_VGA_DEVICE(0x4690, info), \
> - INTEL_VGA_DEVICE(0x4692, info), \
> - INTEL_VGA_DEVICE(0x4693, info)
> +#define INTEL_ADLS_IDS(MACRO__, ...) \
> + MACRO__(0x4680, ## __VA_ARGS__), \
> + MACRO__(0x4682, ## __VA_ARGS__), \
> + MACRO__(0x4688, ## __VA_ARGS__), \
> + MACRO__(0x468A, ## __VA_ARGS__), \
> + MACRO__(0x468B, ## __VA_ARGS__), \
> + MACRO__(0x4690, ## __VA_ARGS__), \
> + MACRO__(0x4692, ## __VA_ARGS__), \
> + MACRO__(0x4693, ## __VA_ARGS__)
>
> /* ADL-P */
> -#define INTEL_ADLP_IDS(info) \
> - INTEL_VGA_DEVICE(0x46A0, info), \
> - INTEL_VGA_DEVICE(0x46A1, info), \
> - INTEL_VGA_DEVICE(0x46A2, info), \
> - INTEL_VGA_DEVICE(0x46A3, info), \
> - INTEL_VGA_DEVICE(0x46A6, info), \
> - INTEL_VGA_DEVICE(0x46A8, info), \
> - INTEL_VGA_DEVICE(0x46AA, info), \
> - INTEL_VGA_DEVICE(0x462A, info), \
> - INTEL_VGA_DEVICE(0x4626, info), \
> - INTEL_VGA_DEVICE(0x4628, info), \
> - INTEL_VGA_DEVICE(0x46B0, info), \
> - INTEL_VGA_DEVICE(0x46B1, info), \
> - INTEL_VGA_DEVICE(0x46B2, info), \
> - INTEL_VGA_DEVICE(0x46B3, info), \
> - INTEL_VGA_DEVICE(0x46C0, info), \
> - INTEL_VGA_DEVICE(0x46C1, info), \
> - INTEL_VGA_DEVICE(0x46C2, info), \
> - INTEL_VGA_DEVICE(0x46C3, info)
> +#define INTEL_ADLP_IDS(MACRO__, ...) \
> + MACRO__(0x46A0, ## __VA_ARGS__), \
> + MACRO__(0x46A1, ## __VA_ARGS__), \
> + MACRO__(0x46A2, ## __VA_ARGS__), \
> + MACRO__(0x46A3, ## __VA_ARGS__), \
> + MACRO__(0x46A6, ## __VA_ARGS__), \
> + MACRO__(0x46A8, ## __VA_ARGS__), \
> + MACRO__(0x46AA, ## __VA_ARGS__), \
> + MACRO__(0x462A, ## __VA_ARGS__), \
> + MACRO__(0x4626, ## __VA_ARGS__), \
> + MACRO__(0x4628, ## __VA_ARGS__), \
> + MACRO__(0x46B0, ## __VA_ARGS__), \
> + MACRO__(0x46B1, ## __VA_ARGS__), \
> + MACRO__(0x46B2, ## __VA_ARGS__), \
> + MACRO__(0x46B3, ## __VA_ARGS__), \
> + MACRO__(0x46C0, ## __VA_ARGS__), \
> + MACRO__(0x46C1, ## __VA_ARGS__), \
> + MACRO__(0x46C2, ## __VA_ARGS__), \
> + MACRO__(0x46C3, ## __VA_ARGS__)
>
> /* ADL-N */
> -#define INTEL_ADLN_IDS(info) \
> - INTEL_VGA_DEVICE(0x46D0, info), \
> - INTEL_VGA_DEVICE(0x46D1, info), \
> - INTEL_VGA_DEVICE(0x46D2, info), \
> - INTEL_VGA_DEVICE(0x46D3, info), \
> - INTEL_VGA_DEVICE(0x46D4, info)
> +#define INTEL_ADLN_IDS(MACRO__, ...) \
> + MACRO__(0x46D0, ## __VA_ARGS__), \
> + MACRO__(0x46D1, ## __VA_ARGS__), \
> + MACRO__(0x46D2, ## __VA_ARGS__), \
> + MACRO__(0x46D3, ## __VA_ARGS__), \
> + MACRO__(0x46D4, ## __VA_ARGS__)
>
> /* RPL-S */
> -#define INTEL_RPLS_IDS(info) \
> - INTEL_VGA_DEVICE(0xA780, info), \
> - INTEL_VGA_DEVICE(0xA781, info), \
> - INTEL_VGA_DEVICE(0xA782, info), \
> - INTEL_VGA_DEVICE(0xA783, info), \
> - INTEL_VGA_DEVICE(0xA788, info), \
> - INTEL_VGA_DEVICE(0xA789, info), \
> - INTEL_VGA_DEVICE(0xA78A, info), \
> - INTEL_VGA_DEVICE(0xA78B, info)
> +#define INTEL_RPLS_IDS(MACRO__, ...) \
> + MACRO__(0xA780, ## __VA_ARGS__), \
> + MACRO__(0xA781, ## __VA_ARGS__), \
> + MACRO__(0xA782, ## __VA_ARGS__), \
> + MACRO__(0xA783, ## __VA_ARGS__), \
> + MACRO__(0xA788, ## __VA_ARGS__), \
> + MACRO__(0xA789, ## __VA_ARGS__), \
> + MACRO__(0xA78A, ## __VA_ARGS__), \
> + MACRO__(0xA78B, ## __VA_ARGS__)
>
> /* RPL-U */
> -#define INTEL_RPLU_IDS(info) \
> - INTEL_VGA_DEVICE(0xA721, info), \
> - INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A9, info), \
> - INTEL_VGA_DEVICE(0xA7AC, info), \
> - INTEL_VGA_DEVICE(0xA7AD, info)
> +#define INTEL_RPLU_IDS(MACRO__, ...) \
> + MACRO__(0xA721, ## __VA_ARGS__), \
> + MACRO__(0xA7A1, ## __VA_ARGS__), \
> + MACRO__(0xA7A9, ## __VA_ARGS__), \
> + MACRO__(0xA7AC, ## __VA_ARGS__), \
> + MACRO__(0xA7AD, ## __VA_ARGS__)
>
> /* RPL-P */
> -#define INTEL_RPLP_IDS(info) \
> - INTEL_VGA_DEVICE(0xA720, info), \
> - INTEL_VGA_DEVICE(0xA7A0, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> - INTEL_VGA_DEVICE(0xA7AA, info), \
> - INTEL_VGA_DEVICE(0xA7AB, info)
> +#define INTEL_RPLP_IDS(MACRO__, ...) \
> + MACRO__(0xA720, ## __VA_ARGS__), \
> + MACRO__(0xA7A0, ## __VA_ARGS__), \
> + MACRO__(0xA7A8, ## __VA_ARGS__), \
> + MACRO__(0xA7AA, ## __VA_ARGS__), \
> + MACRO__(0xA7AB, ## __VA_ARGS__)
>
> /* DG2 */
> -#define INTEL_DG2_G10_IDS(info) \
> - INTEL_VGA_DEVICE(0x5690, info), \
> - INTEL_VGA_DEVICE(0x5691, info), \
> - INTEL_VGA_DEVICE(0x5692, info), \
> - INTEL_VGA_DEVICE(0x56A0, info), \
> - INTEL_VGA_DEVICE(0x56A1, info), \
> - INTEL_VGA_DEVICE(0x56A2, info), \
> - INTEL_VGA_DEVICE(0x56BE, info), \
> - INTEL_VGA_DEVICE(0x56BF, info)
> -
> -#define INTEL_DG2_G11_IDS(info) \
> - INTEL_VGA_DEVICE(0x5693, info), \
> - INTEL_VGA_DEVICE(0x5694, info), \
> - INTEL_VGA_DEVICE(0x5695, info), \
> - INTEL_VGA_DEVICE(0x56A5, info), \
> - INTEL_VGA_DEVICE(0x56A6, info), \
> - INTEL_VGA_DEVICE(0x56B0, info), \
> - INTEL_VGA_DEVICE(0x56B1, info), \
> - INTEL_VGA_DEVICE(0x56BA, info), \
> - INTEL_VGA_DEVICE(0x56BB, info), \
> - INTEL_VGA_DEVICE(0x56BC, info), \
> - INTEL_VGA_DEVICE(0x56BD, info)
> -
> -#define INTEL_DG2_G12_IDS(info) \
> - INTEL_VGA_DEVICE(0x5696, info), \
> - INTEL_VGA_DEVICE(0x5697, info), \
> - INTEL_VGA_DEVICE(0x56A3, info), \
> - INTEL_VGA_DEVICE(0x56A4, info), \
> - INTEL_VGA_DEVICE(0x56B2, info), \
> - INTEL_VGA_DEVICE(0x56B3, info)
> -
> -#define INTEL_DG2_IDS(info) \
> - INTEL_DG2_G10_IDS(info), \
> - INTEL_DG2_G11_IDS(info), \
> - INTEL_DG2_G12_IDS(info)
> -
> -#define INTEL_ATS_M150_IDS(info) \
> - INTEL_VGA_DEVICE(0x56C0, info), \
> - INTEL_VGA_DEVICE(0x56C2, info)
> -
> -#define INTEL_ATS_M75_IDS(info) \
> - INTEL_VGA_DEVICE(0x56C1, info)
> -
> -#define INTEL_ATS_M_IDS(info) \
> - INTEL_ATS_M150_IDS(info), \
> - INTEL_ATS_M75_IDS(info)
> +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__), \
> + MACRO__(0x56A0, ## __VA_ARGS__), \
> + MACRO__(0x56A1, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__), \
> + MACRO__(0x56BE, ## __VA_ARGS__), \
> + MACRO__(0x56BF, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__), \
> + MACRO__(0x56A5, ## __VA_ARGS__), \
> + MACRO__(0x56A6, ## __VA_ARGS__), \
> + MACRO__(0x56B0, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__), \
> + MACRO__(0x56BA, ## __VA_ARGS__), \
> + MACRO__(0x56BB, ## __VA_ARGS__), \
> + MACRO__(0x56BC, ## __VA_ARGS__), \
> + MACRO__(0x56BD, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__), \
> + MACRO__(0x56A3, ## __VA_ARGS__), \
> + MACRO__(0x56A4, ## __VA_ARGS__), \
> + MACRO__(0x56B2, ## __VA_ARGS__), \
> + MACRO__(0x56B3, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M150_IDS(MACRO__, ...) \
> + MACRO__(0x56C0, ## __VA_ARGS__), \
> + MACRO__(0x56C2, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M75_IDS(MACRO__, ...) \
> + MACRO__(0x56C1, ## __VA_ARGS__)
> +
> +#define INTEL_ATS_M_IDS(MACRO__, ...) \
> + INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
>
> /* MTL */
> -#define INTEL_MTL_IDS(info) \
> - INTEL_VGA_DEVICE(0x7D40, info), \
> - INTEL_VGA_DEVICE(0x7D41, info), \
> - INTEL_VGA_DEVICE(0x7D45, info), \
> - INTEL_VGA_DEVICE(0x7D51, info), \
> - INTEL_VGA_DEVICE(0x7D55, info), \
> - INTEL_VGA_DEVICE(0x7D60, info), \
> - INTEL_VGA_DEVICE(0x7D67, info), \
> - INTEL_VGA_DEVICE(0x7DD1, info), \
> - INTEL_VGA_DEVICE(0x7DD5, info)
> +#define INTEL_MTL_IDS(MACRO__, ...) \
> + MACRO__(0x7D40, ## __VA_ARGS__), \
> + MACRO__(0x7D41, ## __VA_ARGS__), \
> + MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D51, ## __VA_ARGS__), \
> + MACRO__(0x7D55, ## __VA_ARGS__), \
> + MACRO__(0x7D60, ## __VA_ARGS__), \
> + MACRO__(0x7D67, ## __VA_ARGS__), \
> + MACRO__(0x7DD1, ## __VA_ARGS__), \
> + MACRO__(0x7DD5, ## __VA_ARGS__)
>
> #endif /* _I915_PCIIDS_H */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
2024-05-20 12:27 ` Jani Nikula
@ 2024-05-22 9:43 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2024-05-22 9:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Bjorn Helgaas, linux-pci, Lucas De Marchi, Rodrigo Vivi
On Mon, 20 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> On Wed, 15 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
>> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
>> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
>> same pattern.
>>
>> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
>> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>>
>> Cc: Bjorn Helgaas <bhelgaas@google.com>
>> Cc: linux-pci@vger.kernel.org
>
> Bjorn, since I asked for acks on the last ones, I probably should here
> too. :)
>
> I'm hoping to stop mucking with the macros after this.
Okay, well, I pushed this to drm-intel-next, since this doesn't really
change x86 functionally, and you weren't all that interested the last
time. Hope it's fine. :)
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 11+ messages in thread