* [PATCH 0/7] drm/i915/display: conversion to struct intel_display
@ 2024-08-22 16:04 Jani Nikula
2024-08-22 16:04 ` [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding Jani Nikula
` (10 more replies)
0 siblings, 11 replies; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
A bunch more intel_display conversions.
BR,
Jani.
Jani Nikula (7):
drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding
drm/i915/vblank: fix context imbalance warnings
drm/i915/vblank: convert to struct intel_display
drm/i915/vrr: convert to struct intel_display
drm/i915/tv: convert to struct intel_display
drm/i915/sprite: convert to struct intel_display
drm/i915/display: convert params to struct intel_display
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../display/intel_display_debugfs_params.c | 8 +-
.../display/intel_display_debugfs_params.h | 4 +-
.../drm/i915/display/intel_display_params.c | 6 +-
.../drm/i915/display/intel_display_params.h | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 209 ++++++++++--------
drivers/gpu/drm/i915/display/intel_tv.c | 203 ++++++++---------
drivers/gpu/drm/i915/display/intel_tv.h | 6 +-
drivers/gpu/drm/i915/display/intel_vblank.c | 111 +++++-----
drivers/gpu/drm/i915/display/intel_vrr.c | 127 +++++------
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +-
13 files changed, 357 insertions(+), 331 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:37 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings Jani Nikula
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
There's a helper for drm->vblank[drm_crtc_index(crtc)], use it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index f183e0d4b2ba..551e9ca9bb99 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -68,7 +68,7 @@
u32 i915_get_vblank_counter(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = to_intel_crtc(crtc)->pipe;
u32 pixel, vbl_start, hsync_start, htotal;
@@ -120,7 +120,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
if (!vblank->max_vblank_count)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
2024-08-22 16:04 ` [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:38 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 3/7] drm/i915/vblank: convert to struct intel_display Jani Nikula
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
When building for xe, we get the context imbalance warning as the actual
locking/unlocking is not compiled:
../drivers/gpu/drm/i915/display/intel_vblank.c:306:13: warning: context imbalance in 'intel_vblank_section_enter' - wrong count at exit
../drivers/gpu/drm/i915/display/intel_vblank.c:314:13: warning: context imbalance in 'intel_vblank_section_exit' - wrong count at exit
Fix by adding separata stubs for xe without __acquires/__releases
annotation.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 551e9ca9bb99..2073e8075af4 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -303,21 +303,27 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
* all register accesses to the same cacheline to be serialized,
* otherwise they may hang.
*/
+#ifdef I915
static void intel_vblank_section_enter(struct drm_i915_private *i915)
__acquires(i915->uncore.lock)
{
-#ifdef I915
spin_lock(&i915->uncore.lock);
-#endif
}
static void intel_vblank_section_exit(struct drm_i915_private *i915)
__releases(i915->uncore.lock)
{
-#ifdef I915
spin_unlock(&i915->uncore.lock);
-#endif
}
+#else
+static void intel_vblank_section_enter(struct drm_i915_private *i915)
+{
+}
+
+static void intel_vblank_section_exit(struct drm_i915_private *i915)
+{
+}
+#endif
static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
bool in_vblank_irq,
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/7] drm/i915/vblank: convert to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
2024-08-22 16:04 ` [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding Jani Nikula
2024-08-22 16:04 ` [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:42 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 4/7] drm/i915/vrr: " Jani Nikula
` (7 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_vblank.[ch] to struct intel_display.
Some stragglers are left behind where needed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 97 +++++++++++----------
1 file changed, 50 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 2073e8075af4..838b55ecb1d8 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -67,7 +67,7 @@
*/
u32 i915_get_vblank_counter(struct drm_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = to_intel_crtc(crtc)->pipe;
@@ -103,8 +103,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
* we get a low value that's stable across two reads of the high
* register.
*/
- frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
- PIPEFRAME(dev_priv, pipe));
+ frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
+ PIPEFRAME(display, pipe));
pixel = frame & PIPE_PIXEL_MASK;
frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
@@ -119,19 +119,19 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_display *display = to_intel_display(crtc->dev);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
if (!vblank->max_vblank_count)
return 0;
- return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
+ return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
}
static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
const struct drm_display_mode *mode = &vblank->hwmode;
u32 htotal = mode->crtc_htotal;
@@ -150,16 +150,16 @@ static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
* pipe frame time stamp. The time stamp value
* is sampled at every start of vertical blank.
*/
- scan_prev_time = intel_de_read_fw(dev_priv,
+ scan_prev_time = intel_de_read_fw(display,
PIPE_FRMTMSTMP(crtc->pipe));
/*
* The TIMESTAMP_CTR register has the current
* time stamp value.
*/
- scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
+ scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
- scan_post_time = intel_de_read_fw(dev_priv,
+ scan_post_time = intel_de_read_fw(display,
PIPE_FRMTMSTMP(crtc->pipe));
} while (scan_post_time != scan_prev_time);
@@ -192,6 +192,7 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
/*
@@ -220,7 +221,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
* However if queried just before the start of vblank we'll get an
* answer that's slightly in the future.
*/
- if (DISPLAY_VER(i915) == 2)
+ if (DISPLAY_VER(display) == 2)
return -1;
else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return 2;
@@ -234,8 +235,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
*/
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(crtc);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = crtc->pipe;
@@ -249,7 +249,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
vtotal = intel_mode_vtotal(mode);
- position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
+ position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
/*
* On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -263,13 +263,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
* problem. We may need to extend this to include other platforms,
* but so far testing only shows the problem on HSW.
*/
- if (HAS_DDI(dev_priv) && !position) {
+ if (HAS_DDI(display) && !position) {
int i, temp;
for (i = 0; i < 100; i++) {
udelay(1);
- temp = intel_de_read_fw(dev_priv,
- PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
+ temp = intel_de_read_fw(display,
+ PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
if (temp != position) {
position = temp;
break;
@@ -304,23 +304,25 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
* otherwise they may hang.
*/
#ifdef I915
-static void intel_vblank_section_enter(struct drm_i915_private *i915)
+static void intel_vblank_section_enter(struct intel_display *display)
__acquires(i915->uncore.lock)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
spin_lock(&i915->uncore.lock);
}
-static void intel_vblank_section_exit(struct drm_i915_private *i915)
+static void intel_vblank_section_exit(struct intel_display *display)
__releases(i915->uncore.lock)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
spin_unlock(&i915->uncore.lock);
}
#else
-static void intel_vblank_section_enter(struct drm_i915_private *i915)
+static void intel_vblank_section_enter(struct intel_display *display)
{
}
-static void intel_vblank_section_exit(struct drm_i915_private *i915)
+static void intel_vblank_section_exit(struct intel_display *display)
{
}
#endif
@@ -331,19 +333,19 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
ktime_t *stime, ktime_t *etime,
const struct drm_display_mode *mode)
{
- struct drm_device *dev = _crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(_crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc = to_intel_crtc(_crtc);
enum pipe pipe = crtc->pipe;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
unsigned long irqflags;
- bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
- IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
+ bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
+ IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 ||
crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
- if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
- drm_dbg(&dev_priv->drm,
+ if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
+ drm_dbg(display->drm,
"trying to get scanoutpos for disabled pipe %c\n",
pipe_name(pipe));
return false;
@@ -361,7 +363,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
* preemption disabled, so the following code must not block.
*/
local_irq_save(irqflags);
- intel_vblank_section_enter(dev_priv);
+ intel_vblank_section_enter(display);
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
@@ -393,7 +395,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
* We can split this into vertical and horizontal
* scanout position.
*/
- position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
+ position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
/* convert to pixel counts */
vbl_start *= htotal;
@@ -429,7 +431,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
- intel_vblank_section_exit(dev_priv);
+ intel_vblank_section_exit(display);
local_irq_restore(irqflags);
/*
@@ -464,42 +466,42 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
unsigned long irqflags;
int position;
local_irq_save(irqflags);
- intel_vblank_section_enter(dev_priv);
+ intel_vblank_section_enter(display);
position = __intel_get_crtc_scanline(crtc);
- intel_vblank_section_exit(dev_priv);
+ intel_vblank_section_exit(display);
local_irq_restore(irqflags);
return position;
}
-static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
+static bool pipe_scanline_is_moving(struct intel_display *display,
enum pipe pipe)
{
- i915_reg_t reg = PIPEDSL(dev_priv, pipe);
+ i915_reg_t reg = PIPEDSL(display, pipe);
u32 line1, line2;
- line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
+ line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
msleep(5);
- line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
+ line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
return line1 != line2;
}
static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
/* Wait for the display line to settle/start moving */
- if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
- drm_err(&dev_priv->drm,
+ if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
+ drm_err(display->drm,
"pipe %c scanline %s wait timed out\n",
pipe_name(pipe), str_on_off(state));
}
@@ -517,8 +519,8 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
bool vrr_enable)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u8 mode_flags = crtc_state->mode_flags;
struct drm_display_mode adjusted_mode;
int vmax_vblank_start = 0;
@@ -527,7 +529,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
if (vrr_enable) {
- drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
+ drm_WARN_ON(display->drm,
+ (mode_flags & I915_MODE_FLAG_VRR) == 0);
adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
@@ -549,8 +552,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
* __intel_get_crtc_scanline()) with vblank_time_lock?
* Need to audit everything to make sure it's safe.
*/
- spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
- intel_vblank_section_enter(i915);
+ spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
+ intel_vblank_section_enter(display);
drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
@@ -559,8 +562,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
crtc->mode_flags = mode_flags;
crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
- intel_vblank_section_exit(i915);
- spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
+ intel_vblank_section_exit(display);
+ spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
}
int intel_mode_vdisplay(const struct drm_display_mode *mode)
@@ -666,7 +669,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
{
struct intel_crtc *crtc = evade->crtc;
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
long timeout = msecs_to_jiffies_timeout(1);
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
DEFINE_WAIT(wait);
@@ -688,7 +691,7 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
break;
if (!timeout) {
- drm_err(&i915->drm,
+ drm_err(display->drm,
"Potential atomic update failure on pipe %c\n",
pipe_name(crtc->pipe));
break;
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/7] drm/i915/vrr: convert to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (2 preceding siblings ...)
2024-08-22 16:04 ` [PATCH 3/7] drm/i915/vblank: convert to struct intel_display Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:44 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 5/7] drm/i915/tv: " Jani Nikula
` (6 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_vrr.[ch] to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 127 +++++++++++------------
1 file changed, 61 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 7e1d9c718214..9a51f5bac307 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -17,8 +17,8 @@
bool intel_vrr_is_capable(struct intel_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector);
const struct drm_display_info *info = &connector->base.display_info;
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp;
/*
@@ -43,7 +43,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
return false;
}
- return HAS_VRR(i915) &&
+ return HAS_VRR(display) &&
info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
}
@@ -89,10 +89,9 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
*/
static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(display) >= 13)
return crtc_state->vrr.guardband;
else
/* The hw imposes the extra scanline before frame start */
@@ -113,11 +112,11 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
static bool
is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- if (!HAS_CMRR(i915))
+ if (!HAS_CMRR(display))
return false;
actual_refresh_k =
@@ -161,8 +160,7 @@ void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -186,7 +184,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (!crtc_state->vrr.in_range)
return;
- if (HAS_LRR(i915))
+ if (HAS_LRR(display))
crtc_state->update_lrr = true;
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
@@ -246,7 +244,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
*/
- if (DISPLAY_VER(i915) >= 13) {
+ if (DISPLAY_VER(display) >= 13) {
crtc_state->vrr.guardband =
crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
} else {
@@ -258,9 +256,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(display) >= 13)
return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
else
@@ -271,7 +269,7 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
@@ -279,133 +277,130 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
* TGL: generate VRR "safe window" for DSB vblank waits
* ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
*/
- if (IS_DISPLAY_VER(dev_priv, 12, 13))
- intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
+ if (IS_DISPLAY_VER(display, 12, 13))
+ intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder),
0, PIPE_VBLANK_WITH_DELAY);
if (!crtc_state->vrr.flipline) {
- intel_de_write(dev_priv,
- TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
+ intel_de_write(display,
+ TRANS_VRR_CTL(display, cpu_transcoder), 0);
return;
}
if (crtc_state->cmrr.enable) {
- intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_m));
- intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_m));
- intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_n));
- intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_n));
}
- intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
crtc_state->vrr.vmin - 1);
- intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
crtc_state->vrr.vmax - 1);
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(crtc_state));
- intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
crtc_state->vrr.flipline - 1);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return;
- intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN | TRANS_PUSH_SEND);
}
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return false;
- return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND;
+ return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
}
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return;
- intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
- if (HAS_AS_SDP(dev_priv))
- intel_de_write(dev_priv,
- TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
+ if (HAS_AS_SDP(display))
+ intel_de_write(display,
+ TRANS_VRR_VSYNC(display, cpu_transcoder),
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
if (crtc_state->cmrr.enable) {
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
trans_vrr_ctl(crtc_state));
} else {
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
}
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
if (!old_crtc_state->vrr.enable)
return;
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
- intel_de_wait_for_clear(dev_priv,
- TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
+ intel_de_wait_for_clear(display,
+ TRANS_VRR_STATUS(display, cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
- intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0);
+ intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
- if (HAS_AS_SDP(dev_priv))
- intel_de_write(dev_priv,
- TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);
+ if (HAS_AS_SDP(display))
+ intel_de_write(display,
+ TRANS_VRR_VSYNC(display, cpu_transcoder), 0);
}
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 trans_vrr_ctl, trans_vrr_vsync;
- trans_vrr_ctl = intel_de_read(dev_priv,
- TRANS_VRR_CTL(dev_priv, cpu_transcoder));
+ trans_vrr_ctl = intel_de_read(display,
+ TRANS_VRR_CTL(display, cpu_transcoder));
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
- if (HAS_CMRR(dev_priv))
+ if (HAS_CMRR(display))
crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
- intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
- TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
+ intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+ TRANS_CMRR_N_HI(display, cpu_transcoder));
crtc_state->cmrr.cmrr_m =
- intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
- TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
+ intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+ TRANS_CMRR_M_HI(display, cpu_transcoder));
}
- if (DISPLAY_VER(dev_priv) >= 13)
+ if (DISPLAY_VER(display) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
else
@@ -414,21 +409,21 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
- crtc_state->vrr.flipline = intel_de_read(dev_priv,
- TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
- crtc_state->vrr.vmax = intel_de_read(dev_priv,
- TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
- crtc_state->vrr.vmin = intel_de_read(dev_priv,
- TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1;
+ crtc_state->vrr.flipline = intel_de_read(display,
+ TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
+ crtc_state->vrr.vmax = intel_de_read(display,
+ TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
+ crtc_state->vrr.vmin = intel_de_read(display,
+ TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
}
if (crtc_state->vrr.enable) {
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- if (HAS_AS_SDP(dev_priv)) {
+ if (HAS_AS_SDP(display)) {
trans_vrr_vsync =
- intel_de_read(dev_priv,
- TRANS_VRR_VSYNC(dev_priv, cpu_transcoder));
+ intel_de_read(display,
+ TRANS_VRR_VSYNC(display, cpu_transcoder));
crtc_state->vrr.vsync_start =
REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
crtc_state->vrr.vsync_end =
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/7] drm/i915/tv: convert to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (3 preceding siblings ...)
2024-08-22 16:04 ` [PATCH 4/7] drm/i915/vrr: " Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:45 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 6/7] drm/i915/sprite: " Jani Nikula
` (5 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_tv.[ch] to struct intel_display.
Some stragglers are left behind where needed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 203 ++++++++++---------
drivers/gpu/drm/i915/display/intel_tv.h | 6 +-
3 files changed, 108 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1042f65967ba..9049b9a1209d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7935,7 +7935,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
g4x_dp_init(dev_priv, DP_D, PORT_D);
if (SUPPORTS_TV(dev_priv))
- intel_tv_init(dev_priv);
+ intel_tv_init(display);
} else if (DISPLAY_VER(dev_priv) == 2) {
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index bfc43bda8532..581844d1db9a 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -914,8 +914,8 @@ static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
static bool
intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 tmp = intel_de_read(dev_priv, TV_CTL);
+ struct intel_display *display = to_intel_display(encoder);
+ u32 tmp = intel_de_read(display, TV_CTL);
*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
@@ -928,13 +928,12 @@ intel_enable_tv(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(state);
/* Prevents vblank waits from timing out in intel_tv_detect_type() */
intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
- intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
+ intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);
}
static void
@@ -943,10 +942,9 @@ intel_disable_tv(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(state);
- intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
+ intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);
}
static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
@@ -960,9 +958,10 @@ static enum drm_mode_status
intel_tv_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *i915 = to_i915(connector->dev);
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
- int max_dotclk = i915->display.cdclk.max_dotclk_freq;
+ int max_dotclk = display->cdclk.max_dotclk_freq;
enum drm_mode_status status;
status = intel_cpu_transcoder_mode_valid(i915, mode);
@@ -1092,6 +1091,7 @@ static void
intel_tv_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -1104,11 +1104,11 @@ intel_tv_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
- tv_ctl = intel_de_read(dev_priv, TV_CTL);
- hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
- hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
- vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
- vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
+ tv_ctl = intel_de_read(display, TV_CTL);
+ hctl1 = intel_de_read(display, TV_H_CTL_1);
+ hctl3 = intel_de_read(display, TV_H_CTL_3);
+ vctl1 = intel_de_read(display, TV_V_CTL_1);
+ vctl2 = intel_de_read(display, TV_V_CTL_2);
tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
@@ -1143,17 +1143,17 @@ intel_tv_get_config(struct intel_encoder *encoder,
break;
}
- tmp = intel_de_read(dev_priv, TV_WIN_POS);
+ tmp = intel_de_read(display, TV_WIN_POS);
xpos = tmp >> 16;
ypos = tmp & 0xffff;
- tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
+ tmp = intel_de_read(display, TV_WIN_SIZE);
xsize = tmp >> 16;
ysize = tmp & 0xffff;
intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
- drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
+ drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(&mode));
intel_tv_scale_mode_horiz(&mode, hdisplay,
@@ -1171,10 +1171,10 @@ intel_tv_get_config(struct intel_encoder *encoder,
I915_MODE_FLAG_USE_SCANLINE_COUNTER;
}
-static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
+static bool intel_tv_source_too_wide(struct intel_display *display,
int hdisplay)
{
- return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
+ return DISPLAY_VER(display) == 3 && hdisplay > 1024;
}
static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
@@ -1192,6 +1192,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_atomic_state *state =
to_intel_atomic_state(pipe_config->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -1214,7 +1215,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
- drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
+ drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");
pipe_config->pipe_bpp = 8*3;
pipe_config->port_clock = tv_mode->clock;
@@ -1228,14 +1229,14 @@ intel_tv_compute_config(struct intel_encoder *encoder,
intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
drm_mode_set_crtcinfo(adjusted_mode, 0);
- if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
+ if (intel_tv_source_too_wide(display, hdisplay) ||
!intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
int extra, top, bottom;
extra = adjusted_mode->crtc_vdisplay - vdisplay;
if (extra < 0) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"No vertical scaling for >1024 pixel wide modes\n");
return -EINVAL;
}
@@ -1269,7 +1270,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
tv_conn_state->bypass_vfilter = false;
}
- drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
+ drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(adjusted_mode));
/*
@@ -1355,7 +1356,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
}
static void
-set_tv_mode_timings(struct drm_i915_private *dev_priv,
+set_tv_mode_timings(struct intel_display *display,
const struct tv_mode *tv_mode,
bool burst_ena)
{
@@ -1401,32 +1402,32 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
- intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
- intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
- intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
- intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
- intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
- intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
- intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
- intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
- intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
- intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
+ intel_de_write(display, TV_H_CTL_1, hctl1);
+ intel_de_write(display, TV_H_CTL_2, hctl2);
+ intel_de_write(display, TV_H_CTL_3, hctl3);
+ intel_de_write(display, TV_V_CTL_1, vctl1);
+ intel_de_write(display, TV_V_CTL_2, vctl2);
+ intel_de_write(display, TV_V_CTL_3, vctl3);
+ intel_de_write(display, TV_V_CTL_4, vctl4);
+ intel_de_write(display, TV_V_CTL_5, vctl5);
+ intel_de_write(display, TV_V_CTL_6, vctl6);
+ intel_de_write(display, TV_V_CTL_7, vctl7);
}
-static void set_color_conversion(struct drm_i915_private *dev_priv,
+static void set_color_conversion(struct intel_display *display,
const struct color_conversion *color_conversion)
{
- intel_de_write(dev_priv, TV_CSC_Y,
+ intel_de_write(display, TV_CSC_Y,
(color_conversion->ry << 16) | color_conversion->gy);
- intel_de_write(dev_priv, TV_CSC_Y2,
+ intel_de_write(display, TV_CSC_Y2,
(color_conversion->by << 16) | color_conversion->ay);
- intel_de_write(dev_priv, TV_CSC_U,
+ intel_de_write(display, TV_CSC_U,
(color_conversion->ru << 16) | color_conversion->gu);
- intel_de_write(dev_priv, TV_CSC_U2,
+ intel_de_write(display, TV_CSC_U2,
(color_conversion->bu << 16) | color_conversion->au);
- intel_de_write(dev_priv, TV_CSC_V,
+ intel_de_write(display, TV_CSC_V,
(color_conversion->rv << 16) | color_conversion->gv);
- intel_de_write(dev_priv, TV_CSC_V2,
+ intel_de_write(display, TV_CSC_V2,
(color_conversion->bv << 16) | color_conversion->av);
}
@@ -1435,6 +1436,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_tv *intel_tv = enc_to_tv(encoder);
@@ -1450,7 +1452,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
int xpos, ypos;
unsigned int xsize, ysize;
- tv_ctl = intel_de_read(dev_priv, TV_CTL);
+ tv_ctl = intel_de_read(display, TV_CTL);
tv_ctl &= TV_CTL_SAVE;
switch (intel_tv->type) {
@@ -1525,21 +1527,21 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
if (IS_I915GM(dev_priv))
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
- set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
+ set_tv_mode_timings(display, tv_mode, burst_ena);
- intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
- intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
- intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
+ intel_de_write(display, TV_SC_CTL_1, scctl1);
+ intel_de_write(display, TV_SC_CTL_2, scctl2);
+ intel_de_write(display, TV_SC_CTL_3, scctl3);
- set_color_conversion(dev_priv, color_conversion);
+ set_color_conversion(display, color_conversion);
- if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
+ if (DISPLAY_VER(display) >= 4)
+ intel_de_write(display, TV_CLR_KNOBS, 0x00404000);
else
- intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
+ intel_de_write(display, TV_CLR_KNOBS, 0x00606000);
if (video_levels)
- intel_de_write(dev_priv, TV_CLR_LEVEL,
+ intel_de_write(display, TV_CLR_LEVEL,
((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
@@ -1548,7 +1550,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
tv_filter_ctl = TV_AUTO_SCALE;
if (tv_conn_state->bypass_vfilter)
tv_filter_ctl |= TV_V_FILTER_BYPASS;
- intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
+ intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);
xsize = tv_mode->hblank_start - tv_mode->hblank_end;
ysize = intel_tv_mode_vdisplay(tv_mode);
@@ -1559,31 +1561,32 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
conn_state->tv.margins.right);
ysize -= (tv_conn_state->margins.top +
tv_conn_state->margins.bottom);
- intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
- intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
+ intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);
+ intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);
j = 0;
for (i = 0; i < 60; i++)
- intel_de_write(dev_priv, TV_H_LUMA(i),
+ intel_de_write(display, TV_H_LUMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 60; i++)
- intel_de_write(dev_priv, TV_H_CHROMA(i),
+ intel_de_write(display, TV_H_CHROMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
- intel_de_write(dev_priv, TV_V_LUMA(i),
+ intel_de_write(display, TV_V_LUMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
- intel_de_write(dev_priv, TV_V_CHROMA(i),
+ intel_de_write(display, TV_V_CHROMA(i),
tv_mode->filter_table[j++]);
- intel_de_write(dev_priv, TV_DAC,
- intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
- intel_de_write(dev_priv, TV_CTL, tv_ctl);
+ intel_de_write(display, TV_DAC,
+ intel_de_read(display, TV_DAC) & TV_DAC_SAVE);
+ intel_de_write(display, TV_CTL, tv_ctl);
}
static int
intel_tv_detect_type(struct intel_tv *intel_tv,
struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1600,8 +1603,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
spin_unlock_irq(&dev_priv->irq_lock);
}
- save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
- save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
+ save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
+ save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
/* Poll for TV detection */
tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
@@ -1627,15 +1630,15 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
- intel_de_write(dev_priv, TV_CTL, tv_ctl);
- intel_de_write(dev_priv, TV_DAC, tv_dac);
- intel_de_posting_read(dev_priv, TV_DAC);
+ intel_de_write(display, TV_CTL, tv_ctl);
+ intel_de_write(display, TV_DAC, tv_dac);
+ intel_de_posting_read(display, TV_DAC);
intel_crtc_wait_for_next_vblank(crtc);
type = -1;
- tv_dac = intel_de_read(dev_priv, TV_DAC);
- drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
+ tv_dac = intel_de_read(display, TV_DAC);
+ drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
/*
* A B C
* 0 1 1 Composite
@@ -1643,25 +1646,25 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
* 0 0 0 Component
*/
if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Detected Composite TV connection\n");
type = DRM_MODE_CONNECTOR_Composite;
} else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Detected S-Video TV connection\n");
type = DRM_MODE_CONNECTOR_SVIDEO;
} else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Detected Component TV connection\n");
type = DRM_MODE_CONNECTOR_Component;
} else {
- drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
+ drm_dbg_kms(display->drm, "Unrecognised TV connection\n");
type = -1;
}
- intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
- intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
- intel_de_posting_read(dev_priv, TV_CTL);
+ intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
+ intel_de_write(display, TV_CTL, save_tv_ctl);
+ intel_de_posting_read(display, TV_CTL);
/* For unknown reasons the hw barfs if we don't do this vblank wait. */
intel_crtc_wait_for_next_vblank(crtc);
@@ -1711,12 +1714,13 @@ intel_tv_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
bool force)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
enum drm_connector_status status;
int type;
- drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
+ drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
connector->base.id, connector->name, force);
if (!intel_display_device_enabled(i915))
@@ -1791,7 +1795,7 @@ intel_tv_set_mode_type(struct drm_display_mode *mode,
static int
intel_tv_get_modes(struct drm_connector *connector)
{
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
+ struct intel_display *display = to_intel_display(connector->dev);
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
int i, count = 0;
@@ -1805,7 +1809,7 @@ intel_tv_get_modes(struct drm_connector *connector)
continue;
/* no vertical scaling with wide sources on gen3 */
- if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
+ if (DISPLAY_VER(display) == 3 && input->w > 1024 &&
input->h > intel_tv_mode_vdisplay(tv_mode))
continue;
@@ -1822,7 +1826,8 @@ intel_tv_get_modes(struct drm_connector *connector)
*/
intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
if (count == 0) {
- drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
+ drm_dbg_kms(display->drm,
+ "TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(mode));
}
intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
@@ -1887,7 +1892,7 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs = {
static void intel_tv_add_properties(struct drm_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_connector_state *conn_state = connector->state;
const char *tv_format_names[ARRAY_SIZE(tv_modes)];
int i;
@@ -1903,45 +1908,44 @@ static void intel_tv_add_properties(struct drm_connector *connector)
/* Create TV properties then attach current values */
for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
/* 1080p50/1080p60 not supported on gen3 */
- if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1)
+ if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)
break;
tv_format_names[i] = tv_modes[i].name;
}
- drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names);
+ drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);
drm_object_attach_property(&connector->base,
- i915->drm.mode_config.legacy_tv_mode_property,
+ display->drm->mode_config.legacy_tv_mode_property,
conn_state->tv.legacy_mode);
drm_object_attach_property(&connector->base,
- i915->drm.mode_config.tv_left_margin_property,
+ display->drm->mode_config.tv_left_margin_property,
conn_state->tv.margins.left);
drm_object_attach_property(&connector->base,
- i915->drm.mode_config.tv_top_margin_property,
+ display->drm->mode_config.tv_top_margin_property,
conn_state->tv.margins.top);
drm_object_attach_property(&connector->base,
- i915->drm.mode_config.tv_right_margin_property,
+ display->drm->mode_config.tv_right_margin_property,
conn_state->tv.margins.right);
drm_object_attach_property(&connector->base,
- i915->drm.mode_config.tv_bottom_margin_property,
+ display->drm->mode_config.tv_bottom_margin_property,
conn_state->tv.margins.bottom);
}
void
-intel_tv_init(struct drm_i915_private *dev_priv)
+intel_tv_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
struct drm_connector *connector;
struct intel_tv *intel_tv;
struct intel_encoder *intel_encoder;
struct intel_connector *intel_connector;
u32 tv_dac_on, tv_dac_off, save_tv_dac;
- if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
+ if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
return;
if (!intel_bios_is_tv_present(display)) {
- drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
+ drm_dbg_kms(display->drm, "Integrated TV is not present.\n");
return;
}
@@ -1949,15 +1953,15 @@ intel_tv_init(struct drm_i915_private *dev_priv)
* Sanity check the TV output by checking to see if the
* DAC register holds a value
*/
- save_tv_dac = intel_de_read(dev_priv, TV_DAC);
+ save_tv_dac = intel_de_read(display, TV_DAC);
- intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
- tv_dac_on = intel_de_read(dev_priv, TV_DAC);
+ intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
+ tv_dac_on = intel_de_read(display, TV_DAC);
- intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
- tv_dac_off = intel_de_read(dev_priv, TV_DAC);
+ intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
+ tv_dac_off = intel_de_read(display, TV_DAC);
- intel_de_write(dev_priv, TV_DAC, save_tv_dac);
+ intel_de_write(display, TV_DAC, save_tv_dac);
/*
* If the register does not hold the state change enable
@@ -1995,10 +1999,11 @@ intel_tv_init(struct drm_i915_private *dev_priv)
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
intel_connector->base.polled = intel_connector->polled;
- drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
+ drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,
DRM_MODE_CONNECTOR_SVIDEO);
- drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs,
+ drm_encoder_init(display->drm, &intel_encoder->base,
+ &intel_tv_enc_funcs,
DRM_MODE_ENCODER_TVDAC, "TV");
intel_encoder->compute_config = intel_tv_compute_config;
diff --git a/drivers/gpu/drm/i915/display/intel_tv.h b/drivers/gpu/drm/i915/display/intel_tv.h
index f08827b8bf2b..0f280f69e73c 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.h
+++ b/drivers/gpu/drm/i915/display/intel_tv.h
@@ -6,12 +6,12 @@
#ifndef __INTEL_TV_H__
#define __INTEL_TV_H__
-struct drm_i915_private;
+struct intel_display;
#ifdef I915
-void intel_tv_init(struct drm_i915_private *dev_priv);
+void intel_tv_init(struct intel_display *display);
#else
-static inline void intel_tv_init(struct drm_i915_private *dev_priv)
+static inline void intel_tv_init(struct intel_display *display)
{
}
#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/7] drm/i915/sprite: convert to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (4 preceding siblings ...)
2024-08-22 16:04 ` [PATCH 5/7] drm/i915/tv: " Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:47 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 7/7] drm/i915/display: convert params " Jani Nikula
` (4 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_sprite.[ch] to struct intel_display.
Some stragglers are left behind where needed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 209 +++++++++++---------
1 file changed, 112 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f8cceb3e5d8e..e657b09ede99 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -48,9 +48,9 @@
#include "intel_sprite.h"
#include "intel_sprite_regs.h"
-static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
+static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)
{
- return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A';
+ return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';
}
static void i9xx_plane_linear_gamma(u16 gamma[8])
@@ -67,7 +67,7 @@ static void
chv_sprite_update_csc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
/*
@@ -100,35 +100,35 @@ chv_sprite_update_csc(const struct intel_plane_state *plane_state)
if (!fb->format->is_yuv)
return;
- intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id),
+ intel_de_write_fw(display, SPCSCYGOFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
- intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id),
+ intel_de_write_fw(display, SPCSCCBOFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
- intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id),
+ intel_de_write_fw(display, SPCSCCROFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
- intel_de_write_fw(dev_priv, SPCSCC01(plane_id),
+ intel_de_write_fw(display, SPCSCC01(plane_id),
SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
- intel_de_write_fw(dev_priv, SPCSCC23(plane_id),
+ intel_de_write_fw(display, SPCSCC23(plane_id),
SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
- intel_de_write_fw(dev_priv, SPCSCC45(plane_id),
+ intel_de_write_fw(display, SPCSCC45(plane_id),
SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
- intel_de_write_fw(dev_priv, SPCSCC67(plane_id),
+ intel_de_write_fw(display, SPCSCC67(plane_id),
SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
- intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
+ intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
- intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),
SPCSC_IMAX(1023) | SPCSC_IMIN(0));
- intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),
SPCSC_IMAX(512) | SPCSC_IMIN(-512));
- intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),
SPCSC_IMAX(512) | SPCSC_IMIN(-512));
- intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
- intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
- intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id),
+ intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
}
@@ -139,7 +139,7 @@ static void
vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@@ -168,9 +168,9 @@ vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
}
/* FIXME these register are single buffered :( */
- intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),
+ intel_de_write_fw(display, SPCLRC0(pipe, plane_id),
SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
- intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),
+ intel_de_write_fw(display, SPCLRC1(pipe, plane_id),
SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
}
@@ -357,7 +357,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@@ -373,7 +373,7 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
/* The two end points are implicit (0.0 and 1.0) */
for (i = 1; i < 8 - 1; i++)
- intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),
+ intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
@@ -382,7 +382,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
int crtc_x = plane_state->uapi.dst.x1;
@@ -390,11 +390,11 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
- intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
+ intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
+ intel_de_write_fw(display, SPPOS(pipe, plane_id),
SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
- intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
+ intel_de_write_fw(display, SPSIZE(pipe, plane_id),
SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
}
@@ -403,6 +403,7 @@ vlv_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@@ -420,18 +421,18 @@ vlv_sprite_update_arm(struct intel_plane *plane,
chv_sprite_update_csc(plane_state);
if (key->flags) {
- intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
+ intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),
key->min_value);
- intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),
+ intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),
key->channel_mask);
- intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),
+ intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),
key->max_value);
}
- intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
+ intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);
- intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
- intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
+ intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset);
+ intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),
SP_OFFSET_Y(y) | SP_OFFSET_X(x));
/*
@@ -439,8 +440,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
- intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);
- intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
+ intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);
+ intel_de_write_fw(display, SPSURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
vlv_sprite_update_clrc(plane_state);
@@ -451,18 +452,19 @@ static void
vlv_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
- intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
- intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
+ intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);
+ intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);
}
static bool
vlv_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
enum plane_id plane_id = plane->id;
@@ -474,7 +476,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
- ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
+ ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
*pipe = plane->pipe;
@@ -766,7 +768,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
u16 gamma[18];
int i;
@@ -778,17 +780,17 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
- intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),
+ intel_de_write_fw(display, SPRGAMC(pipe, i),
gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
- intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);
- intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);
- intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);
i++;
- intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);
- intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);
- intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);
+ intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);
i++;
}
@@ -797,6 +799,7 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
int crtc_x = plane_state->uapi.dst.x1;
@@ -812,14 +815,14 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
SPRITE_SRC_WIDTH(src_w - 1) |
SPRITE_SRC_HEIGHT(src_h - 1);
- intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
+ intel_de_write_fw(display, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, SPRPOS(pipe),
+ intel_de_write_fw(display, SPRPOS(pipe),
SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
- intel_de_write_fw(dev_priv, SPRSIZE(pipe),
+ intel_de_write_fw(display, SPRSIZE(pipe),
SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
- intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
+ intel_de_write_fw(display, SPRSCALE(pipe), sprscale);
}
static void
@@ -827,6 +830,7 @@ ivb_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -840,20 +844,20 @@ ivb_sprite_update_arm(struct intel_plane *plane,
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
- intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
- intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
+ intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);
+ intel_de_write_fw(display, SPRKEYMSK(pipe),
key->channel_mask);
- intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);
+ intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);
}
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, SPROFFSET(pipe),
+ intel_de_write_fw(display, SPROFFSET(pipe),
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
} else {
- intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
- intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
+ intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset);
+ intel_de_write_fw(display, SPRTILEOFF(pipe),
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
}
@@ -862,8 +866,8 @@ ivb_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
- intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);
- intel_de_write_fw(dev_priv, SPRSURF(pipe),
+ intel_de_write_fw(display, SPRCTL(pipe), sprctl);
+ intel_de_write_fw(display, SPRSURF(pipe),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
ivb_sprite_update_gamma(plane_state);
@@ -873,20 +877,22 @@ static void
ivb_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
+ intel_de_write_fw(display, SPRCTL(pipe), 0);
/* Disable the scaler */
if (IS_IVYBRIDGE(dev_priv))
- intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
- intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
+ intel_de_write_fw(display, SPRSCALE(pipe), 0);
+ intel_de_write_fw(display, SPRSURF(pipe), 0);
}
static bool
ivb_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@@ -897,7 +903,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
- ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
+ ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
*pipe = plane->pipe;
@@ -1073,7 +1079,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[8];
@@ -1088,7 +1094,7 @@ static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
/* The two end points are implicit (0.0 and 1.0) */
for (i = 1; i < 8 - 1; i++)
- intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),
+ intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
@@ -1103,7 +1109,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[17];
@@ -1117,12 +1123,12 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
- intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),
+ intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),
gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
- intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
- intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
- intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
+ intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
+ intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
+ intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
i++;
}
@@ -1131,7 +1137,7 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -1146,13 +1152,13 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
DVS_SRC_WIDTH(src_w - 1) |
DVS_SRC_HEIGHT(src_h - 1);
- intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
+ intel_de_write_fw(display, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, DVSPOS(pipe),
+ intel_de_write_fw(display, DVSPOS(pipe),
DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
- intel_de_write_fw(dev_priv, DVSSIZE(pipe),
+ intel_de_write_fw(display, DVSSIZE(pipe),
DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
- intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
+ intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);
}
static void
@@ -1160,6 +1166,7 @@ g4x_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -1173,14 +1180,14 @@ g4x_sprite_update_arm(struct intel_plane *plane,
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
- intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
- intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
+ intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);
+ intel_de_write_fw(display, DVSKEYMSK(pipe),
key->channel_mask);
- intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);
+ intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);
}
- intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);
- intel_de_write_fw(dev_priv, DVSTILEOFF(pipe),
+ intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset);
+ intel_de_write_fw(display, DVSTILEOFF(pipe),
DVS_OFFSET_Y(y) | DVS_OFFSET_X(x));
/*
@@ -1188,8 +1195,8 @@ g4x_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
- intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);
- intel_de_write_fw(dev_priv, DVSSURF(pipe),
+ intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);
+ intel_de_write_fw(display, DVSSURF(pipe),
intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
if (IS_G4X(dev_priv))
@@ -1202,19 +1209,20 @@ static void
g4x_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
- intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
+ intel_de_write_fw(display, DVSCNTR(pipe), 0);
/* Disable the scaler */
- intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
- intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
+ intel_de_write_fw(display, DVSSCALE(pipe), 0);
+ intel_de_write_fw(display, DVSSURF(pipe), 0);
}
static bool
g4x_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@@ -1225,7 +1233,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
- ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;
+ ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;
*pipe = plane->pipe;
@@ -1255,7 +1263,7 @@ static int
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ struct intel_display *display = to_intel_display(crtc_state);
const struct drm_framebuffer *fb = plane_state->hw.fb;
const struct drm_rect *src = &plane_state->uapi.src;
const struct drm_rect *dst = &plane_state->uapi.dst;
@@ -1281,7 +1289,8 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
if (src_h & 1) {
- drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n");
+ drm_dbg_kms(display->drm,
+ "Source height must be even with interlaced modes\n");
return -EINVAL;
}
min_height = 6;
@@ -1293,19 +1302,22 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
if (src_w < min_width || src_h < min_height ||
src_w > 2048 || src_h > 2048) {
- drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
+ drm_dbg_kms(display->drm,
+ "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
src_w, src_h, min_width, min_height, 2048, 2048);
return -EINVAL;
}
if (width_bytes > 4096) {
- drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
+ drm_dbg_kms(display->drm,
+ "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
width_bytes, 4096);
return -EINVAL;
}
if (stride > 4096) {
- drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n",
+ drm_dbg_kms(display->drm,
+ "Stride (%u) exceeds hardware max with scaling (%u)\n",
stride, 4096);
return -EINVAL;
}
@@ -1317,6 +1329,7 @@ static int
g4x_sprite_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
int min_scale = DRM_PLANE_NO_SCALING;
@@ -1324,7 +1337,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int ret;
if (g4x_fb_scalable(plane_state->hw.fb)) {
- if (DISPLAY_VER(dev_priv) < 7) {
+ if (DISPLAY_VER(display) < 7) {
min_scale = 1;
max_scale = 16 << 16;
} else if (IS_IVYBRIDGE(dev_priv)) {
@@ -1353,7 +1366,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (DISPLAY_VER(dev_priv) >= 7)
+ if (DISPLAY_VER(display) >= 7)
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
else
plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
@@ -1364,6 +1377,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
unsigned int rotation = plane_state->hw.rotation;
@@ -1371,7 +1385,7 @@ int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
if (IS_CHERRYVIEW(dev_priv) &&
rotation & DRM_MODE_ROTATE_180 &&
rotation & DRM_MODE_REFLECT_X) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Cannot rotate and reflect at the same time\n");
return -EINVAL;
}
@@ -1573,6 +1587,7 @@ struct intel_plane *
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int sprite)
{
+ struct intel_display *display = &dev_priv->display;
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
@@ -1604,7 +1619,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
}
plane_funcs = &vlv_sprite_funcs;
- } else if (DISPLAY_VER(dev_priv) >= 7) {
+ } else if (DISPLAY_VER(display) >= 7) {
plane->update_noarm = ivb_sprite_update_noarm;
plane->update_arm = ivb_sprite_update_arm;
plane->disable_arm = ivb_sprite_disable_arm;
@@ -1663,11 +1678,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
- ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
+ ret = drm_universal_plane_init(display->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
DRM_PLANE_TYPE_OVERLAY,
- "sprite %c", sprite_name(dev_priv, pipe, sprite));
+ "sprite %c", sprite_name(display, pipe, sprite));
kfree(modifiers);
if (ret)
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 7/7] drm/i915/display: convert params to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (5 preceding siblings ...)
2024-08-22 16:04 ` [PATCH 6/7] drm/i915/sprite: " Jani Nikula
@ 2024-08-22 16:04 ` Jani Nikula
2024-08-22 21:48 ` Rodrigo Vivi
2024-08-22 16:57 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversion " Patchwork
` (3 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Jani Nikula @ 2024-08-22 16:04 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Going forward, struct intel_display shall replace struct
drm_i915_private as the main display device data pointer type. Convert
intel_display_params.[ch] and intel_display_debugfs_params.[ch] to
struct intel_display.
Some stragglers are left behind where needed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
.../gpu/drm/i915/display/intel_display_debugfs_params.c | 8 ++++----
.../gpu/drm/i915/display/intel_display_debugfs_params.h | 4 ++--
drivers/gpu/drm/i915/display/intel_display_params.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_params.h | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
7 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0cf0b4223513..74f527647aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1073,7 +1073,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_opregion_debugfs_register(display);
intel_psr_debugfs_register(i915);
intel_wm_debugfs_register(i915);
- intel_display_debugfs_params(i915);
+ intel_display_debugfs_params(display);
}
static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
index f35718748555..ec3ed29a83c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
@@ -151,13 +151,13 @@ intel_display_debugfs_create_uint(const char *name, umode_t mode,
} while (0)
/* add a subdirectory with files for each intel display param */
-void intel_display_debugfs_params(struct drm_i915_private *i915)
+void intel_display_debugfs_params(struct intel_display *display)
{
- struct drm_minor *minor = i915->drm.primary;
+ struct drm_minor *minor = display->drm->primary;
struct dentry *dir;
char dirname[16];
- snprintf(dirname, sizeof(dirname), "%s_params", i915->drm.driver->name);
+ snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
dir = debugfs_lookup(dirname, minor->debugfs_root);
if (!dir)
dir = debugfs_create_dir(dirname, minor->debugfs_root);
@@ -171,7 +171,7 @@ void intel_display_debugfs_params(struct drm_i915_private *i915)
*/
#define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
- dir, #x, mode, &i915->display.params.x);
+ dir, #x, mode, &display->params.x);
INTEL_DISPLAY_PARAMS_FOR_EACH(REGISTER);
#undef REGISTER
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
index 1e9945a4044c..a1120915a5a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
@@ -6,8 +6,8 @@
#ifndef __INTEL_DISPLAY_DEBUGFS_PARAMS__
#define __INTEL_DISPLAY_DEBUGFS_PARAMS__
-struct drm_i915_private;
+struct intel_display;
-void intel_display_debugfs_params(struct drm_i915_private *i915);
+void intel_display_debugfs_params(struct intel_display *display);
#endif /* __INTEL_DISPLAY_DEBUGFS_PARAMS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index e82bd72d32fa..1a45d300b6f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -173,14 +173,14 @@ static void _param_print_charp(struct drm_printer *p, const char *driver_name,
/**
* intel_display_params_dump - dump intel display modparams
- * @i915: i915 device
+ * @display: display device
* @p: the &drm_printer
*
* Pretty printer for i915 modparams.
*/
-void intel_display_params_dump(struct drm_i915_private *i915, struct drm_printer *p)
+void intel_display_params_dump(struct intel_display *display, struct drm_printer *p)
{
-#define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, i915->display.params.x);
+#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT);
#undef PRINT
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 48c29c55c939..da8dc943234b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -9,7 +9,7 @@
#include <linux/types.h>
struct drm_printer;
-struct drm_i915_private;
+struct intel_display;
/*
* Invoke param, a function-like macro, for each intel display param, with
@@ -56,7 +56,7 @@ struct intel_display_params {
};
#undef MEMBER
-void intel_display_params_dump(struct drm_i915_private *i915,
+void intel_display_params_dump(struct intel_display *display,
struct drm_printer *p);
void intel_display_params_copy(struct intel_display_params *dest);
void intel_display_params_free(struct intel_display_params *params);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index bc717cf544e4..f969f585d07b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -66,6 +66,7 @@ static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_display *display = &i915->display;
struct drm_printer p = drm_seq_file_printer(m);
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
@@ -77,7 +78,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
kernel_param_lock(THIS_MODULE);
i915_params_dump(&i915->params, &p);
- intel_display_params_dump(i915, &p);
+ intel_display_params_dump(display, &p);
kernel_param_unlock(THIS_MODULE);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 96c6cafd5b9e..6469b9bcf2ec 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -660,9 +660,10 @@ static void err_print_params(struct drm_i915_error_state_buf *m,
const struct i915_params *params)
{
struct drm_printer p = i915_error_printer(m);
+ struct intel_display *display = &m->i915->display;
i915_params_dump(params, &p);
- intel_display_params_dump(m->i915, &p);
+ intel_display_params_dump(display, &p);
}
static void err_print_pciid(struct drm_i915_error_state_buf *m,
--
2.39.2
^ permalink raw reply related [flat|nested] 21+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversion to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (6 preceding siblings ...)
2024-08-22 16:04 ` [PATCH 7/7] drm/i915/display: convert params " Jani Nikula
@ 2024-08-22 16:57 ` Patchwork
2024-08-22 16:57 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2024-08-22 16:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversion to struct intel_display
URL : https://patchwork.freedesktop.org/series/137654/
State : warning
== Summary ==
Error: dim checkpatch failed
5c377f41e3c5 drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding
551a14b57e74 drm/i915/vblank: fix context imbalance warnings
68e26512b854 drm/i915/vblank: convert to struct intel_display
-:204: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#204: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:398:
+ position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
total: 0 errors, 1 warnings, 0 checks, 291 lines checked
0e8ad0b68116 drm/i915/vrr: convert to struct intel_display
-:296: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#296: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:413:
+ TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
total: 0 errors, 1 warnings, 0 checks, 289 lines checked
c12e472714ef drm/i915/tv: convert to struct intel_display
-:349: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#349: FILE: drivers/gpu/drm/i915/display/intel_tv.c:1606:
+ save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
-:350: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#350: FILE: drivers/gpu/drm/i915/display/intel_tv.c:1607:
+ save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
total: 0 errors, 0 warnings, 2 checks, 514 lines checked
e3c3b270b9d7 drm/i915/sprite: convert to struct intel_display
e5bcbe1e7d62 drm/i915/display: convert params to struct intel_display
-:91: WARNING:MACRO_ARG_UNUSED: Argument 'T' is not used in function-like macro
#91: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:183:
+#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
-:91: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#91: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:183:
+#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
total: 0 errors, 2 warnings, 0 checks, 101 lines checked
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915/display: conversion to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (7 preceding siblings ...)
2024-08-22 16:57 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversion " Patchwork
@ 2024-08-22 16:57 ` Patchwork
2024-08-22 17:14 ` ✓ Fi.CI.BAT: success " Patchwork
2024-08-23 8:41 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2024-08-22 16:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: conversion to struct intel_display
URL : https://patchwork.freedesktop.org/series/137654/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/display: conversion to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (8 preceding siblings ...)
2024-08-22 16:57 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-08-22 17:14 ` Patchwork
2024-08-23 8:41 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2024-08-22 17:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3877 bytes --]
== Series Details ==
Series: drm/i915/display: conversion to struct intel_display
URL : https://patchwork.freedesktop.org/series/137654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15280 -> Patchwork_137654v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (2): fi-kbl-8809g fi-bsw-n3050
Missing (3): fi-glk-j4005 fi-snb-2520m fi-elk-e7500
Known issues
------------
Here are the changes found in Patchwork_137654v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/fi-kbl-8809g/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][3] +19 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] +30 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/fi-kbl-8809g/igt@kms_force_connector_basic@force-load-detect.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-arls-2: [DMESG-WARN][5] ([i915#11349]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/bat-arls-2/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/bat-arls-2/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
[i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
[i915#11346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11346
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#11666]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11666
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11723
[i915#11724]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11724
[i915#11725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11725
[i915#11726]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11726
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_15280 -> Patchwork_137654v1
CI-20190529: 20190529
CI_DRM_15280: 882c26c7017bdcc4eca493c7bf1ffb034d40be02 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7983: b2e17acf37471073210221724a66d164328dee98 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_137654v1: 882c26c7017bdcc4eca493c7bf1ffb034d40be02 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/index.html
[-- Attachment #2: Type: text/html, Size: 3670 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding
2024-08-22 16:04 ` [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding Jani Nikula
@ 2024-08-22 21:37 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:49PM +0300, Jani Nikula wrote:
> There's a helper for drm->vblank[drm_crtc_index(crtc)], use it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index f183e0d4b2ba..551e9ca9bb99 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -68,7 +68,7 @@
> u32 i915_get_vblank_counter(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> const struct drm_display_mode *mode = &vblank->hwmode;
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> u32 pixel, vbl_start, hsync_start, htotal;
> @@ -120,7 +120,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
> u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> if (!vblank->max_vblank_count)
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings
2024-08-22 16:04 ` [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings Jani Nikula
@ 2024-08-22 21:38 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:50PM +0300, Jani Nikula wrote:
> When building for xe, we get the context imbalance warning as the actual
> locking/unlocking is not compiled:
>
> ../drivers/gpu/drm/i915/display/intel_vblank.c:306:13: warning: context imbalance in 'intel_vblank_section_enter' - wrong count at exit
> ../drivers/gpu/drm/i915/display/intel_vblank.c:314:13: warning: context imbalance in 'intel_vblank_section_exit' - wrong count at exit
>
> Fix by adding separata stubs for xe without __acquires/__releases
> annotation.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 551e9ca9bb99..2073e8075af4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -303,21 +303,27 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
> * all register accesses to the same cacheline to be serialized,
> * otherwise they may hang.
> */
> +#ifdef I915
> static void intel_vblank_section_enter(struct drm_i915_private *i915)
> __acquires(i915->uncore.lock)
> {
> -#ifdef I915
> spin_lock(&i915->uncore.lock);
> -#endif
> }
>
> static void intel_vblank_section_exit(struct drm_i915_private *i915)
> __releases(i915->uncore.lock)
> {
> -#ifdef I915
> spin_unlock(&i915->uncore.lock);
> -#endif
> }
> +#else
> +static void intel_vblank_section_enter(struct drm_i915_private *i915)
> +{
> +}
> +
> +static void intel_vblank_section_exit(struct drm_i915_private *i915)
> +{
> +}
> +#endif
>
> static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
> bool in_vblank_irq,
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 3/7] drm/i915/vblank: convert to struct intel_display
2024-08-22 16:04 ` [PATCH 3/7] drm/i915/vblank: convert to struct intel_display Jani Nikula
@ 2024-08-22 21:42 ` Rodrigo Vivi
2024-08-23 10:07 ` Jani Nikula
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:51PM +0300, Jani Nikula wrote:
> Going forward, struct intel_display shall replace struct
> drm_i915_private as the main display device data pointer type. Convert
> intel_vblank.[ch] to struct intel_display.
>
> Some stragglers are left behind where needed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 97 +++++++++++----------
> 1 file changed, 50 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 2073e8075af4..838b55ecb1d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -67,7 +67,7 @@
> */
> u32 i915_get_vblank_counter(struct drm_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> const struct drm_display_mode *mode = &vblank->hwmode;
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
> @@ -103,8 +103,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
> * we get a low value that's stable across two reads of the high
> * register.
> */
> - frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
> - PIPEFRAME(dev_priv, pipe));
> + frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
> + PIPEFRAME(display, pipe));
>
> pixel = frame & PIPE_PIXEL_MASK;
> frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
> @@ -119,19 +119,19 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>
> u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_display *display = to_intel_display(crtc->dev);
> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> if (!vblank->max_vblank_count)
> return 0;
>
> - return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
> + return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
> }
>
> static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
> const struct drm_display_mode *mode = &vblank->hwmode;
> u32 htotal = mode->crtc_htotal;
> @@ -150,16 +150,16 @@ static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> * pipe frame time stamp. The time stamp value
> * is sampled at every start of vertical blank.
> */
> - scan_prev_time = intel_de_read_fw(dev_priv,
> + scan_prev_time = intel_de_read_fw(display,
> PIPE_FRMTMSTMP(crtc->pipe));
>
> /*
> * The TIMESTAMP_CTR register has the current
> * time stamp value.
> */
> - scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
> + scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
>
> - scan_post_time = intel_de_read_fw(dev_priv,
> + scan_post_time = intel_de_read_fw(display,
> PIPE_FRMTMSTMP(crtc->pipe));
> } while (scan_post_time != scan_prev_time);
>
> @@ -192,6 +192,7 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
>
> static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> @@ -220,7 +221,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
> * However if queried just before the start of vblank we'll get an
> * answer that's slightly in the future.
> */
> - if (DISPLAY_VER(i915) == 2)
> + if (DISPLAY_VER(display) == 2)
> return -1;
> else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> return 2;
> @@ -234,8 +235,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
> */
> static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(crtc);
> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
> const struct drm_display_mode *mode = &vblank->hwmode;
> enum pipe pipe = crtc->pipe;
> @@ -249,7 +249,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>
> vtotal = intel_mode_vtotal(mode);
>
> - position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
> + position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
>
> /*
> * On HSW, the DSL reg (0x70000) appears to return 0 if we
> @@ -263,13 +263,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> * problem. We may need to extend this to include other platforms,
> * but so far testing only shows the problem on HSW.
> */
> - if (HAS_DDI(dev_priv) && !position) {
> + if (HAS_DDI(display) && !position) {
> int i, temp;
>
> for (i = 0; i < 100; i++) {
> udelay(1);
> - temp = intel_de_read_fw(dev_priv,
> - PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
> + temp = intel_de_read_fw(display,
> + PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
> if (temp != position) {
> position = temp;
> break;
> @@ -304,23 +304,25 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
> * otherwise they may hang.
> */
> #ifdef I915
> -static void intel_vblank_section_enter(struct drm_i915_private *i915)
> +static void intel_vblank_section_enter(struct intel_display *display)
> __acquires(i915->uncore.lock)
I'm surprised this works!
thought we would need to have something like
__acquires(to_i915(display->drm)->uncore.lock)
but anyway, if it works let's move on
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> spin_lock(&i915->uncore.lock);
> }
>
> -static void intel_vblank_section_exit(struct drm_i915_private *i915)
> +static void intel_vblank_section_exit(struct intel_display *display)
> __releases(i915->uncore.lock)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> spin_unlock(&i915->uncore.lock);
> }
> #else
> -static void intel_vblank_section_enter(struct drm_i915_private *i915)
> +static void intel_vblank_section_enter(struct intel_display *display)
> {
> }
>
> -static void intel_vblank_section_exit(struct drm_i915_private *i915)
> +static void intel_vblank_section_exit(struct intel_display *display)
> {
> }
> #endif
> @@ -331,19 +333,19 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
> ktime_t *stime, ktime_t *etime,
> const struct drm_display_mode *mode)
> {
> - struct drm_device *dev = _crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(_crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct intel_crtc *crtc = to_intel_crtc(_crtc);
> enum pipe pipe = crtc->pipe;
> int position;
> int vbl_start, vbl_end, hsync_start, htotal, vtotal;
> unsigned long irqflags;
> - bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
> - IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
> + bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
> + IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 ||
> crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
>
> - if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
> - drm_dbg(&dev_priv->drm,
> + if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
> + drm_dbg(display->drm,
> "trying to get scanoutpos for disabled pipe %c\n",
> pipe_name(pipe));
> return false;
> @@ -361,7 +363,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
> * preemption disabled, so the following code must not block.
> */
> local_irq_save(irqflags);
> - intel_vblank_section_enter(dev_priv);
> + intel_vblank_section_enter(display);
>
> /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
>
> @@ -393,7 +395,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
> * We can split this into vertical and horizontal
> * scanout position.
> */
> - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
> + position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>
> /* convert to pixel counts */
> vbl_start *= htotal;
> @@ -429,7 +431,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>
> /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
>
> - intel_vblank_section_exit(dev_priv);
> + intel_vblank_section_exit(display);
> local_irq_restore(irqflags);
>
> /*
> @@ -464,42 +466,42 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
>
> int intel_get_crtc_scanline(struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> unsigned long irqflags;
> int position;
>
> local_irq_save(irqflags);
> - intel_vblank_section_enter(dev_priv);
> + intel_vblank_section_enter(display);
>
> position = __intel_get_crtc_scanline(crtc);
>
> - intel_vblank_section_exit(dev_priv);
> + intel_vblank_section_exit(display);
> local_irq_restore(irqflags);
>
> return position;
> }
>
> -static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
> +static bool pipe_scanline_is_moving(struct intel_display *display,
> enum pipe pipe)
> {
> - i915_reg_t reg = PIPEDSL(dev_priv, pipe);
> + i915_reg_t reg = PIPEDSL(display, pipe);
> u32 line1, line2;
>
> - line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
> + line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
> msleep(5);
> - line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
> + line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
>
> return line1 != line2;
> }
>
> static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> enum pipe pipe = crtc->pipe;
>
> /* Wait for the display line to settle/start moving */
> - if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
> - drm_err(&dev_priv->drm,
> + if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
> + drm_err(display->drm,
> "pipe %c scanline %s wait timed out\n",
> pipe_name(pipe), str_on_off(state));
> }
> @@ -517,8 +519,8 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
> void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> bool vrr_enable)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> u8 mode_flags = crtc_state->mode_flags;
> struct drm_display_mode adjusted_mode;
> int vmax_vblank_start = 0;
> @@ -527,7 +529,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
>
> if (vrr_enable) {
> - drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
> + drm_WARN_ON(display->drm,
> + (mode_flags & I915_MODE_FLAG_VRR) == 0);
>
> adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
> adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
> @@ -549,8 +552,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> * __intel_get_crtc_scanline()) with vblank_time_lock?
> * Need to audit everything to make sure it's safe.
> */
> - spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
> - intel_vblank_section_enter(i915);
> + spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
> + intel_vblank_section_enter(display);
>
> drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
>
> @@ -559,8 +562,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> crtc->mode_flags = mode_flags;
>
> crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
> - intel_vblank_section_exit(i915);
> - spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
> + intel_vblank_section_exit(display);
> + spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
> }
>
> int intel_mode_vdisplay(const struct drm_display_mode *mode)
> @@ -666,7 +669,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
> int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
> {
> struct intel_crtc *crtc = evade->crtc;
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> long timeout = msecs_to_jiffies_timeout(1);
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> DEFINE_WAIT(wait);
> @@ -688,7 +691,7 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
> break;
>
> if (!timeout) {
> - drm_err(&i915->drm,
> + drm_err(display->drm,
> "Potential atomic update failure on pipe %c\n",
> pipe_name(crtc->pipe));
> break;
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/7] drm/i915/vrr: convert to struct intel_display
2024-08-22 16:04 ` [PATCH 4/7] drm/i915/vrr: " Jani Nikula
@ 2024-08-22 21:44 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:44 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:52PM +0300, Jani Nikula wrote:
> Going forward, struct intel_display shall replace struct
> drm_i915_private as the main display device data pointer type. Convert
> intel_vrr.[ch] to struct intel_display.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 127 +++++++++++------------
> 1 file changed, 61 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 7e1d9c718214..9a51f5bac307 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -17,8 +17,8 @@
>
> bool intel_vrr_is_capable(struct intel_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector);
> const struct drm_display_info *info = &connector->base.display_info;
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_dp *intel_dp;
>
> /*
> @@ -43,7 +43,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
> return false;
> }
>
> - return HAS_VRR(i915) &&
> + return HAS_VRR(display) &&
> info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> }
>
> @@ -89,10 +89,9 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
> */
> static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(display) >= 13)
> return crtc_state->vrr.guardband;
> else
> /* The hw imposes the extra scanline before frame start */
> @@ -113,11 +112,11 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
> static bool
> is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> - if (!HAS_CMRR(i915))
> + if (!HAS_CMRR(display))
> return false;
>
> actual_refresh_k =
> @@ -161,8 +160,7 @@ void
> intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> @@ -186,7 +184,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (!crtc_state->vrr.in_range)
> return;
>
> - if (HAS_LRR(i915))
> + if (HAS_LRR(display))
> crtc_state->update_lrr = true;
>
> vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
> @@ -246,7 +244,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> * For XE_LPD+, we use guardband and pipeline override
> * is deprecated.
> */
> - if (DISPLAY_VER(i915) >= 13) {
> + if (DISPLAY_VER(display) >= 13) {
> crtc_state->vrr.guardband =
> crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
> } else {
> @@ -258,9 +256,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>
> static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
>
> - if (DISPLAY_VER(i915) >= 13)
> + if (DISPLAY_VER(display) >= 13)
> return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
> XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
> else
> @@ -271,7 +269,7 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
>
> void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -279,133 +277,130 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> * TGL: generate VRR "safe window" for DSB vblank waits
> * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
> */
> - if (IS_DISPLAY_VER(dev_priv, 12, 13))
> - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
> + if (IS_DISPLAY_VER(display, 12, 13))
> + intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder),
> 0, PIPE_VBLANK_WITH_DELAY);
>
> if (!crtc_state->vrr.flipline) {
> - intel_de_write(dev_priv,
> - TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
> + intel_de_write(display,
> + TRANS_VRR_CTL(display, cpu_transcoder), 0);
> return;
> }
>
> if (crtc_state->cmrr.enable) {
> - intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
> upper_32_bits(crtc_state->cmrr.cmrr_m));
> - intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> lower_32_bits(crtc_state->cmrr.cmrr_m));
> - intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
> upper_32_bits(crtc_state->cmrr.cmrr_n));
> - intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> lower_32_bits(crtc_state->cmrr.cmrr_n));
> }
>
> - intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> crtc_state->vrr.vmin - 1);
> - intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> crtc_state->vrr.vmax - 1);
> - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> trans_vrr_ctl(crtc_state));
> - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> crtc_state->vrr.flipline - 1);
> }
>
> void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (!crtc_state->vrr.enable)
> return;
>
> - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> TRANS_PUSH_EN | TRANS_PUSH_SEND);
> }
>
> bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (!crtc_state->vrr.enable)
> return false;
>
> - return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND;
> + return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
> }
>
> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (!crtc_state->vrr.enable)
> return;
>
> - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> TRANS_PUSH_EN);
>
> - if (HAS_AS_SDP(dev_priv))
> - intel_de_write(dev_priv,
> - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
> + if (HAS_AS_SDP(display))
> + intel_de_write(display,
> + TRANS_VRR_VSYNC(display, cpu_transcoder),
> VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> VRR_VSYNC_START(crtc_state->vrr.vsync_start));
>
> if (crtc_state->cmrr.enable) {
> - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
> trans_vrr_ctl(crtc_state));
> } else {
> - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> }
> }
>
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(old_crtc_state);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> if (!old_crtc_state->vrr.enable)
> return;
>
> - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> trans_vrr_ctl(old_crtc_state));
> - intel_de_wait_for_clear(dev_priv,
> - TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
> + intel_de_wait_for_clear(display,
> + TRANS_VRR_STATUS(display, cpu_transcoder),
> VRR_STATUS_VRR_EN_LIVE, 1000);
> - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0);
> + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
>
> - if (HAS_AS_SDP(dev_priv))
> - intel_de_write(dev_priv,
> - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);
> + if (HAS_AS_SDP(display))
> + intel_de_write(display,
> + TRANS_VRR_VSYNC(display, cpu_transcoder), 0);
> }
>
> void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 trans_vrr_ctl, trans_vrr_vsync;
>
> - trans_vrr_ctl = intel_de_read(dev_priv,
> - TRANS_VRR_CTL(dev_priv, cpu_transcoder));
> + trans_vrr_ctl = intel_de_read(display,
> + TRANS_VRR_CTL(display, cpu_transcoder));
>
> crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
> - if (HAS_CMRR(dev_priv))
> + if (HAS_CMRR(display))
> crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
>
> if (crtc_state->cmrr.enable) {
> crtc_state->cmrr.cmrr_n =
> - intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
> - TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
> + intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
> + TRANS_CMRR_N_HI(display, cpu_transcoder));
> crtc_state->cmrr.cmrr_m =
> - intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
> - TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
> + intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
> + TRANS_CMRR_M_HI(display, cpu_transcoder));
> }
>
> - if (DISPLAY_VER(dev_priv) >= 13)
> + if (DISPLAY_VER(display) >= 13)
> crtc_state->vrr.guardband =
> REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> else
> @@ -414,21 +409,21 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
>
> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> - crtc_state->vrr.flipline = intel_de_read(dev_priv,
> - TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
> - crtc_state->vrr.vmax = intel_de_read(dev_priv,
> - TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
> - crtc_state->vrr.vmin = intel_de_read(dev_priv,
> - TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1;
> + crtc_state->vrr.flipline = intel_de_read(display,
> + TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
> + crtc_state->vrr.vmax = intel_de_read(display,
> + TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
> + crtc_state->vrr.vmin = intel_de_read(display,
> + TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
> }
>
> if (crtc_state->vrr.enable) {
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>
> - if (HAS_AS_SDP(dev_priv)) {
> + if (HAS_AS_SDP(display)) {
> trans_vrr_vsync =
> - intel_de_read(dev_priv,
> - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder));
> + intel_de_read(display,
> + TRANS_VRR_VSYNC(display, cpu_transcoder));
> crtc_state->vrr.vsync_start =
> REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
> crtc_state->vrr.vsync_end =
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/7] drm/i915/tv: convert to struct intel_display
2024-08-22 16:04 ` [PATCH 5/7] drm/i915/tv: " Jani Nikula
@ 2024-08-22 21:45 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:45 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:53PM +0300, Jani Nikula wrote:
> Going forward, struct intel_display shall replace struct
> drm_i915_private as the main display device data pointer type. Convert
> intel_tv.[ch] to struct intel_display.
>
> Some stragglers are left behind where needed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 203 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_tv.h | 6 +-
> 3 files changed, 108 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1042f65967ba..9049b9a1209d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7935,7 +7935,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> g4x_dp_init(dev_priv, DP_D, PORT_D);
>
> if (SUPPORTS_TV(dev_priv))
> - intel_tv_init(dev_priv);
> + intel_tv_init(display);
> } else if (DISPLAY_VER(dev_priv) == 2) {
> if (IS_I85X(dev_priv))
> intel_lvds_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index bfc43bda8532..581844d1db9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -914,8 +914,8 @@ static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
> static bool
> intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - u32 tmp = intel_de_read(dev_priv, TV_CTL);
> + struct intel_display *display = to_intel_display(encoder);
> + u32 tmp = intel_de_read(display, TV_CTL);
>
> *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
>
> @@ -928,13 +928,12 @@ intel_enable_tv(struct intel_atomic_state *state,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(state);
>
> /* Prevents vblank waits from timing out in intel_tv_detect_type() */
> intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
>
> - intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
> + intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);
> }
>
> static void
> @@ -943,10 +942,9 @@ intel_disable_tv(struct intel_atomic_state *state,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state *old_conn_state)
> {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(state);
>
> - intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
> + intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);
> }
>
> static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
> @@ -960,9 +958,10 @@ static enum drm_mode_status
> intel_tv_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_i915_private *i915 = to_i915(connector->dev);
> const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
> - int max_dotclk = i915->display.cdclk.max_dotclk_freq;
> + int max_dotclk = display->cdclk.max_dotclk_freq;
> enum drm_mode_status status;
>
> status = intel_cpu_transcoder_mode_valid(i915, mode);
> @@ -1092,6 +1091,7 @@ static void
> intel_tv_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> @@ -1104,11 +1104,11 @@ intel_tv_get_config(struct intel_encoder *encoder,
>
> pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
>
> - tv_ctl = intel_de_read(dev_priv, TV_CTL);
> - hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
> - hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
> - vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
> - vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
> + tv_ctl = intel_de_read(display, TV_CTL);
> + hctl1 = intel_de_read(display, TV_H_CTL_1);
> + hctl3 = intel_de_read(display, TV_H_CTL_3);
> + vctl1 = intel_de_read(display, TV_V_CTL_1);
> + vctl2 = intel_de_read(display, TV_V_CTL_2);
>
> tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
> tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
> @@ -1143,17 +1143,17 @@ intel_tv_get_config(struct intel_encoder *encoder,
> break;
> }
>
> - tmp = intel_de_read(dev_priv, TV_WIN_POS);
> + tmp = intel_de_read(display, TV_WIN_POS);
> xpos = tmp >> 16;
> ypos = tmp & 0xffff;
>
> - tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
> + tmp = intel_de_read(display, TV_WIN_SIZE);
> xsize = tmp >> 16;
> ysize = tmp & 0xffff;
>
> intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
>
> - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
> + drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
> DRM_MODE_ARG(&mode));
>
> intel_tv_scale_mode_horiz(&mode, hdisplay,
> @@ -1171,10 +1171,10 @@ intel_tv_get_config(struct intel_encoder *encoder,
> I915_MODE_FLAG_USE_SCANLINE_COUNTER;
> }
>
> -static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
> +static bool intel_tv_source_too_wide(struct intel_display *display,
> int hdisplay)
> {
> - return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
> + return DISPLAY_VER(display) == 3 && hdisplay > 1024;
> }
>
> static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
> @@ -1192,6 +1192,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_atomic_state *state =
> to_intel_atomic_state(pipe_config->uapi.state);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -1214,7 +1215,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> - drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
> + drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");
> pipe_config->pipe_bpp = 8*3;
>
> pipe_config->port_clock = tv_mode->clock;
> @@ -1228,14 +1229,14 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
> drm_mode_set_crtcinfo(adjusted_mode, 0);
>
> - if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
> + if (intel_tv_source_too_wide(display, hdisplay) ||
> !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
> int extra, top, bottom;
>
> extra = adjusted_mode->crtc_vdisplay - vdisplay;
>
> if (extra < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "No vertical scaling for >1024 pixel wide modes\n");
> return -EINVAL;
> }
> @@ -1269,7 +1270,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> tv_conn_state->bypass_vfilter = false;
> }
>
> - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
> + drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
> DRM_MODE_ARG(adjusted_mode));
>
> /*
> @@ -1355,7 +1356,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> }
>
> static void
> -set_tv_mode_timings(struct drm_i915_private *dev_priv,
> +set_tv_mode_timings(struct intel_display *display,
> const struct tv_mode *tv_mode,
> bool burst_ena)
> {
> @@ -1401,32 +1402,32 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
> vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
> (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
>
> - intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
> - intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
> - intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
> - intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
> - intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
> - intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
> - intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
> - intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
> - intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
> - intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
> + intel_de_write(display, TV_H_CTL_1, hctl1);
> + intel_de_write(display, TV_H_CTL_2, hctl2);
> + intel_de_write(display, TV_H_CTL_3, hctl3);
> + intel_de_write(display, TV_V_CTL_1, vctl1);
> + intel_de_write(display, TV_V_CTL_2, vctl2);
> + intel_de_write(display, TV_V_CTL_3, vctl3);
> + intel_de_write(display, TV_V_CTL_4, vctl4);
> + intel_de_write(display, TV_V_CTL_5, vctl5);
> + intel_de_write(display, TV_V_CTL_6, vctl6);
> + intel_de_write(display, TV_V_CTL_7, vctl7);
> }
>
> -static void set_color_conversion(struct drm_i915_private *dev_priv,
> +static void set_color_conversion(struct intel_display *display,
> const struct color_conversion *color_conversion)
> {
> - intel_de_write(dev_priv, TV_CSC_Y,
> + intel_de_write(display, TV_CSC_Y,
> (color_conversion->ry << 16) | color_conversion->gy);
> - intel_de_write(dev_priv, TV_CSC_Y2,
> + intel_de_write(display, TV_CSC_Y2,
> (color_conversion->by << 16) | color_conversion->ay);
> - intel_de_write(dev_priv, TV_CSC_U,
> + intel_de_write(display, TV_CSC_U,
> (color_conversion->ru << 16) | color_conversion->gu);
> - intel_de_write(dev_priv, TV_CSC_U2,
> + intel_de_write(display, TV_CSC_U2,
> (color_conversion->bu << 16) | color_conversion->au);
> - intel_de_write(dev_priv, TV_CSC_V,
> + intel_de_write(display, TV_CSC_V,
> (color_conversion->rv << 16) | color_conversion->gv);
> - intel_de_write(dev_priv, TV_CSC_V2,
> + intel_de_write(display, TV_CSC_V2,
> (color_conversion->bv << 16) | color_conversion->av);
> }
>
> @@ -1435,6 +1436,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_tv *intel_tv = enc_to_tv(encoder);
> @@ -1450,7 +1452,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
> int xpos, ypos;
> unsigned int xsize, ysize;
>
> - tv_ctl = intel_de_read(dev_priv, TV_CTL);
> + tv_ctl = intel_de_read(display, TV_CTL);
> tv_ctl &= TV_CTL_SAVE;
>
> switch (intel_tv->type) {
> @@ -1525,21 +1527,21 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
> if (IS_I915GM(dev_priv))
> tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
>
> - set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
> + set_tv_mode_timings(display, tv_mode, burst_ena);
>
> - intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
> - intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
> - intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
> + intel_de_write(display, TV_SC_CTL_1, scctl1);
> + intel_de_write(display, TV_SC_CTL_2, scctl2);
> + intel_de_write(display, TV_SC_CTL_3, scctl3);
>
> - set_color_conversion(dev_priv, color_conversion);
> + set_color_conversion(display, color_conversion);
>
> - if (DISPLAY_VER(dev_priv) >= 4)
> - intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
> + if (DISPLAY_VER(display) >= 4)
> + intel_de_write(display, TV_CLR_KNOBS, 0x00404000);
> else
> - intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
> + intel_de_write(display, TV_CLR_KNOBS, 0x00606000);
>
> if (video_levels)
> - intel_de_write(dev_priv, TV_CLR_LEVEL,
> + intel_de_write(display, TV_CLR_LEVEL,
> ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
>
> assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
> @@ -1548,7 +1550,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
> tv_filter_ctl = TV_AUTO_SCALE;
> if (tv_conn_state->bypass_vfilter)
> tv_filter_ctl |= TV_V_FILTER_BYPASS;
> - intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
> + intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);
>
> xsize = tv_mode->hblank_start - tv_mode->hblank_end;
> ysize = intel_tv_mode_vdisplay(tv_mode);
> @@ -1559,31 +1561,32 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
> conn_state->tv.margins.right);
> ysize -= (tv_conn_state->margins.top +
> tv_conn_state->margins.bottom);
> - intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
> - intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
> + intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);
> + intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);
>
> j = 0;
> for (i = 0; i < 60; i++)
> - intel_de_write(dev_priv, TV_H_LUMA(i),
> + intel_de_write(display, TV_H_LUMA(i),
> tv_mode->filter_table[j++]);
> for (i = 0; i < 60; i++)
> - intel_de_write(dev_priv, TV_H_CHROMA(i),
> + intel_de_write(display, TV_H_CHROMA(i),
> tv_mode->filter_table[j++]);
> for (i = 0; i < 43; i++)
> - intel_de_write(dev_priv, TV_V_LUMA(i),
> + intel_de_write(display, TV_V_LUMA(i),
> tv_mode->filter_table[j++]);
> for (i = 0; i < 43; i++)
> - intel_de_write(dev_priv, TV_V_CHROMA(i),
> + intel_de_write(display, TV_V_CHROMA(i),
> tv_mode->filter_table[j++]);
> - intel_de_write(dev_priv, TV_DAC,
> - intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
> - intel_de_write(dev_priv, TV_CTL, tv_ctl);
> + intel_de_write(display, TV_DAC,
> + intel_de_read(display, TV_DAC) & TV_DAC_SAVE);
> + intel_de_write(display, TV_CTL, tv_ctl);
> }
>
> static int
> intel_tv_detect_type(struct intel_tv *intel_tv,
> struct drm_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -1600,8 +1603,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> - save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
> - save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
> + save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
> + save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
>
> /* Poll for TV detection */
> tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
> @@ -1627,15 +1630,15 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
> TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
>
> - intel_de_write(dev_priv, TV_CTL, tv_ctl);
> - intel_de_write(dev_priv, TV_DAC, tv_dac);
> - intel_de_posting_read(dev_priv, TV_DAC);
> + intel_de_write(display, TV_CTL, tv_ctl);
> + intel_de_write(display, TV_DAC, tv_dac);
> + intel_de_posting_read(display, TV_DAC);
>
> intel_crtc_wait_for_next_vblank(crtc);
>
> type = -1;
> - tv_dac = intel_de_read(dev_priv, TV_DAC);
> - drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
> + tv_dac = intel_de_read(display, TV_DAC);
> + drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
> /*
> * A B C
> * 0 1 1 Composite
> @@ -1643,25 +1646,25 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> * 0 0 0 Component
> */
> if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Detected Composite TV connection\n");
> type = DRM_MODE_CONNECTOR_Composite;
> } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Detected S-Video TV connection\n");
> type = DRM_MODE_CONNECTOR_SVIDEO;
> } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Detected Component TV connection\n");
> type = DRM_MODE_CONNECTOR_Component;
> } else {
> - drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
> + drm_dbg_kms(display->drm, "Unrecognised TV connection\n");
> type = -1;
> }
>
> - intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
> - intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
> - intel_de_posting_read(dev_priv, TV_CTL);
> + intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
> + intel_de_write(display, TV_CTL, save_tv_ctl);
> + intel_de_posting_read(display, TV_CTL);
>
> /* For unknown reasons the hw barfs if we don't do this vblank wait. */
> intel_crtc_wait_for_next_vblank(crtc);
> @@ -1711,12 +1714,13 @@ intel_tv_detect(struct drm_connector *connector,
> struct drm_modeset_acquire_ctx *ctx,
> bool force)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_i915_private *i915 = to_i915(connector->dev);
> struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
> enum drm_connector_status status;
> int type;
>
> - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
> + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
> connector->base.id, connector->name, force);
>
> if (!intel_display_device_enabled(i915))
> @@ -1791,7 +1795,7 @@ intel_tv_set_mode_type(struct drm_display_mode *mode,
> static int
> intel_tv_get_modes(struct drm_connector *connector)
> {
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
> int i, count = 0;
>
> @@ -1805,7 +1809,7 @@ intel_tv_get_modes(struct drm_connector *connector)
> continue;
>
> /* no vertical scaling with wide sources on gen3 */
> - if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
> + if (DISPLAY_VER(display) == 3 && input->w > 1024 &&
> input->h > intel_tv_mode_vdisplay(tv_mode))
> continue;
>
> @@ -1822,7 +1826,8 @@ intel_tv_get_modes(struct drm_connector *connector)
> */
> intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
> if (count == 0) {
> - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
> + drm_dbg_kms(display->drm,
> + "TV mode: " DRM_MODE_FMT "\n",
> DRM_MODE_ARG(mode));
> }
> intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
> @@ -1887,7 +1892,7 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs = {
>
> static void intel_tv_add_properties(struct drm_connector *connector)
> {
> - struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_connector_state *conn_state = connector->state;
> const char *tv_format_names[ARRAY_SIZE(tv_modes)];
> int i;
> @@ -1903,45 +1908,44 @@ static void intel_tv_add_properties(struct drm_connector *connector)
> /* Create TV properties then attach current values */
> for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
> /* 1080p50/1080p60 not supported on gen3 */
> - if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1)
> + if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)
> break;
>
> tv_format_names[i] = tv_modes[i].name;
> }
> - drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names);
> + drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);
>
> drm_object_attach_property(&connector->base,
> - i915->drm.mode_config.legacy_tv_mode_property,
> + display->drm->mode_config.legacy_tv_mode_property,
> conn_state->tv.legacy_mode);
> drm_object_attach_property(&connector->base,
> - i915->drm.mode_config.tv_left_margin_property,
> + display->drm->mode_config.tv_left_margin_property,
> conn_state->tv.margins.left);
> drm_object_attach_property(&connector->base,
> - i915->drm.mode_config.tv_top_margin_property,
> + display->drm->mode_config.tv_top_margin_property,
> conn_state->tv.margins.top);
> drm_object_attach_property(&connector->base,
> - i915->drm.mode_config.tv_right_margin_property,
> + display->drm->mode_config.tv_right_margin_property,
> conn_state->tv.margins.right);
> drm_object_attach_property(&connector->base,
> - i915->drm.mode_config.tv_bottom_margin_property,
> + display->drm->mode_config.tv_bottom_margin_property,
> conn_state->tv.margins.bottom);
> }
>
> void
> -intel_tv_init(struct drm_i915_private *dev_priv)
> +intel_tv_init(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> struct drm_connector *connector;
> struct intel_tv *intel_tv;
> struct intel_encoder *intel_encoder;
> struct intel_connector *intel_connector;
> u32 tv_dac_on, tv_dac_off, save_tv_dac;
>
> - if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
> + if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
> return;
>
> if (!intel_bios_is_tv_present(display)) {
> - drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
> + drm_dbg_kms(display->drm, "Integrated TV is not present.\n");
> return;
> }
>
> @@ -1949,15 +1953,15 @@ intel_tv_init(struct drm_i915_private *dev_priv)
> * Sanity check the TV output by checking to see if the
> * DAC register holds a value
> */
> - save_tv_dac = intel_de_read(dev_priv, TV_DAC);
> + save_tv_dac = intel_de_read(display, TV_DAC);
>
> - intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
> - tv_dac_on = intel_de_read(dev_priv, TV_DAC);
> + intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
> + tv_dac_on = intel_de_read(display, TV_DAC);
>
> - intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
> - tv_dac_off = intel_de_read(dev_priv, TV_DAC);
> + intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
> + tv_dac_off = intel_de_read(display, TV_DAC);
>
> - intel_de_write(dev_priv, TV_DAC, save_tv_dac);
> + intel_de_write(display, TV_DAC, save_tv_dac);
>
> /*
> * If the register does not hold the state change enable
> @@ -1995,10 +1999,11 @@ intel_tv_init(struct drm_i915_private *dev_priv)
> intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
> intel_connector->base.polled = intel_connector->polled;
>
> - drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
> + drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,
> DRM_MODE_CONNECTOR_SVIDEO);
>
> - drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs,
> + drm_encoder_init(display->drm, &intel_encoder->base,
> + &intel_tv_enc_funcs,
> DRM_MODE_ENCODER_TVDAC, "TV");
>
> intel_encoder->compute_config = intel_tv_compute_config;
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.h b/drivers/gpu/drm/i915/display/intel_tv.h
> index f08827b8bf2b..0f280f69e73c 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.h
> +++ b/drivers/gpu/drm/i915/display/intel_tv.h
> @@ -6,12 +6,12 @@
> #ifndef __INTEL_TV_H__
> #define __INTEL_TV_H__
>
> -struct drm_i915_private;
> +struct intel_display;
>
> #ifdef I915
> -void intel_tv_init(struct drm_i915_private *dev_priv);
> +void intel_tv_init(struct intel_display *display);
> #else
> -static inline void intel_tv_init(struct drm_i915_private *dev_priv)
> +static inline void intel_tv_init(struct intel_display *display)
> {
> }
> #endif
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 6/7] drm/i915/sprite: convert to struct intel_display
2024-08-22 16:04 ` [PATCH 6/7] drm/i915/sprite: " Jani Nikula
@ 2024-08-22 21:47 ` Rodrigo Vivi
0 siblings, 0 replies; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:47 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:54PM +0300, Jani Nikula wrote:
> Going forward, struct intel_display shall replace struct
> drm_i915_private as the main display device data pointer type. Convert
> intel_sprite.[ch] to struct intel_display.
>
> Some stragglers are left behind where needed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 209 +++++++++++---------
> 1 file changed, 112 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f8cceb3e5d8e..e657b09ede99 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -48,9 +48,9 @@
> #include "intel_sprite.h"
> #include "intel_sprite_regs.h"
>
> -static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
> +static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)
> {
> - return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A';
> + return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';
> }
>
> static void i9xx_plane_linear_gamma(u16 gamma[8])
> @@ -67,7 +67,7 @@ static void
> chv_sprite_update_csc(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> enum plane_id plane_id = plane->id;
> /*
> @@ -100,35 +100,35 @@ chv_sprite_update_csc(const struct intel_plane_state *plane_state)
> if (!fb->format->is_yuv)
> return;
>
> - intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id),
> + intel_de_write_fw(display, SPCSCYGOFF(plane_id),
> SPCSC_OOFF(0) | SPCSC_IOFF(0));
> - intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id),
> + intel_de_write_fw(display, SPCSCCBOFF(plane_id),
> SPCSC_OOFF(0) | SPCSC_IOFF(0));
> - intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id),
> + intel_de_write_fw(display, SPCSCCROFF(plane_id),
> SPCSC_OOFF(0) | SPCSC_IOFF(0));
>
> - intel_de_write_fw(dev_priv, SPCSCC01(plane_id),
> + intel_de_write_fw(display, SPCSCC01(plane_id),
> SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
> - intel_de_write_fw(dev_priv, SPCSCC23(plane_id),
> + intel_de_write_fw(display, SPCSCC23(plane_id),
> SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
> - intel_de_write_fw(dev_priv, SPCSCC45(plane_id),
> + intel_de_write_fw(display, SPCSCC45(plane_id),
> SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
> - intel_de_write_fw(dev_priv, SPCSCC67(plane_id),
> + intel_de_write_fw(display, SPCSCC67(plane_id),
> SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
> - intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
> + intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
>
> - intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),
> SPCSC_IMAX(1023) | SPCSC_IMIN(0));
> - intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),
> SPCSC_IMAX(512) | SPCSC_IMIN(-512));
> - intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),
> SPCSC_IMAX(512) | SPCSC_IMIN(-512));
>
> - intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),
> SPCSC_OMAX(1023) | SPCSC_OMIN(0));
> - intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),
> SPCSC_OMAX(1023) | SPCSC_OMIN(0));
> - intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id),
> + intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),
> SPCSC_OMAX(1023) | SPCSC_OMIN(0));
> }
>
> @@ -139,7 +139,7 @@ static void
> vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> @@ -168,9 +168,9 @@ vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
> }
>
> /* FIXME these register are single buffered :( */
> - intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),
> + intel_de_write_fw(display, SPCLRC0(pipe, plane_id),
> SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
> - intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),
> + intel_de_write_fw(display, SPCLRC1(pipe, plane_id),
> SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
> }
>
> @@ -357,7 +357,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
> static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> @@ -373,7 +373,7 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
> /* FIXME these register are single buffered :( */
> /* The two end points are implicit (0.0 and 1.0) */
> for (i = 1; i < 8 - 1; i++)
> - intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),
> + intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),
> gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
> }
>
> @@ -382,7 +382,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> int crtc_x = plane_state->uapi.dst.x1;
> @@ -390,11 +390,11 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
> u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
>
> - intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> + intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> + intel_de_write_fw(display, SPPOS(pipe, plane_id),
> SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
> - intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> + intel_de_write_fw(display, SPSIZE(pipe, plane_id),
> SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
> }
>
> @@ -403,6 +403,7 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> @@ -420,18 +421,18 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> chv_sprite_update_csc(plane_state);
>
> if (key->flags) {
> - intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
> + intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),
> key->min_value);
> - intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),
> + intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),
> key->channel_mask);
> - intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),
> + intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),
> key->max_value);
> }
>
> - intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
> + intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);
>
> - intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
> - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
> + intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset);
> + intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),
> SP_OFFSET_Y(y) | SP_OFFSET_X(x));
>
> /*
> @@ -439,8 +440,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
> * disabled. Try to make the plane enable atomic by writing
> * the control register just before the surface register.
> */
> - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);
> - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
> + intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);
> + intel_de_write_fw(display, SPSURF(pipe, plane_id),
> intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
>
> vlv_sprite_update_clrc(plane_state);
> @@ -451,18 +452,19 @@ static void
> vlv_sprite_disable_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
>
> - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
> - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
> + intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);
> + intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);
> }
>
> static bool
> vlv_sprite_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> enum plane_id plane_id = plane->id;
> @@ -474,7 +476,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane,
> if (!wakeref)
> return false;
>
> - ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
> + ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
>
> *pipe = plane->pipe;
>
> @@ -766,7 +768,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
> static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> enum pipe pipe = plane->pipe;
> u16 gamma[18];
> int i;
> @@ -778,17 +780,17 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
>
> /* FIXME these register are single buffered :( */
> for (i = 0; i < 16; i++)
> - intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),
> + intel_de_write_fw(display, SPRGAMC(pipe, i),
> gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
>
> - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);
> - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);
> - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);
> i++;
>
> - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);
> - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);
> - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);
> + intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);
> i++;
> }
>
> @@ -797,6 +799,7 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> int crtc_x = plane_state->uapi.dst.x1;
> @@ -812,14 +815,14 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> SPRITE_SRC_WIDTH(src_w - 1) |
> SPRITE_SRC_HEIGHT(src_h - 1);
>
> - intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> + intel_de_write_fw(display, SPRSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, SPRPOS(pipe),
> + intel_de_write_fw(display, SPRPOS(pipe),
> SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
> - intel_de_write_fw(dev_priv, SPRSIZE(pipe),
> + intel_de_write_fw(display, SPRSIZE(pipe),
> SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
> if (IS_IVYBRIDGE(dev_priv))
> - intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
> + intel_de_write_fw(display, SPRSCALE(pipe), sprscale);
> }
>
> static void
> @@ -827,6 +830,7 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> @@ -840,20 +844,20 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (key->flags) {
> - intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
> - intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
> + intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);
> + intel_de_write_fw(display, SPRKEYMSK(pipe),
> key->channel_mask);
> - intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);
> + intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);
> }
>
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> * register */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - intel_de_write_fw(dev_priv, SPROFFSET(pipe),
> + intel_de_write_fw(display, SPROFFSET(pipe),
> SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> } else {
> - intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
> - intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
> + intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset);
> + intel_de_write_fw(display, SPRTILEOFF(pipe),
> SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
> }
>
> @@ -862,8 +866,8 @@ ivb_sprite_update_arm(struct intel_plane *plane,
> * disabled. Try to make the plane enable atomic by writing
> * the control register just before the surface register.
> */
> - intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);
> - intel_de_write_fw(dev_priv, SPRSURF(pipe),
> + intel_de_write_fw(display, SPRCTL(pipe), sprctl);
> + intel_de_write_fw(display, SPRSURF(pipe),
> intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
>
> ivb_sprite_update_gamma(plane_state);
> @@ -873,20 +877,22 @@ static void
> ivb_sprite_disable_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> - intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
> + intel_de_write_fw(display, SPRCTL(pipe), 0);
> /* Disable the scaler */
> if (IS_IVYBRIDGE(dev_priv))
> - intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
> - intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
> + intel_de_write_fw(display, SPRSCALE(pipe), 0);
> + intel_de_write_fw(display, SPRSURF(pipe), 0);
> }
>
> static bool
> ivb_sprite_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> @@ -897,7 +903,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane,
> if (!wakeref)
> return false;
>
> - ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
> + ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
>
> *pipe = plane->pipe;
>
> @@ -1073,7 +1079,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> enum pipe pipe = plane->pipe;
> u16 gamma[8];
> @@ -1088,7 +1094,7 @@ static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
> /* FIXME these register are single buffered :( */
> /* The two end points are implicit (0.0 and 1.0) */
> for (i = 1; i < 8 - 1; i++)
> - intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),
> + intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),
> gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
> }
>
> @@ -1103,7 +1109,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
> static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> enum pipe pipe = plane->pipe;
> u16 gamma[17];
> @@ -1117,12 +1123,12 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
>
> /* FIXME these register are single buffered :( */
> for (i = 0; i < 16; i++)
> - intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),
> + intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),
> gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
>
> - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
> - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
> - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
> + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
> + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
> + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
> i++;
> }
>
> @@ -1131,7 +1137,7 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> enum pipe pipe = plane->pipe;
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> @@ -1146,13 +1152,13 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> DVS_SRC_WIDTH(src_w - 1) |
> DVS_SRC_HEIGHT(src_h - 1);
>
> - intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> + intel_de_write_fw(display, DVSSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> - intel_de_write_fw(dev_priv, DVSPOS(pipe),
> + intel_de_write_fw(display, DVSPOS(pipe),
> DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
> - intel_de_write_fw(dev_priv, DVSSIZE(pipe),
> + intel_de_write_fw(display, DVSSIZE(pipe),
> DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
> - intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
> + intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);
> }
>
> static void
> @@ -1160,6 +1166,7 @@ g4x_sprite_update_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> @@ -1173,14 +1180,14 @@ g4x_sprite_update_arm(struct intel_plane *plane,
> linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (key->flags) {
> - intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
> - intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
> + intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);
> + intel_de_write_fw(display, DVSKEYMSK(pipe),
> key->channel_mask);
> - intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);
> + intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);
> }
>
> - intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);
> - intel_de_write_fw(dev_priv, DVSTILEOFF(pipe),
> + intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset);
> + intel_de_write_fw(display, DVSTILEOFF(pipe),
> DVS_OFFSET_Y(y) | DVS_OFFSET_X(x));
>
> /*
> @@ -1188,8 +1195,8 @@ g4x_sprite_update_arm(struct intel_plane *plane,
> * disabled. Try to make the plane enable atomic by writing
> * the control register just before the surface register.
> */
> - intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);
> - intel_de_write_fw(dev_priv, DVSSURF(pipe),
> + intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);
> + intel_de_write_fw(display, DVSSURF(pipe),
> intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
>
> if (IS_G4X(dev_priv))
> @@ -1202,19 +1209,20 @@ static void
> g4x_sprite_disable_arm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> enum pipe pipe = plane->pipe;
>
> - intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
> + intel_de_write_fw(display, DVSCNTR(pipe), 0);
> /* Disable the scaler */
> - intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
> - intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
> + intel_de_write_fw(display, DVSSCALE(pipe), 0);
> + intel_de_write_fw(display, DVSSURF(pipe), 0);
> }
>
> static bool
> g4x_sprite_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum intel_display_power_domain power_domain;
> intel_wakeref_t wakeref;
> @@ -1225,7 +1233,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane,
> if (!wakeref)
> return false;
>
> - ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;
> + ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;
>
> *pipe = plane->pipe;
>
> @@ -1255,7 +1263,7 @@ static int
> g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> const struct drm_rect *src = &plane_state->uapi.src;
> const struct drm_rect *dst = &plane_state->uapi.dst;
> @@ -1281,7 +1289,8 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> if (src_h & 1) {
> - drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n");
> + drm_dbg_kms(display->drm,
> + "Source height must be even with interlaced modes\n");
> return -EINVAL;
> }
> min_height = 6;
> @@ -1293,19 +1302,22 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
>
> if (src_w < min_width || src_h < min_height ||
> src_w > 2048 || src_h > 2048) {
> - drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
> + drm_dbg_kms(display->drm,
> + "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
> src_w, src_h, min_width, min_height, 2048, 2048);
> return -EINVAL;
> }
>
> if (width_bytes > 4096) {
> - drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
> + drm_dbg_kms(display->drm,
> + "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
> width_bytes, 4096);
> return -EINVAL;
> }
>
> if (stride > 4096) {
> - drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n",
> + drm_dbg_kms(display->drm,
> + "Stride (%u) exceeds hardware max with scaling (%u)\n",
> stride, 4096);
> return -EINVAL;
> }
> @@ -1317,6 +1329,7 @@ static int
> g4x_sprite_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> int min_scale = DRM_PLANE_NO_SCALING;
> @@ -1324,7 +1337,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> int ret;
>
> if (g4x_fb_scalable(plane_state->hw.fb)) {
> - if (DISPLAY_VER(dev_priv) < 7) {
> + if (DISPLAY_VER(display) < 7) {
> min_scale = 1;
> max_scale = 16 << 16;
> } else if (IS_IVYBRIDGE(dev_priv)) {
> @@ -1353,7 +1366,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - if (DISPLAY_VER(dev_priv) >= 7)
> + if (DISPLAY_VER(display) >= 7)
> plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
> else
> plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
> @@ -1364,6 +1377,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> + struct intel_display *display = to_intel_display(plane->base.dev);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> unsigned int rotation = plane_state->hw.rotation;
>
> @@ -1371,7 +1385,7 @@ int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
> if (IS_CHERRYVIEW(dev_priv) &&
> rotation & DRM_MODE_ROTATE_180 &&
> rotation & DRM_MODE_REFLECT_X) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Cannot rotate and reflect at the same time\n");
> return -EINVAL;
> }
> @@ -1573,6 +1587,7 @@ struct intel_plane *
> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, int sprite)
> {
> + struct intel_display *display = &dev_priv->display;
> struct intel_plane *plane;
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> @@ -1604,7 +1619,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> }
>
> plane_funcs = &vlv_sprite_funcs;
> - } else if (DISPLAY_VER(dev_priv) >= 7) {
> + } else if (DISPLAY_VER(display) >= 7) {
> plane->update_noarm = ivb_sprite_update_noarm;
> plane->update_arm = ivb_sprite_update_arm;
> plane->disable_arm = ivb_sprite_disable_arm;
> @@ -1663,11 +1678,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
>
> - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> + ret = drm_universal_plane_init(display->drm, &plane->base,
> 0, plane_funcs,
> formats, num_formats, modifiers,
> DRM_PLANE_TYPE_OVERLAY,
> - "sprite %c", sprite_name(dev_priv, pipe, sprite));
> + "sprite %c", sprite_name(display, pipe, sprite));
> kfree(modifiers);
>
> if (ret)
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 7/7] drm/i915/display: convert params to struct intel_display
2024-08-22 16:04 ` [PATCH 7/7] drm/i915/display: convert params " Jani Nikula
@ 2024-08-22 21:48 ` Rodrigo Vivi
2024-08-23 10:08 ` Jani Nikula
0 siblings, 1 reply; 21+ messages in thread
From: Rodrigo Vivi @ 2024-08-22 21:48 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Thu, Aug 22, 2024 at 07:04:55PM +0300, Jani Nikula wrote:
> Going forward, struct intel_display shall replace struct
> drm_i915_private as the main display device data pointer type. Convert
> intel_display_params.[ch] and intel_display_debugfs_params.[ch] to
> struct intel_display.
>
> Some stragglers are left behind where needed.
^ just noticed the extra tab on this, but
likely present in the other commit messages where you had
left some cases behind...
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> .../gpu/drm/i915/display/intel_display_debugfs_params.c | 8 ++++----
> .../gpu/drm/i915/display/intel_display_debugfs_params.h | 4 ++--
> drivers/gpu/drm/i915/display/intel_display_params.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_display_params.h | 4 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
> drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
> 7 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 0cf0b4223513..74f527647aa9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1073,7 +1073,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> intel_opregion_debugfs_register(display);
> intel_psr_debugfs_register(i915);
> intel_wm_debugfs_register(i915);
> - intel_display_debugfs_params(i915);
> + intel_display_debugfs_params(display);
> }
>
> static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
> index f35718748555..ec3ed29a83c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
> @@ -151,13 +151,13 @@ intel_display_debugfs_create_uint(const char *name, umode_t mode,
> } while (0)
>
> /* add a subdirectory with files for each intel display param */
> -void intel_display_debugfs_params(struct drm_i915_private *i915)
> +void intel_display_debugfs_params(struct intel_display *display)
> {
> - struct drm_minor *minor = i915->drm.primary;
> + struct drm_minor *minor = display->drm->primary;
> struct dentry *dir;
> char dirname[16];
>
> - snprintf(dirname, sizeof(dirname), "%s_params", i915->drm.driver->name);
> + snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
> dir = debugfs_lookup(dirname, minor->debugfs_root);
> if (!dir)
> dir = debugfs_create_dir(dirname, minor->debugfs_root);
> @@ -171,7 +171,7 @@ void intel_display_debugfs_params(struct drm_i915_private *i915)
> */
>
> #define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
> - dir, #x, mode, &i915->display.params.x);
> + dir, #x, mode, &display->params.x);
> INTEL_DISPLAY_PARAMS_FOR_EACH(REGISTER);
> #undef REGISTER
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
> index 1e9945a4044c..a1120915a5a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
> @@ -6,8 +6,8 @@
> #ifndef __INTEL_DISPLAY_DEBUGFS_PARAMS__
> #define __INTEL_DISPLAY_DEBUGFS_PARAMS__
>
> -struct drm_i915_private;
> +struct intel_display;
>
> -void intel_display_debugfs_params(struct drm_i915_private *i915);
> +void intel_display_debugfs_params(struct intel_display *display);
>
> #endif /* __INTEL_DISPLAY_DEBUGFS_PARAMS__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index e82bd72d32fa..1a45d300b6f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -173,14 +173,14 @@ static void _param_print_charp(struct drm_printer *p, const char *driver_name,
>
> /**
> * intel_display_params_dump - dump intel display modparams
> - * @i915: i915 device
> + * @display: display device
> * @p: the &drm_printer
> *
> * Pretty printer for i915 modparams.
> */
> -void intel_display_params_dump(struct drm_i915_private *i915, struct drm_printer *p)
> +void intel_display_params_dump(struct intel_display *display, struct drm_printer *p)
> {
> -#define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, i915->display.params.x);
> +#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
> INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT);
> #undef PRINT
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 48c29c55c939..da8dc943234b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -9,7 +9,7 @@
> #include <linux/types.h>
>
> struct drm_printer;
> -struct drm_i915_private;
> +struct intel_display;
>
> /*
> * Invoke param, a function-like macro, for each intel display param, with
> @@ -56,7 +56,7 @@ struct intel_display_params {
> };
> #undef MEMBER
>
> -void intel_display_params_dump(struct drm_i915_private *i915,
> +void intel_display_params_dump(struct intel_display *display,
> struct drm_printer *p);
> void intel_display_params_copy(struct intel_display_params *dest);
> void intel_display_params_free(struct intel_display_params *params);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index bc717cf544e4..f969f585d07b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -66,6 +66,7 @@ static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
> static int i915_capabilities(struct seq_file *m, void *data)
> {
> struct drm_i915_private *i915 = node_to_i915(m->private);
> + struct intel_display *display = &i915->display;
> struct drm_printer p = drm_seq_file_printer(m);
>
> seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
> @@ -77,7 +78,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
>
> kernel_param_lock(THIS_MODULE);
> i915_params_dump(&i915->params, &p);
> - intel_display_params_dump(i915, &p);
> + intel_display_params_dump(display, &p);
> kernel_param_unlock(THIS_MODULE);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 96c6cafd5b9e..6469b9bcf2ec 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -660,9 +660,10 @@ static void err_print_params(struct drm_i915_error_state_buf *m,
> const struct i915_params *params)
> {
> struct drm_printer p = i915_error_printer(m);
> + struct intel_display *display = &m->i915->display;
>
> i915_params_dump(params, &p);
> - intel_display_params_dump(m->i915, &p);
> + intel_display_params_dump(display, &p);
> }
>
> static void err_print_pciid(struct drm_i915_error_state_buf *m,
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/display: conversion to struct intel_display
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
` (9 preceding siblings ...)
2024-08-22 17:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-08-23 8:41 ` Patchwork
10 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2024-08-23 8:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 69796 bytes --]
== Series Details ==
Series: drm/i915/display: conversion to struct intel_display
URL : https://patchwork.freedesktop.org/series/137654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15280_full -> Patchwork_137654v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_137654v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][1] ([i915#6230])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@api_intel_bb@crc32.html
* igt@drm_fdinfo@busy-idle-check-all@vcs1:
- shard-dg1: NOTRUN -> [SKIP][2] ([i915#8414]) +14 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@drm_fdinfo@busy-idle-check-all@vcs1.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-tglu: NOTRUN -> [SKIP][4] ([i915#3555] / [i915#9323])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#6335])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][6] ([i915#8562])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@hang:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8555])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@hostile:
- shard-tglu: [PASS][8] -> [FAIL][9] ([i915#11980])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-5/igt@gem_ctx_persistence@hostile.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-6/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#280])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][11] ([i915#7975] / [i915#8213])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg1: NOTRUN -> [FAIL][12] ([i915#5784])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#4771])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#4812]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#4525])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-dg2: [PASS][16] -> [TIMEOUT][17] ([i915#3778] / [i915#7016])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-1/igt@gem_exec_endless@dispatch@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-10/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglu: [PASS][18] -> [TIMEOUT][19] ([i915#3778])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-8/igt@gem_exec_endless@dispatch@vcs1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-7/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][20] -> [FAIL][21] ([i915#2846])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852]) +4 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][23] ([i915#2842]) +1 other test fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][24] -> [FAIL][25] ([i915#2842])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-rkl: NOTRUN -> [FAIL][26] ([i915#2842]) +1 other test fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fence@concurrent:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#4812])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#3539] / [i915#4852]) +3 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#3539])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3281]) +4 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3281]) +9 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#3281]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4537] / [i915#4812])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4860]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#4613] / [i915#7582])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglu: NOTRUN -> [SKIP][36] ([i915#4613])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][37] ([i915#4613]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk6/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_madvise@dontneed-before-exec:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#3282])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@gem_madvise@dontneed-before-exec.html
* igt@gem_mmap@bad-offset:
- shard-dg1: NOTRUN -> [SKIP][39] ([i915#4083]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@gem_mmap@bad-offset.html
* igt@gem_mmap_gtt@basic-read:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4077]) +7 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_mmap_gtt@basic-read.html
* igt@gem_mmap_gtt@coherency:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4077]) +6 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_mmap_gtt@coherency.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4077])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_mmap_offset@clear@smem0:
- shard-mtlp: [PASS][43] -> [ABORT][44] ([i915#10029] / [i915#10729])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-mtlp-7/igt@gem_mmap_offset@clear@smem0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-7/igt@gem_mmap_offset@clear@smem0.html
* igt@gem_mmap_wc@bad-offset:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#4083]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@gem_mmap_wc@bad-offset.html
* igt@gem_mmap_wc@invalid-flags:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4083]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_mmap_wc@invalid-flags.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#3282]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@exhaustion:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#3282]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#3282]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#4270])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4270]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#8428])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#5190] / [i915#8428]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs.html
* igt@gem_softpin@allocator-evict@vecs0:
- shard-dg2: [PASS][54] -> [INCOMPLETE][55] ([i915#10652])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-11/igt@gem_softpin@allocator-evict@vecs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gem_softpin@allocator-evict@vecs0.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#3297] / [i915#3323])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][57] ([i915#3297] / [i915#4880])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@gem_userptr_blits@readonly-pwrite-unsync.html
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3297])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#3297])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen9_exec_parse@allowed-single:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#2856])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-oversize:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#2527]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu: NOTRUN -> [SKIP][63] ([i915#2527] / [i915#2856])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#2856]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@gen9_exec_parse@secure-batches.html
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#2527]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][66] -> [ABORT][67] ([i915#10887] / [i915#9820])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [PASS][68] -> [ABORT][69] ([i915#9820])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-4/igt@i915_module_load@reload-with-fault-injection.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#8399])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#11681])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@i915_pm_rps@thresholds-park.html
* igt@i915_pm_sseu@full-enable:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#8437])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@i915_pm_sseu@full-enable.html
* igt@intel_hwmon@hwmon-read:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#7707])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#4212])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4212]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- shard-glk: NOTRUN -> [FAIL][76] ([i915#11859])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][77] ([i915#5956])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-11/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-dp-4.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][78] -> [FAIL][79] ([i915#11808])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-3/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-9/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
- shard-snb: [PASS][80] -> [FAIL][81] ([i915#5956])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-snb6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-snb7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#5286]) +3 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#5286])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#4538] / [i915#5286]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#3638]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#3638]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][87] +4 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#4538] / [i915#5190]) +4 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#5190])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#4538]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#6095]) +35 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-c-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#6095]) +47 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-c-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#6095]) +11 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#10307] / [i915#6095]) +151 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4087]) +3 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#7828]) +4 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#7828]) +2 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#7828]) +4 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-dg1: NOTRUN -> [SKIP][100] ([i915#7828]) +6 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#7828]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#3116])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#3299])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#9424])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#11453])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#11453])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-sliding-128x42:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#8814]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_cursor_crc@cursor-sliding-128x42.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#11453]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#4103] / [i915#4213])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#9809])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: NOTRUN -> [FAIL][111] ([i915#2346])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#4103])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-dg1: [PASS][113] -> [DMESG-WARN][114] ([i915#10166])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg1-16/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-15/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3555])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#3804])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-dg2: [PASS][117] -> [SKIP][118] ([i915#1257])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-11/igt@kms_dp_aux_dev.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#8812])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-basic:
- shard-dg1: NOTRUN -> [SKIP][120] ([i915#3555] / [i915#3840])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#3840] / [i915#9688])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_dsc@dsc-fractional-bpp.html
- shard-tglu: NOTRUN -> [SKIP][122] ([i915#3840])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_feature_discovery@chamelium:
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#4854])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@psr1:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#658])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#3637]) +1 other test skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][126] +7 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-rkl: NOTRUN -> [SKIP][127] +14 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#8381])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#9934]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglu: NOTRUN -> [SKIP][130] ([i915#3637])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a4:
- shard-dg1: [PASS][131] -> [FAIL][132] ([i915#2122])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg1-15/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a4.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_flip@flip-vs-wf_vblank-interruptible@a-hdmi-a4.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-valid-mode:
- shard-dg1: [PASS][133] -> [FAIL][134] ([i915#12035])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-valid-mode.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#2587] / [i915#2672]) +2 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#2672])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#2672]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][138] ([i915#2587] / [i915#2672])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][139] ([i915#1825]) +4 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-snb: [PASS][140] -> [SKIP][141] +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][142] ([i915#5439])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#3458]) +7 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#8708]) +10 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#1825]) +13 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][146] +31 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#9766])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#3458]) +8 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#3023]) +12 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#8708]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#8708]) +7 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#5354]) +13 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#1839])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-3:
- shard-mtlp: [PASS][154] -> [ABORT][155] ([i915#10354])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-mtlp-2/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-3.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-3/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-3.html
* igt@kms_plane_lowres@tiling-4@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#11614] / [i915#3582]) +3 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_plane_lowres@tiling-4@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][157] +273 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#9423]) +19 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2.html
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#9423]) +3 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][160] ([i915#5176] / [i915#9423]) +3 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][161] ([i915#5235]) +2 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#3555] / [i915#5235])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#5354])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#5978])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_pm_dc@dc6-dpms.html
- shard-rkl: NOTRUN -> [FAIL][165] ([i915#9295])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#9340])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#9519])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-tglu: NOTRUN -> [SKIP][168] ([i915#9519])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][169] -> [SKIP][170] ([i915#9519]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#6524])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_prime@basic-crc-vgem.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#11520]) +2 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
- shard-tglu: NOTRUN -> [SKIP][173] ([i915#11520])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#11520]) +3 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#11520]) +3 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#9732]) +4 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_psr@fbc-psr2-primary-blt:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#1072] / [i915#9732]) +9 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_psr@fbc-psr2-primary-blt.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#1072] / [i915#9732]) +14 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@pr-suspend:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#9688]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_psr@pr-suspend.html
* igt@kms_psr@psr2-cursor-blt:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9732]) +9 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_psr@psr2-cursor-blt.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg1: NOTRUN -> [SKIP][181] ([i915#4884])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#4235])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][183] ([i915#5289])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-18/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#11131] / [i915#5190])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#5289])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#3555]) +4 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-17/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#3555])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#8623])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-rkl: [PASS][189] -> [FAIL][190] ([i915#9196])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#9906])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_vrr@flip-basic-fastset.html
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#9906])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][193] ([i915#2437])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_writeback@writeback-check-output.html
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#2437])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#2437] / [i915#9412])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-tglu: NOTRUN -> [SKIP][196] ([i915#2437] / [i915#9412])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#2437] / [i915#9412])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-dg2: [PASS][198] -> [FAIL][199] ([i915#4349])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-10/igt@perf_pmu@busy-double-start@ccs0.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-8/igt@perf_pmu@busy-double-start@ccs0.html
* igt@perf_pmu@busy-double-start@vcs0:
- shard-dg1: [PASS][200] -> [FAIL][201] ([i915#4349])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg1-16/igt@perf_pmu@busy-double-start@vcs0.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-15/igt@perf_pmu@busy-double-start@vcs0.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#8516])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg1-13/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#8516])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#3291] / [i915#3708])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@prime_vgem@basic-read.html
- shard-rkl: NOTRUN -> [SKIP][205] ([i915#3291] / [i915#3708])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-write-hang:
- shard-tglu: NOTRUN -> [SKIP][206] +20 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-10/igt@prime_vgem@fence-write-hang.html
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#3708])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-2/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#9917]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#9917])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@sriov_basic@enable-vfs-bind-unbind-each.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][210] ([i915#7742]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: [FAIL][212] ([i915#11900] / [i915#7742]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@drm_fdinfo@virtual-idle.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [FAIL][214] ([i915#2842]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_softpin@allocator-evict@ccs0:
- shard-mtlp: [INCOMPLETE][216] ([i915#10652]) -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-mtlp-8/igt@gem_softpin@allocator-evict@ccs0.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-8/igt@gem_softpin@allocator-evict@ccs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][218] ([i915#5566]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][220] ([i915#10887] / [i915#11231]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
- shard-glk: [FAIL][222] ([i915#11859]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk6/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1:
- shard-mtlp: [FAIL][224] ([i915#11808] / [i915#5956]) -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][226] ([i915#11808]) -> [PASS][227]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][228] ([i915#2122]) -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-snb5/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][230] ([i915#8292]) -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-5/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][232] ([i915#9295]) -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][234] ([i915#9519]) -> [PASS][235]
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [SKIP][236] ([i915#9519]) -> [PASS][237] +2 other tests pass
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-7/igt@kms_pm_rpm@modeset-lpsp-stress.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp-stress.html
#### Warnings ####
* igt@kms_content_protection@lic-type-0:
- shard-snb: [INCOMPLETE][238] ([i915#8816]) -> [SKIP][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-snb7/igt@kms_content_protection@lic-type-0.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-snb5/igt@kms_content_protection@lic-type-0.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: [SKIP][240] ([i915#11453]) -> [SKIP][241] ([i915#11453] / [i915#3359]) +1 other test skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-2/igt@kms_cursor_crc@cursor-onscreen-512x170.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: [SKIP][242] ([i915#11453] / [i915#3359]) -> [SKIP][243] ([i915#11453])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x512.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][244] ([i915#10433] / [i915#3458]) -> [SKIP][245] ([i915#3458])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: [SKIP][246] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][247] ([i915#1072] / [i915#9732]) +9 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-11/igt@kms_psr@psr-cursor-mmap-cpu.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-6/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: [SKIP][248] ([i915#1072] / [i915#9732]) -> [SKIP][249] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-2/igt@kms_psr@psr2-primary-mmap-gtt.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: [SKIP][250] ([i915#11131] / [i915#4235] / [i915#5190]) -> [SKIP][251] ([i915#11131] / [i915#5190])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-dg2-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-glk: [SKIP][252] -> [FAIL][253] ([i915#10959])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15280/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/shard-glk7/igt@kms_tiled_display@basic-test-pattern.html
[i915#10029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10029
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10652]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10652
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10729
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11231]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11231
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11614]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11614
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11900]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11900
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#12035]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12035
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4884]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4884
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
[i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8816
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15280 -> Patchwork_137654v1
CI-20190529: 20190529
CI_DRM_15280: 882c26c7017bdcc4eca493c7bf1ffb034d40be02 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7983: b2e17acf37471073210221724a66d164328dee98 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_137654v1: 882c26c7017bdcc4eca493c7bf1ffb034d40be02 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_137654v1/index.html
[-- Attachment #2: Type: text/html, Size: 84898 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 3/7] drm/i915/vblank: convert to struct intel_display
2024-08-22 21:42 ` Rodrigo Vivi
@ 2024-08-23 10:07 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-08-23 10:07 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, intel-xe
On Thu, 22 Aug 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Aug 22, 2024 at 07:04:51PM +0300, Jani Nikula wrote:
>> Going forward, struct intel_display shall replace struct
>> drm_i915_private as the main display device data pointer type. Convert
>> intel_vblank.[ch] to struct intel_display.
>>
>> Some stragglers are left behind where needed.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vblank.c | 97 +++++++++++----------
>> 1 file changed, 50 insertions(+), 47 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
>> index 2073e8075af4..838b55ecb1d8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
>> @@ -67,7 +67,7 @@
>> */
>> u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> + struct intel_display *display = to_intel_display(crtc->dev);
>> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
>> const struct drm_display_mode *mode = &vblank->hwmode;
>> enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> @@ -103,8 +103,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>> * we get a low value that's stable across two reads of the high
>> * register.
>> */
>> - frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
>> - PIPEFRAME(dev_priv, pipe));
>> + frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
>> + PIPEFRAME(display, pipe));
>>
>> pixel = frame & PIPE_PIXEL_MASK;
>> frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
>> @@ -119,19 +119,19 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>>
>> u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> + struct intel_display *display = to_intel_display(crtc->dev);
>> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
>> enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>
>> if (!vblank->max_vblank_count)
>> return 0;
>>
>> - return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
>> + return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
>> }
>>
>> static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + struct intel_display *display = to_intel_display(crtc);
>> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
>> const struct drm_display_mode *mode = &vblank->hwmode;
>> u32 htotal = mode->crtc_htotal;
>> @@ -150,16 +150,16 @@ static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
>> * pipe frame time stamp. The time stamp value
>> * is sampled at every start of vertical blank.
>> */
>> - scan_prev_time = intel_de_read_fw(dev_priv,
>> + scan_prev_time = intel_de_read_fw(display,
>> PIPE_FRMTMSTMP(crtc->pipe));
>>
>> /*
>> * The TIMESTAMP_CTR register has the current
>> * time stamp value.
>> */
>> - scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
>> + scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
>>
>> - scan_post_time = intel_de_read_fw(dev_priv,
>> + scan_post_time = intel_de_read_fw(display,
>> PIPE_FRMTMSTMP(crtc->pipe));
>> } while (scan_post_time != scan_prev_time);
>>
>> @@ -192,6 +192,7 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
>>
>> static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
>> {
>> + struct intel_display *display = to_intel_display(crtc_state);
>> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>>
>> /*
>> @@ -220,7 +221,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
>> * However if queried just before the start of vblank we'll get an
>> * answer that's slightly in the future.
>> */
>> - if (DISPLAY_VER(i915) == 2)
>> + if (DISPLAY_VER(display) == 2)
>> return -1;
>> else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>> return 2;
>> @@ -234,8 +235,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
>> */
>> static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>> {
>> - struct drm_device *dev = crtc->base.dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_display *display = to_intel_display(crtc);
>> struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
>> const struct drm_display_mode *mode = &vblank->hwmode;
>> enum pipe pipe = crtc->pipe;
>> @@ -249,7 +249,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>>
>> vtotal = intel_mode_vtotal(mode);
>>
>> - position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>> + position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
>>
>> /*
>> * On HSW, the DSL reg (0x70000) appears to return 0 if we
>> @@ -263,13 +263,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>> * problem. We may need to extend this to include other platforms,
>> * but so far testing only shows the problem on HSW.
>> */
>> - if (HAS_DDI(dev_priv) && !position) {
>> + if (HAS_DDI(display) && !position) {
>> int i, temp;
>>
>> for (i = 0; i < 100; i++) {
>> udelay(1);
>> - temp = intel_de_read_fw(dev_priv,
>> - PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>> + temp = intel_de_read_fw(display,
>> + PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
>> if (temp != position) {
>> position = temp;
>> break;
>> @@ -304,23 +304,25 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
>> * otherwise they may hang.
>> */
>> #ifdef I915
>> -static void intel_vblank_section_enter(struct drm_i915_private *i915)
>> +static void intel_vblank_section_enter(struct intel_display *display)
>> __acquires(i915->uncore.lock)
>
> I'm surprised this works!
> thought we would need to have something like
> __acquires(to_i915(display->drm)->uncore.lock)
It's actually not a C identifier, although one is commonly used. From
sparse Documentation/annotations.rst:
The first argument, *ctxt*, is an expression only used as documentation
to identify the context. Usually, what is used is a pointer to the structure
containing the context, for example, the structure protected by the lock.
> but anyway, if it works let's move on
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Agreed, and thanks. The series pushed to din.
BR,
Jani.
>
>> {
>> + struct drm_i915_private *i915 = to_i915(display->drm);
>> spin_lock(&i915->uncore.lock);
>> }
>>
>> -static void intel_vblank_section_exit(struct drm_i915_private *i915)
>> +static void intel_vblank_section_exit(struct intel_display *display)
>> __releases(i915->uncore.lock)
>> {
>> + struct drm_i915_private *i915 = to_i915(display->drm);
>> spin_unlock(&i915->uncore.lock);
>> }
>> #else
>> -static void intel_vblank_section_enter(struct drm_i915_private *i915)
>> +static void intel_vblank_section_enter(struct intel_display *display)
>> {
>> }
>>
>> -static void intel_vblank_section_exit(struct drm_i915_private *i915)
>> +static void intel_vblank_section_exit(struct intel_display *display)
>> {
>> }
>> #endif
>> @@ -331,19 +333,19 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>> ktime_t *stime, ktime_t *etime,
>> const struct drm_display_mode *mode)
>> {
>> - struct drm_device *dev = _crtc->dev;
>> - struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_display *display = to_intel_display(_crtc->dev);
>> + struct drm_i915_private *dev_priv = to_i915(display->drm);
>> struct intel_crtc *crtc = to_intel_crtc(_crtc);
>> enum pipe pipe = crtc->pipe;
>> int position;
>> int vbl_start, vbl_end, hsync_start, htotal, vtotal;
>> unsigned long irqflags;
>> - bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
>> - IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
>> + bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
>> + IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 ||
>> crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
>>
>> - if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
>> - drm_dbg(&dev_priv->drm,
>> + if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
>> + drm_dbg(display->drm,
>> "trying to get scanoutpos for disabled pipe %c\n",
>> pipe_name(pipe));
>> return false;
>> @@ -361,7 +363,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>> * preemption disabled, so the following code must not block.
>> */
>> local_irq_save(irqflags);
>> - intel_vblank_section_enter(dev_priv);
>> + intel_vblank_section_enter(display);
>>
>> /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
>>
>> @@ -393,7 +395,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>> * We can split this into vertical and horizontal
>> * scanout position.
>> */
>> - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>> + position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>>
>> /* convert to pixel counts */
>> vbl_start *= htotal;
>> @@ -429,7 +431,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>>
>> /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
>>
>> - intel_vblank_section_exit(dev_priv);
>> + intel_vblank_section_exit(display);
>> local_irq_restore(irqflags);
>>
>> /*
>> @@ -464,42 +466,42 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
>>
>> int intel_get_crtc_scanline(struct intel_crtc *crtc)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + struct intel_display *display = to_intel_display(crtc);
>> unsigned long irqflags;
>> int position;
>>
>> local_irq_save(irqflags);
>> - intel_vblank_section_enter(dev_priv);
>> + intel_vblank_section_enter(display);
>>
>> position = __intel_get_crtc_scanline(crtc);
>>
>> - intel_vblank_section_exit(dev_priv);
>> + intel_vblank_section_exit(display);
>> local_irq_restore(irqflags);
>>
>> return position;
>> }
>>
>> -static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
>> +static bool pipe_scanline_is_moving(struct intel_display *display,
>> enum pipe pipe)
>> {
>> - i915_reg_t reg = PIPEDSL(dev_priv, pipe);
>> + i915_reg_t reg = PIPEDSL(display, pipe);
>> u32 line1, line2;
>>
>> - line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
>> + line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
>> msleep(5);
>> - line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
>> + line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
>>
>> return line1 != line2;
>> }
>>
>> static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
>> {
>> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + struct intel_display *display = to_intel_display(crtc);
>> enum pipe pipe = crtc->pipe;
>>
>> /* Wait for the display line to settle/start moving */
>> - if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
>> - drm_err(&dev_priv->drm,
>> + if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
>> + drm_err(display->drm,
>> "pipe %c scanline %s wait timed out\n",
>> pipe_name(pipe), str_on_off(state));
>> }
>> @@ -517,8 +519,8 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
>> void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>> bool vrr_enable)
>> {
>> + struct intel_display *display = to_intel_display(crtc_state);
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> u8 mode_flags = crtc_state->mode_flags;
>> struct drm_display_mode adjusted_mode;
>> int vmax_vblank_start = 0;
>> @@ -527,7 +529,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>> drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
>>
>> if (vrr_enable) {
>> - drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
>> + drm_WARN_ON(display->drm,
>> + (mode_flags & I915_MODE_FLAG_VRR) == 0);
>>
>> adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
>> adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
>> @@ -549,8 +552,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>> * __intel_get_crtc_scanline()) with vblank_time_lock?
>> * Need to audit everything to make sure it's safe.
>> */
>> - spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
>> - intel_vblank_section_enter(i915);
>> + spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
>> + intel_vblank_section_enter(display);
>>
>> drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
>>
>> @@ -559,8 +562,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
>> crtc->mode_flags = mode_flags;
>>
>> crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
>> - intel_vblank_section_exit(i915);
>> - spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
>> + intel_vblank_section_exit(display);
>> + spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
>> }
>>
>> int intel_mode_vdisplay(const struct drm_display_mode *mode)
>> @@ -666,7 +669,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>> int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>> {
>> struct intel_crtc *crtc = evade->crtc;
>> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>> + struct intel_display *display = to_intel_display(crtc);
>> long timeout = msecs_to_jiffies_timeout(1);
>> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
>> DEFINE_WAIT(wait);
>> @@ -688,7 +691,7 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>> break;
>>
>> if (!timeout) {
>> - drm_err(&i915->drm,
>> + drm_err(display->drm,
>> "Potential atomic update failure on pipe %c\n",
>> pipe_name(crtc->pipe));
>> break;
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 7/7] drm/i915/display: convert params to struct intel_display
2024-08-22 21:48 ` Rodrigo Vivi
@ 2024-08-23 10:08 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2024-08-23 10:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, intel-xe
On Thu, 22 Aug 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Thu, Aug 22, 2024 at 07:04:55PM +0300, Jani Nikula wrote:
>> Going forward, struct intel_display shall replace struct
>> drm_i915_private as the main display device data pointer type. Convert
>> intel_display_params.[ch] and intel_display_debugfs_params.[ch] to
>> struct intel_display.
>>
>> Some stragglers are left behind where needed.
>
> ^ just noticed the extra tab on this, but
> likely present in the other commit messages where you had
> left some cases behind...
Thanks, fixed while applying.
BR,
Jani.
>
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
>> .../gpu/drm/i915/display/intel_display_debugfs_params.c | 8 ++++----
>> .../gpu/drm/i915/display/intel_display_debugfs_params.h | 4 ++--
>> drivers/gpu/drm/i915/display/intel_display_params.c | 6 +++---
>> drivers/gpu/drm/i915/display/intel_display_params.h | 4 ++--
>> drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>> drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
>> 7 files changed, 16 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 0cf0b4223513..74f527647aa9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -1073,7 +1073,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>> intel_opregion_debugfs_register(display);
>> intel_psr_debugfs_register(i915);
>> intel_wm_debugfs_register(i915);
>> - intel_display_debugfs_params(i915);
>> + intel_display_debugfs_params(display);
>> }
>>
>> static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
>> index f35718748555..ec3ed29a83c9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
>> @@ -151,13 +151,13 @@ intel_display_debugfs_create_uint(const char *name, umode_t mode,
>> } while (0)
>>
>> /* add a subdirectory with files for each intel display param */
>> -void intel_display_debugfs_params(struct drm_i915_private *i915)
>> +void intel_display_debugfs_params(struct intel_display *display)
>> {
>> - struct drm_minor *minor = i915->drm.primary;
>> + struct drm_minor *minor = display->drm->primary;
>> struct dentry *dir;
>> char dirname[16];
>>
>> - snprintf(dirname, sizeof(dirname), "%s_params", i915->drm.driver->name);
>> + snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
>> dir = debugfs_lookup(dirname, minor->debugfs_root);
>> if (!dir)
>> dir = debugfs_create_dir(dirname, minor->debugfs_root);
>> @@ -171,7 +171,7 @@ void intel_display_debugfs_params(struct drm_i915_private *i915)
>> */
>>
>> #define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
>> - dir, #x, mode, &i915->display.params.x);
>> + dir, #x, mode, &display->params.x);
>> INTEL_DISPLAY_PARAMS_FOR_EACH(REGISTER);
>> #undef REGISTER
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
>> index 1e9945a4044c..a1120915a5a8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
>> @@ -6,8 +6,8 @@
>> #ifndef __INTEL_DISPLAY_DEBUGFS_PARAMS__
>> #define __INTEL_DISPLAY_DEBUGFS_PARAMS__
>>
>> -struct drm_i915_private;
>> +struct intel_display;
>>
>> -void intel_display_debugfs_params(struct drm_i915_private *i915);
>> +void intel_display_debugfs_params(struct intel_display *display);
>>
>> #endif /* __INTEL_DISPLAY_DEBUGFS_PARAMS__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
>> index e82bd72d32fa..1a45d300b6f0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
>> @@ -173,14 +173,14 @@ static void _param_print_charp(struct drm_printer *p, const char *driver_name,
>>
>> /**
>> * intel_display_params_dump - dump intel display modparams
>> - * @i915: i915 device
>> + * @display: display device
>> * @p: the &drm_printer
>> *
>> * Pretty printer for i915 modparams.
>> */
>> -void intel_display_params_dump(struct drm_i915_private *i915, struct drm_printer *p)
>> +void intel_display_params_dump(struct intel_display *display, struct drm_printer *p)
>> {
>> -#define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, i915->display.params.x);
>> +#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
>> INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT);
>> #undef PRINT
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
>> index 48c29c55c939..da8dc943234b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
>> @@ -9,7 +9,7 @@
>> #include <linux/types.h>
>>
>> struct drm_printer;
>> -struct drm_i915_private;
>> +struct intel_display;
>>
>> /*
>> * Invoke param, a function-like macro, for each intel display param, with
>> @@ -56,7 +56,7 @@ struct intel_display_params {
>> };
>> #undef MEMBER
>>
>> -void intel_display_params_dump(struct drm_i915_private *i915,
>> +void intel_display_params_dump(struct intel_display *display,
>> struct drm_printer *p);
>> void intel_display_params_copy(struct intel_display_params *dest);
>> void intel_display_params_free(struct intel_display_params *params);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index bc717cf544e4..f969f585d07b 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -66,6 +66,7 @@ static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
>> static int i915_capabilities(struct seq_file *m, void *data)
>> {
>> struct drm_i915_private *i915 = node_to_i915(m->private);
>> + struct intel_display *display = &i915->display;
>> struct drm_printer p = drm_seq_file_printer(m);
>>
>> seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
>> @@ -77,7 +78,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
>>
>> kernel_param_lock(THIS_MODULE);
>> i915_params_dump(&i915->params, &p);
>> - intel_display_params_dump(i915, &p);
>> + intel_display_params_dump(display, &p);
>> kernel_param_unlock(THIS_MODULE);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 96c6cafd5b9e..6469b9bcf2ec 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -660,9 +660,10 @@ static void err_print_params(struct drm_i915_error_state_buf *m,
>> const struct i915_params *params)
>> {
>> struct drm_printer p = i915_error_printer(m);
>> + struct intel_display *display = &m->i915->display;
>>
>> i915_params_dump(params, &p);
>> - intel_display_params_dump(m->i915, &p);
>> + intel_display_params_dump(display, &p);
>> }
>>
>> static void err_print_pciid(struct drm_i915_error_state_buf *m,
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2024-08-23 10:08 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-22 16:04 [PATCH 0/7] drm/i915/display: conversion to struct intel_display Jani Nikula
2024-08-22 16:04 ` [PATCH 1/7] drm/i915/vblank: use drm_crtc_vblank_crtc() instead of open-coding Jani Nikula
2024-08-22 21:37 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 2/7] drm/i915/vblank: fix context imbalance warnings Jani Nikula
2024-08-22 21:38 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 3/7] drm/i915/vblank: convert to struct intel_display Jani Nikula
2024-08-22 21:42 ` Rodrigo Vivi
2024-08-23 10:07 ` Jani Nikula
2024-08-22 16:04 ` [PATCH 4/7] drm/i915/vrr: " Jani Nikula
2024-08-22 21:44 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 5/7] drm/i915/tv: " Jani Nikula
2024-08-22 21:45 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 6/7] drm/i915/sprite: " Jani Nikula
2024-08-22 21:47 ` Rodrigo Vivi
2024-08-22 16:04 ` [PATCH 7/7] drm/i915/display: convert params " Jani Nikula
2024-08-22 21:48 ` Rodrigo Vivi
2024-08-23 10:08 ` Jani Nikula
2024-08-22 16:57 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversion " Patchwork
2024-08-22 16:57 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-08-22 17:14 ` ✓ Fi.CI.BAT: success " Patchwork
2024-08-23 8:41 ` ✓ Fi.CI.IGT: " Patchwork
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