[PATCH 0/7] DP DSC min/max src bpc fixes

[PATCH 0/7] DP DSC min/max src bpc fixes

[Ankit Nautiyal]

Use helpers for source min/max src bpc appropriately for dp mst case and
to limit max_requested_bpc property min/max values. 

Rev2: Dropped patch to limit max_requested_bpc based on src DSC bpc
limits. Instead added change to ignore max_requested_bpc if its
too low for DSC.

Rev3: Updated patch#1 commit message.

Rev4: Rebase.

Rev5: Addressed Jani's comment on patch#3.

Rev6: Rebase.

Rev7: Added patch to fix return type for dsc_min/max_src bpc helpers to
int.

Rev8: Drop the first patch and added patches to refactor pipe_bpp limits
and link limits.

Ankit Nautiyal (7):
  drm/i915/dp: Use HAS_DSC macro in intel_dp_dsc_max_src_input_bpc
  drm/i915/dp: Return int from dsc_max/min_src_input_bpc helpers
  drm/i915/dp_mst: Use helpers to get dsc min/max input bpc
  drm/i915/dp: Drop max_requested_bpc for dsc pipe_min/max bpp
  drm/i915/dp: Refactor pipe_bpp limits with dsc
  drm/i915/dp: Use clamp for pipe_bpp limits with DSC
  drm/i915/dp: Set the DSC link limits
    intel_dp_compute_config_link_bpp_limits

 drivers/gpu/drm/i915/display/intel_dp.c     | 142 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_dp.h     |   7 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  14 +-
 3 files changed, 79 insertions(+), 84 deletions(-)

-- 
2.45.2

[PATCH 1/7] drm/i915/dp: Use HAS_DSC macro in intel_dp_dsc_max_src_input_bpc

[Ankit Nautiyal]

Use HAS_DSC macro to take into account platforms for which DSC is fused.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c4fdae5097ec..c47748905506 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1766,6 +1766,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 static
 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
 {
+	if (!HAS_DSC(i915))
+		return 0;
+
 	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 	if (DISPLAY_VER(i915) >= 12)
 		return 12;
-- 
2.45.2

[PATCH 2/7] drm/i915/dp: Return int from dsc_max/min_src_input_bpc helpers

[Ankit Nautiyal]

Use ints for dsc_max/min_bpc instead of u8 in
dsc_max/min_src_input_bpc helpers and their callers.
This will also help replace min_t/max_t macros with min/max ones.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c47748905506..cf09698b0ee9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1764,7 +1764,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 }
 
 static
-u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+int intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
 {
 	if (!HAS_DSC(i915))
 		return 0;
@@ -1784,14 +1784,14 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	int i, num_bpc;
 	u8 dsc_bpc[3] = {};
-	u8 dsc_max_bpc;
+	int dsc_max_bpc;
 
 	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
 
 	if (!dsc_max_bpc)
 		return dsc_max_bpc;
 
-	dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
 
 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 						       dsc_bpc);
@@ -2161,7 +2161,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 }
 
 static
-u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+int intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
 {
 	/* Min DSC Input BPC for ICL+ is 8 */
 	return HAS_DSC(i915) ? 8 : 0;
@@ -2173,7 +2173,7 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
 				struct link_config_limits *limits,
 				int pipe_bpp)
 {
-	u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
 
 	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
 	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
@@ -2218,9 +2218,9 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	const struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	u8 max_req_bpc = conn_state->max_requested_bpc;
-	u8 dsc_max_bpc, dsc_max_bpp;
-	u8 dsc_min_bpc, dsc_min_bpp;
+	int max_req_bpc = conn_state->max_requested_bpc;
+	int dsc_max_bpc, dsc_max_bpp;
+	int dsc_min_bpc, dsc_min_bpp;
 	u8 dsc_bpc[3] = {};
 	int forced_bpp, pipe_bpp;
 	int num_bpc, i, ret;
@@ -2240,7 +2240,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	if (!dsc_max_bpc)
 		return -EINVAL;
 
-	dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
 	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
 
 	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
-- 
2.45.2

[PATCH 3/7] drm/i915/dp_mst: Use helpers to get dsc min/max input bpc

[Ankit Nautiyal]

Use helpers for source min/max input bpc with DSC.
While at it, make them return int instead of u8 and use struct
intel_display.

v2: Make the helpers return int instead of u8. (Jani)
v3: Use min/max macros instead of min_t/max_t. (Jani)
v4: Use struct intel_display.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 29 ++++++++++-----------
 drivers/gpu/drm/i915/display/intel_dp.h     |  3 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++++-----
 3 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cf09698b0ee9..b553b24604e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1763,16 +1763,15 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	return -EINVAL;
 }
 
-static
-int intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
 {
-	if (!HAS_DSC(i915))
+	if (!HAS_DSC(display))
 		return 0;
 
 	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
-	if (DISPLAY_VER(i915) >= 12)
+	if (DISPLAY_VER(display) >= 12)
 		return 12;
-	if (DISPLAY_VER(i915) == 11)
+	if (DISPLAY_VER(display) == 11)
 		return 10;
 
 	return 0;
@@ -1781,12 +1780,12 @@ int intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
 				 u8 max_req_bpc)
 {
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	int i, num_bpc;
 	u8 dsc_bpc[3] = {};
 	int dsc_max_bpc;
 
-	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
 
 	if (!dsc_max_bpc)
 		return dsc_max_bpc;
@@ -2160,11 +2159,10 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 					   dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
 }
 
-static
-int intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+int intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
 {
 	/* Min DSC Input BPC for ICL+ is 8 */
-	return HAS_DSC(i915) ? 8 : 0;
+	return HAS_DSC(display) ? 8 : 0;
 }
 
 static
@@ -2173,10 +2171,11 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
 				struct link_config_limits *limits,
 				int pipe_bpp)
 {
+	struct intel_display *display = to_intel_display(&i915->drm);
 	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
 
-	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
-	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(display), conn_state->max_requested_bpc);
+	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
 
 	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
 	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
@@ -2215,7 +2214,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 					 struct link_config_limits *limits,
 					 int timeslots)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct intel_display *display = to_intel_display(intel_dp);
 	const struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	int max_req_bpc = conn_state->max_requested_bpc;
@@ -2236,14 +2235,14 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 		}
 	}
 
-	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
 	if (!dsc_max_bpc)
 		return -EINVAL;
 
 	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
 	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
 
-	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
 	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 53d1217800ef..8bd0bb4ec0e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -20,6 +20,7 @@ struct intel_atomic_state;
 struct intel_connector;
 struct intel_crtc_state;
 struct intel_digital_port;
+struct intel_display;
 struct intel_dp;
 struct intel_encoder;
 
@@ -205,5 +206,7 @@ bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 				u8 lane_count);
 bool intel_dp_has_connector(struct intel_dp *intel_dp,
 			    const struct drm_connector_state *conn_state);
+int intel_dp_dsc_max_src_input_bpc(struct intel_display *display);
+int intel_dp_dsc_min_src_input_bpc(struct intel_display *display);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4765bda154c1..9453f3531910 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -328,6 +328,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 						struct drm_connector_state *conn_state,
 						struct link_config_limits *limits)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -335,17 +336,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	int i, num_bpc;
 	u8 dsc_bpc[3] = {};
 	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
-	u8 dsc_max_bpc;
+	int dsc_max_bpc, dsc_min_bpc;
 	int min_compressed_bpp, max_compressed_bpp;
 
-	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
-	if (DISPLAY_VER(i915) >= 12)
-		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
-	else
-		dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
+	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
+	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
 
-	max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
-	min_bpp = limits->pipe.min_bpp;
+	max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
+	min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
 
 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 						       dsc_bpc);
-- 
2.45.2

[PATCH 4/7] drm/i915/dp: Drop max_requested_bpc for dsc pipe_min/max bpp

[Ankit Nautiyal]

Currently we are including both max_requested_bpc and
limits->pipe.bpp_max while computing maximum possible pipe bpp with dsc.
However, while setting limits->pipe.max_bpp, the max_requested_bpc is
already taken into account.

Drop the redundant check for max_requested_bpc and use only
limits->pipe.bpp_max. This will also result in dropping conn_state
argument in functions where it was used only to get max_requested_bpc.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b553b24604e1..46f3b680afe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2167,14 +2167,13 @@ int intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
 
 static
 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
-				struct drm_connector_state *conn_state,
 				struct link_config_limits *limits,
 				int pipe_bpp)
 {
 	struct intel_display *display = to_intel_display(&i915->drm);
 	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
 
-	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(display), conn_state->max_requested_bpc);
+	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
 	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
 
 	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
@@ -2186,7 +2185,6 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
 
 static
 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
-				struct drm_connector_state *conn_state,
 				struct link_config_limits *limits)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -2197,7 +2195,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
 
 	forced_bpp = intel_dp->force_dsc_bpc * 3;
 
-	if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
+	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
 		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
 		return forced_bpp;
 	}
@@ -2217,14 +2215,13 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	struct intel_display *display = to_intel_display(intel_dp);
 	const struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	int max_req_bpc = conn_state->max_requested_bpc;
 	int dsc_max_bpc, dsc_max_bpp;
 	int dsc_min_bpc, dsc_min_bpp;
 	u8 dsc_bpc[3] = {};
 	int forced_bpp, pipe_bpp;
 	int num_bpc, i, ret;
 
-	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
+	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
 
 	if (forced_bpp) {
 		ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
@@ -2239,7 +2236,6 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	if (!dsc_max_bpc)
 		return -EINVAL;
 
-	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
 	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
 
 	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
@@ -2279,16 +2275,16 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
 	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
 
-	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
+	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
 
 	if (forced_bpp) {
 		pipe_bpp = forced_bpp;
 	} else {
-		int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
+		int max_bpc = limits->pipe.max_bpp / 3;
 
 		/* For eDP use max bpp that can be supported with DSC. */
 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
-		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
+		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
 			drm_dbg_kms(&i915->drm,
 				    "Computed BPC is not in DSC BPC limits\n");
 			return -EINVAL;
-- 
2.45.2

[PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc

[Ankit Nautiyal]

With DSC there are additional limits for pipe_bpp. Currently these are
scattered in different places.
Instead set the limits->pipe.max/min_bpp in one place and use them
wherever required.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++++---------------
 1 file changed, 17 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 46f3b680afe9..55ee438a4fec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2166,21 +2166,11 @@ int intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
 }
 
 static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
-				struct link_config_limits *limits,
+bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
 				int pipe_bpp)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
-	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
-
-	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
-	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
-
-	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
-	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
-
-	return pipe_bpp >= dsc_min_pipe_bpp &&
-	       pipe_bpp <= dsc_max_pipe_bpp;
+	return pipe_bpp >= limits->pipe.min_bpp &&
+	       pipe_bpp <= limits->pipe.max_bpp;
 }
 
 static
@@ -2195,7 +2185,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
 
 	forced_bpp = intel_dp->force_dsc_bpc * 3;
 
-	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
+	if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
 		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
 		return forced_bpp;
 	}
@@ -2212,11 +2202,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 					 struct link_config_limits *limits,
 					 int timeslots)
 {
-	struct intel_display *display = to_intel_display(intel_dp);
 	const struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	int dsc_max_bpc, dsc_max_bpp;
-	int dsc_min_bpc, dsc_min_bpp;
+	int dsc_max_bpp;
+	int dsc_min_bpp;
 	u8 dsc_bpc[3] = {};
 	int forced_bpp, pipe_bpp;
 	int num_bpc, i, ret;
@@ -2232,14 +2221,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 		}
 	}
 
-	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
-	if (!dsc_max_bpc)
-		return -EINVAL;
-
-	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
-
-	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
-	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
+	dsc_max_bpp = limits->pipe.max_bpp;
+	dsc_min_bpp = limits->pipe.min_bpp;
 
 	/*
 	 * Get the maximum DSC bpc that will be supported by any valid
@@ -2284,7 +2267,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 
 		/* For eDP use max bpp that can be supported with DSC. */
 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
-		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
+		if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
 			drm_dbg_kms(&i915->drm,
 				    "Computed BPC is not in DSC BPC limits\n");
 			return -EINVAL;
@@ -2502,6 +2485,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 						     respect_downstream_limits);
+	if (dsc) {
+		struct intel_display *display = to_intel_display(intel_dp);
+		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
+		int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
+
+		limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);
+		limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);
+	}
 
 	if (intel_dp->use_max_params) {
 		/*
-- 
2.45.2

[PATCH 6/7] drm/i915/dp: Use clamp for pipe_bpp limits with DSC

[Ankit Nautiyal]

Currently to get the max pipe_bpp with dsc we take the min of
limits->pipe.max_bpp and dsc max bpp (dsc max bpc * 3). This can result
in problems when limits->pipe.max_bpp is less than the computed dsc min bpp
(dsc min bpc * 3).

Replace the min/max functions with clamp while computing
limits->pipe.max/min_bpp to ensure that the pipe_bpp limits are constrained
within the DSC-defined minimum and maximum values.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 55ee438a4fec..02009ae03840 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2490,8 +2490,11 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
 		int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
 
-		limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);
-		limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);
+		limits->pipe.max_bpp = clamp(limits->pipe.max_bpp,
+					     dsc_min_bpc * 3, dsc_max_bpc * 3);
+
+		limits->pipe.min_bpp = clamp(limits->pipe.min_bpp,
+					     dsc_min_bpc * 3, dsc_max_bpc * 3);
 	}
 
 	if (intel_dp->use_max_params) {
-- 
2.45.2

[PATCH 7/7] drm/i915/dp: Set the DSC link limits intel_dp_compute_config_link_bpp_limits

[Ankit Nautiyal]

The helper intel_dp_compute_config_link_bpp_limits is the correct place
to set the DSC link limits. Move the code to this function and remove
the #TODO item.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++------------
 drivers/gpu/drm/i915/display/intel_dp.h |  4 +-
 2 files changed, 35 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 02009ae03840..bfc31b3af864 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1958,7 +1958,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 
 static
 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
-					    struct intel_crtc_state *pipe_config,
+					    const struct intel_crtc_state *pipe_config,
 					    int bpc)
 {
 	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
@@ -1983,7 +1983,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
 	return 0;
 }
 
-int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
 {
 	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
 	switch (pipe_config->output_format) {
@@ -2001,7 +2001,7 @@ int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
 }
 
 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
-					 struct intel_crtc_state *pipe_config,
+					 const struct intel_crtc_state *pipe_config,
 					 int bpc)
 {
 	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
@@ -2130,21 +2130,16 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
-	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+	int dsc_min_bpp;
+	int dsc_max_bpp;
 	int dsc_joiner_max_bpp;
 	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
 
-	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
-	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
-	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
-	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
+	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
 
-	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
-	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
-								pipe_config,
-								pipe_bpp / 3);
-	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+							   pipe_config,
+							   pipe_bpp / 3);
 
 	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
 								adjusted_mode->hdisplay,
@@ -2255,8 +2250,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	int pipe_bpp, forced_bpp;
-	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
-	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+	int dsc_min_bpp;
+	int dsc_max_bpp;
 
 	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
 
@@ -2276,16 +2271,12 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	pipe_config->port_clock = limits->max_rate;
 	pipe_config->lane_count = limits->max_lane_count;
 
-	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
-	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
-	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
-	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
+	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
+
+	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+							   pipe_config,
+							   pipe_bpp / 3);
 
-	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
-	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
-								pipe_config,
-								pipe_bpp / 3);
-	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
 	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
 
 	/* Compressed BPP should be less than the Input DSC bpp */
@@ -2428,6 +2419,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 		&crtc_state->hw.adjusted_mode;
 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct intel_connector *connector = intel_dp->attached_connector;
 	int max_link_bpp_x16;
 
 	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
@@ -2441,12 +2433,22 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
 
 		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
 	} else {
-		/*
-		 * TODO: set the DSC link limits already here, atm these are
-		 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
-		 * intel_dp_dsc_compute_pipe_bpp()
-		 */
-		limits->link.min_bpp_x16 = 0;
+		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+
+		dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+		dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+		dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
+
+		dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+		dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
+									crtc_state,
+									limits->pipe.max_bpp / 3);
+		dsc_max_bpp = dsc_sink_max_bpp ?
+			      min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+		max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
 	}
 
 	limits->link.max_bpp_x16 = max_link_bpp_x16;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 8bd0bb4ec0e1..d4ca00ba49b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -145,9 +145,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 					enum intel_output_format output_format,
 					u32 pipe_bpp,
 					u32 timeslots);
-int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config);
 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
-					 struct intel_crtc_state *pipe_config,
+					 const struct intel_crtc_state *pipe_config,
 					 int bpc);
 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 				int mode_clock, int mode_hdisplay,
-- 
2.45.2

RE: [PATCH 1/7] drm/i915/dp: Use HAS_DSC macro in intel_dp_dsc_max_src_input_bpc

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 1/7] drm/i915/dp: Use HAS_DSC macro in
> intel_dp_dsc_max_src_input_bpc
> 
> Use HAS_DSC macro to take into account platforms for which DSC is fused.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c4fdae5097ec..c47748905506 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1766,6 +1766,9 @@ intel_dp_compute_link_config_wide(struct
> intel_dp *intel_dp,  static
>  u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)  {
> +	if (!HAS_DSC(i915))
> +		return 0;
> +
>  	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
>  	if (DISPLAY_VER(i915) >= 12)
>  		return 12;
> --
> 2.45.2

✗ Fi.CI.CHECKPATCH: warning for DP DSC min/max src bpc fixes (rev8)

[Patchwork]

== Series Details ==

Series: DP DSC min/max src bpc fixes (rev8)
URL   : https://patchwork.freedesktop.org/series/125571/
State : warning

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/125571/revisions/8/mbox/ not found

✓ Fi.CI.BAT: success for DP DSC min/max src bpc fixes (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 22913 bytes --]

== Series Details ==

Series: DP DSC min/max src bpc fixes (rev8)
URL   : https://patchwork.freedesktop.org/series/125571/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_15478 -> Patchwork_125571v8
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/index.html

Participating hosts (43 -> 43)
------------------------------

  Additional (1): bat-rpls-4 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_125571v8 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rpls-4:         NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@debugfs_test@basic-hwmon.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-rpls-4:         NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_mmap@basic:
    - bat-dg2-14:         NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-dg2-14:         NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg2-14:         NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-rpls-4:         NOTRUN -> [SKIP][6] ([i915#3282])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-7567u:       [PASS][7] -> [DMESG-WARN][8] ([i915#11621] / [i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/fi-kbl-7567u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-14:         NOTRUN -> [SKIP][9] ([i915#11681] / [i915#6621])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live:
    - bat-arls-2:         [PASS][10] -> [ABORT][11] ([i915#12061] / [i915#12133])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@i915_selftest@live.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@i915_selftest@live.html
    - bat-dg2-11:         [PASS][12] -> [ABORT][13] ([i915#12133])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-dg2-11/igt@i915_selftest@live.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-11/igt@i915_selftest@live.html

  * igt@i915_selftest@live@active:
    - bat-dg2-11:         [PASS][14] -> [ABORT][15] ([i915#12305])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-dg2-11/igt@i915_selftest@live@active.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-11/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-7567u:       [PASS][16] -> [DMESG-WARN][17] ([i915#11621]) +31 other tests dmesg-warn
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-2:         [PASS][18] -> [ABORT][19] ([i915#12061])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@i915_selftest@live@workarounds.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-14:         NOTRUN -> [SKIP][20] ([i915#5190])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-14:         NOTRUN -> [SKIP][21] ([i915#4215] / [i915#5190])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - bat-dg2-14:         NOTRUN -> [SKIP][22] ([i915#4212]) +7 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg2-14:         NOTRUN -> [SKIP][23] ([i915#4103] / [i915#4213]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-rpls-4:         NOTRUN -> [SKIP][24] ([i915#4103]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-rpls-4:         NOTRUN -> [SKIP][25] ([i915#3555] / [i915#3840] / [i915#9886])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_dsc@dsc-basic.html
    - bat-dg2-14:         NOTRUN -> [SKIP][26] ([i915#3555] / [i915#3840])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg2-14:         NOTRUN -> [SKIP][27]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_force_connector_basic@force-load-detect.html
    - bat-rpls-4:         NOTRUN -> [SKIP][28]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-14:         NOTRUN -> [SKIP][29] ([i915#5274])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg2-14:         NOTRUN -> [SKIP][30] ([i915#5354])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_pm_backlight@basic-brightness.html
    - bat-rpls-4:         NOTRUN -> [SKIP][31] ([i915#5354])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-rpls-4:         NOTRUN -> [SKIP][32] ([i915#1072] / [i915#9732]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - bat-dg2-14:         NOTRUN -> [SKIP][33] ([i915#1072] / [i915#9732]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rpls-4:         NOTRUN -> [SKIP][34] ([i915#3555])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg2-14:         NOTRUN -> [SKIP][35] ([i915#3555])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-14:         NOTRUN -> [SKIP][36] ([i915#3708])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg2-14:         NOTRUN -> [SKIP][37] ([i915#3708] / [i915#4077]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-read:
    - bat-rpls-4:         NOTRUN -> [SKIP][38] ([i915#3708]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-rpls-4/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-14:         NOTRUN -> [SKIP][39] ([i915#3291] / [i915#3708]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-dg2-14/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - fi-hsw-4770:        [DMESG-WARN][40] ([i915#12310]) -> [PASS][41] +1 other test pass
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/fi-hsw-4770/igt@i915_selftest@live.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/fi-hsw-4770/igt@i915_selftest@live.html
    - bat-mtlp-8:         [ABORT][42] ([i915#12216]) -> [PASS][43] +1 other test pass
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-mtlp-8/igt@i915_selftest@live.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-mtlp-8/igt@i915_selftest@live.html
    - {bat-arlh-3}:       [ABORT][44] ([i915#12061] / [i915#12133]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-3/igt@i915_selftest@live.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - {bat-arlh-3}:       [ABORT][46] ([i915#12061]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@gem_lmem_swapping@basic:
    - bat-twl-2:          [SKIP][48] ([i915#11671]) -> [SKIP][49] ([i915#10213] / [i915#11671]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-2/igt@gem_lmem_swapping@basic.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-2/igt@gem_lmem_swapping@basic.html
    - bat-arls-1:         [SKIP][50] ([i915#11671]) -> [SKIP][51] ([i915#10213] / [i915#11671]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-1/igt@gem_lmem_swapping@basic.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-1/igt@gem_lmem_swapping@basic.html
    - bat-arls-5:         [SKIP][52] ([i915#11671]) -> [SKIP][53] ([i915#10213] / [i915#11671]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-5/igt@gem_lmem_swapping@basic.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-5/igt@gem_lmem_swapping@basic.html
    - bat-arlh-2:         [SKIP][54] ([i915#11671]) -> [SKIP][55] ([i915#10213] / [i915#11671]) +3 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-2/igt@gem_lmem_swapping@basic.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-2/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-twl-1:          [SKIP][56] ([i915#11671]) -> [SKIP][57] ([i915#10213] / [i915#11671]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-1/igt@gem_lmem_swapping@parallel-random-engines.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-1/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-arls-2:         [SKIP][58] ([i915#11671]) -> [SKIP][59] ([i915#10213] / [i915#11671]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@gem_lmem_swapping@verify-random.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_render_tiled_blits@basic:
    - bat-arls-2:         [SKIP][60] ([i915#10211] / [i915#4079]) -> [SKIP][61] ([i915#10197] / [i915#10211] / [i915#4079])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@gem_render_tiled_blits@basic.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@gem_render_tiled_blits@basic.html
    - bat-arls-1:         [SKIP][62] ([i915#10211] / [i915#4079]) -> [SKIP][63] ([i915#10197] / [i915#10211] / [i915#4079])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-1/igt@gem_render_tiled_blits@basic.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-1/igt@gem_render_tiled_blits@basic.html
    - bat-arls-5:         [SKIP][64] ([i915#10211] / [i915#4079]) -> [SKIP][65] ([i915#10197] / [i915#10211] / [i915#4079])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-5/igt@gem_render_tiled_blits@basic.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-5/igt@gem_render_tiled_blits@basic.html
    - bat-arlh-2:         [SKIP][66] ([i915#10211] / [i915#11725]) -> [SKIP][67] ([i915#10197] / [i915#10211] / [i915#11725])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-2/igt@gem_render_tiled_blits@basic.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-2/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-arls-5:         [SKIP][68] ([i915#4079]) -> [SKIP][69] ([i915#10206] / [i915#4079])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-5/igt@gem_tiled_pread_basic.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-5/igt@gem_tiled_pread_basic.html
    - bat-arlh-2:         [SKIP][70] ([i915#11724]) -> [SKIP][71] ([i915#10206] / [i915#11724])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-2/igt@gem_tiled_pread_basic.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-2/igt@gem_tiled_pread_basic.html
    - bat-arls-2:         [SKIP][72] ([i915#4079]) -> [SKIP][73] ([i915#10206] / [i915#4079])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@gem_tiled_pread_basic.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@gem_tiled_pread_basic.html
    - bat-arls-1:         [SKIP][74] ([i915#4079]) -> [SKIP][75] ([i915#10206] / [i915#4079])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-1/igt@gem_tiled_pread_basic.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-twl-2:          [SKIP][76] ([i915#11681]) -> [SKIP][77] ([i915#10209] / [i915#11681])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-2/igt@i915_pm_rps@basic-api.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-2/igt@i915_pm_rps@basic-api.html
    - bat-arls-1:         [SKIP][78] ([i915#11681]) -> [SKIP][79] ([i915#10209] / [i915#11681])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-1/igt@i915_pm_rps@basic-api.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-1/igt@i915_pm_rps@basic-api.html
    - bat-twl-1:          [SKIP][80] ([i915#11681]) -> [SKIP][81] ([i915#10209] / [i915#11681])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-1/igt@i915_pm_rps@basic-api.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-1/igt@i915_pm_rps@basic-api.html
    - bat-arls-5:         [SKIP][82] ([i915#11681]) -> [SKIP][83] ([i915#10209] / [i915#11681])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-5/igt@i915_pm_rps@basic-api.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-5/igt@i915_pm_rps@basic-api.html
    - bat-arlh-2:         [SKIP][84] ([i915#11681]) -> [SKIP][85] ([i915#10209] / [i915#11681])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arlh-2/igt@i915_pm_rps@basic-api.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arlh-2/igt@i915_pm_rps@basic-api.html
    - bat-arls-2:         [SKIP][86] ([i915#11681]) -> [SKIP][87] ([i915#10209] / [i915#11681])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@i915_pm_rps@basic-api.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@i915_pm_rps@basic-api.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-twl-2:          [SKIP][88] ([i915#11731]) -> [SKIP][89] ([i915#11030] / [i915#11731]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-arls-1:         [SKIP][90] ([i915#11346]) -> [SKIP][91] ([i915#10202] / [i915#11346]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-twl-1:          [SKIP][92] ([i915#11731]) -> [SKIP][93] ([i915#11030] / [i915#11731]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-twl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-arls-5:         [SKIP][94] ([i915#11346]) -> [SKIP][95] ([i915#10202] / [i915#11346]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-arls-2:         [SKIP][96] ([i915#11346]) -> [SKIP][97] ([i915#10202] / [i915#11346]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/bat-arls-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/bat-arls-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
  [i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
  [i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
  [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
  [i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
  [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11030
  [i915#11346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11346
  [i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
  [i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11724]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11724
  [i915#11725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11725
  [i915#11731]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11731
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
  [i915#12216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12216
  [i915#12305]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12305
  [i915#12310]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12310
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886


Build changes
-------------

  * Linux: CI_DRM_15478 -> Patchwork_125571v8

  CI-20190529: 20190529
  CI_DRM_15478: af143300756485947a455fe84414adb35904c230 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8050: 0000bc070385689633718cbab01ab02a524f2c61 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_125571v8: af143300756485947a455fe84414adb35904c230 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/index.html

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✗ Fi.CI.IGT: failure for DP DSC min/max src bpc fixes (rev8)

[Patchwork]

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== Series Details ==

Series: DP DSC min/max src bpc fixes (rev8)
URL   : https://patchwork.freedesktop.org/series/125571/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_15478_full -> Patchwork_125571v8_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_125571v8_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125571v8_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 8)
------------------------------

  Missing    (2): shard-snb-0 shard-dg2-set2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_125571v8_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          ([PASS][1], [PASS][2]) -> [INCOMPLETE][3] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-3/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@kms_draw_crc@draw-method-blt:
    - shard-glk:          [PASS][4] -> [DMESG-WARN][5] +1 other test dmesg-warn
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk2/igt@kms_draw_crc@draw-method-blt.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk7/igt@kms_draw_crc@draw-method-blt.html

  * igt@perf_pmu@busy-accuracy-98:
    - shard-tglu:         ([PASS][6], [PASS][7]) -> [FAIL][8] +4 other tests fail
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-2/igt@perf_pmu@busy-accuracy-98.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-7/igt@perf_pmu@busy-accuracy-98.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-5/igt@perf_pmu@busy-accuracy-98.html

  
#### Warnings ####

  * igt@gem_exec_balancer@nop:
    - shard-mtlp:         ([PASS][9], [DMESG-WARN][10]) -> [DMESG-WARN][11]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@gem_exec_balancer@nop.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-6/igt@gem_exec_balancer@nop.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@gem_exec_balancer@nop.html

  
Known issues
------------

  Here are the changes found in Patchwork_125571v8_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-mtlp:         NOTRUN -> [SKIP][12] ([i915#8411])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-4/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@drm_fdinfo@virtual-busy-hang:
    - shard-dg1:          NOTRUN -> [SKIP][13] ([i915#8414]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@drm_fdinfo@virtual-busy-hang.html

  * igt@drm_fdinfo@virtual-busy-idle-all:
    - shard-mtlp:         NOTRUN -> [SKIP][14] ([i915#8414])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@drm_fdinfo@virtual-busy-idle-all.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          ([PASS][15], [PASS][16]) -> [INCOMPLETE][17] ([i915#7297])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-3/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-tglu:         NOTRUN -> [SKIP][18] ([i915#7697])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#6335])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_engines@invalid-engines:
    - shard-rkl:          [PASS][20] -> [FAIL][21] ([i915#12027])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@gem_ctx_engines@invalid-engines.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-5/igt@gem_ctx_engines@invalid-engines.html

  * igt@gem_eio@reset-stress:
    - shard-dg2:          ([PASS][22], [PASS][23]) -> [FAIL][24] ([i915#5784])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@gem_eio@reset-stress.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@gem_eio@reset-stress.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-pace-solo:
    - shard-glk:          NOTRUN -> [FAIL][25] ([i915#2842]) +1 other test fail
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk7/igt@gem_exec_fair@basic-pace-solo.html

  * igt@gem_exec_reloc@basic-active:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#3281]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-concurrent0:
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#3281]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@gem_exec_reloc@basic-concurrent0.html

  * igt@gem_exec_reloc@basic-cpu-read-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][28] ([i915#3281]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-6/igt@gem_exec_reloc@basic-cpu-read-noreloc.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          ([PASS][29], [PASS][30]) -> [INCOMPLETE][31] ([i915#11441]) +1 other test incomplete
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-10/igt@gem_exec_suspend@basic-s0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-1/igt@gem_exec_suspend@basic-s0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-5/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#4613])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#4613])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_mmap@big-bo:
    - shard-dg1:          NOTRUN -> [SKIP][34] ([i915#4083]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@gem_mmap@big-bo.html
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#4083]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-6/igt@gem_mmap@big-bo.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-dg1:          NOTRUN -> [SKIP][36] ([i915#4077]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_gtt@fault-concurrent-x:
    - shard-mtlp:         NOTRUN -> [SKIP][37] ([i915#4077])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@gem_mmap_gtt@fault-concurrent-x.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#3282]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-rkl:          NOTRUN -> [SKIP][39] ([i915#4270]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-tglu:         NOTRUN -> [SKIP][40] ([i915#4270])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#8428]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-4/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#2527])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          ([PASS][43], [PASS][44]) -> [ABORT][45] ([i915#9820])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb1/igt@i915_module_load@reload-with-fault-injection.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
    - shard-dg1:          ([PASS][46], [PASS][47]) -> [FAIL][48] ([i915#3591]) +1 other test fail
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html

  * igt@i915_pm_rps@reset:
    - shard-tglu:         ([PASS][49], [PASS][50]) -> [ABORT][51] ([i915#12309])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-7/igt@i915_pm_rps@reset.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-4/igt@i915_pm_rps@reset.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@i915_pm_rps@reset.html

  * igt@i915_pm_rps@thresholds-park:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#11681])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@i915_pm_rps@thresholds-park.html

  * igt@i915_pm_rps@waitboost:
    - shard-mtlp:         NOTRUN -> [FAIL][53] ([i915#8346])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@i915_pm_rps@waitboost.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-glk:          [PASS][54] -> [FAIL][55] ([i915#12177])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk4/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
    - shard-glk:          [PASS][56] -> [FAIL][57] ([i915#11859])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk4/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
    - shard-mtlp:         ([PASS][58], [PASS][59]) -> [FAIL][60] ([i915#11808] / [i915#5956]) +1 other test fail
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-1/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-3/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-mtlp:         ([PASS][61], [PASS][62]) -> [FAIL][63] ([i915#5138])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][64] +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-5/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][65] ([i915#4538] / [i915#5286]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#5286])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][67] ([i915#5286])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][68] ([i915#3638])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][69] ([i915#3638])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#4538])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][72] ([i915#6095]) +4 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-edp-1.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#6095]) +46 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-5/igt@kms_ccs@crc-primary-basic-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#6095]) +19 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#10307] / [i915#6095]) +130 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#6095]) +56 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#4087]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([i915#7828]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#7828]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#7828])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@dp-crc-multiple:
    - shard-dg1:          NOTRUN -> [SKIP][81] ([i915#7828])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_chamelium_frames@dp-crc-multiple.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#7828]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#7118] / [i915#9424])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [TIMEOUT][84] ([i915#7173])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_content_protection@atomic-dpms@pipe-a-dp-3.html

  * igt@kms_content_protection@content-type-change:
    - shard-dg1:          NOTRUN -> [SKIP][85] ([i915#9424])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_content_protection@content-type-change.html
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#6944] / [i915#9424])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#3116] / [i915#3299])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][88] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-snb:          NOTRUN -> [SKIP][89]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb1/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#3555])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][91] +98 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk7/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][92] ([i915#11453])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][93] -> [FAIL][94] ([i915#2346])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][95] ([i915#9197]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#3555] / [i915#3840])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#3555] / [i915#3840])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-mtlp:         NOTRUN -> [SKIP][98] ([i915#9337])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#3637] / [i915#3966])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#9934])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-rkl:          NOTRUN -> [SKIP][101] +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_flip@2x-wf_vblank-ts-check.html
    - shard-snb:          ([PASS][102], [PASS][103]) -> [FAIL][104] ([i915#2122]) +4 other tests fail
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb4/igt@kms_flip@2x-wf_vblank-ts-check.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb1/igt@kms_flip@2x-wf_vblank-ts-check.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb4/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg1:          ([PASS][105], [PASS][106]) -> [DMESG-WARN][107] ([i915#4423]) +2 other tests dmesg-warn
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interruptible.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-19/igt@kms_flip@flip-vs-suspend-interruptible.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3:
    - shard-dg1:          [PASS][108] -> [DMESG-WARN][109] ([i915#4423])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][110] ([i915#4839])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk9/igt@kms_flip@flip-vs-suspend@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a2:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][111] ([i915#4839] / [i915#6113])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-11/igt@kms_flip@flip-vs-suspend@c-hdmi-a2.html

  * igt@kms_flip@plain-flip-ts-check@b-hdmi-a2:
    - shard-rkl:          NOTRUN -> [FAIL][112] ([i915#11989]) +1 other test fail
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-5/igt@kms_flip@plain-flip-ts-check@b-hdmi-a2.html

  * igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-dg2:          ([PASS][113], [PASS][114]) -> [SKIP][115] ([i915#5354]) +4 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][116] ([i915#2672] / [i915#3555]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#2587] / [i915#2672]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-dg2:          ([PASS][118], [PASS][119]) -> [SKIP][120] ([i915#3555]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][121] ([i915#2672] / [i915#3555])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][122] ([i915#2587] / [i915#2672])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#1825]) +2 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][124] ([i915#8708]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#5354]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][126] ([i915#1825]) +9 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-tglu:         NOTRUN -> [SKIP][127] +20 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#3458])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][129] +8 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#3023]) +3 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#8708]) +2 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#8708])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][133] ([i915#3555] / [i915#8228])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][134] ([i915#3555] / [i915#8228])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#10656])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#6301])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
    - shard-mtlp:         NOTRUN -> [SKIP][137] +5 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html

  * igt@kms_plane@plane-position-hole:
    - shard-dg2:          ([PASS][138], [PASS][139]) -> [SKIP][140] ([i915#8825])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane@plane-position-hole.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane@plane-position-hole.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane@plane-position-hole.html

  * igt@kms_plane_alpha_blend@constant-alpha-max:
    - shard-dg2:          ([PASS][141], [PASS][142]) -> [SKIP][143] ([i915#7294])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_alpha_blend@constant-alpha-max.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_alpha_blend@constant-alpha-max.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_alpha_blend@constant-alpha-max.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#12247]) +9 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#8152] / [i915#9423])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-c:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#12247]) +2 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-c.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#8152])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20:
    - shard-dg2:          ([PASS][148], [PASS][149]) -> [SKIP][150] ([i915#12247] / [i915#8152] / [i915#9423])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25:
    - shard-dg2:          ([PASS][151], [PASS][152]) -> [SKIP][153] ([i915#6953] / [i915#8152] / [i915#9423])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d:
    - shard-dg2:          ([PASS][154], [PASS][155]) -> [SKIP][156] ([i915#12247] / [i915#8152]) +1 other test skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-dg2:          ([PASS][157], [PASS][158]) -> [SKIP][159] ([i915#3555] / [i915#6953] / [i915#8152] / [i915#9423])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b:
    - shard-dg2:          ([PASS][160], [PASS][161]) -> [SKIP][162] ([i915#12247]) +8 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d:
    - shard-dg2:          ([PASS][163], [PASS][164]) -> [SKIP][165] ([i915#8152])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#9685])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg1:          NOTRUN -> [SKIP][167] ([i915#9685])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-dg2:          ([PASS][168], [PASS][169]) -> [FAIL][170] ([i915#7330])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_pm_dc@dc9-dpms.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_pm_dc@dc9-dpms.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-rkl:          ([PASS][171], [PASS][172]) -> [SKIP][173] ([i915#9519])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [PASS][174] -> [SKIP][175] ([i915#9519])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-tglu:         NOTRUN -> [SKIP][176] ([i915#6524])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_properties@crtc-properties-legacy:
    - shard-dg2:          ([PASS][177], [PASS][178]) -> [SKIP][179] ([i915#11521])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_properties@crtc-properties-legacy.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_properties@crtc-properties-legacy.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_properties@crtc-properties-legacy.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#11520]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-dg1:          NOTRUN -> [SKIP][181] ([i915#11520]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
    - shard-mtlp:         NOTRUN -> [SKIP][182] ([i915#12316]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][183] ([i915#9808])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#11520])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-glk:          NOTRUN -> [SKIP][185] ([i915#11520]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#9683])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-sprite-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][187] ([i915#1072] / [i915#9732]) +1 other test skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html

  * igt@kms_psr@fbc-psr-sprite-plane-move:
    - shard-dg1:          NOTRUN -> [SKIP][188] ([i915#1072] / [i915#9732]) +2 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_psr@fbc-psr-sprite-plane-move.html
    - shard-mtlp:         NOTRUN -> [SKIP][189] ([i915#9688]) +3 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_psr@fbc-psr-sprite-plane-move.html

  * igt@kms_psr@pr-primary-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#1072] / [i915#9732]) +2 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@kms_psr@pr-primary-mmap-gtt.html

  * igt@kms_psr@psr-no-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][191] ([i915#9732]) +3 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_psr@psr-no-drrs.html

  * igt@kms_psr@psr-sprite-mmap-gtt@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][192] ([i915#4077] / [i915#9688]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_psr@psr-sprite-mmap-gtt@edp-1.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-mtlp:         NOTRUN -> [SKIP][193] ([i915#11131])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-mtlp:         NOTRUN -> [SKIP][194] ([i915#5289])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-tglu:         NOTRUN -> [SKIP][195] ([i915#3555])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#8623])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@ts-continuation-modeset:
    - shard-dg2:          ([PASS][197], [PASS][198]) -> [SKIP][199] ([i915#9197]) +32 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_vblank@ts-continuation-modeset.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_vblank@ts-continuation-modeset.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_vblank@ts-continuation-modeset.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][200] ([i915#9906])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-8/igt@kms_vrr@flip-basic-fastset.html

  * igt@prime_mmap_kms@buffer-sharing:
    - shard-dg2:          ([PASS][201], [PASS][202]) -> [SKIP][203]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@prime_mmap_kms@buffer-sharing.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@prime_mmap_kms@buffer-sharing.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@prime_mmap_kms@buffer-sharing.html

  
#### Possible fixes ####

  * igt@fbdev@info:
    - shard-dg2:          ([SKIP][204], [PASS][205]) ([i915#1849] / [i915#2582]) -> [PASS][206]
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@fbdev@info.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@fbdev@info.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@fbdev@info.html

  * igt@fbdev@read:
    - shard-dg2:          ([PASS][207], [SKIP][208]) ([i915#2582]) -> [PASS][209]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@fbdev@read.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@fbdev@read.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@fbdev@read.html

  * igt@gem_ctx_persistence@hostile:
    - shard-tglu:         [FAIL][210] ([i915#11980]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-4/igt@gem_ctx_persistence@hostile.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-6/igt@gem_ctx_persistence@hostile.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          ([FAIL][212], [FAIL][213]) ([i915#5784]) -> [PASS][214]
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-13/igt@gem_eio@unwedge-stress.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-18/igt@gem_eio@unwedge-stress.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][215] ([i915#2842]) -> [PASS][216] +1 other test pass
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-rkl:          ([FAIL][217], [PASS][218]) ([i915#2842]) -> [PASS][219] +1 other test pass
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-tglu:         ([FAIL][220], [PASS][221]) ([i915#2842]) -> [PASS][222] +1 other test pass
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          ([ABORT][223], [PASS][224]) ([i915#9820]) -> [PASS][225]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@i915_module_load@reload-with-fault-injection.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
    - shard-dg1:          ([ABORT][226], [PASS][227]) ([i915#9820]) -> [PASS][228]
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-14/igt@i915_module_load@reload-with-fault-injection.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-19/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          ([PASS][229], [INCOMPLETE][230]) ([i915#7790]) -> [PASS][231]
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb6/igt@i915_pm_rps@reset.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb2/igt@i915_pm_rps@reset.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb6/igt@i915_pm_rps@reset.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [INCOMPLETE][232] ([i915#4817]) -> [PASS][233]
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-tglu:         ([PASS][234], [FAIL][235]) ([i915#10991]) -> [PASS][236] +1 other test pass
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-6/igt@kms_async_flips@alternate-sync-async-flip.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-3/igt@kms_async_flips@alternate-sync-async-flip.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-7/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-glk:          [FAIL][237] ([i915#12238]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk3/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs:
    - shard-glk:          [FAIL][239] ([i915#11859]) -> [PASS][240]
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk3/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@2x-outputs.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-dg2:          ([PASS][241], [SKIP][242]) ([i915#9197]) -> [PASS][243] +66 other tests pass
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-180:
    - shard-rkl:          ([PASS][244], [ABORT][245]) ([i915#10354]) -> [PASS][246]
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-5/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-7/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-3/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-dg1:          [INCOMPLETE][247] ([i915#2295]) -> [PASS][248]
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-14/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-16/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [FAIL][249] ([i915#2346]) -> [PASS][250]
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-snb:          [FAIL][251] -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
    - shard-mtlp:         ([FAIL][253], [PASS][254]) ([i915#2346]) -> [PASS][255]
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-dg2:          ([PASS][256], [SKIP][257]) ([i915#1849]) -> [PASS][258]
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_fbcon_fbt@fbc.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_fbcon_fbt@fbc.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-rkl:          ([FAIL][259], [PASS][260]) ([i915#4767]) -> [PASS][261]
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-5/igt@kms_fbcon_fbt@fbc-suspend.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@kms_fbcon_fbt@fbc-suspend.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1:
    - shard-snb:          ([PASS][262], [FAIL][263]) ([i915#2122]) -> [PASS][264] +1 other test pass
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb5/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html

  * igt@kms_flip@dpms-vs-vblank-race:
    - shard-mtlp:         ([PASS][265], [FAIL][266]) -> [PASS][267] +1 other test pass
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-2/igt@kms_flip@dpms-vs-vblank-race.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-4/igt@kms_flip@dpms-vs-vblank-race.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-4/igt@kms_flip@dpms-vs-vblank-race.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-rkl:          [FAIL][268] ([i915#2122]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
    - shard-mtlp:         ([FAIL][270], [PASS][271]) ([i915#2122]) -> [PASS][272]
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check@b-edp1:
    - shard-mtlp:         ([FAIL][273], [FAIL][274]) ([i915#11989]) -> [PASS][275]
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-7/igt@kms_flip@plain-flip-ts-check@b-edp1.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@kms_flip@plain-flip-ts-check@b-edp1.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@kms_flip@plain-flip-ts-check@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check@c-edp1:
    - shard-mtlp:         ([FAIL][276], [FAIL][277]) ([i915#2122]) -> [PASS][278]
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-7/igt@kms_flip@plain-flip-ts-check@c-edp1.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@kms_flip@plain-flip-ts-check@c-edp1.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@kms_flip@plain-flip-ts-check@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check@d-hdmi-a1:
    - shard-tglu:         ([PASS][279], [FAIL][280]) ([i915#2122]) -> [PASS][281] +4 other tests pass
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-8/igt@kms_flip@plain-flip-ts-check@d-hdmi-a1.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-9/igt@kms_flip@plain-flip-ts-check@d-hdmi-a1.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-2/igt@kms_flip@plain-flip-ts-check@d-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-dg2:          ([PASS][282], [SKIP][283]) ([i915#3555]) -> [PASS][284] +7 other tests pass
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-dg2:          ([FAIL][285], [SKIP][286]) ([i915#5354] / [i915#6880]) -> [PASS][287]
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-snb:          ([SKIP][288], [SKIP][289]) -> [PASS][290] +1 other test pass
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
    - shard-dg2:          ([SKIP][291], [PASS][292]) ([i915#5354]) -> [PASS][293] +24 other tests pass
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html

  * igt@kms_hdr@static-swap:
    - shard-dg2:          ([SKIP][294], [SKIP][295]) ([i915#3555] / [i915#8228] / [i915#9197]) -> [PASS][296]
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_hdr@static-swap.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_hdr@static-swap.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          ([SKIP][297], [SKIP][298]) ([i915#3555] / [i915#8228]) -> [PASS][299] +1 other test pass
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_hdr@static-toggle-suspend.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_hdr@static-toggle-suspend.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-dg2:          ([PASS][300], [INCOMPLETE][301]) ([i915#1982]) -> [PASS][302]
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-10/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
    - shard-dg1:          ([INCOMPLETE][303], [PASS][304]) ([i915#1982]) -> [PASS][305]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-12/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-14/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-14/igt@kms_pipe_crc_basic@suspend-read-crc.html
    - shard-mtlp:         ([INCOMPLETE][306], [INCOMPLETE][307]) -> [PASS][308] +1 other test pass
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-5/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-1/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_plane@planar-pixel-format-settings:
    - shard-dg2:          ([PASS][309], [SKIP][310]) ([i915#9581]) -> [PASS][311]
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_plane@planar-pixel-format-settings.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane@planar-pixel-format-settings.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_plane@planar-pixel-format-settings.html

  * igt@kms_plane@plane-panning-bottom-right:
    - shard-dg2:          ([SKIP][312], [PASS][313]) ([i915#8825]) -> [PASS][314]
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane@plane-panning-bottom-right.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_plane@plane-panning-bottom-right.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_plane@plane-panning-bottom-right.html

  * igt@kms_plane_alpha_blend@alpha-7efc:
    - shard-dg2:          ([PASS][315], [SKIP][316]) ([i915#7294]) -> [PASS][317] +1 other test pass
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_plane_alpha_blend@alpha-7efc.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_alpha_blend@alpha-7efc.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_plane_alpha_blend@alpha-7efc.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-rkl:          ([FAIL][318], [PASS][319]) ([i915#8292]) -> [PASS][320]
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@kms_plane_scaling@intel-max-src-size.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d:
    - shard-dg2:          ([SKIP][321], [PASS][322]) ([i915#8152]) -> [PASS][323] +1 other test pass
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-d.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation:
    - shard-dg2:          ([SKIP][324], [PASS][325]) ([i915#12247] / [i915#8152] / [i915#9423]) -> [PASS][326] +1 other test pass
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling:
    - shard-dg2:          ([SKIP][327], [PASS][328]) ([i915#12247] / [i915#3558] / [i915#8152] / [i915#9423]) -> [PASS][329]
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html

  * igt@kms_plane_scaling@planes-scaler-unity-scaling:
    - shard-dg2:          ([SKIP][330], [PASS][331]) ([i915#3555] / [i915#8152] / [i915#9423]) -> [PASS][332] +1 other test pass
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-scaler-unity-scaling.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_plane_scaling@planes-scaler-unity-scaling.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_plane_scaling@planes-scaler-unity-scaling.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b:
    - shard-dg2:          ([PASS][333], [SKIP][334]) ([i915#12247]) -> [PASS][335] +26 other tests pass
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-20x20:
    - shard-dg2:          ([SKIP][336], [PASS][337]) ([i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][338] +1 other test pass
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_plane_scaling@planes-upscale-20x20.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_plane_scaling@planes-upscale-20x20.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-dg2:          ([PASS][339], [SKIP][340]) ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][341]
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d:
    - shard-dg2:          ([PASS][342], [SKIP][343]) ([i915#12247] / [i915#8152]) -> [PASS][344] +6 other tests pass
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-dg2:          ([PASS][345], [SKIP][346]) ([i915#12247] / [i915#6953] / [i915#8152] / [i915#9423]) -> [PASS][347]
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         ([PASS][348], [FAIL][349]) ([i915#9295]) -> [PASS][350]
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-7/igt@kms_pm_dc@dc6-dpms.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         ([SKIP][351], [PASS][352]) ([i915#4281]) -> [PASS][353]
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-5/igt@kms_pm_dc@dc9-dpms.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-5/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          ([PASS][354], [SKIP][355]) ([i915#9519]) -> [PASS][356] +2 other tests pass
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-dg2:          ([SKIP][357], [PASS][358]) ([i915#3547]) -> [PASS][359]
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_pm_rpm@drm-resources-equal.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_pm_rpm@drm-resources-equal.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg2:          ([PASS][360], [SKIP][361]) -> [PASS][362]
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_pm_rpm@i2c.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_pm_rpm@i2c.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          ([SKIP][363], [SKIP][364]) ([i915#9519]) -> [PASS][365] +1 other test pass
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][366] ([i915#9519]) -> [PASS][367]
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg2:          ([SKIP][368], [PASS][369]) ([i915#9519]) -> [PASS][370] +3 other tests pass
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_properties@get_properties-sanity-atomic:
    - shard-dg1:          ([DMESG-WARN][371], [PASS][372]) ([i915#4423]) -> [PASS][373] +1 other test pass
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-17/igt@kms_properties@get_properties-sanity-atomic.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-13/igt@kms_properties@get_properties-sanity-atomic.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-15/igt@kms_properties@get_properties-sanity-atomic.html

  * igt@kms_universal_plane@cursor-fb-leak:
    - shard-mtlp:         ([PASS][374], [FAIL][375]) ([i915#9196]) -> [PASS][376] +1 other test pass
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak.html

  * igt@perf_pmu@busy-double-start@bcs0:
    - shard-mtlp:         ([FAIL][377], [PASS][378]) ([i915#4349]) -> [PASS][379]
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@perf_pmu@busy-double-start@bcs0.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-6/igt@perf_pmu@busy-double-start@bcs0.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-8/igt@perf_pmu@busy-double-start@bcs0.html

  
#### Warnings ####

  * igt@gem_ctx_engines@invalid-engines:
    - shard-tglu:         ([PASS][380], [FAIL][381]) ([i915#12027]) -> [FAIL][382] ([i915#12027])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-9/igt@gem_ctx_engines@invalid-engines.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-8/igt@gem_ctx_engines@invalid-engines.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-2/igt@gem_ctx_engines@invalid-engines.html
    - shard-mtlp:         ([FAIL][383], [PASS][384]) ([i915#12027]) -> [FAIL][385] ([i915#12027])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-8/igt@gem_ctx_engines@invalid-engines.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-7/igt@gem_ctx_engines@invalid-engines.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@gem_ctx_engines@invalid-engines.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglu:         ([FAIL][386], [FAIL][387]) ([i915#2842] / [i915#2876]) -> [FAIL][388] ([i915#2842])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-10/igt@gem_exec_fair@basic-pace@rcs0.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-10/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          ([ABORT][389], [PASS][390]) ([i915#9820]) -> [ABORT][391] ([i915#9820])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu:         ([PASS][392], [ABORT][393]) ([i915#10887] / [i915#9820]) -> [ABORT][394] ([i915#9820])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-9/igt@i915_module_load@reload-with-fault-injection.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         ([PASS][395], [ABORT][396]) ([i915#10131] / [i915#9820]) -> [ABORT][397] ([i915#10131] / [i915#9820])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2:          ([SKIP][398], [SKIP][399]) ([i915#7091]) -> [SKIP][400] ([i915#9197])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@i915_selftest@mock:
    - shard-glk:          [DMESG-WARN][401] ([i915#9311]) -> [DMESG-WARN][402] ([i915#1982] / [i915#9311])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-glk7/igt@i915_selftest@mock.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-glk4/igt@i915_selftest@mock.html
    - shard-dg2:          ([DMESG-WARN][403], [DMESG-WARN][404]) ([i915#1982] / [i915#9311]) -> [DMESG-WARN][405] ([i915#9311])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@i915_selftest@mock.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@i915_selftest@mock.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-5/igt@i915_selftest@mock.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-dg2:          ([SKIP][406], [SKIP][407]) ([i915#1769] / [i915#3555]) -> [SKIP][408] ([i915#9197])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2:          ([SKIP][409], [SKIP][410]) -> [SKIP][411] ([i915#9197]) +2 other tests skip
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         ([PASS][412], [FAIL][413]) ([i915#5138]) -> [FAIL][414] ([i915#5138])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-dg2:          ([SKIP][415], [SKIP][416]) ([i915#9197]) -> [SKIP][417] +4 other tests skip
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-0:
    - shard-dg2:          ([SKIP][418], [SKIP][419]) ([i915#4538] / [i915#5190] / [i915#9197]) -> [SKIP][420] ([i915#4538] / [i915#5190]) +14 other tests skip
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2:          ([SKIP][421], [SKIP][422]) ([i915#4538] / [i915#5190]) -> [SKIP][423] ([i915#5190] / [i915#9197]) +4 other tests skip
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
    - shard-dg2:          ([SKIP][424], [SKIP][425]) ([i915#10307] / [i915#6095] / [i915#9197]) -> [SKIP][426] ([i915#10307] / [i915#6095]) +19 other tests skip
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-dg2:          ([SKIP][427], [SKIP][428]) ([i915#12313]) -> [SKIP][429] ([i915#9197]) +2 other tests skip
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg2:          ([SKIP][430], [SKIP][431]) ([i915#12313] / [i915#9197]) -> [SKIP][432] ([i915#12313]) +1 other test skip
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - shard-dg2:          ([SKIP][433], [SKIP][434]) ([i915#10307] / [i915#6095]) -> [SKIP][435] ([i915#9197]) +6 other tests skip
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition:
    - shard-dg2:          ([SKIP][436], [SKIP][437]) ([i915#11616] / [i915#7213] / [i915#9197]) -> [SKIP][438] ([i915#11616] / [i915#7213])
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_cdclk@mode-transition.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cdclk@mode-transition.html
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_cdclk@mode-transition.html

  * igt@kms_color@deep-color:
    - shard-dg2:          ([SKIP][439], [SKIP][440]) ([i915#3555] / [i915#5354]) -> [SKIP][441] ([i915#3555])
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_color@deep-color.html
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_color@deep-color.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          ([SKIP][442], [SKIP][443]) ([i915#7118] / [i915#9424]) -> [TIMEOUT][444] ([i915#7173])
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_content_protection@atomic-dpms.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_content_protection@atomic-dpms.html
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
    - shard-snb:          ([SKIP][445], [SKIP][446]) -> [INCOMPLETE][447] ([i915#8816])
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb1/igt@kms_content_protection@atomic-dpms.html
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-snb4/igt@kms_content_protection@atomic-dpms.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-snb4/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2:          ([SKIP][448], [SKIP][449]) ([i915#3299] / [i915#9197]) -> [SKIP][450] ([i915#3299])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_content_protection@dp-mst-type-0.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_content_protection@dp-mst-type-0.html
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@lic-type-1:
    - shard-dg2:          ([SKIP][451], [SKIP][452]) ([i915#9424]) -> [SKIP][453] ([i915#9197])
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_content_protection@lic-type-1.html
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_content_protection@lic-type-1.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_content_protection@lic-type-1.html
    - shard-dg1:          ([SKIP][454], [SKIP][455]) ([i915#9424]) -> [SKIP][456] ([i915#4423] / [i915#9424])
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-17/igt@kms_content_protection@lic-type-1.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-19/igt@kms_content_protection@lic-type-1.html
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-17/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg2:          ([SKIP][457], [SKIP][458]) ([i915#9197] / [i915#9424]) -> [SKIP][459] ([i915#9424])
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_content_protection@mei-interface.html
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_content_protection@mei-interface.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-1/igt@kms_content_protection@mei-interface.html
    - shard-dg1:          ([SKIP][460], [SKIP][461]) ([i915#9424] / [i915#9433]) -> [SKIP][462] ([i915#9424])
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-12/igt@kms_content_protection@mei-interface.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-18/igt@kms_content_protection@mei-interface.html
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-15/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          ([SKIP][463], [SKIP][464]) ([i915#7118] / [i915#9424]) -> [SKIP][465] ([i915#7118] / [i915#7162] / [i915#9424])
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_content_protection@type1.html
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_content_protection@type1.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2:          ([SKIP][466], [SKIP][467]) ([i915#11453] / [i915#9197]) -> [SKIP][468] ([i915#11453]) +1 other test skip
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg2:          ([SKIP][469], [SKIP][470]) ([i915#3555]) -> [SKIP][471] ([i915#9197]) +2 other tests skip
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-32x10.html
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_cursor_crc@cursor-sliding-32x10.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg2:          ([SKIP][472], [SKIP][473]) ([i915#11453]) -> [SKIP][474] ([i915#9197])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2:          ([SKIP][475], [SKIP][476]) ([i915#4103] / [i915#4213] / [i915#9197]) -> [SKIP][477] ([i915#4103] / [i915#4213]) +2 other tests skip
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
    - shard-dg2:          ([SKIP][478], [SKIP][479]) ([i915#5354]) -> [SKIP][480] ([i915#9197])
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-dg2:          ([SKIP][481], [SKIP][482]) ([i915#5354] / [i915#9197]) -> [SKIP][483] ([i915#5354]) +9 other tests skip
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-dg2:          ([SKIP][484], [SKIP][485]) ([i915#9197] / [i915#9833]) -> [SKIP][486] ([i915#9833])
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2:          ([SKIP][487], [SKIP][488]) ([i915#8588] / [i915#9197]) -> [SKIP][489] ([i915#8588])
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-5/igt@kms_display_modes@mst-extended-mode-negative.html
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_display_modes@mst-extended-mode-negative.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-10/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-dg2:          ([SKIP][490], [PASS][491]) ([i915#3555]) -> [SKIP][492] ([i915#3555])
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          ([SKIP][493], [SKIP][494]) ([i915#3555] / [i915#9197]) -> [SKIP][495] ([i915#3555]) +6 other tests skip
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg2:          ([SKIP][496], [SKIP][497]) ([i915#8812] / [i915#9197]) -> [SKIP][498] ([i915#8812])
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-7/igt@kms_draw_crc@draw-method-mmap-wc.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-wc.html
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-8/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2:          ([SKIP][499], [SKIP][500]) ([i915#3840] / [i915#9197] / [i915#9688]) -> [SKIP][501] ([i915#3840] / [i915#9688])
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_dsc@dsc-fractional-bpp.html
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-4/igt@kms_dsc@dsc-fractional-bpp.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-7/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2:          ([SKIP][502], [SKIP][503]) ([i915#3840] / [i915#9197]) -> [SKIP][504] ([i915#3840])
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-3/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-4/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fence_pin_leak:
    - shard-dg2:          ([SKIP][505], [SKIP][506]) ([i915#4881]) -> [SKIP][507] ([i915#9197])
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-8/igt@kms_fence_pin_leak.html
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg2-6/igt@kms_fence_pin_leak.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg2-2/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-dg1:          ([SKIP][508], [SKIP][509]) ([i915#4423]) -> [SKIP][510]
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-13/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15478/shard-dg1-17/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/shard-dg1-15/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-dg1:          ([SKIP][5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125571v8/index.html

[-- Attachment #2: Type: text/html, Size: 106455 bytes --]

RE: [PATCH 4/7] drm/i915/dp: Drop max_requested_bpc for dsc pipe_min/max bpp

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 4/7] drm/i915/dp: Drop max_requested_bpc for dsc
> pipe_min/max bpp
> 
> Currently we are including both max_requested_bpc and
> limits->pipe.bpp_max while computing maximum possible pipe bpp with
> dsc.
> However, while setting limits->pipe.max_bpp, the max_requested_bpc is
> already taken into account.
> 
> Drop the redundant check for max_requested_bpc and use only
> limits->pipe.bpp_max. This will also result in dropping conn_state
> argument in functions where it was used only to get max_requested_bpc.
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++----------
>  1 file changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b553b24604e1..46f3b680afe9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2167,14 +2167,13 @@ int intel_dp_dsc_min_src_input_bpc(struct
> intel_display *display)
> 
>  static
>  bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
> -				struct drm_connector_state *conn_state,
>  				struct link_config_limits *limits,
>  				int pipe_bpp)
>  {
>  	struct intel_display *display = to_intel_display(&i915->drm);
>  	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp,
> dsc_min_pipe_bpp;
> 
> -	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(display),
> conn_state->max_requested_bpc);
> +	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>  	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> 
>  	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> @@ -2186,7 +2185,6 @@ bool is_dsc_pipe_bpp_sufficient(struct
> drm_i915_private *i915,
> 
>  static
>  int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
> -				struct drm_connector_state *conn_state,
>  				struct link_config_limits *limits)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -2197,7
> +2195,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
> 
>  	forced_bpp = intel_dp->force_dsc_bpc * 3;
> 
> -	if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp))
> {
> +	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
>  		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
> intel_dp->force_dsc_bpc);
>  		return forced_bpp;
>  	}
> @@ -2217,14 +2215,13 @@ static int
> intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	const struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> -	int max_req_bpc = conn_state->max_requested_bpc;
>  	int dsc_max_bpc, dsc_max_bpp;
>  	int dsc_min_bpc, dsc_min_bpp;
>  	u8 dsc_bpc[3] = {};
>  	int forced_bpp, pipe_bpp;
>  	int num_bpc, i, ret;
> 
> -	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state,
> limits);
> +	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
> 
>  	if (forced_bpp) {
>  		ret = dsc_compute_compressed_bpp(intel_dp, connector,
> pipe_config, @@ -2239,7 +2236,6 @@ static int
> intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	if (!dsc_max_bpc)
>  		return -EINVAL;
> 
> -	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
>  	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> 
>  	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> @@ -2279,16 +2275,16 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
>  	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> 
> -	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state,
> limits);
> +	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
> 
>  	if (forced_bpp) {
>  		pipe_bpp = forced_bpp;
>  	} else {
> -		int max_bpc = min(limits->pipe.max_bpp / 3,
> (int)conn_state->max_requested_bpc);
> +		int max_bpc = limits->pipe.max_bpp / 3;
> 
>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector,
> max_bpc);
> -		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits,
> pipe_bpp)) {
> +		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC
> limits\n");
>  			return -EINVAL;
> --
> 2.45.2

RE: [PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc
> 
> With DSC there are additional limits for pipe_bpp. Currently these are
> scattered in different places.
> Instead set the limits->pipe.max/min_bpp in one place and use them
> wherever required.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++++---------------
>  1 file changed, 17 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 46f3b680afe9..55ee438a4fec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2166,21 +2166,11 @@ int intel_dp_dsc_min_src_input_bpc(struct
> intel_display *display)  }
> 
>  static
> -bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
> -				struct link_config_limits *limits,
> +bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
>  				int pipe_bpp)
>  {
> -	struct intel_display *display = to_intel_display(&i915->drm);
> -	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp,
> dsc_min_pipe_bpp;
> -
> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> -
> -	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> -	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
> -
> -	return pipe_bpp >= dsc_min_pipe_bpp &&
> -	       pipe_bpp <= dsc_max_pipe_bpp;
> +	return pipe_bpp >= limits->pipe.min_bpp &&
> +	       pipe_bpp <= limits->pipe.max_bpp;
>  }
> 
>  static
> @@ -2195,7 +2185,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp
> *intel_dp,
> 
>  	forced_bpp = intel_dp->force_dsc_bpc * 3;
> 
> -	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
> +	if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
>  		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
> intel_dp->force_dsc_bpc);
>  		return forced_bpp;
>  	}
> @@ -2212,11 +2202,10 @@ static int
> intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  					 struct link_config_limits *limits,
>  					 int timeslots)
>  {
> -	struct intel_display *display = to_intel_display(intel_dp);
>  	const struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> -	int dsc_max_bpc, dsc_max_bpp;
> -	int dsc_min_bpc, dsc_min_bpp;
> +	int dsc_max_bpp;
> +	int dsc_min_bpp;
>  	u8 dsc_bpc[3] = {};
>  	int forced_bpp, pipe_bpp;
>  	int num_bpc, i, ret;
> @@ -2232,14 +2221,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
>  		}
>  	}
> 
> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
> -	if (!dsc_max_bpc)
> -		return -EINVAL;
> -
> -	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> -
> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> -	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
> +	dsc_max_bpp = limits->pipe.max_bpp;
> +	dsc_min_bpp = limits->pipe.min_bpp;
> 
>  	/*
>  	 * Get the maximum DSC bpc that will be supported by any valid
> @@ -2284,7 +2267,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
> 
>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector,
> max_bpc);
> -		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
> +		if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC
> limits\n");
>  			return -EINVAL;
> @@ -2502,6 +2485,14 @@ intel_dp_compute_config_limits(struct intel_dp
> *intel_dp,
>  	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state-
> >output_format);
>  	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> 
> respect_downstream_limits);
> +	if (dsc) {
> +		struct intel_display *display = to_intel_display(intel_dp);
> +		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> +		int dsc_max_bpc =
> intel_dp_dsc_max_src_input_bpc(display);
> +
> +		limits->pipe.max_bpp = min(limits->pipe.max_bpp,
> dsc_max_bpc * 3);
> +		limits->pipe.min_bpp = max(limits->pipe.min_bpp,
> dsc_min_bpc * 3);
> +	}
> 
>  	if (intel_dp->use_max_params) {
>  		/*
> --
> 2.45.2

RE: [PATCH 6/7] drm/i915/dp: Use clamp for pipe_bpp limits with DSC

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 6/7] drm/i915/dp: Use clamp for pipe_bpp limits with DSC
> 
> Currently to get the max pipe_bpp with dsc we take the min of
> limits->pipe.max_bpp and dsc max bpp (dsc max bpc * 3). This can result
> in problems when limits->pipe.max_bpp is less than the computed dsc min
> bpp (dsc min bpc * 3).
> 
> Replace the min/max functions with clamp while computing
> limits->pipe.max/min_bpp to ensure that the pipe_bpp limits are
> limits->constrained
> within the DSC-defined minimum and maximum values.
> 

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 55ee438a4fec..02009ae03840 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2490,8 +2490,11 @@ intel_dp_compute_config_limits(struct intel_dp
> *intel_dp,
>  		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>  		int dsc_max_bpc =
> intel_dp_dsc_max_src_input_bpc(display);
> 
> -		limits->pipe.max_bpp = min(limits->pipe.max_bpp,
> dsc_max_bpc * 3);
> -		limits->pipe.min_bpp = max(limits->pipe.min_bpp,
> dsc_min_bpc * 3);
> +		limits->pipe.max_bpp = clamp(limits->pipe.max_bpp,
> +					     dsc_min_bpc * 3, dsc_max_bpc *
> 3);
> +
> +		limits->pipe.min_bpp = clamp(limits->pipe.min_bpp,
> +					     dsc_min_bpc * 3, dsc_max_bpc *
> 3);
>  	}
> 
>  	if (intel_dp->use_max_params) {
> --
> 2.45.2

RE: [PATCH 7/7] drm/i915/dp: Set the DSC link limits intel_dp_compute_config_link_bpp_limits

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 7/7] drm/i915/dp: Set the DSC link limits
> intel_dp_compute_config_link_bpp_limits
> 
> The helper intel_dp_compute_config_link_bpp_limits is the correct place to
> set the DSC link limits. Move the code to this function and remove the
> #TODO item.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++------------
> drivers/gpu/drm/i915/display/intel_dp.h |  4 +-
>  2 files changed, 35 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 02009ae03840..bfc31b3af864 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1958,7 +1958,7 @@ static int dsc_compute_link_config(struct intel_dp
> *intel_dp,
> 
>  static
>  u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct
> intel_connector *connector,
> -					    struct intel_crtc_state
> *pipe_config,
> +					    const struct intel_crtc_state
> *pipe_config,
>  					    int bpc)
>  {
>  	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector-
> >dp.dsc_dpcd);
> @@ -1983,7 +1983,7 @@ u16
> intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector
> *connec
>  	return 0;
>  }
> 
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config)
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state
> +*pipe_config)
>  {
>  	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
>  	switch (pipe_config->output_format) {
> @@ -2001,7 +2001,7 @@ int
> intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config)  }
> 
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector
> *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state
> *pipe_config,
>  					 int bpc)
>  {
>  	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
> @@ -2130,21 +2130,16 @@ static int dsc_compute_compressed_bpp(struct
> intel_dp *intel_dp,  {
>  	const struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode;
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
>  	int dsc_joiner_max_bpp;
>  	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
> 
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits-
> >link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
> 
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp /
> 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp,
> dsc_src_max_bpp) : dsc_src_max_bpp;
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
> 
>  	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915,
> adjusted_mode->clock,
> 
> 	adjusted_mode->hdisplay,
> @@ -2255,8 +2250,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	int pipe_bpp, forced_bpp;
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
> 
>  	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
> 
> @@ -2276,16 +2271,12 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	pipe_config->port_clock = limits->max_rate;
>  	pipe_config->lane_count = limits->max_lane_count;
> 
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits-
> >link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
> +
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
> 
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp /
> 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp,
> dsc_src_max_bpp) : dsc_src_max_bpp;
>  	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits-
> >link.max_bpp_x16));
> 
>  	/* Compressed BPP should be less than the Input DSC bpp */ @@ -
> 2428,6 +2419,7 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_dp *intel_dp,
>  		&crtc_state->hw.adjusted_mode;
>  	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)-
> >base;
> +	struct intel_connector *connector = intel_dp->attached_connector;
>  	int max_link_bpp_x16;
> 
>  	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, @@ -
> 2441,12 +2433,22 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_dp *intel_dp,
> 
>  		limits->link.min_bpp_x16 = fxp_q4_from_int(limits-
> >pipe.min_bpp);
>  	} else {
> -		/*
> -		 * TODO: set the DSC link limits already here, atm these are
> -		 * initialized only later in
> intel_edp_dsc_compute_pipe_bpp() /
> -		 * intel_dp_dsc_compute_pipe_bpp()
> -		 */
> -		limits->link.min_bpp_x16 = 0;
> +		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> +		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +
> +		dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> +		dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
> +		dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> +		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
> +
> +		dsc_src_max_bpp =
> dsc_src_max_compressed_bpp(intel_dp);
> +		dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> +
> 	crtc_state,
> +									limits-
> >pipe.max_bpp / 3);
> +		dsc_max_bpp = dsc_sink_max_bpp ?
> +			      min(dsc_sink_max_bpp, dsc_src_max_bpp) :
> dsc_src_max_bpp;
> +
> +		max_link_bpp_x16 = min(max_link_bpp_x16,
> +fxp_q4_from_int(dsc_max_bpp));
>  	}
> 
>  	limits->link.max_bpp_x16 = max_link_bpp_x16; diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 8bd0bb4ec0e1..d4ca00ba49b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -145,9 +145,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
> drm_i915_private *i915,
>  					enum intel_output_format
> output_format,
>  					u32 pipe_bpp,
>  					u32 timeslots);
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config);
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state
> +*pipe_config);
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector
> *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state
> *pipe_config,
>  					 int bpc);
>  u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  				int mode_clock, int mode_hdisplay,
> --
> 2.45.2

RE: [PATCH 7/7] drm/i915/dp: Set the DSC link limits intel_dp_compute_config_link_bpp_limits

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Thursday, October 3, 2024 4:14 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal@intel.com>; jani.nikula@linux.intel.com
> Subject: [PATCH 7/7] drm/i915/dp: Set the DSC link limits
> intel_dp_compute_config_link_bpp_limits
> 
> The helper intel_dp_compute_config_link_bpp_limits is the correct place to
> set the DSC link limits. Move the code to this function and remove the
> #TODO item.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++------------
> drivers/gpu/drm/i915/display/intel_dp.h |  4 +-
>  2 files changed, 35 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 02009ae03840..bfc31b3af864 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1958,7 +1958,7 @@ static int dsc_compute_link_config(struct intel_dp
> *intel_dp,
> 
>  static
>  u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct
> intel_connector *connector,
> -					    struct intel_crtc_state
> *pipe_config,
> +					    const struct intel_crtc_state
> *pipe_config,
>  					    int bpc)
>  {
>  	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector-
> >dp.dsc_dpcd);
> @@ -1983,7 +1983,7 @@ u16
> intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector
> *connec
>  	return 0;
>  }
> 
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config)
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state
> +*pipe_config)
>  {
>  	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
>  	switch (pipe_config->output_format) {
> @@ -2001,7 +2001,7 @@ int
> intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config)  }
> 
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector
> *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state
> *pipe_config,
>  					 int bpc)
>  {
>  	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
> @@ -2130,21 +2130,16 @@ static int dsc_compute_compressed_bpp(struct
> intel_dp *intel_dp,  {
>  	const struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode;
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
>  	int dsc_joiner_max_bpp;
>  	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
> 
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits-
> >link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
> 
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp /
> 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp,
> dsc_src_max_bpp) : dsc_src_max_bpp;
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
> 
>  	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915,
> adjusted_mode->clock,
> 
> 	adjusted_mode->hdisplay,
> @@ -2255,8 +2250,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	int pipe_bpp, forced_bpp;
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
> 
>  	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
> 
> @@ -2276,16 +2271,12 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	pipe_config->port_clock = limits->max_rate;
>  	pipe_config->lane_count = limits->max_lane_count;
> 
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits-
> >link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
> +
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
> 
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp /
> 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp,
> dsc_src_max_bpp) : dsc_src_max_bpp;
>  	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits-
> >link.max_bpp_x16));
> 
>  	/* Compressed BPP should be less than the Input DSC bpp */ @@ -
> 2428,6 +2419,7 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_dp *intel_dp,
>  		&crtc_state->hw.adjusted_mode;
>  	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)-
> >base;
> +	struct intel_connector *connector = intel_dp->attached_connector;
>  	int max_link_bpp_x16;
> 
>  	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, @@ -
> 2441,12 +2433,22 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_dp *intel_dp,
> 
>  		limits->link.min_bpp_x16 = fxp_q4_from_int(limits-
> >pipe.min_bpp);
>  	} else {
> -		/*
> -		 * TODO: set the DSC link limits already here, atm these are
> -		 * initialized only later in
> intel_edp_dsc_compute_pipe_bpp() /
> -		 * intel_dp_dsc_compute_pipe_bpp()
> -		 */
> -		limits->link.min_bpp_x16 = 0;
> +		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> +		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +
> +		dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> +		dsc_sink_min_bpp =
> intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
> +		dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> +		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
> +
> +		dsc_src_max_bpp =
> dsc_src_max_compressed_bpp(intel_dp);
> +		dsc_sink_max_bpp =
> intel_dp_dsc_sink_max_compressed_bpp(connector,
> +
> 	crtc_state,
> +									limits-
> >pipe.max_bpp / 3);
> +		dsc_max_bpp = dsc_sink_max_bpp ?
> +			      min(dsc_sink_max_bpp, dsc_src_max_bpp) :
> dsc_src_max_bpp;
> +
> +		max_link_bpp_x16 = min(max_link_bpp_x16,
> +fxp_q4_from_int(dsc_max_bpp));
>  	}
> 
>  	limits->link.max_bpp_x16 = max_link_bpp_x16; diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 8bd0bb4ec0e1..d4ca00ba49b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -145,9 +145,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct
> drm_i915_private *i915,
>  					enum intel_output_format
> output_format,
>  					u32 pipe_bpp,
>  					u32 timeslots);
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state
> *pipe_config);
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state
> +*pipe_config);
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector
> *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state
> *pipe_config,
>  					 int bpc);
>  u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  				int mode_clock, int mode_hdisplay,
> --
> 2.45.2

Re: [PATCH 1/7] drm/i915/dp: Use HAS_DSC macro in intel_dp_dsc_max_src_input_bpc

[Imre Deak]

On Thu, Oct 03, 2024 at 04:13:37PM +0530, Ankit Nautiyal wrote:
> Use HAS_DSC macro to take into account platforms for which DSC is fused.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c4fdae5097ec..c47748905506 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1766,6 +1766,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  static
>  u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
>  {
> +	if (!HAS_DSC(i915))

This is checked already earlier via intel_dp_has_dsc(), couldn't we rely
on that instead of checking it in these lower level functions?

> +		return 0;
> +
>  	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
>  	if (DISPLAY_VER(i915) >= 12)
>  		return 12;
> -- 
> 2.45.2
> 

Re: [PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc

[Imre Deak]

On Thu, Oct 03, 2024 at 04:13:41PM +0530, Ankit Nautiyal wrote:
> With DSC there are additional limits for pipe_bpp. Currently these are
> scattered in different places.
> Instead set the limits->pipe.max/min_bpp in one place and use them
> wherever required.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++++---------------
>  1 file changed, 17 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 46f3b680afe9..55ee438a4fec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2166,21 +2166,11 @@ int intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
>  }
>  
>  static
> -bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
> -				struct link_config_limits *limits,
> +bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
>  				int pipe_bpp)
>  {
> -	struct intel_display *display = to_intel_display(&i915->drm);
> -	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
> -
> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> -
> -	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> -	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
> -
> -	return pipe_bpp >= dsc_min_pipe_bpp &&
> -	       pipe_bpp <= dsc_max_pipe_bpp;
> +	return pipe_bpp >= limits->pipe.min_bpp &&
> +	       pipe_bpp <= limits->pipe.max_bpp;
>  }
>  
>  static
> @@ -2195,7 +2185,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
>  
>  	forced_bpp = intel_dp->force_dsc_bpc * 3;
>  
> -	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
> +	if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
>  		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
>  		return forced_bpp;
>  	}
> @@ -2212,11 +2202,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  					 struct link_config_limits *limits,
>  					 int timeslots)
>  {
> -	struct intel_display *display = to_intel_display(intel_dp);
>  	const struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
> -	int dsc_max_bpc, dsc_max_bpp;
> -	int dsc_min_bpc, dsc_min_bpp;
> +	int dsc_max_bpp;
> +	int dsc_min_bpp;
>  	u8 dsc_bpc[3] = {};
>  	int forced_bpp, pipe_bpp;
>  	int num_bpc, i, ret;
> @@ -2232,14 +2221,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  		}
>  	}
>  
> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
> -	if (!dsc_max_bpc)
> -		return -EINVAL;
> -
> -	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
> -
> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> -	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
> +	dsc_max_bpp = limits->pipe.max_bpp;
> +	dsc_min_bpp = limits->pipe.min_bpp;
>  
>  	/*
>  	 * Get the maximum DSC bpc that will be supported by any valid
> @@ -2284,7 +2267,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  
>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
> -		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
> +		if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC limits\n");
>  			return -EINVAL;
> @@ -2502,6 +2485,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
>  	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
>  						     respect_downstream_limits);
> +	if (dsc) {
> +		struct intel_display *display = to_intel_display(intel_dp);
> +		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
> +		int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
> +
> +		limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);
> +		limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);
> +	}

Then intel_dp_mst_compute_config_limits() would also need to do the
same.

>  
>  	if (intel_dp->use_max_params) {
>  		/*
> -- 
> 2.45.2
> 

Re: [PATCH 7/7] drm/i915/dp: Set the DSC link limits intel_dp_compute_config_link_bpp_limits

[Imre Deak]

On Thu, Oct 03, 2024 at 04:13:43PM +0530, Ankit Nautiyal wrote:
> The helper intel_dp_compute_config_link_bpp_limits is the correct place
> to set the DSC link limits. Move the code to this function and remove
> the #TODO item.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++------------
>  drivers/gpu/drm/i915/display/intel_dp.h |  4 +-
>  2 files changed, 35 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 02009ae03840..bfc31b3af864 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1958,7 +1958,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>  
>  static
>  u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
> -					    struct intel_crtc_state *pipe_config,
> +					    const struct intel_crtc_state *pipe_config,
>  					    int bpc)
>  {
>  	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
> @@ -1983,7 +1983,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
>  	return 0;
>  }
>  
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
>  {
>  	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
>  	switch (pipe_config->output_format) {
> @@ -2001,7 +2001,7 @@ int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
>  }
>  
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state *pipe_config,
>  					 int bpc)
>  {
>  	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
> @@ -2130,21 +2130,16 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
>  {
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
>  	int dsc_joiner_max_bpp;
>  	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
>  
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
>  
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp / 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
>  
>  	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
>  								adjusted_mode->hdisplay,
> @@ -2255,8 +2250,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	int pipe_bpp, forced_bpp;
> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +	int dsc_min_bpp;
> +	int dsc_max_bpp;
>  
>  	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
>  
> @@ -2276,16 +2271,12 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	pipe_config->port_clock = limits->max_rate;
>  	pipe_config->lane_count = limits->max_lane_count;
>  
> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> -	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
> +
> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +							   pipe_config,
> +							   pipe_bpp / 3);
>  
> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> -	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> -								pipe_config,
> -								pipe_bpp / 3);
> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
>  	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
>  
>  	/* Compressed BPP should be less than the Input DSC bpp */
> @@ -2428,6 +2419,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
>  		&crtc_state->hw.adjusted_mode;
>  	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct intel_connector *connector = intel_dp->attached_connector;

This would use the wrong (root) connector for MST.

>  	int max_link_bpp_x16;
>  
>  	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
> @@ -2441,12 +2433,22 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
>  
>  		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
>  	} else {
> -		/*
> -		 * TODO: set the DSC link limits already here, atm these are
> -		 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
> -		 * intel_dp_dsc_compute_pipe_bpp()
> -		 */
> -		limits->link.min_bpp_x16 = 0;
> +		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
> +		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
> +
> +		dsc_src_min_bpp = dsc_src_min_compressed_bpp();
> +		dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
> +		dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
> +		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
> +
> +		dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
> +		dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
> +									crtc_state,
> +									limits->pipe.max_bpp / 3);
> +		dsc_max_bpp = dsc_sink_max_bpp ?
> +			      min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
> +
> +		max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
>  	}
>  
>  	limits->link.max_bpp_x16 = max_link_bpp_x16;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 8bd0bb4ec0e1..d4ca00ba49b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -145,9 +145,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>  					enum intel_output_format output_format,
>  					u32 pipe_bpp,
>  					u32 timeslots);
> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config);
>  int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
> -					 struct intel_crtc_state *pipe_config,
> +					 const struct intel_crtc_state *pipe_config,
>  					 int bpc);
>  u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>  				int mode_clock, int mode_hdisplay,
> -- 
> 2.45.2
> 

Re: [PATCH 1/7] drm/i915/dp: Use HAS_DSC macro in intel_dp_dsc_max_src_input_bpc

[Nautiyal, Ankit K]

On 10/17/2024 5:43 PM, Imre Deak wrote:
> On Thu, Oct 03, 2024 at 04:13:37PM +0530, Ankit Nautiyal wrote:
>> Use HAS_DSC macro to take into account platforms for which DSC is fused.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index c4fdae5097ec..c47748905506 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1766,6 +1766,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>>   static
>>   u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
>>   {
>> +	if (!HAS_DSC(i915))
> This is checked already earlier via intel_dp_has_dsc(), couldn't we rely
> on that instead of checking it in these lower level functions?

Sorry for replying late to this.

You are right currently we already check this long before calling this 
function.

However I am intending to use this in 
intel_dp_compute_config_link_bpp_limits which is earlier than the check 
for DSC, for that perhaps need to add a check before computing link bpp 
limits for DSC.

In any case we can avoid the HAS_DSC() check here and in corresponding 
min helper too.

Regards,

Ankit

>
>> +		return 0;
>> +
>>   	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
>>   	if (DISPLAY_VER(i915) >= 12)
>>   		return 12;
>> -- 
>> 2.45.2
>>

Re: [PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc

[Nautiyal, Ankit K]

On 10/17/2024 5:50 PM, Imre Deak wrote:
> On Thu, Oct 03, 2024 at 04:13:41PM +0530, Ankit Nautiyal wrote:
>> With DSC there are additional limits for pipe_bpp. Currently these are
>> scattered in different places.
>> Instead set the limits->pipe.max/min_bpp in one place and use them
>> wherever required.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++++---------------
>>   1 file changed, 17 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 46f3b680afe9..55ee438a4fec 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2166,21 +2166,11 @@ int intel_dp_dsc_min_src_input_bpc(struct intel_display *display)
>>   }
>>   
>>   static
>> -bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
>> -				struct link_config_limits *limits,
>> +bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
>>   				int pipe_bpp)
>>   {
>> -	struct intel_display *display = to_intel_display(&i915->drm);
>> -	int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
>> -
>> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>> -
>> -	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
>> -	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
>> -
>> -	return pipe_bpp >= dsc_min_pipe_bpp &&
>> -	       pipe_bpp <= dsc_max_pipe_bpp;
>> +	return pipe_bpp >= limits->pipe.min_bpp &&
>> +	       pipe_bpp <= limits->pipe.max_bpp;
>>   }
>>   
>>   static
>> @@ -2195,7 +2185,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
>>   
>>   	forced_bpp = intel_dp->force_dsc_bpc * 3;
>>   
>> -	if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
>> +	if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
>>   		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
>>   		return forced_bpp;
>>   	}
>> @@ -2212,11 +2202,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   					 struct link_config_limits *limits,
>>   					 int timeslots)
>>   {
>> -	struct intel_display *display = to_intel_display(intel_dp);
>>   	const struct intel_connector *connector =
>>   		to_intel_connector(conn_state->connector);
>> -	int dsc_max_bpc, dsc_max_bpp;
>> -	int dsc_min_bpc, dsc_min_bpp;
>> +	int dsc_max_bpp;
>> +	int dsc_min_bpp;
>>   	u8 dsc_bpc[3] = {};
>>   	int forced_bpp, pipe_bpp;
>>   	int num_bpc, i, ret;
>> @@ -2232,14 +2221,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   		}
>>   	}
>>   
>> -	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>> -	if (!dsc_max_bpc)
>> -		return -EINVAL;
>> -
>> -	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
>> -
>> -	dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>> -	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
>> +	dsc_max_bpp = limits->pipe.max_bpp;
>> +	dsc_min_bpp = limits->pipe.min_bpp;
>>   
>>   	/*
>>   	 * Get the maximum DSC bpc that will be supported by any valid
>> @@ -2284,7 +2267,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   
>>   		/* For eDP use max bpp that can be supported with DSC. */
>>   		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
>> -		if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
>> +		if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
>>   			drm_dbg_kms(&i915->drm,
>>   				    "Computed BPC is not in DSC BPC limits\n");
>>   			return -EINVAL;
>> @@ -2502,6 +2485,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>>   	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
>>   	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
>>   						     respect_downstream_limits);
>> +	if (dsc) {
>> +		struct intel_display *display = to_intel_display(intel_dp);
>> +		int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>> +		int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>> +
>> +		limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);
>> +		limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);
>> +	}
> Then intel_dp_mst_compute_config_limits() would also need to do the
> same.

The function mst_stream_compute_config_limits() is calling this 
function, so that should be covered.

Regards,

Ankit


>
>>   
>>   	if (intel_dp->use_max_params) {
>>   		/*
>> -- 
>> 2.45.2
>>

Re: [PATCH 5/7] drm/i915/dp: Refactor pipe_bpp limits with dsc

[Nautiyal, Ankit K]

On 11/15/2024 1:43 PM, Nautiyal, Ankit K wrote:
>
> On 10/17/2024 5:50 PM, Imre Deak wrote:
>> On Thu, Oct 03, 2024 at 04:13:41PM +0530, Ankit Nautiyal wrote:
>>> With DSC there are additional limits for pipe_bpp. Currently these are
>>> scattered in different places.
>>> Instead set the limits->pipe.max/min_bpp in one place and use them
>>> wherever required.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_dp.c | 43 
>>> ++++++++++---------------
>>>   1 file changed, 17 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 46f3b680afe9..55ee438a4fec 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -2166,21 +2166,11 @@ int intel_dp_dsc_min_src_input_bpc(struct 
>>> intel_display *display)
>>>   }
>>>     static
>>> -bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
>>> -                struct link_config_limits *limits,
>>> +bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits,
>>>                   int pipe_bpp)
>>>   {
>>> -    struct intel_display *display = to_intel_display(&i915->drm);
>>> -    int dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
>>> -
>>> -    dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>>> -    dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>>> -
>>> -    dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
>>> -    dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
>>> -
>>> -    return pipe_bpp >= dsc_min_pipe_bpp &&
>>> -           pipe_bpp <= dsc_max_pipe_bpp;
>>> +    return pipe_bpp >= limits->pipe.min_bpp &&
>>> +           pipe_bpp <= limits->pipe.max_bpp;
>>>   }
>>>     static
>>> @@ -2195,7 +2185,7 @@ int intel_dp_force_dsc_pipe_bpp(struct 
>>> intel_dp *intel_dp,
>>>         forced_bpp = intel_dp->force_dsc_bpc * 3;
>>>   -    if (is_dsc_pipe_bpp_sufficient(i915, limits, forced_bpp)) {
>>> +    if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
>>>           drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", 
>>> intel_dp->force_dsc_bpc);
>>>           return forced_bpp;
>>>       }
>>> @@ -2212,11 +2202,10 @@ static int 
>>> intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>>                        struct link_config_limits *limits,
>>>                        int timeslots)
>>>   {
>>> -    struct intel_display *display = to_intel_display(intel_dp);
>>>       const struct intel_connector *connector =
>>>           to_intel_connector(conn_state->connector);
>>> -    int dsc_max_bpc, dsc_max_bpp;
>>> -    int dsc_min_bpc, dsc_min_bpp;
>>> +    int dsc_max_bpp;
>>> +    int dsc_min_bpp;
>>>       u8 dsc_bpc[3] = {};
>>>       int forced_bpp, pipe_bpp;
>>>       int num_bpc, i, ret;
>>> @@ -2232,14 +2221,8 @@ static int 
>>> intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>>           }
>>>       }
>>>   -    dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>>> -    if (!dsc_max_bpc)
>>> -        return -EINVAL;
>>> -
>>> -    dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
>>> -
>>> -    dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>>> -    dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
>>> +    dsc_max_bpp = limits->pipe.max_bpp;
>>> +    dsc_min_bpp = limits->pipe.min_bpp;
>>>         /*
>>>        * Get the maximum DSC bpc that will be supported by any valid
>>> @@ -2284,7 +2267,7 @@ static int 
>>> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>>             /* For eDP use max bpp that can be supported with DSC. */
>>>           pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
>>> -        if (!is_dsc_pipe_bpp_sufficient(i915, limits, pipe_bpp)) {
>>> +        if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
>>>               drm_dbg_kms(&i915->drm,
>>>                       "Computed BPC is not in DSC BPC limits\n");
>>>               return -EINVAL;
>>> @@ -2502,6 +2485,14 @@ intel_dp_compute_config_limits(struct 
>>> intel_dp *intel_dp,
>>>       limits->pipe.min_bpp = 
>>> intel_dp_min_bpp(crtc_state->output_format);
>>>       limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
>>>                                respect_downstream_limits);
>>> +    if (dsc) {
>>> +        struct intel_display *display = to_intel_display(intel_dp);
>>> +        int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(display);
>>> +        int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
>>> +
>>> +        limits->pipe.max_bpp = min(limits->pipe.max_bpp, 
>>> dsc_max_bpc * 3);
>>> +        limits->pipe.min_bpp = max(limits->pipe.min_bpp, 
>>> dsc_min_bpc * 3);
>>> +    }
>> Then intel_dp_mst_compute_config_limits() would also need to do the
>> same.
>
> The function mst_stream_compute_config_limits() is calling this 
> function, so that should be covered.

Scratch that. You are right, I got confused with other function.

This is needed in mst as well, I will add the change in next version.

Thanks for pointing this out.

Regards,

Ankit

>
> Regards,
>
> Ankit
>
>
>>
>>>         if (intel_dp->use_max_params) {
>>>           /*
>>> -- 
>>> 2.45.2
>>>

Re: [PATCH 7/7] drm/i915/dp: Set the DSC link limits intel_dp_compute_config_link_bpp_limits

[Nautiyal, Ankit K]

On 10/17/2024 6:12 PM, Imre Deak wrote:
> On Thu, Oct 03, 2024 at 04:13:43PM +0530, Ankit Nautiyal wrote:
>> The helper intel_dp_compute_config_link_bpp_limits is the correct place
>> to set the DSC link limits. Move the code to this function and remove
>> the #TODO item.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++------------
>>   drivers/gpu/drm/i915/display/intel_dp.h |  4 +-
>>   2 files changed, 35 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 02009ae03840..bfc31b3af864 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1958,7 +1958,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>>   
>>   static
>>   u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
>> -					    struct intel_crtc_state *pipe_config,
>> +					    const struct intel_crtc_state *pipe_config,
>>   					    int bpc)
>>   {
>>   	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
>> @@ -1983,7 +1983,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
>>   	return 0;
>>   }
>>   
>> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
>> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
>>   {
>>   	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
>>   	switch (pipe_config->output_format) {
>> @@ -2001,7 +2001,7 @@ int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
>>   }
>>   
>>   int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
>> -					 struct intel_crtc_state *pipe_config,
>> +					 const struct intel_crtc_state *pipe_config,
>>   					 int bpc)
>>   {
>>   	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
>> @@ -2130,21 +2130,16 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
>>   {
>>   	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>>   	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
>> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
>> +	int dsc_min_bpp;
>> +	int dsc_max_bpp;
>>   	int dsc_joiner_max_bpp;
>>   	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
>>   
>> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
>> -	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
>> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
>> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
>> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
>>   
>> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
>> -	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
>> -								pipe_config,
>> -								pipe_bpp / 3);
>> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
>> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
>> +							   pipe_config,
>> +							   pipe_bpp / 3);
>>   
>>   	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
>>   								adjusted_mode->hdisplay,
>> @@ -2255,8 +2250,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	struct intel_connector *connector =
>>   		to_intel_connector(conn_state->connector);
>>   	int pipe_bpp, forced_bpp;
>> -	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
>> -	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
>> +	int dsc_min_bpp;
>> +	int dsc_max_bpp;
>>   
>>   	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
>>   
>> @@ -2276,16 +2271,12 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	pipe_config->port_clock = limits->max_rate;
>>   	pipe_config->lane_count = limits->max_lane_count;
>>   
>> -	dsc_src_min_bpp = dsc_src_min_compressed_bpp();
>> -	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
>> -	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
>> -	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
>> +	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
>> +
>> +	dsc_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
>> +							   pipe_config,
>> +							   pipe_bpp / 3);
>>   
>> -	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
>> -	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
>> -								pipe_config,
>> -								pipe_bpp / 3);
>> -	dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
>>   	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
>>   
>>   	/* Compressed BPP should be less than the Input DSC bpp */
>> @@ -2428,6 +2419,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
>>   		&crtc_state->hw.adjusted_mode;
>>   	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> +	struct intel_connector *connector = intel_dp->attached_connector;
> This would use the wrong (root) connector for MST.

Right, will need to pass the correct connector from MST.

Thanks again for spotting the issue.

Will change this in next version.


Regards,

Ankit


>
>>   	int max_link_bpp_x16;
>>   
>>   	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
>> @@ -2441,12 +2433,22 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
>>   
>>   		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
>>   	} else {
>> -		/*
>> -		 * TODO: set the DSC link limits already here, atm these are
>> -		 * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
>> -		 * intel_dp_dsc_compute_pipe_bpp()
>> -		 */
>> -		limits->link.min_bpp_x16 = 0;
>> +		int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
>> +		int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
>> +
>> +		dsc_src_min_bpp = dsc_src_min_compressed_bpp();
>> +		dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
>> +		dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
>> +		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
>> +
>> +		dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
>> +		dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
>> +									crtc_state,
>> +									limits->pipe.max_bpp / 3);
>> +		dsc_max_bpp = dsc_sink_max_bpp ?
>> +			      min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
>> +
>> +		max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
>>   	}
>>   
>>   	limits->link.max_bpp_x16 = max_link_bpp_x16;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 8bd0bb4ec0e1..d4ca00ba49b4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -145,9 +145,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
>>   					enum intel_output_format output_format,
>>   					u32 pipe_bpp,
>>   					u32 timeslots);
>> -int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
>> +int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config);
>>   int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
>> -					 struct intel_crtc_state *pipe_config,
>> +					 const struct intel_crtc_state *pipe_config,
>>   					 int bpc);
>>   u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
>>   				int mode_clock, int mode_hdisplay,
>> -- 
>> 2.45.2
>>