[PATCH v2] drm/i915/display: Use static values for min_hblank

[PATCH v2] drm/i915/display: Use static values for min_hblank

[Arun R Murthy]

Use recommended static values as per wa_14021694213 for min_hblank to
avoid underruns.

v2: corrected checkpatch warning and retain the restriction for
min_hblank (Jani)

Bspec: 74379
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20250624-min_hblank-v1-1-5c100e4a8b05@intel.com
---
 drivers/gpu/drm/i915/display/intel_dp.c | 62 ++++++---------------------------
 1 file changed, 10 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f48912f308df7fd26c9d089e8f1bd096bfc8df95..b657340648cd2be72cec3fae606c0bc2ec8dba3d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3115,22 +3115,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 				const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	const struct drm_display_mode *adjusted_mode =
-					&crtc_state->hw.adjusted_mode;
-	struct intel_connector *connector = to_intel_connector(conn_state->connector);
-	int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
-	/*
-	 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
-	 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
-	 */
-	int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
-	int min_hblank;
-	int max_lane_count = 4;
-	int hactive_sym_cycles, htotal_sym_cycles;
-	int dsc_slices = 0;
-	int link_bpp_x16;
 
 	if (DISPLAY_VER(display) < 30)
 		return 0;
@@ -3139,45 +3124,18 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 	if (!is_mst && !intel_dp_is_uhbr(crtc_state))
 		return 0;
 
-	if (crtc_state->dsc.compression_enable) {
-		dsc_slices = intel_dp_dsc_get_slice_count(connector,
-							  adjusted_mode->crtc_clock,
-							  adjusted_mode->crtc_hdisplay,
-							  num_joined_pipes);
-		if (!dsc_slices) {
-			drm_dbg(display->drm, "failed to calculate dsc slice count\n");
-			return -EINVAL;
-		}
+	/* min_hblank formula is undergoing a change and the recomendation is to use static value */
+	if (intel_dp_is_uhbr(crtc_state)) {
+		if (crtc_state->dsc.compression_enable &&
+		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+		    crtc_state->pipe_bpp == 18)
+			crtc_state->min_hblank = 2;
+		else
+			crtc_state->min_hblank = 3;
+	} else {
+		crtc_state->min_hblank = 10;
 	}
 
-	if (crtc_state->dsc.compression_enable)
-		link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
-	else
-		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
-								   crtc_state->pipe_bpp));
-
-	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
-	hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,
-						       adjusted_mode->hdisplay,
-						       dsc_slices,
-						       link_bpp_x16,
-						       symbol_size, is_mst);
-	htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles /
-			     adjusted_mode->hdisplay;
-
-	min_hblank = htotal_sym_cycles - hactive_sym_cycles;
-	/* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
-	min_hblank = max(min_hblank, min_sym_cycles);
-
-	/*
-	 * adjust the BlankingStart/BlankingEnd framing control from
-	 * the calculated value
-	 */
-	min_hblank = min_hblank - 2;
-
-	min_hblank = min(10, min_hblank);
-	crtc_state->min_hblank = min_hblank;
-
 	return 0;
 }
 

---
base-commit: da56936fad6f5e1d5f0cef8b50277bfb071eefe7
change-id: 20250624-min_hblank-8af8d2626ff8

Best regards,
-- 
Arun R Murthy <arun.r.murthy@intel.com>

✗ i915.CI.BAT: failure for drm/i915/display: Use static values for min_hblank

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4853 bytes --]

== Series Details ==

Series: drm/i915/display: Use static values for min_hblank
URL   : https://patchwork.freedesktop.org/series/150684/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16748 -> Patchwork_150684v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_150684v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_150684v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/index.html

Participating hosts (45 -> 43)
------------------------------

  Missing    (2): fi-kbl-guc fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_150684v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-jsl-1:          [PASS][1] -> [DMESG-FAIL][2] +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-jsl-1/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-jsl-1/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_150684v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [PASS][3] -> [INCOMPLETE][4] ([i915#12904]) +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-apl-1/igt@dmabuf@all-tests.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-n3050:       [PASS][5] -> [INCOMPLETE][6] ([i915#12904]) +1 other test incomplete
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-mtlp-8/igt@i915_selftest@live.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-arlh-3:         [DMESG-FAIL][11] ([i915#14243]) -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-arlh-3/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-arlh-3/igt@i915_selftest@live.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][13] ([i915#12061] / [i915#13929]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#14204])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-atsm-1/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][15] ([i915#13929]) -> [DMESG-FAIL][16] ([i915#14204])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16748/bat-atsm-1/igt@i915_selftest@live@mman.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#14243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14243


Build changes
-------------

  * Linux: CI_DRM_16748 -> Patchwork_150684v1

  CI-20190529: 20190529
  CI_DRM_16748: fb5dada21e3cfa26179ca58e1d7c26cdad217201 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8423: 8423
  Patchwork_150684v1: fb5dada21e3cfa26179ca58e1d7c26cdad217201 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_150684v1/index.html

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Re: [PATCH v2] drm/i915/display: Use static values for min_hblank

[Imre Deak]

On Tue, Jun 24, 2025 at 03:29:27PM +0530, Arun R Murthy wrote:
> Use recommended static values as per wa_14021694213 for min_hblank to
> avoid underruns.
> 
> v2: corrected checkpatch warning and retain the restriction for
> min_hblank (Jani)
> 
> Bspec: 74379
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> Changes in v2:
> - EDITME: describe what is new in this series revision.
> - EDITME: use bulletpoints and terse descriptions.
> - Link to v1: https://lore.kernel.org/r/20250624-min_hblank-v1-1-5c100e4a8b05@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 62 ++++++---------------------------
>  1 file changed, 10 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f48912f308df7fd26c9d089e8f1bd096bfc8df95..b657340648cd2be72cec3fae606c0bc2ec8dba3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3115,22 +3115,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
>  				const struct drm_connector_state *conn_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -	const struct drm_display_mode *adjusted_mode =
> -					&crtc_state->hw.adjusted_mode;
> -	struct intel_connector *connector = to_intel_connector(conn_state->connector);
> -	int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
> -	/*
> -	 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
> -	 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
> -	 */
> -	int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
>  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> -	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
> -	int min_hblank;
> -	int max_lane_count = 4;
> -	int hactive_sym_cycles, htotal_sym_cycles;
> -	int dsc_slices = 0;
> -	int link_bpp_x16;
>  
>  	if (DISPLAY_VER(display) < 30)
>  		return 0;
> @@ -3139,45 +3124,18 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
>  	if (!is_mst && !intel_dp_is_uhbr(crtc_state))
>  		return 0;
>  
> -	if (crtc_state->dsc.compression_enable) {
> -		dsc_slices = intel_dp_dsc_get_slice_count(connector,
> -							  adjusted_mode->crtc_clock,
> -							  adjusted_mode->crtc_hdisplay,
> -							  num_joined_pipes);
> -		if (!dsc_slices) {
> -			drm_dbg(display->drm, "failed to calculate dsc slice count\n");
> -			return -EINVAL;
> -		}
> +	/* min_hblank formula is undergoing a change and the recomendation is to use static value */
> +	if (intel_dp_is_uhbr(crtc_state)) {
> +		if (crtc_state->dsc.compression_enable &&
> +		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> +		    crtc_state->pipe_bpp == 18)
> +			crtc_state->min_hblank = 2;
> +		else
> +			crtc_state->min_hblank = 3;
> +	} else {
> +		crtc_state->min_hblank = 10;
>  	}

The min hblank programmed can't be higher than the hblank period of the
mode. So the hblank symbol cycles for the mode should be still calculated
as now and the above new limit of 2/3 cycles for UHBR should be used
as needed for the upper bound of min_hblank below at

	min_hblank = min(10, min_hblank);

instead of the fixed limit of 10 cycles.

>  
> -	if (crtc_state->dsc.compression_enable)
> -		link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
> -	else
> -		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format,
> -								   crtc_state->pipe_bpp));
> -
> -	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
> -	hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,
> -						       adjusted_mode->hdisplay,
> -						       dsc_slices,
> -						       link_bpp_x16,
> -						       symbol_size, is_mst);
> -	htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles /
> -			     adjusted_mode->hdisplay;
> -
> -	min_hblank = htotal_sym_cycles - hactive_sym_cycles;
> -	/* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
> -	min_hblank = max(min_hblank, min_sym_cycles);
> -
> -	/*
> -	 * adjust the BlankingStart/BlankingEnd framing control from
> -	 * the calculated value
> -	 */
> -	min_hblank = min_hblank - 2;
> -
> -	min_hblank = min(10, min_hblank);
> -	crtc_state->min_hblank = min_hblank;
> -
>  	return 0;
>  }
>  
> 
> ---
> base-commit: da56936fad6f5e1d5f0cef8b50277bfb071eefe7
> change-id: 20250624-min_hblank-8af8d2626ff8
> 
> Best regards,
> -- 
> Arun R Murthy <arun.r.murthy@intel.com>
>