[PATCH v3 0/3] Selective Fetch and async flip

[PATCH v3 0/3] Selective Fetch and async flip

[Jouni Högander]

This patch set contains fixes for Selective Fetch async flip
sequences. On async flip selective fetch is choosing full ftrame
update. Also subsequent flip/update is still using full frame update
to ensure plane with pending async flip is not taken in to selective
fetch/update.

v3:
  - rebase
  - fix old_crtc_state->pipe_srcsz_early_tpt
  - fix using intel_atomic_get_new_crtc_state
v2:
  - check also crtc_state->async_flip_planes in
    psr2_sel_fetch_plane_state_supported

Jouni Högander (3):
  drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for
    PSR
  drm/i915/psr: Perform full frame update on async flip
  drm/i915/psr: Allow async flip when Selective Fetch enabled

 drivers/gpu/drm/i915/display/intel_display.c |  8 ---
 drivers/gpu/drm/i915/display/intel_plane.c   | 10 ++-
 drivers/gpu/drm/i915/display/intel_psr.c     | 72 +++++++++++---------
 3 files changed, 49 insertions(+), 41 deletions(-)

-- 
2.43.0

[PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR

[Jouni Högander]

Currently plane id bit is set in crtc_state->async_flip_planes only when
async flip toggle workaround is needed. We want to utilize
crtc_state->async_flip_planes further in Selective Fetch calculation.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 7b7619d59251..de0a69c55582 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -603,8 +603,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
 	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
 		new_crtc_state->do_async_flip = true;
 		new_crtc_state->async_flip_planes |= BIT(plane->id);
-	} else if (plane->need_async_flip_toggle_wa &&
-		   new_crtc_state->uapi.async_flip) {
+	} else if (new_crtc_state->uapi.async_flip) {
 		/*
 		 * On platforms with double buffered async flip bit we
 		 * set the bit already one frame early during the sync
@@ -612,6 +611,13 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
 		 * hardware will therefore be ready to perform a real
 		 * async flip during the next commit, without having
 		 * to wait yet another frame for the bit to latch.
+		 *
+		 * async_flip_planes bitmask is also used by selective
+		 * fetch calculation to continue full frame updates as
+		 * long as there may be pending async flip on any
+		 * plane which is part of selective
+		 * update. I.e. old_crtc_state->async_flip_planes &
+		 * BIT(<plane in su area>->id).
 		 */
 		new_crtc_state->async_flip_planes |= BIT(plane->id);
 	}
-- 
2.43.0

Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR

[Ville Syrjälä]

On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> Currently plane id bit is set in crtc_state->async_flip_planes only when
> async flip toggle workaround is needed. We want to utilize
> crtc_state->async_flip_planes further in Selective Fetch calculation.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index 7b7619d59251..de0a69c55582 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -603,8 +603,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
>  	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
>  		new_crtc_state->do_async_flip = true;
>  		new_crtc_state->async_flip_planes |= BIT(plane->id);
> -	} else if (plane->need_async_flip_toggle_wa &&
> -		   new_crtc_state->uapi.async_flip) {
> +	} else if (new_crtc_state->uapi.async_flip) {

I'd get rid of the if-else construct here now, and just do something
like:

if (intel_plane_do_async_flip(...))
	new_crtc_state->do_async_flip = true;

if (new_crtc_state->uapi.async_flip) {
	/* ... */
	new_crtc_state->async_flip_planes |= BIT(plane->id);
}

We should probably also move the plane->async_flip check
out from intel_plane_do_async_flip() and just make it a
drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
But that's probably better left for a separate patch.

>  		/*
>  		 * On platforms with double buffered async flip bit we
>  		 * set the bit already one frame early during the sync
> @@ -612,6 +611,13 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
>  		 * hardware will therefore be ready to perform a real
>  		 * async flip during the next commit, without having
>  		 * to wait yet another frame for the bit to latch.
> +		 *
> +		 * async_flip_planes bitmask is also used by selective
> +		 * fetch calculation to continue full frame updates as
> +		 * long as there may be pending async flip on any
> +		 * plane which is part of selective
> +		 * update. I.e. old_crtc_state->async_flip_planes &
> +		 * BIT(<plane in su area>->id).
>  		 */
>  		new_crtc_state->async_flip_planes |= BIT(plane->id);
>  	}
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR

[Hogander, Jouni]

On Wed, 2025-12-03 at 15:15 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> > Currently plane id bit is set in crtc_state->async_flip_planes only
> > when
> > async flip toggle workaround is needed. We want to utilize
> > crtc_state->async_flip_planes further in Selective Fetch
> > calculation.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> > b/drivers/gpu/drm/i915/display/intel_plane.c
> > index 7b7619d59251..de0a69c55582 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> > @@ -603,8 +603,7 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> >  	if (intel_plane_do_async_flip(plane, old_crtc_state,
> > new_crtc_state)) {
> >  		new_crtc_state->do_async_flip = true;
> >  		new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> > -	} else if (plane->need_async_flip_toggle_wa &&
> > -		   new_crtc_state->uapi.async_flip) {
> > +	} else if (new_crtc_state->uapi.async_flip) {
> 
> I'd get rid of the if-else construct here now, and just do something
> like:
> 
> if (intel_plane_do_async_flip(...))
> 	new_crtc_state->do_async_flip = true;
> 
> if (new_crtc_state->uapi.async_flip) {
> 	/* ... */
> 	new_crtc_state->async_flip_planes |= BIT(plane->id);
> }

> 
> We should probably also move the plane->async_flip check
> out from intel_plane_do_async_flip() and just make it a
> drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
> But that's probably better left for a separate patch.

Sent new version, please check. Left out this drm_WARN_ON change. I
will send it afterwards.

BR,

Jouni Högander

> 
> >  		/*
> >  		 * On platforms with double buffered async flip
> > bit we
> >  		 * set the bit already one frame early during the
> > sync
> > @@ -612,6 +611,13 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> >  		 * hardware will therefore be ready to perform a
> > real
> >  		 * async flip during the next commit, without
> > having
> >  		 * to wait yet another frame for the bit to latch.
> > +		 *
> > +		 * async_flip_planes bitmask is also used by
> > selective
> > +		 * fetch calculation to continue full frame
> > updates as
> > +		 * long as there may be pending async flip on any
> > +		 * plane which is part of selective
> > +		 * update. I.e. old_crtc_state->async_flip_planes
> > &
> > +		 * BIT(<plane in su area>->id).
> >  		 */
> >  		new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> >  	}
> > -- 
> > 2.43.0
> 

Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR

[Hogander, Jouni]

On Wed, 2025-12-03 at 15:15 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> > Currently plane id bit is set in crtc_state->async_flip_planes only
> > when
> > async flip toggle workaround is needed. We want to utilize
> > crtc_state->async_flip_planes further in Selective Fetch
> > calculation.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> > b/drivers/gpu/drm/i915/display/intel_plane.c
> > index 7b7619d59251..de0a69c55582 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> > @@ -603,8 +603,7 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> >  	if (intel_plane_do_async_flip(plane, old_crtc_state,
> > new_crtc_state)) {
> >  		new_crtc_state->do_async_flip = true;
> >  		new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> > -	} else if (plane->need_async_flip_toggle_wa &&
> > -		   new_crtc_state->uapi.async_flip) {
> > +	} else if (new_crtc_state->uapi.async_flip) {
> 
> I'd get rid of the if-else construct here now, and just do something
> like:
> 
> if (intel_plane_do_async_flip(...))
> 	new_crtc_state->do_async_flip = true;
> 
> if (new_crtc_state->uapi.async_flip) {
> 	/* ... */
> 	new_crtc_state->async_flip_planes |= BIT(plane->id);
> }
> 
> We should probably also move the plane->async_flip check
> out from intel_plane_do_async_flip() and just make it a
> drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
> But that's probably better left for a separate patch.

I have sent a patch for this:

https://patchwork.freedesktop.org/series/159086/

BR,
Jouni Högander

[PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Jouni Högander]

According to bspec selective fetch is not supported with async flips and
instructing full frame update on async flip.

v3:
  - rebase
  - fix old_crtc_state->pipe_srcsz_early_tpt
  - fix using intel_atomic_get_new_crtc_state
v2:
  - check also crtc_state->async_flip_planes in
    psr2_sel_fetch_plane_state_supported

Bspec: 55229
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++----------
 1 file changed, 41 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 15ef3b6caad6..53cf292247d7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
  * Plane scaling and rotation is not supported by selective fetch and both
  * properties can change without a modeset, so need to be check at every
  * atomic commit.
+ *
+ * If plane was having async flip previously we can't use selective
+ * fetch as we don't know if the flip is completed.
  */
-static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
+static bool psr2_sel_fetch_plane_state_supported(const struct intel_crtc_state *old_crtc_state,
+						 const struct intel_plane_state *plane_state)
 {
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+
 	if (plane_state->uapi.dst.y1 < 0 ||
 	    plane_state->uapi.dst.x1 < 0 ||
 	    plane_state->scaler_id >= 0 ||
-	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
+	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
+	    old_crtc_state->async_flip_planes & plane->id)
 		return false;
 
 	return true;
@@ -2749,7 +2756,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
  */
 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
 {
-	if (crtc_state->scaler_state.scaler_id >= 0)
+	if (crtc_state->scaler_state.scaler_id >= 0 ||
+	    crtc_state->uapi.async_flip)
 		return false;
 
 	return true;
@@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_plane_state *new_plane_state, *old_plane_state;
 	struct intel_plane *plane;
 	bool full_update = false, cursor_in_su_area = false;
 	int i, ret;
 
-	if (!crtc_state->enable_psr2_sel_fetch)
+	if (!new_crtc_state->enable_psr2_sel_fetch)
 		return 0;
 
-	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
+	if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state)) {
 		full_update = true;
 		goto skip_sel_fetch_set_loop;
 	}
 
-	crtc_state->psr2_su_area.x1 = 0;
-	crtc_state->psr2_su_area.y1 = -1;
-	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
-	crtc_state->psr2_su_area.y2 = -1;
+	new_crtc_state->psr2_su_area.x1 = 0;
+	new_crtc_state->psr2_su_area.y1 = -1;
+	new_crtc_state->psr2_su_area.x2 = drm_rect_width(&new_crtc_state->pipe_src);
+	new_crtc_state->psr2_su_area.y2 = -1;
 
 	/*
 	 * Calculate minimal selective fetch area of each plane and calculate
@@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
 						      .x2 = INT_MAX };
 
-		if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)
+		if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc)
 			continue;
 
 		if (!new_plane_state->uapi.visible &&
 		    !old_plane_state->uapi.visible)
 			continue;
 
-		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
+		if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
 			full_update = true;
 			break;
 		}
@@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 			if (old_plane_state->uapi.visible) {
 				damaged_area.y1 = old_plane_state->uapi.dst.y1;
 				damaged_area.y2 = old_plane_state->uapi.dst.y2;
-				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
-						 &crtc_state->pipe_src);
+				clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+						 &new_crtc_state->pipe_src);
 			}
 
 			if (new_plane_state->uapi.visible) {
 				damaged_area.y1 = new_plane_state->uapi.dst.y1;
 				damaged_area.y2 = new_plane_state->uapi.dst.y2;
-				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
-						 &crtc_state->pipe_src);
+				clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+						 &new_crtc_state->pipe_src);
 			}
 			continue;
 		} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
 			/* If alpha changed mark the whole plane area as damaged */
 			damaged_area.y1 = new_plane_state->uapi.dst.y1;
 			damaged_area.y2 = new_plane_state->uapi.dst.y2;
-			clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
-					 &crtc_state->pipe_src);
+			clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+					 &new_crtc_state->pipe_src);
 			continue;
 		}
 
@@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
 		damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
 
-		clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
+		clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+				 &new_crtc_state->pipe_src);
 	}
 
 	/*
@@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	 * should identify cases where this happens and fix the area
 	 * calculation for those.
 	 */
-	if (crtc_state->psr2_su_area.y1 == -1) {
+	if (new_crtc_state->psr2_su_area.y1 == -1) {
 		drm_info_once(display->drm,
 			      "Selective fetch area calculation failed in pipe %c\n",
 			      pipe_name(crtc->pipe));
@@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	if (full_update)
 		goto skip_sel_fetch_set_loop;
 
-	intel_psr_apply_su_area_workarounds(crtc_state);
+	intel_psr_apply_su_area_workarounds(new_crtc_state);
 
 	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 	if (ret)
@@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	 */
 	intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
 
-	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
+	intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
 
 	/*
 	 * Now that we have the pipe damaged area check if it intersect with
@@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		struct drm_rect *sel_fetch_area, inter;
 		struct intel_plane *linked = new_plane_state->planar_linked_plane;
 
-		if (new_plane_state->hw.crtc != crtc_state->uapi.crtc ||
+		if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc ||
 		    !new_plane_state->uapi.visible)
 			continue;
 
-		inter = crtc_state->psr2_su_area;
+		inter = new_crtc_state->psr2_su_area;
 		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
 		if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
 			sel_fetch_area->y1 = -1;
@@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 			 * disable it
 			 */
 			if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
-				crtc_state->update_planes |= BIT(plane->id);
+				new_crtc_state->update_planes |= BIT(plane->id);
 
 			continue;
 		}
 
-		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
+		if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
 			full_update = true;
 			break;
 		}
@@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
 		sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
 		sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
-		crtc_state->update_planes |= BIT(plane->id);
+		new_crtc_state->update_planes |= BIT(plane->id);
 
 		/*
 		 * Sel_fetch_area is calculated for UV plane. Use
@@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 			linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
 			linked_sel_fetch_area->y1 = sel_fetch_area->y1;
 			linked_sel_fetch_area->y2 = sel_fetch_area->y2;
-			crtc_state->update_planes |= BIT(linked->id);
+			new_crtc_state->update_planes |= BIT(linked->id);
 		}
 	}
 
 skip_sel_fetch_set_loop:
-	psr2_man_trk_ctl_calc(crtc_state, full_update);
-	crtc_state->pipe_srcsz_early_tpt =
-		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
+	psr2_man_trk_ctl_calc(new_crtc_state, full_update);
+	new_crtc_state->pipe_srcsz_early_tpt =
+		psr2_pipe_srcsz_early_tpt_calc(new_crtc_state, full_update);
 	return 0;
 }
 
-- 
2.43.0

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Ville Syrjälä]

On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> According to bspec selective fetch is not supported with async flips and
> instructing full frame update on async flip.
> 
> v3:
>   - rebase
>   - fix old_crtc_state->pipe_srcsz_early_tpt
>   - fix using intel_atomic_get_new_crtc_state
> v2:
>   - check also crtc_state->async_flip_planes in
>     psr2_sel_fetch_plane_state_supported
> 
> Bspec: 55229
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++----------
>  1 file changed, 41 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 15ef3b6caad6..53cf292247d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
>   * Plane scaling and rotation is not supported by selective fetch and both
>   * properties can change without a modeset, so need to be check at every
>   * atomic commit.
> + *
> + * If plane was having async flip previously we can't use selective
> + * fetch as we don't know if the flip is completed.
>   */
> -static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
> +static bool psr2_sel_fetch_plane_state_supported(const struct intel_crtc_state *old_crtc_state,
> +						 const struct intel_plane_state *plane_state)
>  {
> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +
>  	if (plane_state->uapi.dst.y1 < 0 ||
>  	    plane_state->uapi.dst.x1 < 0 ||
>  	    plane_state->scaler_id >= 0 ||
> -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> +	    old_crtc_state->async_flip_planes & plane->id)

Why are you looking at the old crtc state? There should be nothing of
interest to us there.

>  		return false;
>  
>  	return true;
> @@ -2749,7 +2756,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
>   */
>  static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
>  {
> -	if (crtc_state->scaler_state.scaler_id >= 0)
> +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> +	    crtc_state->uapi.async_flip)

I think just checking crtc_state->async_flip_planes!=0 here should be
sufficient. The rest of the patch seems unnecessary.

On a related note, someone should add a new igt that does async flips
while eg. the cursor is enabled and overlapping the plane doing the
async flips. That's basically how I noticed the problem in the first
place (with Xorg), so would be good to have an igt to make sure we
don't break this in the future.

>  		return false;
>  
>  	return true;
> @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc)
>  {
>  	struct intel_display *display = to_intel_display(state);
> -	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_plane_state *new_plane_state, *old_plane_state;
>  	struct intel_plane *plane;
>  	bool full_update = false, cursor_in_su_area = false;
>  	int i, ret;
>  
> -	if (!crtc_state->enable_psr2_sel_fetch)
> +	if (!new_crtc_state->enable_psr2_sel_fetch)
>  		return 0;
>  
> -	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> +	if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state)) {
>  		full_update = true;
>  		goto skip_sel_fetch_set_loop;
>  	}
>  
> -	crtc_state->psr2_su_area.x1 = 0;
> -	crtc_state->psr2_su_area.y1 = -1;
> -	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
> -	crtc_state->psr2_su_area.y2 = -1;
> +	new_crtc_state->psr2_su_area.x1 = 0;
> +	new_crtc_state->psr2_su_area.y1 = -1;
> +	new_crtc_state->psr2_su_area.x2 = drm_rect_width(&new_crtc_state->pipe_src);
> +	new_crtc_state->psr2_su_area.y2 = -1;
>  
>  	/*
>  	 * Calculate minimal selective fetch area of each plane and calculate
> @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
>  						      .x2 = INT_MAX };
>  
> -		if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)
> +		if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc)
>  			continue;
>  
>  		if (!new_plane_state->uapi.visible &&
>  		    !old_plane_state->uapi.visible)
>  			continue;
>  
> -		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> +		if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
>  			full_update = true;
>  			break;
>  		}
> @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  			if (old_plane_state->uapi.visible) {
>  				damaged_area.y1 = old_plane_state->uapi.dst.y1;
>  				damaged_area.y2 = old_plane_state->uapi.dst.y2;
> -				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> -						 &crtc_state->pipe_src);
> +				clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> +						 &new_crtc_state->pipe_src);
>  			}
>  
>  			if (new_plane_state->uapi.visible) {
>  				damaged_area.y1 = new_plane_state->uapi.dst.y1;
>  				damaged_area.y2 = new_plane_state->uapi.dst.y2;
> -				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> -						 &crtc_state->pipe_src);
> +				clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> +						 &new_crtc_state->pipe_src);
>  			}
>  			continue;
>  		} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
>  			/* If alpha changed mark the whole plane area as damaged */
>  			damaged_area.y1 = new_plane_state->uapi.dst.y1;
>  			damaged_area.y2 = new_plane_state->uapi.dst.y2;
> -			clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> -					 &crtc_state->pipe_src);
> +			clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> +					 &new_crtc_state->pipe_src);
>  			continue;
>  		}
>  
> @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
>  		damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
>  
> -		clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
> +		clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> +				 &new_crtc_state->pipe_src);
>  	}
>  
>  	/*
> @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  	 * should identify cases where this happens and fix the area
>  	 * calculation for those.
>  	 */
> -	if (crtc_state->psr2_su_area.y1 == -1) {
> +	if (new_crtc_state->psr2_su_area.y1 == -1) {
>  		drm_info_once(display->drm,
>  			      "Selective fetch area calculation failed in pipe %c\n",
>  			      pipe_name(crtc->pipe));
> @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  	if (full_update)
>  		goto skip_sel_fetch_set_loop;
>  
> -	intel_psr_apply_su_area_workarounds(crtc_state);
> +	intel_psr_apply_su_area_workarounds(new_crtc_state);
>  
>  	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>  	if (ret)
> @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  	 */
>  	intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
>  
> -	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> +	intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
>  
>  	/*
>  	 * Now that we have the pipe damaged area check if it intersect with
> @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		struct drm_rect *sel_fetch_area, inter;
>  		struct intel_plane *linked = new_plane_state->planar_linked_plane;
>  
> -		if (new_plane_state->hw.crtc != crtc_state->uapi.crtc ||
> +		if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc ||
>  		    !new_plane_state->uapi.visible)
>  			continue;
>  
> -		inter = crtc_state->psr2_su_area;
> +		inter = new_crtc_state->psr2_su_area;
>  		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
>  		if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
>  			sel_fetch_area->y1 = -1;
> @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  			 * disable it
>  			 */
>  			if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
> -				crtc_state->update_planes |= BIT(plane->id);
> +				new_crtc_state->update_planes |= BIT(plane->id);
>  
>  			continue;
>  		}
>  
> -		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> +		if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
>  			full_update = true;
>  			break;
>  		}
> @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
>  		sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
>  		sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
> -		crtc_state->update_planes |= BIT(plane->id);
> +		new_crtc_state->update_planes |= BIT(plane->id);
>  
>  		/*
>  		 * Sel_fetch_area is calculated for UV plane. Use
> @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  			linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
>  			linked_sel_fetch_area->y1 = sel_fetch_area->y1;
>  			linked_sel_fetch_area->y2 = sel_fetch_area->y2;
> -			crtc_state->update_planes |= BIT(linked->id);
> +			new_crtc_state->update_planes |= BIT(linked->id);
>  		}
>  	}
>  
>  skip_sel_fetch_set_loop:
> -	psr2_man_trk_ctl_calc(crtc_state, full_update);
> -	crtc_state->pipe_srcsz_early_tpt =
> -		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
> +	psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> +	new_crtc_state->pipe_srcsz_early_tpt =
> +		psr2_pipe_srcsz_early_tpt_calc(new_crtc_state, full_update);
>  	return 0;
>  }
>  
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Hogander, Jouni]

On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > According to bspec selective fetch is not supported with async
> > flips and
> > instructing full frame update on async flip.
> > 
> > v3:
> >   - rebase
> >   - fix old_crtc_state->pipe_srcsz_early_tpt
> >   - fix using intel_atomic_get_new_crtc_state
> > v2:
> >   - check also crtc_state->async_flip_planes in
> >     psr2_sel_fetch_plane_state_supported
> > 
> > Bspec: 55229
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > ----
> >  1 file changed, 41 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 15ef3b6caad6..53cf292247d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > intel_atomic_state *state,
> >   * Plane scaling and rotation is not supported by selective fetch
> > and both
> >   * properties can change without a modeset, so need to be check at
> > every
> >   * atomic commit.
> > + *
> > + * If plane was having async flip previously we can't use
> > selective
> > + * fetch as we don't know if the flip is completed.
> >   */
> > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_plane_state *plane_state)
> > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_crtc_state *old_crtc_state,
> > +						 const struct
> > intel_plane_state *plane_state)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(plane_state-
> > >uapi.plane);
> > +
> >  	if (plane_state->uapi.dst.y1 < 0 ||
> >  	    plane_state->uapi.dst.x1 < 0 ||
> >  	    plane_state->scaler_id >= 0 ||
> > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > +	    old_crtc_state->async_flip_planes & plane->id)
> 
> Why are you looking at the old crtc state? There should be nothing of
> interest to us there.

To continue keeping CFF bit set if previous update was async flip. This
is how I understood it (please correct):

0. syncronous update

1. async_flip:
   new_crtc_state->async_flip_planes != 0
   old_crtc_state->async_flip_planes == 0
   crtc_state->uapi.async_flip == true)
   -> full frame update

2. async_flip:
   new_crtc_state->async_flip_planes != 0
   old_crtc_state->async_flip_planes != 0
   crtc_state->uapi.async_flip == true
   -> full frame update

3. syncronous update
   new_crtc_state->async_flip_planes == 0
   old_crtc_state->async_flip_planes != 0
   crtc_state->uapi.async_flip == false
   -> full frame update

4. syncronous update
   new_crtc_state->async_flip_planes == 0
   old_crtc_state->async_flip_planes == 0
   crtc_state->uapi.async_flip == false
   -> selective update

> 
> >  		return false;
> >  
> >  	return true;
> > @@ -2749,7 +2756,8 @@ static bool
> > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> >   */
> >  static bool psr2_sel_fetch_pipe_state_supported(const struct
> > intel_crtc_state *crtc_state)
> >  {
> > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > +	    crtc_state->uapi.async_flip)
> 
> I think just checking crtc_state->async_flip_planes!=0 here should be
> sufficient.

I'm doing this to handle step 1. above. Alternatively I could check
both new_crtc_state->async_flip_planes and old_crtc_state-
>async_flip_planes. When using crtc_state->uapi.async_flip I can decide
earlier.

> The rest of the patch seems unnecessary.

No need to handle selective update where planes having pending async
flip are not involved?

BR,
Jouni Högander

> 
> On a related note, someone should add a new igt that does async flips
> while eg. the cursor is enabled and overlapping the plane doing the
> async flips. That's basically how I noticed the problem in the first
> place (with Xorg), so would be good to have an igt to make sure we
> don't break this in the future.
> 
> >  		return false;
> >  
> >  	return true;
> > @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  				struct intel_crtc *crtc)
> >  {
> >  	struct intel_display *display = to_intel_display(state);
> > -	struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > +	struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > +	struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> >  	struct intel_plane_state *new_plane_state,
> > *old_plane_state;
> >  	struct intel_plane *plane;
> >  	bool full_update = false, cursor_in_su_area = false;
> >  	int i, ret;
> >  
> > -	if (!crtc_state->enable_psr2_sel_fetch)
> > +	if (!new_crtc_state->enable_psr2_sel_fetch)
> >  		return 0;
> >  
> > -	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> > +	if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state))
> > {
> >  		full_update = true;
> >  		goto skip_sel_fetch_set_loop;
> >  	}
> >  
> > -	crtc_state->psr2_su_area.x1 = 0;
> > -	crtc_state->psr2_su_area.y1 = -1;
> > -	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state-
> > >pipe_src);
> > -	crtc_state->psr2_su_area.y2 = -1;
> > +	new_crtc_state->psr2_su_area.x1 = 0;
> > +	new_crtc_state->psr2_su_area.y1 = -1;
> > +	new_crtc_state->psr2_su_area.x2 =
> > drm_rect_width(&new_crtc_state->pipe_src);
> > +	new_crtc_state->psr2_su_area.y2 = -1;
> >  
> >  	/*
> >  	 * Calculate minimal selective fetch area of each plane
> > and calculate
> > @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		struct drm_rect src, damaged_area = { .x1 = 0, .y1
> > = -1,
> >  						      .x2 =
> > INT_MAX };
> >  
> > -		if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc)
> > +		if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc)
> >  			continue;
> >  
> >  		if (!new_plane_state->uapi.visible &&
> >  		    !old_plane_state->uapi.visible)
> >  			continue;
> >  
> > -		if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > +		if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> >  			full_update = true;
> >  			break;
> >  		}
> > @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			if (old_plane_state->uapi.visible) {
> >  				damaged_area.y1 = old_plane_state-
> > >uapi.dst.y1;
> >  				damaged_area.y2 = old_plane_state-
> > >uapi.dst.y2;
> > -				clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -						 &crtc_state-
> > >pipe_src);
> > +				clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +						 &new_crtc_state-
> > >pipe_src);
> >  			}
> >  
> >  			if (new_plane_state->uapi.visible) {
> >  				damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> >  				damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > -				clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -						 &crtc_state-
> > >pipe_src);
> > +				clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +						 &new_crtc_state-
> > >pipe_src);
> >  			}
> >  			continue;
> >  		} else if (new_plane_state->uapi.alpha !=
> > old_plane_state->uapi.alpha) {
> >  			/* If alpha changed mark the whole plane
> > area as damaged */
> >  			damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> >  			damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > -			clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -					 &crtc_state->pipe_src);
> > +			clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +					 &new_crtc_state-
> > >pipe_src);
> >  			continue;
> >  		}
> >  
> > @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		damaged_area.x1 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >  		damaged_area.x2 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >  
> > -		clip_area_update(&crtc_state->psr2_su_area,
> > &damaged_area, &crtc_state->pipe_src);
> > +		clip_area_update(&new_crtc_state->psr2_su_area,
> > &damaged_area,
> > +				 &new_crtc_state->pipe_src);
> >  	}
> >  
> >  	/*
> > @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	 * should identify cases where this happens and fix the
> > area
> >  	 * calculation for those.
> >  	 */
> > -	if (crtc_state->psr2_su_area.y1 == -1) {
> > +	if (new_crtc_state->psr2_su_area.y1 == -1) {
> >  		drm_info_once(display->drm,
> >  			      "Selective fetch area calculation
> > failed in pipe %c\n",
> >  			      pipe_name(crtc->pipe));
> > @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	if (full_update)
> >  		goto skip_sel_fetch_set_loop;
> >  
> > -	intel_psr_apply_su_area_workarounds(crtc_state);
> > +	intel_psr_apply_su_area_workarounds(new_crtc_state);
> >  
> >  	ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > >base);
> >  	if (ret)
> > @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	 */
> >  	intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> >  
> > -	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> > +	intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
> >  
> >  	/*
> >  	 * Now that we have the pipe damaged area check if it
> > intersect with
> > @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		struct drm_rect *sel_fetch_area, inter;
> >  		struct intel_plane *linked = new_plane_state-
> > >planar_linked_plane;
> >  
> > -		if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc ||
> > +		if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc ||
> >  		    !new_plane_state->uapi.visible)
> >  			continue;
> >  
> > -		inter = crtc_state->psr2_su_area;
> > +		inter = new_crtc_state->psr2_su_area;
> >  		sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> >  		if (!drm_rect_intersect(&inter, &new_plane_state-
> > >uapi.dst)) {
> >  			sel_fetch_area->y1 = -1;
> > @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			 * disable it
> >  			 */
> >  			if (drm_rect_height(&old_plane_state-
> > >psr2_sel_fetch_area) > 0)
> > -				crtc_state->update_planes |=
> > BIT(plane->id);
> > +				new_crtc_state->update_planes |=
> > BIT(plane->id);
> >  
> >  			continue;
> >  		}
> >  
> > -		if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > +		if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> >  			full_update = true;
> >  			break;
> >  		}
> > @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> >  		sel_fetch_area->y1 = inter.y1 - new_plane_state-
> > >uapi.dst.y1;
> >  		sel_fetch_area->y2 = inter.y2 - new_plane_state-
> > >uapi.dst.y1;
> > -		crtc_state->update_planes |= BIT(plane->id);
> > +		new_crtc_state->update_planes |= BIT(plane->id);
> >  
> >  		/*
> >  		 * Sel_fetch_area is calculated for UV plane. Use
> > @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			linked_sel_fetch_area =
> > &linked_new_plane_state->psr2_sel_fetch_area;
> >  			linked_sel_fetch_area->y1 =
> > sel_fetch_area->y1;
> >  			linked_sel_fetch_area->y2 =
> > sel_fetch_area->y2;
> > -			crtc_state->update_planes |= BIT(linked-
> > >id);
> > +			new_crtc_state->update_planes |=
> > BIT(linked->id);
> >  		}
> >  	}
> >  
> >  skip_sel_fetch_set_loop:
> > -	psr2_man_trk_ctl_calc(crtc_state, full_update);
> > -	crtc_state->pipe_srcsz_early_tpt =
> > -		psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > +	psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> > +	new_crtc_state->pipe_srcsz_early_tpt =
> > +		psr2_pipe_srcsz_early_tpt_calc(new_crtc_state,
> > full_update);
> >  	return 0;
> >  }
> >  
> > -- 
> > 2.43.0
> 

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Ville Syrjälä]

On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > According to bspec selective fetch is not supported with async
> > > flips and
> > > instructing full frame update on async flip.
> > > 
> > > v3:
> > >   - rebase
> > >   - fix old_crtc_state->pipe_srcsz_early_tpt
> > >   - fix using intel_atomic_get_new_crtc_state
> > > v2:
> > >   - check also crtc_state->async_flip_planes in
> > >     psr2_sel_fetch_plane_state_supported
> > > 
> > > Bspec: 55229
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > > ----
> > >  1 file changed, 41 insertions(+), 31 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 15ef3b6caad6..53cf292247d7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > > intel_atomic_state *state,
> > >   * Plane scaling and rotation is not supported by selective fetch
> > > and both
> > >   * properties can change without a modeset, so need to be check at
> > > every
> > >   * atomic commit.
> > > + *
> > > + * If plane was having async flip previously we can't use
> > > selective
> > > + * fetch as we don't know if the flip is completed.
> > >   */
> > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > intel_plane_state *plane_state)
> > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > intel_crtc_state *old_crtc_state,
> > > +						 const struct
> > > intel_plane_state *plane_state)
> > >  {
> > > +	struct intel_plane *plane = to_intel_plane(plane_state-
> > > >uapi.plane);
> > > +
> > >  	if (plane_state->uapi.dst.y1 < 0 ||
> > >  	    plane_state->uapi.dst.x1 < 0 ||
> > >  	    plane_state->scaler_id >= 0 ||
> > > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > +	    old_crtc_state->async_flip_planes & plane->id)
> > 
> > Why are you looking at the old crtc state? There should be nothing of
> > interest to us there.
> 
> To continue keeping CFF bit set if previous update was async flip. This
> is how I understood it (please correct):
> 
> 0. syncronous update
> 
> 1. async_flip:
>    new_crtc_state->async_flip_planes != 0
>    old_crtc_state->async_flip_planes == 0
>    crtc_state->uapi.async_flip == true)
>    -> full frame update
> 
> 2. async_flip:
>    new_crtc_state->async_flip_planes != 0
>    old_crtc_state->async_flip_planes != 0
>    crtc_state->uapi.async_flip == true
>    -> full frame update
> 
> 3. syncronous update
>    new_crtc_state->async_flip_planes == 0
>    old_crtc_state->async_flip_planes != 0
>    crtc_state->uapi.async_flip == false
>    -> full frame update
> 
> 4. syncronous update
>    new_crtc_state->async_flip_planes == 0
>    old_crtc_state->async_flip_planes == 0
>    crtc_state->uapi.async_flip == false
>    -> selective update
> 
> > 
> > >  		return false;
> > >  
> > >  	return true;
> > > @@ -2749,7 +2756,8 @@ static bool
> > > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> > >   */
> > >  static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > intel_crtc_state *crtc_state)
> > >  {
> > > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > +	    crtc_state->uapi.async_flip)
> > 
> > I think just checking crtc_state->async_flip_planes!=0 here should be
> > sufficient.
> 
> I'm doing this to handle step 1. above. Alternatively I could check
> both new_crtc_state->async_flip_planes and old_crtc_state-
> >async_flip_planes. When using crtc_state->uapi.async_flip I can decide
> earlier.
> 
> > The rest of the patch seems unnecessary.
> 
> No need to handle selective update where planes having pending async
> flip are not involved?

There won't be pending flips of any kind. We whole CRTC commit queue
is handled in a strict FIFO order (apart from the legacy cursor
special case).

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Hogander, Jouni]

On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > > According to bspec selective fetch is not supported with async
> > > > flips and
> > > > instructing full frame update on async flip.
> > > > 
> > > > v3:
> > > >   - rebase
> > > >   - fix old_crtc_state->pipe_srcsz_early_tpt
> > > >   - fix using intel_atomic_get_new_crtc_state
> > > > v2:
> > > >   - check also crtc_state->async_flip_planes in
> > > >     psr2_sel_fetch_plane_state_supported
> > > > 
> > > > Bspec: 55229
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++--
> > > > ----
> > > > ----
> > > >  1 file changed, 41 insertions(+), 31 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -2728,13 +2728,20 @@
> > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > intel_atomic_state *state,
> > > >   * Plane scaling and rotation is not supported by selective
> > > > fetch
> > > > and both
> > > >   * properties can change without a modeset, so need to be
> > > > check at
> > > > every
> > > >   * atomic commit.
> > > > + *
> > > > + * If plane was having async flip previously we can't use
> > > > selective
> > > > + * fetch as we don't know if the flip is completed.
> > > >   */
> > > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_plane_state *plane_state)
> > > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_crtc_state *old_crtc_state,
> > > > +						 const struct
> > > > intel_plane_state *plane_state)
> > > >  {
> > > > +	struct intel_plane *plane =
> > > > to_intel_plane(plane_state-
> > > > > uapi.plane);
> > > > +
> > > >  	if (plane_state->uapi.dst.y1 < 0 ||
> > > >  	    plane_state->uapi.dst.x1 < 0 ||
> > > >  	    plane_state->scaler_id >= 0 ||
> > > > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > > +	    old_crtc_state->async_flip_planes & plane->id)
> > > 
> > > Why are you looking at the old crtc state? There should be
> > > nothing of
> > > interest to us there.
> > 
> > To continue keeping CFF bit set if previous update was async flip.
> > This
> > is how I understood it (please correct):
> > 
> > 0. syncronous update
> > 
> > 1. async_flip:
> >    new_crtc_state->async_flip_planes != 0
> >    old_crtc_state->async_flip_planes == 0
> >    crtc_state->uapi.async_flip == true)
> >    -> full frame update
> > 
> > 2. async_flip:
> >    new_crtc_state->async_flip_planes != 0
> >    old_crtc_state->async_flip_planes != 0
> >    crtc_state->uapi.async_flip == true
> >    -> full frame update
> > 
> > 3. syncronous update
> >    new_crtc_state->async_flip_planes == 0
> >    old_crtc_state->async_flip_planes != 0
> >    crtc_state->uapi.async_flip == false
> >    -> full frame update
> > 
> > 4. syncronous update
> >    new_crtc_state->async_flip_planes == 0
> >    old_crtc_state->async_flip_planes == 0
> >    crtc_state->uapi.async_flip == false
> >    -> selective update
> > 
> > > 
> > > >  		return false;
> > > >  
> > > >  	return true;
> > > > @@ -2749,7 +2756,8 @@ static bool
> > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_plane_state
> > > >   */
> > > >  static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > > intel_crtc_state *crtc_state)
> > > >  {
> > > > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > > > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > +	    crtc_state->uapi.async_flip)
> > > 
> > > I think just checking crtc_state->async_flip_planes!=0 here
> > > should be
> > > sufficient.
> > 
> > I'm doing this to handle step 1. above. Alternatively I could check
> > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > async_flip_planes. When using crtc_state->uapi.async_flip I can
> > > decide
> > earlier.
> > 
> > > The rest of the patch seems unnecessary.
> > 
> > No need to handle selective update where planes having pending
> > async
> > flip are not involved?
> 
> There won't be pending flips of any kind. We whole CRTC commit queue
> is handled in a strict FIFO order (apart from the legacy cursor
> special case).
> 

Ok, so it's not possible to take in new CRTC commit before async flip
is completed?

BR,

Jouni Högander

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Ville Syrjälä]

On Wed, Dec 03, 2025 at 03:13:11PM +0000, Hogander, Jouni wrote:
> On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> > On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > > > According to bspec selective fetch is not supported with async
> > > > > flips and
> > > > > instructing full frame update on async flip.
> > > > > 
> > > > > v3:
> > > > >   - rebase
> > > > >   - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > >   - fix using intel_atomic_get_new_crtc_state
> > > > > v2:
> > > > >   - check also crtc_state->async_flip_planes in
> > > > >     psr2_sel_fetch_plane_state_supported
> > > > > 
> > > > > Bspec: 55229
> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++--
> > > > > ----
> > > > > ----
> > > > >  1 file changed, 41 insertions(+), 31 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -2728,13 +2728,20 @@
> > > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > > intel_atomic_state *state,
> > > > >   * Plane scaling and rotation is not supported by selective
> > > > > fetch
> > > > > and both
> > > > >   * properties can change without a modeset, so need to be
> > > > > check at
> > > > > every
> > > > >   * atomic commit.
> > > > > + *
> > > > > + * If plane was having async flip previously we can't use
> > > > > selective
> > > > > + * fetch as we don't know if the flip is completed.
> > > > >   */
> > > > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_plane_state *plane_state)
> > > > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_crtc_state *old_crtc_state,
> > > > > +						 const struct
> > > > > intel_plane_state *plane_state)
> > > > >  {
> > > > > +	struct intel_plane *plane =
> > > > > to_intel_plane(plane_state-
> > > > > > uapi.plane);
> > > > > +
> > > > >  	if (plane_state->uapi.dst.y1 < 0 ||
> > > > >  	    plane_state->uapi.dst.x1 < 0 ||
> > > > >  	    plane_state->scaler_id >= 0 ||
> > > > > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > > > +	    old_crtc_state->async_flip_planes & plane->id)
> > > > 
> > > > Why are you looking at the old crtc state? There should be
> > > > nothing of
> > > > interest to us there.
> > > 
> > > To continue keeping CFF bit set if previous update was async flip.
> > > This
> > > is how I understood it (please correct):
> > > 
> > > 0. syncronous update
> > > 
> > > 1. async_flip:
> > >    new_crtc_state->async_flip_planes != 0
> > >    old_crtc_state->async_flip_planes == 0
> > >    crtc_state->uapi.async_flip == true)
> > >    -> full frame update
> > > 
> > > 2. async_flip:
> > >    new_crtc_state->async_flip_planes != 0
> > >    old_crtc_state->async_flip_planes != 0
> > >    crtc_state->uapi.async_flip == true
> > >    -> full frame update
> > > 
> > > 3. syncronous update
> > >    new_crtc_state->async_flip_planes == 0
> > >    old_crtc_state->async_flip_planes != 0
> > >    crtc_state->uapi.async_flip == false
> > >    -> full frame update
> > > 
> > > 4. syncronous update
> > >    new_crtc_state->async_flip_planes == 0
> > >    old_crtc_state->async_flip_planes == 0
> > >    crtc_state->uapi.async_flip == false
> > >    -> selective update
> > > 
> > > > 
> > > > >  		return false;
> > > > >  
> > > > >  	return true;
> > > > > @@ -2749,7 +2756,8 @@ static bool
> > > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_plane_state
> > > > >   */
> > > > >  static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > > > intel_crtc_state *crtc_state)
> > > > >  {
> > > > > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > > +	    crtc_state->uapi.async_flip)
> > > > 
> > > > I think just checking crtc_state->async_flip_planes!=0 here
> > > > should be
> > > > sufficient.
> > > 
> > > I'm doing this to handle step 1. above. Alternatively I could check
> > > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > > async_flip_planes. When using crtc_state->uapi.async_flip I can
> > > > decide
> > > earlier.
> > > 
> > > > The rest of the patch seems unnecessary.
> > > 
> > > No need to handle selective update where planes having pending
> > > async
> > > flip are not involved?
> > 
> > There won't be pending flips of any kind. We whole CRTC commit queue
> > is handled in a strict FIFO order (apart from the legacy cursor
> > special case).
> > 
> 
> Ok, so it's not possible to take in new CRTC commit before async flip
> is completed?

More or less. The new request can come in before that, but it won't
be commited to the hardware until the previous one has finished.

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Hogander, Jouni]

On Wed, 2025-12-03 at 17:55 +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2025 at 03:13:11PM +0000, Hogander, Jouni wrote:
> > On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> > > On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > > > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander
> > > > > wrote:
> > > > > > According to bspec selective fetch is not supported with
> > > > > > async
> > > > > > flips and
> > > > > > instructing full frame update on async flip.
> > > > > > 
> > > > > > v3:
> > > > > >   - rebase
> > > > > >   - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > > >   - fix using intel_atomic_get_new_crtc_state
> > > > > > v2:
> > > > > >   - check also crtc_state->async_flip_planes in
> > > > > >     psr2_sel_fetch_plane_state_supported
> > > > > > 
> > > > > > Bspec: 55229
> > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.c | 72
> > > > > > ++++++++++++++--
> > > > > > ----
> > > > > > ----
> > > > > >  1 file changed, 41 insertions(+), 31 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -2728,13 +2728,20 @@
> > > > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > > > intel_atomic_state *state,
> > > > > >   * Plane scaling and rotation is not supported by
> > > > > > selective
> > > > > > fetch
> > > > > > and both
> > > > > >   * properties can change without a modeset, so need to be
> > > > > > check at
> > > > > > every
> > > > > >   * atomic commit.
> > > > > > + *
> > > > > > + * If plane was having async flip previously we can't use
> > > > > > selective
> > > > > > + * fetch as we don't know if the flip is completed.
> > > > > >   */
> > > > > > -static bool psr2_sel_fetch_plane_state_supported(const
> > > > > > struct
> > > > > > intel_plane_state *plane_state)
> > > > > > +static bool psr2_sel_fetch_plane_state_supported(const
> > > > > > struct
> > > > > > intel_crtc_state *old_crtc_state,
> > > > > > +						 const
> > > > > > struct
> > > > > > intel_plane_state *plane_state)
> > > > > >  {
> > > > > > +	struct intel_plane *plane =
> > > > > > to_intel_plane(plane_state-
> > > > > > > uapi.plane);
> > > > > > +
> > > > > >  	if (plane_state->uapi.dst.y1 < 0 ||
> > > > > >  	    plane_state->uapi.dst.x1 < 0 ||
> > > > > >  	    plane_state->scaler_id >= 0 ||
> > > > > > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > > > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0
> > > > > > ||
> > > > > > +	    old_crtc_state->async_flip_planes & plane->id)
> > > > > 
> > > > > Why are you looking at the old crtc state? There should be
> > > > > nothing of
> > > > > interest to us there.
> > > > 
> > > > To continue keeping CFF bit set if previous update was async
> > > > flip.
> > > > This
> > > > is how I understood it (please correct):
> > > > 
> > > > 0. syncronous update
> > > > 
> > > > 1. async_flip:
> > > >    new_crtc_state->async_flip_planes != 0
> > > >    old_crtc_state->async_flip_planes == 0
> > > >    crtc_state->uapi.async_flip == true)
> > > >    -> full frame update
> > > > 
> > > > 2. async_flip:
> > > >    new_crtc_state->async_flip_planes != 0
> > > >    old_crtc_state->async_flip_planes != 0
> > > >    crtc_state->uapi.async_flip == true
> > > >    -> full frame update
> > > > 
> > > > 3. syncronous update
> > > >    new_crtc_state->async_flip_planes == 0
> > > >    old_crtc_state->async_flip_planes != 0
> > > >    crtc_state->uapi.async_flip == false
> > > >    -> full frame update
> > > > 
> > > > 4. syncronous update
> > > >    new_crtc_state->async_flip_planes == 0
> > > >    old_crtc_state->async_flip_planes == 0
> > > >    crtc_state->uapi.async_flip == false
> > > >    -> selective update
> > > > 
> > > > > 
> > > > > >  		return false;
> > > > > >  
> > > > > >  	return true;
> > > > > > @@ -2749,7 +2756,8 @@ static bool
> > > > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > > > intel_plane_state
> > > > > >   */
> > > > > >  static bool psr2_sel_fetch_pipe_state_supported(const
> > > > > > struct
> > > > > > intel_crtc_state *crtc_state)
> > > > > >  {
> > > > > > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > > > +	    crtc_state->uapi.async_flip)
> > > > > 
> > > > > I think just checking crtc_state->async_flip_planes!=0 here
> > > > > should be
> > > > > sufficient.
> > > > 
> > > > I'm doing this to handle step 1. above. Alternatively I could
> > > > check
> > > > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > > > async_flip_planes. When using crtc_state->uapi.async_flip I
> > > > > can
> > > > > decide
> > > > earlier.
> > > > 
> > > > > The rest of the patch seems unnecessary.
> > > > 
> > > > No need to handle selective update where planes having pending
> > > > async
> > > > flip are not involved?
> > > 
> > > There won't be pending flips of any kind. We whole CRTC commit
> > > queue
> > > is handled in a strict FIFO order (apart from the legacy cursor
> > > special case).
> > > 
> > 
> > Ok, so it's not possible to take in new CRTC commit before async
> > flip
> > is completed?
> 
> More or less. The new request can come in before that, but it won't
> be commited to the hardware until the previous one has finished.
> 

Ok, I misunderstood your original comment. I got impression it's
different for async flip.

BR,

Jouni Högander

Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip

[Hogander, Jouni]

On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > According to bspec selective fetch is not supported with async
> > flips and
> > instructing full frame update on async flip.
> > 
> > v3:
> >   - rebase
> >   - fix old_crtc_state->pipe_srcsz_early_tpt
> >   - fix using intel_atomic_get_new_crtc_state
> > v2:
> >   - check also crtc_state->async_flip_planes in
> >     psr2_sel_fetch_plane_state_supported
> > 
> > Bspec: 55229
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > ----
> >  1 file changed, 41 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 15ef3b6caad6..53cf292247d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > intel_atomic_state *state,
> >   * Plane scaling and rotation is not supported by selective fetch
> > and both
> >   * properties can change without a modeset, so need to be check at
> > every
> >   * atomic commit.
> > + *
> > + * If plane was having async flip previously we can't use
> > selective
> > + * fetch as we don't know if the flip is completed.
> >   */
> > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_plane_state *plane_state)
> > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_crtc_state *old_crtc_state,
> > +						 const struct
> > intel_plane_state *plane_state)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(plane_state-
> > >uapi.plane);
> > +
> >  	if (plane_state->uapi.dst.y1 < 0 ||
> >  	    plane_state->uapi.dst.x1 < 0 ||
> >  	    plane_state->scaler_id >= 0 ||
> > -	    plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > +	    plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > +	    old_crtc_state->async_flip_planes & plane->id)
> 
> Why are you looking at the old crtc state? There should be nothing of
> interest to us there.
> 
> >  		return false;
> >  
> >  	return true;
> > @@ -2749,7 +2756,8 @@ static bool
> > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> >   */
> >  static bool psr2_sel_fetch_pipe_state_supported(const struct
> > intel_crtc_state *crtc_state)
> >  {
> > -	if (crtc_state->scaler_state.scaler_id >= 0)
> > +	if (crtc_state->scaler_state.scaler_id >= 0 ||
> > +	    crtc_state->uapi.async_flip)
> 
> I think just checking crtc_state->async_flip_planes!=0 here should be
> sufficient. The rest of the patch seems unnecessary.
> 
> On a related note, someone should add a new igt that does async flips
> while eg. the cursor is enabled and overlapping the plane doing the
> async flips. That's basically how I noticed the problem in the first
> place (with Xorg), so would be good to have an igt to make sure we
> don't break this in the future.

I will add ticket for this.

BR,

Jouni Högander

> 
> >  		return false;
> >  
> >  	return true;
> > @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  				struct intel_crtc *crtc)
> >  {
> >  	struct intel_display *display = to_intel_display(state);
> > -	struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > +	struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > +	struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> >  	struct intel_plane_state *new_plane_state,
> > *old_plane_state;
> >  	struct intel_plane *plane;
> >  	bool full_update = false, cursor_in_su_area = false;
> >  	int i, ret;
> >  
> > -	if (!crtc_state->enable_psr2_sel_fetch)
> > +	if (!new_crtc_state->enable_psr2_sel_fetch)
> >  		return 0;
> >  
> > -	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> > +	if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state))
> > {
> >  		full_update = true;
> >  		goto skip_sel_fetch_set_loop;
> >  	}
> >  
> > -	crtc_state->psr2_su_area.x1 = 0;
> > -	crtc_state->psr2_su_area.y1 = -1;
> > -	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state-
> > >pipe_src);
> > -	crtc_state->psr2_su_area.y2 = -1;
> > +	new_crtc_state->psr2_su_area.x1 = 0;
> > +	new_crtc_state->psr2_su_area.y1 = -1;
> > +	new_crtc_state->psr2_su_area.x2 =
> > drm_rect_width(&new_crtc_state->pipe_src);
> > +	new_crtc_state->psr2_su_area.y2 = -1;
> >  
> >  	/*
> >  	 * Calculate minimal selective fetch area of each plane
> > and calculate
> > @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		struct drm_rect src, damaged_area = { .x1 = 0, .y1
> > = -1,
> >  						      .x2 =
> > INT_MAX };
> >  
> > -		if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc)
> > +		if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc)
> >  			continue;
> >  
> >  		if (!new_plane_state->uapi.visible &&
> >  		    !old_plane_state->uapi.visible)
> >  			continue;
> >  
> > -		if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > +		if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> >  			full_update = true;
> >  			break;
> >  		}
> > @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			if (old_plane_state->uapi.visible) {
> >  				damaged_area.y1 = old_plane_state-
> > >uapi.dst.y1;
> >  				damaged_area.y2 = old_plane_state-
> > >uapi.dst.y2;
> > -				clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -						 &crtc_state-
> > >pipe_src);
> > +				clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +						 &new_crtc_state-
> > >pipe_src);
> >  			}
> >  
> >  			if (new_plane_state->uapi.visible) {
> >  				damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> >  				damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > -				clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -						 &crtc_state-
> > >pipe_src);
> > +				clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +						 &new_crtc_state-
> > >pipe_src);
> >  			}
> >  			continue;
> >  		} else if (new_plane_state->uapi.alpha !=
> > old_plane_state->uapi.alpha) {
> >  			/* If alpha changed mark the whole plane
> > area as damaged */
> >  			damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> >  			damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > -			clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > -					 &crtc_state->pipe_src);
> > +			clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > +					 &new_crtc_state-
> > >pipe_src);
> >  			continue;
> >  		}
> >  
> > @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		damaged_area.x1 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >  		damaged_area.x2 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >  
> > -		clip_area_update(&crtc_state->psr2_su_area,
> > &damaged_area, &crtc_state->pipe_src);
> > +		clip_area_update(&new_crtc_state->psr2_su_area,
> > &damaged_area,
> > +				 &new_crtc_state->pipe_src);
> >  	}
> >  
> >  	/*
> > @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	 * should identify cases where this happens and fix the
> > area
> >  	 * calculation for those.
> >  	 */
> > -	if (crtc_state->psr2_su_area.y1 == -1) {
> > +	if (new_crtc_state->psr2_su_area.y1 == -1) {
> >  		drm_info_once(display->drm,
> >  			      "Selective fetch area calculation
> > failed in pipe %c\n",
> >  			      pipe_name(crtc->pipe));
> > @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	if (full_update)
> >  		goto skip_sel_fetch_set_loop;
> >  
> > -	intel_psr_apply_su_area_workarounds(crtc_state);
> > +	intel_psr_apply_su_area_workarounds(new_crtc_state);
> >  
> >  	ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > >base);
> >  	if (ret)
> > @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  	 */
> >  	intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> >  
> > -	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> > +	intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
> >  
> >  	/*
> >  	 * Now that we have the pipe damaged area check if it
> > intersect with
> > @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		struct drm_rect *sel_fetch_area, inter;
> >  		struct intel_plane *linked = new_plane_state-
> > >planar_linked_plane;
> >  
> > -		if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc ||
> > +		if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc ||
> >  		    !new_plane_state->uapi.visible)
> >  			continue;
> >  
> > -		inter = crtc_state->psr2_su_area;
> > +		inter = new_crtc_state->psr2_su_area;
> >  		sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> >  		if (!drm_rect_intersect(&inter, &new_plane_state-
> > >uapi.dst)) {
> >  			sel_fetch_area->y1 = -1;
> > @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			 * disable it
> >  			 */
> >  			if (drm_rect_height(&old_plane_state-
> > >psr2_sel_fetch_area) > 0)
> > -				crtc_state->update_planes |=
> > BIT(plane->id);
> > +				new_crtc_state->update_planes |=
> > BIT(plane->id);
> >  
> >  			continue;
> >  		}
> >  
> > -		if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > +		if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> >  			full_update = true;
> >  			break;
> >  		}
> > @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  		sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> >  		sel_fetch_area->y1 = inter.y1 - new_plane_state-
> > >uapi.dst.y1;
> >  		sel_fetch_area->y2 = inter.y2 - new_plane_state-
> > >uapi.dst.y1;
> > -		crtc_state->update_planes |= BIT(plane->id);
> > +		new_crtc_state->update_planes |= BIT(plane->id);
> >  
> >  		/*
> >  		 * Sel_fetch_area is calculated for UV plane. Use
> > @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >  			linked_sel_fetch_area =
> > &linked_new_plane_state->psr2_sel_fetch_area;
> >  			linked_sel_fetch_area->y1 =
> > sel_fetch_area->y1;
> >  			linked_sel_fetch_area->y2 =
> > sel_fetch_area->y2;
> > -			crtc_state->update_planes |= BIT(linked-
> > >id);
> > +			new_crtc_state->update_planes |=
> > BIT(linked->id);
> >  		}
> >  	}
> >  
> >  skip_sel_fetch_set_loop:
> > -	psr2_man_trk_ctl_calc(crtc_state, full_update);
> > -	crtc_state->pipe_srcsz_early_tpt =
> > -		psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > +	psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> > +	new_crtc_state->pipe_srcsz_early_tpt =
> > +		psr2_pipe_srcsz_early_tpt_calc(new_crtc_state,
> > full_update);
> >  	return 0;
> >  }
> >  
> > -- 
> > 2.43.0
> 

[PATCH v3 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled

[Jouni Högander]

Now as Selective Fetch is performing full frame update on async flip and
vblank evasion is done as needed we can allow async flip even when
Selective Fetch is enabled.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e5ce47efc809..b262c033f24e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6017,14 +6017,6 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
 		return -EINVAL;
 	}
 
-	/* FIXME: selective fetch should be disabled for async flips */
-	if (new_crtc_state->enable_psr2_sel_fetch) {
-		drm_dbg_kms(display->drm,
-			    "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
-			    crtc->base.base.id, crtc->base.name);
-		return -EINVAL;
-	}
-
 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 					     new_plane_state, i) {
 		if (plane->pipe != crtc->pipe)
-- 
2.43.0

✗ i915.CI.BAT: failure for Selective Fetch and async flip (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4104 bytes --]

== Series Details ==

Series: Selective Fetch and async flip (rev3)
URL   : https://patchwork.freedesktop.org/series/158003/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17613 -> Patchwork_158003v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_158003v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_158003v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_158003v3:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - bat-rplp-1:         [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-rplp-1/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-rplp-1/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_158003v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-arls-5:         [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-arls-5/igt@i915_selftest@live@workarounds.html
    - bat-dg2-9:          [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-11:         [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17613/bat-dg2-11/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/bat-dg2-11/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_17613 -> Patchwork_158003v3

  CI-20190529: 20190529
  CI_DRM_17613: 4ee45005b5548f7cf1ab059413eaaa41dbd2ecf6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8646: 8646
  Patchwork_158003v3: 4ee45005b5548f7cf1ab059413eaaa41dbd2ecf6 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v3/index.html

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✓ i915.CI.BAT: success for Selective Fetch and async flip (rev4)

[Patchwork]

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== Series Details ==

Series: Selective Fetch and async flip (rev4)
URL   : https://patchwork.freedesktop.org/series/158003/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17618 -> Patchwork_158003v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v4/index.html

Participating hosts (40 -> 39)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_158003v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17618/bat-mtlp-8/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v4/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17618/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v4/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17618/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v4/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_17618 -> Patchwork_158003v4

  CI-20190529: 20190529
  CI_DRM_17618: 4ffeb1fd1362e2148a7ada498cbaef7b1de27867 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8647: 8647
  Patchwork_158003v4: 4ffeb1fd1362e2148a7ada498cbaef7b1de27867 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158003v4/index.html

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