[PATCH] drm/i915/display: Enable AS SDP Skip Frames

[PATCH] drm/i915/display: Enable AS SDP Skip Frames

[Uma Shankar]

Hardware provides mechanism to skip AS SDP for programmed
number of frames. Enable the same to drive to 1Hz if hardware
supports it.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 3 +++
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index b3334bc4d0f9..76a8919cdba2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -395,6 +395,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			if (crtc_state->disable_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
+			if (DISPLAY_VER(display) >= 35)
+				pr_alpm_ctl |= PR_ALPM_CTL_ASSDP_SKIP_FRAMES(32);
+
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
 				       pr_alpm_ctl);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..8c35df795955 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -268,6 +268,8 @@
 
 #define _PR_ALPM_CTL_A	0x60948
 #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
+#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK			REG_GENMASK(27, 16)
+#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES(val)			REG_FIELD_PREP(PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK, val)
 #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
 #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
 #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
-- 
2.50.1

✗ i915.CI.BAT: failure for drm/i915/display: Enable AS SDP Skip Frames

[Patchwork]

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== Series Details ==

Series: drm/i915/display: Enable AS SDP Skip Frames
URL   : https://patchwork.freedesktop.org/series/162016/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18022 -> Patchwork_162016v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_162016v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_162016v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162016v1/index.html

Participating hosts (43 -> 41)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_162016v1:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_pipe_crc_basic@read-crc:
    - fi-cfl-8109u:       [PASS][1] -> [DMESG-WARN][2] +48 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18022/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162016v1/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html

  
Known issues
------------

  Here are the changes found in Patchwork_162016v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18022/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162016v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18022/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162016v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_18022 -> Patchwork_162016v1

  CI-20190529: 20190529
  CI_DRM_18022: 45a3045fc0dc46a893cb8bbe304afafd4120c904 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8765: 8765
  Patchwork_162016v1: 45a3045fc0dc46a893cb8bbe304afafd4120c904 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162016v1/index.html

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Re: [PATCH] drm/i915/display: Enable AS SDP Skip Frames

[Ville Syrjälä]

On Tue, Feb 24, 2026 at 02:37:07AM +0530, Uma Shankar wrote:
> Hardware provides mechanism to skip AS SDP for programmed
> number of frames. Enable the same to drive to 1Hz if hardware
> supports it.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 3 +++
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index b3334bc4d0f9..76a8919cdba2 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -395,6 +395,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			if (crtc_state->disable_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
>  
> +			if (DISPLAY_VER(display) >= 35)
> +				pr_alpm_ctl |= PR_ALPM_CTL_ASSDP_SKIP_FRAMES(32);

Where did that magic 32 frames come from?

This whole thing seems to involve a lot of details (Bspec:75539)
that someone needs to think through.

There are also some things in the DP 2.1a spec (eg. 2.18.8.1.1
Enabling Autonomous Sink Device Refresh Rate Timing) that seem
relevant for this stuff. Sadly the bspec page makes no mention
of any of this :/

> +
>  			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
>  				       pr_alpm_ctl);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8afbf5a38335..8c35df795955 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -268,6 +268,8 @@
>  
>  #define _PR_ALPM_CTL_A	0x60948
>  #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
> +#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK			REG_GENMASK(27, 16)
> +#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES(val)			REG_FIELD_PREP(PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK, val)
>  #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
>  #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
>  #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
> -- 
> 2.50.1

-- 
Ville Syrjälä
Intel

RE: [PATCH] drm/i915/display: Enable AS SDP Skip Frames

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 24, 2026 1:43 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Golani,
> Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: Re: [PATCH] drm/i915/display: Enable AS SDP Skip Frames
> 
> On Tue, Feb 24, 2026 at 02:37:07AM +0530, Uma Shankar wrote:
> > Hardware provides mechanism to skip AS SDP for programmed number of
> > frames. Enable the same to drive to 1Hz if hardware supports it.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c     | 3 +++
> >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++
> >  2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index b3334bc4d0f9..76a8919cdba2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -395,6 +395,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
> >  			if (crtc_state->disable_as_sdp_when_pr_active)
> >  				pr_alpm_ctl |=
> PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
> >
> > +			if (DISPLAY_VER(display) >= 35)
> > +				pr_alpm_ctl |=
> PR_ALPM_CTL_ASSDP_SKIP_FRAMES(32);
> 
> Where did that magic 32 frames come from?

Sorry missed to call out, this is just a default value to test on hardware.
Will update it and make it truly programmable.

> This whole thing seems to involve a lot of details (Bspec:75539) that someone
> needs to think through.
> 
> There are also some things in the DP 2.1a spec (eg. 2.18.8.1.1 Enabling
> Autonomous Sink Device Refresh Rate Timing) that seem relevant for this stuff.
> Sadly the bspec page makes no mention of any of this :/

I will try to add the relevant restrictions and DC3Co dependencies. Need to check on hardware
to cover all corner cases.

Thanks Ville for pointing out the DP spec link relevant to this. Will refer and get back.

Regards,
Uma Shankar

> > +
> >  			intel_de_write(display, PR_ALPM_CTL(display,
> cpu_transcoder),
> >  				       pr_alpm_ctl);
> >  		}
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > index 8afbf5a38335..8c35df795955 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > @@ -268,6 +268,8 @@
> >
> >  #define _PR_ALPM_CTL_A	0x60948
> >  #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran,
> _PR_ALPM_CTL_A)
> > +#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK
> 	REG_GENMASK(27, 16)
> > +#define  PR_ALPM_CTL_ASSDP_SKIP_FRAMES(val)
> 	REG_FIELD_PREP(PR_ALPM_CTL_ASSDP_SKIP_FRAMES_MASK, val)
> >  #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU
> 	BIT(6)
> >  #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL
> 	BIT(5)
> >  #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE
> 	BIT(4)
> > --
> > 2.50.1
> 
> --
> Ville Syrjälä
> Intel