[PATCH] drm/i915/bw: reduce the pm demand peak bw based on display data-rate

[PATCH] drm/i915/bw: reduce the pm demand peak bw based on display data-rate

[Vinod Govindapillai]

In xe3+, soc can lower the fabric frequency when the display
needs less bandwidth than the minimum GV point. The threshold
has been defined as 20GB/s. So if the required display data rate
is less than this threshold and the slelected GV point is 0 and
the GV point peak bw is greater than 20GB/s, we could set the
peak bw for the pm demand to this threshold. The currentc pcode
can handle this and adjust the fabric frequency accordingly.

Bspec: 68880
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 9c3a9bbb49f6..005761baca93 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -52,6 +52,8 @@ struct intel_qgv_point {
 
 #define DEPROGBWPCLIMIT		60
 
+#define XE3_PEAK_BW_THRESHOLD	20000
+
 struct intel_psf_gv_point {
 	u8 clk; /* clock in multiples of 16.6666 MHz */
 };
@@ -1045,6 +1047,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
 	unsigned int best_rate = UINT_MAX;
 	unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
 	unsigned int qgv_peak_bw  = 0;
+	int qgv_point = num_qgv_points;
 	int i;
 	int ret;
 
@@ -1083,6 +1086,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
 		if (max_data_rate - data_rate < best_rate) {
 			best_rate = max_data_rate - data_rate;
 			qgv_peak_bw = display->bw.max[bw_index].peakbw[i];
+			qgv_point = i;
 		}
 
 		drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
@@ -1102,6 +1106,18 @@ static int mtl_find_qgv_points(struct intel_display *display,
 		return -EINVAL;
 	}
 
+	/*
+	 * For xe3+, if display's required memory bw <= 20GB/s and the selected
+	 * peak bw of QGV[0] is >= 20 GB/s, we can reduce the peak bw for the
+	 * pm demand QCLK GV to 20GB/s
+	 */
+	if (DISPLAY_VER(display) >= 30 && data_rate <= XE3_PEAK_BW_THRESHOLD &&
+	    qgv_point == 0 && qgv_peak_bw >= XE3_PEAK_BW_THRESHOLD) {
+		qgv_peak_bw = XE3_PEAK_BW_THRESHOLD;
+		drm_dbg_kms(display->drm, "Low display data-rate. Reduce PM demand bw for QGV: %d",
+			    qgv_peak_bw);
+	}
+
 	/* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
 	new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
 
-- 
2.43.0

Re: [PATCH] drm/i915/bw: reduce the pm demand peak bw based on display data-rate

[Ville Syrjälä]

On Mon, Apr 27, 2026 at 12:11:16PM +0300, Vinod Govindapillai wrote:
> In xe3+, soc can lower the fabric frequency when the display
> needs less bandwidth than the minimum GV point. The threshold
> has been defined as 20GB/s. So if the required display data rate
> is less than this threshold and the slelected GV point is 0 and
> the GV point peak bw is greater than 20GB/s, we could set the
> peak bw for the pm demand to this threshold. The currentc pcode
> can handle this and adjust the fabric frequency accordingly.
> 
> Bspec: 68880
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 9c3a9bbb49f6..005761baca93 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -52,6 +52,8 @@ struct intel_qgv_point {
>  
>  #define DEPROGBWPCLIMIT		60
>  
> +#define XE3_PEAK_BW_THRESHOLD	20000
> +
>  struct intel_psf_gv_point {
>  	u8 clk; /* clock in multiples of 16.6666 MHz */
>  };
> @@ -1045,6 +1047,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
>  	unsigned int best_rate = UINT_MAX;
>  	unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;
>  	unsigned int qgv_peak_bw  = 0;
> +	int qgv_point = num_qgv_points;
>  	int i;
>  	int ret;
>  
> @@ -1083,6 +1086,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
>  		if (max_data_rate - data_rate < best_rate) {
>  			best_rate = max_data_rate - data_rate;
>  			qgv_peak_bw = display->bw.max[bw_index].peakbw[i];
> +			qgv_point = i;
>  		}
>  
>  		drm_dbg_kms(display->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n",
> @@ -1102,6 +1106,18 @@ static int mtl_find_qgv_points(struct intel_display *display,
>  		return -EINVAL;
>  	}
>  
> +	/*
> +	 * For xe3+, if display's required memory bw <= 20GB/s and the selected
> +	 * peak bw of QGV[0] is >= 20 GB/s, we can reduce the peak bw for the
> +	 * pm demand QCLK GV to 20GB/s
> +	 */
> +	if (DISPLAY_VER(display) >= 30 && data_rate <= XE3_PEAK_BW_THRESHOLD &&
> +	    qgv_point == 0 && qgv_peak_bw >= XE3_PEAK_BW_THRESHOLD) {
> +		qgv_peak_bw = XE3_PEAK_BW_THRESHOLD;
> +		drm_dbg_kms(display->drm, "Low display data-rate. Reduce PM demand bw for QGV: %d",
> +			    qgv_peak_bw);
> +	}

I can't figure out what that does. If this is the thing I think it is,
then the plan was to just add a new QGV point (in driver) for the lower
frequency.

> +
>  	/* MTL PM DEMAND expects QGV BW parameter in multiples of 100 mbps */
>  	new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
>  
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

Re: [PATCH] drm/i915/bw: reduce the pm demand peak bw based on display data-rate

[Govindapillai, Vinod]

On Mon, 2026-04-27 at 15:37 +0300, Ville Syrjälä wrote:
> On Mon, Apr 27, 2026 at 12:11:16PM +0300, Vinod Govindapillai wrote:
> > In xe3+, soc can lower the fabric frequency when the display
> > needs less bandwidth than the minimum GV point. The threshold
> > has been defined as 20GB/s. So if the required display data rate
> > is less than this threshold and the slelected GV point is 0 and
> > the GV point peak bw is greater than 20GB/s, we could set the
> > peak bw for the pm demand to this threshold. The currentc pcode
> > can handle this and adjust the fabric frequency accordingly.
> > 
> > Bspec: 68880
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 9c3a9bbb49f6..005761baca93 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -52,6 +52,8 @@ struct intel_qgv_point {
> >  
> >  #define DEPROGBWPCLIMIT		60
> >  
> > +#define XE3_PEAK_BW_THRESHOLD	20000
> > +
> >  struct intel_psf_gv_point {
> >  	u8 clk; /* clock in multiples of 16.6666 MHz */
> >  };
> > @@ -1045,6 +1047,7 @@ static int mtl_find_qgv_points(struct
> > intel_display *display,
> >  	unsigned int best_rate = UINT_MAX;
> >  	unsigned int num_qgv_points = display-
> > >bw.max[0].num_qgv_points;
> >  	unsigned int qgv_peak_bw  = 0;
> > +	int qgv_point = num_qgv_points;
> >  	int i;
> >  	int ret;
> >  
> > @@ -1083,6 +1086,7 @@ static int mtl_find_qgv_points(struct
> > intel_display *display,
> >  		if (max_data_rate - data_rate < best_rate) {
> >  			best_rate = max_data_rate - data_rate;
> >  			qgv_peak_bw = display-
> > >bw.max[bw_index].peakbw[i];
> > +			qgv_point = i;
> >  		}
> >  
> >  		drm_dbg_kms(display->drm, "QGV point %d: max bw %d
> > required %d qgv_peak_bw: %d\n",
> > @@ -1102,6 +1106,18 @@ static int mtl_find_qgv_points(struct
> > intel_display *display,
> >  		return -EINVAL;
> >  	}
> >  
> > +	/*
> > +	 * For xe3+, if display's required memory bw <= 20GB/s and
> > the selected
> > +	 * peak bw of QGV[0] is >= 20 GB/s, we can reduce the peak
> > bw for the
> > +	 * pm demand QCLK GV to 20GB/s
> > +	 */
> > +	if (DISPLAY_VER(display) >= 30 && data_rate <=
> > XE3_PEAK_BW_THRESHOLD &&
> > +	    qgv_point == 0 && qgv_peak_bw >=
> > XE3_PEAK_BW_THRESHOLD) {
> > +		qgv_peak_bw = XE3_PEAK_BW_THRESHOLD;
> > +		drm_dbg_kms(display->drm, "Low display data-rate.
> > Reduce PM demand bw for QGV: %d",
> > +			    qgv_peak_bw);
> > +	}
> 
> I can't figure out what that does. If this is the thing I think it
> is,
> then the plan was to just add a new QGV point (in driver) for the
> lower
> frequency.
> 
qgv_peak_bw will be set to 20gbps on the next pmdemand request if the
condition matches.
new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);

Technically it could be a new driver level QGV point as you mentioned.
But that would be tweaking the existing QGC points related code in PTL+
with populating rest of the struct intel_qgv_point members from qgv[0].
We have the maximum number of qgv points defined as 8. So if there were
8 points already defined in bios, we will be in trouble I think. 

Also I did not see any such plans if it was suggested somewhere. Could
you pls point that to me?

As per the Bspec 68880, this is what I found!
"
If lowest unmasked GV point is point 0 AND GV point 0 bandwidth >= 20
GB/s AND display required memory bandwidth <= 20 GB/s, PM_DMD Bandwidth
for QCLK GV = INT(200)
Else, PM_DMD Bandwidth for QCLK GV = INT(GV point bandwidth / 100) in
100s of MB/s 
"

BR
Vinod

> > +
> >  	/* MTL PM DEMAND expects QGV BW parameter in multiples of
> > 100 mbps */
> >  	new_bw_state->qgv_point_peakbw =
> > DIV_ROUND_CLOSEST(qgv_peak_bw, 100);
> >  
> > -- 
> > 2.43.0
>