From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v3 5/6] drm/i915/irq: add intel_display_irq_ack() to irq funcs
Date: Wed, 13 May 2026 17:30:27 +0300 [thread overview]
Message-ID: <agSLAz2q4ksazecu@intel.com> (raw)
In-Reply-To: <cdeee940180b0009bc71753e065c02cc496ae272.1778666967.git.jani.nikula@intel.com>
On Wed, May 13, 2026 at 01:10:10PM +0300, Jani Nikula wrote:
> Some platforms have a separate step for acking display irqs. Call the
> platform specific display irq ack hooks, if any, via
> intel_display_irq_ack().
>
> Introduce struct intel_display_irq_state to group together all the data
> the ack hooks need. In the follow-up, this state will be passed on to a
> shared handler function.
This also might be a bit cleaner done in two steps:
1. extract the gmch ack() funcs
2. add the vfunc
>
> Check for HAS_DISPLAY() in intel_display_irq_ack() for completeness even
> though fusing is not possible on the platforms in question.
>
> v2:
> - Include LPE audio in the ack part
> - Check for HAS_DISPLAY()
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 58 ++++++-
> .../gpu/drm/i915/display/intel_display_irq.h | 12 +-
> drivers/gpu/drm/i915/i915_irq.c | 144 ++++++------------
> 3 files changed, 113 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 1c3c8095765d..4b2a61e97ed1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -23,6 +23,7 @@
> #include "intel_fifo_underrun.h"
> #include "intel_gmbus.h"
> #include "intel_hotplug_irq.h"
> +#include "intel_lpe_audio.h"
> #include "intel_parent.h"
> #include "intel_pipe_crc_regs.h"
> #include "intel_plane.h"
> @@ -529,8 +530,8 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display)
> }
> }
>
> -void i9xx_pipestat_irq_ack(struct intel_display *display,
> - u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> +static void i9xx_pipestat_irq_ack(struct intel_display *display,
> + u32 iir, u32 pipe_stats[I915_MAX_PIPES])
> {
> enum pipe pipe;
>
> @@ -1898,8 +1899,8 @@ static void vlv_page_table_error_irq_handler(struct intel_display *display, u32
> }
> }
>
> -void vlv_display_error_irq_ack(struct intel_display *display,
> - u32 *eir, u32 *dpinvgtt)
> +static void vlv_display_error_irq_ack(struct intel_display *display,
> + u32 *eir, u32 *dpinvgtt)
> {
> u32 emr;
>
> @@ -2010,6 +2011,16 @@ static void i965_display_irq_postinstall(struct intel_display *display)
> i915_enable_asle_pipestat(display);
> }
>
> +static void i9xx_display_irq_ack(struct intel_display *display,
> + struct intel_display_irq_state *state)
> +{
> + if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
> + state->hotplug_status = i9xx_hpd_irq_ack(display);
> +
> + /* Call regardless, as some status bits might not be signalled in IIR */
> + i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
> +}
> +
> static u32 vlv_error_mask(void)
> {
> /* TODO enable other errors too? */
> @@ -2065,6 +2076,32 @@ static void vlv_display_irq_postinstall(struct intel_display *display)
> spin_unlock_irq(&display->irq.lock);
> }
>
> +static u32 vlv_lpe_irq_mask(struct intel_display *display)
> +{
> + if (display->platform.cherryview)
> + return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT |
> + I915_LPE_PIPE_C_INTERRUPT;
> + else
> + return I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT;
> +}
> +
> +static void vlv_display_irq_ack(struct intel_display *display,
> + struct intel_display_irq_state *state)
> +{
> + if (state->iir & I915_DISPLAY_PORT_INTERRUPT)
> + state->hotplug_status = i9xx_hpd_irq_ack(display);
> +
> + if (state->iir & I915_MASTER_ERROR_INTERRUPT)
> + vlv_display_error_irq_ack(display, &state->eir, &state->dpinvgtt);
> +
> + /* Call regardless, as some status bits might not be signalled in IIR */
> + i9xx_pipestat_irq_ack(display, state->iir, state->pipe_stats);
> +
> + /* The handler acks the irq, so need to call the handler here */
> + if (state->iir & vlv_lpe_irq_mask(display))
> + intel_lpe_audio_irq_handler(display);
> +}
> +
> static void ibx_display_irq_reset(struct intel_display *display)
> {
> if (HAS_PCH_NOP(display))
> @@ -2443,6 +2480,7 @@ static void gen11_de_irq_postinstall(struct intel_display *display)
> struct intel_display_irq_funcs {
> void (*reset)(struct intel_display *display);
> void (*postinstall)(struct intel_display *display);
> + void (*ack)(struct intel_display *display, struct intel_display_irq_state *state);
> };
>
> static const struct intel_display_irq_funcs gen11_display_irq_funcs = {
> @@ -2458,6 +2496,7 @@ static const struct intel_display_irq_funcs gen8_display_irq_funcs = {
> static const struct intel_display_irq_funcs vlv_display_irq_funcs = {
> .reset = vlv_display_irq_reset,
> .postinstall = vlv_display_irq_postinstall,
> + .ack = vlv_display_irq_ack,
> };
>
> static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
> @@ -2468,11 +2507,13 @@ static const struct intel_display_irq_funcs ilk_display_irq_funcs = {
> static const struct intel_display_irq_funcs i965_display_irq_funcs = {
> .reset = i9xx_display_irq_reset,
> .postinstall = i965_display_irq_postinstall,
> + .ack = i9xx_display_irq_ack,
> };
>
> static const struct intel_display_irq_funcs i915_display_irq_funcs = {
> .reset = i9xx_display_irq_reset,
> .postinstall = i915_display_irq_postinstall,
> + .ack = i9xx_display_irq_ack,
> };
>
> void intel_display_irq_reset(struct intel_display *display)
> @@ -2491,6 +2532,15 @@ void intel_display_irq_postinstall(struct intel_display *display)
> display->irq.funcs->postinstall(display);
> }
>
> +void intel_display_irq_ack(struct intel_display *display,
> + struct intel_display_irq_state *state)
> +{
> + if (!HAS_DISPLAY(display) || !display->irq.funcs->ack)
> + return;
> +
> + display->irq.funcs->ack(display, state);
> +}
> +
> void intel_display_irq_init(struct intel_display *display)
> {
> spin_lock_init(&display->irq.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h
> index fd9873ce9755..3773a31e48f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
> @@ -58,8 +58,17 @@ void gen11_display_irq_handler(struct intel_display *display);
> u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl);
> void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir);
>
> +struct intel_display_irq_state {
> + u32 iir;
> + u32 eir;
> + u32 hotplug_status;
> + u32 dpinvgtt;
> + u32 pipe_stats[I915_MAX_PIPES];
> +};
> +
> void intel_display_irq_reset(struct intel_display *display);
> void intel_display_irq_postinstall(struct intel_display *display);
> +void intel_display_irq_ack(struct intel_display *display, struct intel_display_irq_state *state);
>
> u32 i9xx_display_irq_enable_mask(struct intel_display *display);
>
> @@ -67,13 +76,10 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe);
> void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
> void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);
>
> -void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
> -
> void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, const u32 pipe_stats[I915_MAX_PIPES]);
> void valleyview_pipestat_irq_handler(struct intel_display *display, const u32 pipe_stats[I915_MAX_PIPES]);
>
> -void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt);
> void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt);
>
> void intel_display_irq_init(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c21b289b8007..b28e89fdb6fd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -39,7 +39,6 @@
> #include "display/intel_display_irq.h"
> #include "display/intel_hotplug.h"
> #include "display/intel_hotplug_irq.h"
> -#include "display/intel_lpe_audio.h"
>
> #include "gt/intel_breadcrumbs.h"
> #include "gt/intel_gt.h"
> @@ -236,17 +235,15 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> do {
> - u32 iir, gt_iir, pm_iir;
> - u32 eir = 0, dpinvgtt = 0;
> - u32 pipe_stats[I915_MAX_PIPES] = {};
> - u32 hotplug_status = 0;
> + struct intel_display_irq_state state = {};
> + u32 gt_iir, pm_iir;
> u32 ier = 0;
>
> gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
> pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
> - iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
> + state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
>
> - if (gt_iir == 0 && pm_iir == 0 && iir == 0)
> + if (gt_iir == 0 && pm_iir == 0 && state.iir == 0)
> break;
>
> ret = IRQ_HANDLED;
> @@ -272,26 +269,14 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> if (pm_iir)
> intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
>
> - if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(display);
> -
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> - vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> -
> - /* Call regardless, as some status bits might not be
> - * signalled in IIR */
> - i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> - if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> - I915_LPE_PIPE_B_INTERRUPT))
> - intel_lpe_audio_irq_handler(display);
> + intel_display_irq_ack(display, &state);
>
> /*
> * VLV_IIR is single buffered, and reflects the level
> * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
> */
> - if (iir)
> - intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
> + if (state.iir)
> + intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
>
> intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
> intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> @@ -301,13 +286,13 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> if (pm_iir)
> gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
>
> - if (hotplug_status)
> - i9xx_hpd_irq_handler(display, hotplug_status);
> + if (state.hotplug_status)
> + i9xx_hpd_irq_handler(display, state.hotplug_status);
>
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> - vlv_display_error_irq_handler(display, eir, dpinvgtt);
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> + vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
>
> - valleyview_pipestat_irq_handler(display, pipe_stats);
> + valleyview_pipestat_irq_handler(display, state.pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -330,16 +315,14 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> do {
> - u32 master_ctl, iir;
> - u32 eir = 0, dpinvgtt = 0;
> - u32 pipe_stats[I915_MAX_PIPES] = {};
> - u32 hotplug_status = 0;
> + struct intel_display_irq_state state = {};
> + u32 master_ctl;
> u32 ier = 0;
>
> master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> - iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
> + state.iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
>
> - if (master_ctl == 0 && iir == 0)
> + if (master_ctl == 0 && state.iir == 0)
> break;
>
> ret = IRQ_HANDLED;
> @@ -362,38 +345,25 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>
> gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
>
> - if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(display);
> -
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> - vlv_display_error_irq_ack(display, &eir, &dpinvgtt);
> -
> - /* Call regardless, as some status bits might not be
> - * signalled in IIR */
> - i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> - if (iir & (I915_LPE_PIPE_A_INTERRUPT |
> - I915_LPE_PIPE_B_INTERRUPT |
> - I915_LPE_PIPE_C_INTERRUPT))
> - intel_lpe_audio_irq_handler(display);
> + intel_display_irq_ack(display, &state);
>
> /*
> * VLV_IIR is single buffered, and reflects the level
> * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
> */
> - if (iir)
> - intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
> + if (state.iir)
> + intel_uncore_write(&dev_priv->uncore, VLV_IIR, state.iir);
>
> intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
> intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>
> - if (hotplug_status)
> - i9xx_hpd_irq_handler(display, hotplug_status);
> + if (state.hotplug_status)
> + i9xx_hpd_irq_handler(display, state.hotplug_status);
>
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> - vlv_display_error_irq_handler(display, eir, dpinvgtt);
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> + vlv_display_error_irq_handler(display, state.eir, state.dpinvgtt);
>
> - valleyview_pipestat_irq_handler(display, pipe_stats);
> + valleyview_pipestat_irq_handler(display, state.pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -904,39 +874,32 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> do {
> - u32 pipe_stats[I915_MAX_PIPES] = {};
> + struct intel_display_irq_state state = {};
> u32 eir = 0, eir_stuck = 0;
> - u32 hotplug_status = 0;
> - u32 iir;
>
> - iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> - if (iir == 0)
> + state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> + if (state.iir == 0)
> break;
>
> ret = IRQ_HANDLED;
>
> - if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(display);
> + intel_display_irq_ack(display, &state);
>
> - /* Call regardless, as some status bits might not be
> - * signalled in IIR */
> - i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> -
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>
> - intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
> + intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
>
> - if (iir & I915_USER_INTERRUPT)
> - intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
> + if (state.iir & I915_USER_INTERRUPT)
> + intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], state.iir);
>
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>
> - if (hotplug_status)
> - i9xx_hpd_irq_handler(display, hotplug_status);
> + if (state.hotplug_status)
> + i9xx_hpd_irq_handler(display, state.hotplug_status);
>
> - i915_pipestat_irq_handler(display, iir, pipe_stats);
> + i915_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, ret);
> @@ -1013,44 +976,37 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
> do {
> - u32 pipe_stats[I915_MAX_PIPES] = {};
> + struct intel_display_irq_state state = {};
> u32 eir = 0, eir_stuck = 0;
> - u32 hotplug_status = 0;
> - u32 iir;
>
> - iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> - if (iir == 0)
> + state.iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
> + if (state.iir == 0)
> break;
>
> ret = IRQ_HANDLED;
>
> - if (iir & I915_DISPLAY_PORT_INTERRUPT)
> - hotplug_status = i9xx_hpd_irq_ack(display);
> -
> - /* Call regardless, as some status bits might not be
> - * signalled in IIR */
> - i9xx_pipestat_irq_ack(display, iir, pipe_stats);
> + intel_display_irq_ack(display, &state);
>
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>
> - intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
> + intel_uncore_write(&dev_priv->uncore, GEN2_IIR, state.iir);
>
> - if (iir & I915_USER_INTERRUPT)
> + if (state.iir & I915_USER_INTERRUPT)
> intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
> - iir);
> + state.iir);
>
> - if (iir & I915_BSD_USER_INTERRUPT)
> + if (state.iir & I915_BSD_USER_INTERRUPT)
> intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
> - iir >> 25);
> + state.iir >> 25);
>
> - if (iir & I915_MASTER_ERROR_INTERRUPT)
> + if (state.iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
>
> - if (hotplug_status)
> - i9xx_hpd_irq_handler(display, hotplug_status);
> + if (state.hotplug_status)
> + i9xx_hpd_irq_handler(display, state.hotplug_status);
>
> - i965_pipestat_irq_handler(display, iir, pipe_stats);
> + i965_pipestat_irq_handler(display, state.iir, state.pipe_stats);
> } while (0);
>
> pmu_irq_stats(dev_priv, IRQ_HANDLED);
> --
> 2.47.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-05-13 14:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 10:10 [PATCH v3 0/6] drm/i915: add display irq hooks Jani Nikula
2026-05-13 10:10 ` [PATCH v3 1/6] drm/i915/irq: deduplicate dg1_de_irq_postinstall() and gen11_de_irq_postinstall() Jani Nikula
2026-05-13 13:53 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 2/6] drm/i915/irq: constify pipe stats parameters Jani Nikula
2026-05-13 13:54 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 3/6] drm/i915/irq: add display irq funcs, start with intel_display_irq_reset() Jani Nikula
2026-05-13 13:56 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 4/6] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs Jani Nikula
2026-05-13 13:57 ` Ville Syrjälä
2026-05-13 10:10 ` [PATCH v3 5/6] drm/i915/irq: add intel_display_irq_ack() " Jani Nikula
2026-05-13 14:30 ` Ville Syrjälä [this message]
2026-05-13 16:15 ` Jani Nikula
2026-05-13 10:10 ` [PATCH v3 6/6] drm/i915/irq: add intel_display_irq_handler() " Jani Nikula
2026-05-13 12:38 ` Ville Syrjälä
2026-05-13 12:22 ` ✗ i915.CI.BAT: failure for drm/i915: add display irq hooks (rev2) Patchwork
2026-05-13 12:22 ` Patchwork
2026-05-13 12:22 ` Patchwork
2026-05-13 12:22 ` Patchwork
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