[PATCH 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring

[PATCH 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix up some bugs around the cdclk pcode notificatiosn on DG2,
follow up with some unification/cleanups, and finally convert
the pcode stuff (except on dg2, due to it doing weird things)
into vfuncs (goal being to make the code less messy).

Ville Syrjälä (14):
  drm/i915/cdclk: Don't bail if pcode post nofify fails
  drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2
  drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly
  drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of
    CDCLK
  drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2
  drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()
  drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff
  drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk()
  drm/i915/cdclk: Unify pcode related debugs
  drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Extract skl_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Introduce CDCLK .{pre,post}_notify() vfuncs
  drm/i915/cdclk: Hoist intel_cdclk_{pre,post}_notify() calls upwards

 drivers/gpu/drm/i915/display/intel_cdclk.c | 301 ++++++++++++---------
 1 file changed, 171 insertions(+), 130 deletions(-)

-- 
2.53.0

[PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We already changed the actual cdclk frequency by the time we do
the pcode post notify. So skipping the subsequent readout is plain
wrong.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 189ae2d3cfc9..9ca56bab281f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2301,12 +2301,10 @@ static void bxt_set_cdclk(struct intel_display *display,
 						       HSW_PCODE_DE_WRITE_FREQ_REQ,
 						       cdclk_config->voltage_level, 2);
 	}
-	if (ret) {
+	if (ret)
 		drm_err(display->drm,
 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
 			ret, cdclk);
-		return;
-	}
 
 	intel_update_cdclk(display);
 
-- 
2.53.0

[PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are currently trying to pass the CDCLK in kHz to the pcode
on DG2, while the pcode expects a value in MHz units. Adjust
the units appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9ca56bab281f..9718062d8d6c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
 	 * which basically means we choose the maximum of old and new CDCLK, if we know both
 	 */
-	if (change_cdclk)
+	if (change_cdclk) {
 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
+		cdclk = DIV_ROUND_UP(cdclk, 1000);
+	}
 
 	/*
 	 * According to "Sequence For Pipe Count Change",
@@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	 * According to "Sequence After Frequency Change",
 	 * set bits 25:16 to current CDCLK
 	 */
-	if (update_cdclk)
+	if (update_cdclk) {
 		cdclk = new_cdclk_state->actual.cdclk;
+		cdclk = DIV_ROUND_UP(cdclk, 1000);
+	}
 
 	/*
 	 * According to "Sequence For Pipe Count Change",
-- 
2.53.0

[PATCH 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The pcode post notufy needs to happen after the CDCLK has been
changed, not before. Also move the pre_notify call a bit for the
sake of symmetry.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9718062d8d6c..d60b3369b4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2796,9 +2796,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 				 &new_cdclk_state->actual))
 		return;
 
-	if (display->platform.dg2)
-		intel_cdclk_pcode_pre_notify(state);
-
 	if (new_cdclk_state->disable_pipes) {
 		cdclk_config = new_cdclk_state->actual;
 		pipe = INVALID_PIPE;
@@ -2823,6 +2820,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 
 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
 
+	if (display->platform.dg2)
+		intel_cdclk_pcode_pre_notify(state);
+
 	intel_set_cdclk(display, &cdclk_config, pipe,
 			"Pre changing CDCLK to");
 }
@@ -2851,9 +2851,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 				 &new_cdclk_state->actual))
 		return;
 
-	if (display->platform.dg2)
-		intel_cdclk_pcode_post_notify(state);
-
 	if (!new_cdclk_state->disable_pipes &&
 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
 		pipe = new_cdclk_state->pipe;
@@ -2864,6 +2861,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 
 	intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
 			"Post changing CDCLK to");
+
+	if (display->platform.dg2)
+		intel_cdclk_pcode_post_notify(state);
 }
 
 /* pixels per CDCLK */
-- 
2.53.0

[PATCH 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're currently skipping the pcode notifies on DG2 if the CDCLK isn't
changing while the power well counts would still need updating.
Do the pcode notifications also for pure pipe power well changes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d60b3369b4d2..7259048361a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2793,7 +2793,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 		return;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
-				 &new_cdclk_state->actual))
+				 &new_cdclk_state->actual) &&
+	    dg2_power_well_count(display, old_cdclk_state) ==
+	    dg2_power_well_count(display, new_cdclk_state))
 		return;
 
 	if (new_cdclk_state->disable_pipes) {
@@ -2848,7 +2850,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 		return;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
-				 &new_cdclk_state->actual))
+				 &new_cdclk_state->actual) &&
+	    dg2_power_well_count(display, old_cdclk_state) ==
+	    dg2_power_well_count(display, new_cdclk_state))
 		return;
 
 	if (!new_cdclk_state->disable_pipes &&
-- 
2.53.0

[PATCH 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
we are currently forcing the voltage level to 3 all the time on
DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
this.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7259048361a7..ecb6be3383ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2598,7 +2598,6 @@ static void intel_pcode_notify(struct intel_display *display,
 		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
 
 	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 SKL_CDCLK_PREPARE_FOR_CHANGE |
 					 update_mask,
 					 SKL_CDCLK_READY_FOR_CHANGE,
 					 SKL_CDCLK_READY_FOR_CHANGE, 3);
-- 
2.53.0

[PATCH 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Overwrite cdclk.hw.voltage_level from intel_update_cdclk() at the
end on bxt_set_cdclk() also on bxt/glk. While this isn't actually
necessary due to bxt/glk not having any extra DDI based voltage
level requirements, it does avoid one less silly 'if' in the code.

On icl+ the value derived by bxt_get_cdclk() may not be correct
if the voltage level was bumped up due to DDI requirements, thus
overwriting the assumed value is crucial there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ecb6be3383ca..bbf3603f889b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2308,12 +2308,11 @@ static void bxt_set_cdclk(struct intel_display *display,
 
 	intel_update_cdclk(display);
 
-	if (DISPLAY_VER(display) >= 11)
-		/*
-		 * Can't read out the voltage level :(
-		 * Let's just assume everything is as expected.
-		 */
-		display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+	/*
+	 * Can't read out the voltage level :(
+	 * Let's just assume everything is as expected.
+	 */
+	display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
 }
 
 static void bxt_sanitize_cdclk(struct intel_display *display)
-- 
2.53.0

[PATCH 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_pcode_*notify() are all DG2 specific code. Rename them
to have a dg2_ namespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 31 ++++++++++------------
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bbf3603f889b..659c1c0e3432 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2575,19 +2575,16 @@ void intel_cdclk_dump_config(struct intel_display *display,
 		    cdclk_config->voltage_level);
 }
 
-static void intel_pcode_notify(struct intel_display *display,
-			       u8 voltage_level,
-			       u8 active_pipe_count,
-			       u16 cdclk,
-			       bool cdclk_update_valid,
-			       bool pipe_count_update_valid)
+static void dg2_cdclk_pcode_notify(struct intel_display *display,
+				   u8 voltage_level,
+				   u8 active_pipe_count,
+				   u16 cdclk,
+				   bool cdclk_update_valid,
+				   bool pipe_count_update_valid)
 {
 	int ret;
 	u32 update_mask = 0;
 
-	if (!display->platform.dg2)
-		return;
-
 	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
 
 	if (cdclk_update_valid)
@@ -2672,7 +2669,7 @@ static bool dg2_power_well_count(struct intel_display *display,
 	return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
 }
 
-static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
+static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 	const struct intel_cdclk_state *old_cdclk_state =
@@ -2715,11 +2712,11 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			   change_cdclk, update_pipe_count);
+	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+			       change_cdclk, update_pipe_count);
 }
 
-static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
+static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 	const struct intel_cdclk_state *new_cdclk_state =
@@ -2754,8 +2751,8 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			   update_cdclk, update_pipe_count);
+	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+			       update_cdclk, update_pipe_count);
 }
 
 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
@@ -2821,7 +2818,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
 
 	if (display->platform.dg2)
-		intel_cdclk_pcode_pre_notify(state);
+		dg2_cdclk_pcode_pre_notify(state);
 
 	intel_set_cdclk(display, &cdclk_config, pipe,
 			"Pre changing CDCLK to");
@@ -2865,7 +2862,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 			"Post changing CDCLK to");
 
 	if (display->platform.dg2)
-		intel_cdclk_pcode_post_notify(state);
+		dg2_cdclk_pcode_post_notify(state);
 }
 
 /* pixels per CDCLK */
-- 
2.53.0

[PATCH 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The control flow between the pcode pre and post notifications ibn
bxt_set_cdclk() is written in two different ways, even though
they end up doing the same thing. Unify the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 659c1c0e3432..09981a112db4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2237,7 +2237,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 {
 	struct intel_cdclk_config mid_cdclk_config;
 	int cdclk = cdclk_config->cdclk;
-	int ret = 0;
+	int ret;
 
 	/*
 	 * Inform power controller of upcoming frequency change.
@@ -2246,7 +2246,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	 * this step.
 	 */
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		; /* NOOP */
+		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
 		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
 						 SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -2282,15 +2282,12 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	if (DISPLAY_VER(display) >= 14)
-		/*
-		 * NOOP - No Pcode communication needed for
-		 * Display versions 14 and beyond
-		 */;
-	else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
+	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
+		ret = 0; /* NOOP */
+	else if (DISPLAY_VER(display) >= 11)
 		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
 					       cdclk_config->voltage_level);
-	if (DISPLAY_VER(display) < 11) {
+	else
 		/*
 		 * The timeout isn't specified, the 2ms used here is based on
 		 * experiment.
@@ -2300,7 +2297,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 		ret = intel_parent_pcode_write_timeout(display,
 						       HSW_PCODE_DE_WRITE_FREQ_REQ,
 						       cdclk_config->voltage_level, 2);
-	}
 	if (ret)
 		drm_err(display->drm,
 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
-- 
2.53.0

[PATCH 09/14] drm/i915/cdclk: Unify pcode related debugs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The debug spew for the cdclk pcode per/post notify is very
inconsistent between different platforms. Unify it all to
the same form.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 65 ++++++++++++----------
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 09981a112db4..542724256d0f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -891,7 +891,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 	if (ret) {
 		drm_err(display->drm,
-			"failed to inform pcode about cdclk change\n");
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -918,8 +918,11 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				 cdclk_config->voltage_level);
+	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+				       cdclk_config->voltage_level);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1181,7 +1184,7 @@ static void skl_set_cdclk(struct intel_display *display,
 					 SKL_CDCLK_READY_FOR_CHANGE, 3);
 	if (ret) {
 		drm_err(display->drm,
-			"Failed to inform PCU about cdclk change (%d)\n", ret);
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -1221,8 +1224,11 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_posting_read(display, CDCLK_CTL);
 
 	/* inform PCU of the change */
-	intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-				 cdclk_config->voltage_level);
+	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+				       cdclk_config->voltage_level);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_update_cdclk(display);
 }
@@ -2263,8 +2269,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 
 	if (ret) {
 		drm_err(display->drm,
-			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
-			ret, cdclk);
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -2299,8 +2304,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 						       cdclk_config->voltage_level, 2);
 	if (ret)
 		drm_err(display->drm,
-			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
-			ret, cdclk);
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_update_cdclk(display);
 
@@ -2571,14 +2575,13 @@ void intel_cdclk_dump_config(struct intel_display *display,
 		    cdclk_config->voltage_level);
 }
 
-static void dg2_cdclk_pcode_notify(struct intel_display *display,
-				   u8 voltage_level,
-				   u8 active_pipe_count,
-				   u16 cdclk,
-				   bool cdclk_update_valid,
-				   bool pipe_count_update_valid)
+static int dg2_cdclk_pcode_notify(struct intel_display *display,
+				  u8 voltage_level,
+				  u8 active_pipe_count,
+				  u16 cdclk,
+				  bool cdclk_update_valid,
+				  bool pipe_count_update_valid)
 {
-	int ret;
 	u32 update_mask = 0;
 
 	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
@@ -2589,14 +2592,10 @@ static void dg2_cdclk_pcode_notify(struct intel_display *display,
 	if (pipe_count_update_valid)
 		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
 
-	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 update_mask,
-					 SKL_CDCLK_READY_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE, 3);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCU about display config (err %d)\n",
-			ret);
+	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+					  update_mask,
+					  SKL_CDCLK_READY_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE, 3);
 }
 
 static void intel_set_cdclk(struct intel_display *display,
@@ -2674,6 +2673,7 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 		intel_atomic_get_new_cdclk_state(state);
 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
 	bool change_cdclk, update_pipe_count;
+	int ret;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual) &&
@@ -2708,8 +2708,11 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			       change_cdclk, update_pipe_count);
+	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+				     change_cdclk, update_pipe_count);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 }
 
 static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
@@ -2721,6 +2724,7 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
 	bool update_cdclk, update_pipe_count;
+	int ret;
 
 	/* According to "Sequence After Frequency Change", set voltage to used level */
 	voltage_level = new_cdclk_state->actual.voltage_level;
@@ -2747,8 +2751,11 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			       update_cdclk, update_pipe_count);
+	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+				     update_cdclk, update_pipe_count);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 }
 
 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
-- 
2.53.0

[PATCH 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the BSW pcode notify stuff to a few small helpers. The
plan is to unify these between all the platforms and turn them
into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 542724256d0f..041b1fc8b3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -872,6 +872,19 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
 	}
 }
 
+static int bdw_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ,
+					0x0);
+}
+
+static int bdw_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+					cdclk_config->voltage_level);
+}
+
 static void bdw_set_cdclk(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -888,7 +901,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+	ret = bdw_cdclk_pcode_pre_notify(display);
 	if (ret) {
 		drm_err(display->drm,
 			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
@@ -918,8 +931,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				       cdclk_config->voltage_level);
+	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
-- 
2.53.0

[PATCH 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the SKL/ICL+ pcode notify stuff to a few small helpers.
The plan is to unify these between all the platforms and turn
them into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++---------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 041b1fc8b3ee..bb47fc4c86ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1170,6 +1170,21 @@ static u32 skl_cdclk_freq_sel(struct intel_display *display,
 	}
 }
 
+static int skl_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+					  SKL_CDCLK_PREPARE_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE, 3);
+}
+
+static int skl_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	return intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+					cdclk_config->voltage_level);
+}
+
 static void skl_set_cdclk(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1190,10 +1205,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 SKL_CDCLK_PREPARE_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE, 3);
+	ret = skl_cdclk_pcode_pre_notify(display);
 	if (ret) {
 		drm_err(display->drm,
 			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
@@ -1235,9 +1247,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	/* inform PCU of the change */
-	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-				       cdclk_config->voltage_level);
+	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
@@ -2266,10 +2276,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
 		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
-		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-						 SKL_CDCLK_PREPARE_FOR_CHANGE,
-						 SKL_CDCLK_READY_FOR_CHANGE,
-						 SKL_CDCLK_READY_FOR_CHANGE, 3);
+		ret = skl_cdclk_pcode_pre_notify(display);
 	else
 		/*
 		 * BSpec requires us to wait up to 150usec, but that leads to
@@ -2302,8 +2309,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
 		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
-		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-					       cdclk_config->voltage_level);
+		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	else
 		/*
 		 * The timeout isn't specified, the 2ms used here is based on
-- 
2.53.0

[PATCH 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the BXT/GLK pcode notify stuff to a few small helpers.
The plan is to unify these between all the platforms and turn
them into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 42 +++++++++++++---------
 1 file changed, 26 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bb47fc4c86ee..749e366e60ab 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2226,6 +2226,29 @@ static u32 bxt_cdclk_ctl(struct intel_display *display,
 	return val;
 }
 
+static int bxt_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	/*
+	 * BSpec requires us to wait up to 150usec, but that leads to
+	 * timeouts; the 2ms used here is based on experiment.
+	 */
+	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+						0x80000000, 2);
+}
+
+static int bxt_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	/*
+	 * The timeout isn't specified, the 2ms used here is based on
+	 * experiment.
+	 * FIXME: Waiting for the request completion could be delayed
+	 * until the next PCODE request based on BSpec.
+	 */
+	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+						cdclk_config->voltage_level, 2);
+}
+
 static void _bxt_set_cdclk(struct intel_display *display,
 			   const struct intel_cdclk_config *cdclk_config,
 			   enum pipe pipe)
@@ -2278,13 +2301,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	else if (DISPLAY_VER(display) >= 11)
 		ret = skl_cdclk_pcode_pre_notify(display);
 	else
-		/*
-		 * BSpec requires us to wait up to 150usec, but that leads to
-		 * timeouts; the 2ms used here is based on experiment.
-		 */
-		ret = intel_parent_pcode_write_timeout(display,
-						       HSW_PCODE_DE_WRITE_FREQ_REQ,
-						       0x80000000, 2);
+		ret = bxt_cdclk_pcode_pre_notify(display);
 
 	if (ret) {
 		drm_err(display->drm,
@@ -2311,15 +2328,8 @@ static void bxt_set_cdclk(struct intel_display *display,
 	else if (DISPLAY_VER(display) >= 11)
 		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	else
-		/*
-		 * The timeout isn't specified, the 2ms used here is based on
-		 * experiment.
-		 * FIXME: Waiting for the request completion could be delayed
-		 * until the next PCODE request based on BSpec.
-		 */
-		ret = intel_parent_pcode_write_timeout(display,
-						       HSW_PCODE_DE_WRITE_FREQ_REQ,
-						       cdclk_config->voltage_level, 2);
+		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
+
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
-- 
2.53.0

[PATCH 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Turn the cdclk pcode pre/post notify functiosn into vfuncs.
Mainly to get rid of the hideous if-ladders in bxt_set_cdclk().

DG2 is currently doing its own thing with its pcode notify funcs so
can't be converted yet. And MTL+ go via the pmdemand stuff so this
is all supposedly handled elsewhere.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 122 ++++++++++++---------
 1 file changed, 73 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 749e366e60ab..4154b4888eff 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -163,6 +163,9 @@ struct intel_cdclk_funcs {
 	void (*set_cdclk)(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe);
+	int (*pre_notify)(struct intel_display *display);
+	int (*post_notify)(struct intel_display *display,
+			   const struct intel_cdclk_config *cdclk_config);
 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
 };
@@ -173,6 +176,35 @@ void intel_cdclk_get_cdclk(struct intel_display *display,
 	display->cdclk.funcs->get_cdclk(display, cdclk_config);
 }
 
+static int intel_cdclk_pre_notify(struct intel_display *display)
+{
+	int ret;
+
+	if (!display->cdclk.funcs->pre_notify)
+		return 0;
+
+	ret = display->cdclk.funcs->pre_notify(display);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform system about start of CDCLK change (%d)\n", ret);
+
+	return ret;
+}
+
+static void intel_cdclk_post_notify(struct intel_display *display,
+				    const struct intel_cdclk_config *cdclk_config)
+{
+	int ret;
+
+	if (!display->cdclk.funcs->post_notify)
+		return;
+
+	ret = display->cdclk.funcs->post_notify(display, cdclk_config);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform system about end of CDCLK change (%d)\n", ret);
+}
+
 static void intel_cdclk_set_cdclk(struct intel_display *display,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
@@ -901,12 +933,9 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = bdw_cdclk_pcode_pre_notify(display);
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	intel_de_rmw(display, LCPLL_CTL,
 		     0, LCPLL_CD_SOURCE_FCLK);
@@ -931,10 +960,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1205,12 +1231,9 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = skl_cdclk_pcode_pre_notify(display);
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
 
@@ -1247,10 +1270,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_update_cdclk(display);
 }
@@ -2290,24 +2310,9 @@ static void bxt_set_cdclk(struct intel_display *display,
 	int cdclk = cdclk_config->cdclk;
 	int ret;
 
-	/*
-	 * Inform power controller of upcoming frequency change.
-	 * Display versions 14 and beyond do not follow the PUnit
-	 * mailbox communication, skip
-	 * this step.
-	 */
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		ret = 0; /* NOOP */
-	else if (DISPLAY_VER(display) >= 11)
-		ret = skl_cdclk_pcode_pre_notify(display);
-	else
-		ret = bxt_cdclk_pcode_pre_notify(display);
-
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
@@ -2323,16 +2328,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		ret = 0; /* NOOP */
-	else if (DISPLAY_VER(display) >= 11)
-		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
-	else
-		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
-
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_update_cdclk(display);
 
@@ -3929,9 +3925,25 @@ static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
 	.calc_voltage_level = xe3lpd_calc_voltage_level,
 };
 
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = rplu_calc_voltage_level,
+};
+
+static const struct intel_cdclk_funcs dg2_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = tgl_calc_voltage_level,
+};
+
 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = rplu_calc_voltage_level,
 };
@@ -3939,6 +3951,8 @@ static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = tgl_calc_voltage_level,
 };
@@ -3946,6 +3960,8 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = ehl_calc_voltage_level,
 };
@@ -3953,6 +3969,8 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = icl_calc_voltage_level,
 };
@@ -3960,6 +3978,8 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = bxt_cdclk_pcode_pre_notify,
+	.post_notify = bxt_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = bxt_calc_voltage_level,
 };
@@ -3967,12 +3987,16 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
 	.get_cdclk = skl_get_cdclk,
 	.set_cdclk = skl_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
 	.get_cdclk = bdw_get_cdclk,
 	.set_cdclk = bdw_set_cdclk,
+	.pre_notify = bdw_cdclk_pcode_pre_notify,
+	.post_notify = bdw_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
 };
 
@@ -4078,16 +4102,16 @@ void intel_init_cdclk_hooks(struct intel_display *display)
 		display->cdclk.funcs = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 20) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = xe2lpd_cdclk_table;
 	} else if (DISPLAY_VERx100(display) >= 1401) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = xe2hpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 14) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = mtl_cdclk_table;
 	} else if (display->platform.dg2) {
-		display->cdclk.funcs = &tgl_cdclk_funcs;
+		display->cdclk.funcs = &dg2_cdclk_funcs;
 		display->cdclk.table = dg2_cdclk_table;
 	} else if (display->platform.alderlake_p) {
 		/* Wa_22011320316:adl-p[a0] */
-- 
2.53.0

[PATCH 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that intel_cdclk_{pre,post}_notify() are implemented via vfuncs
there is no need to keep them inside the .set_cdclk() hooks. Move
the calls one level up to intel_cdclk_set_cdclk().

We do need to adjust {skl,bxt}_cdclk_(un)init_hw() to call the wrapper
rather than the low level implementation directly, or else they would
not do the pcode notification anymore.

The two slight functions changes here are:
- bdw_set_cdclk() might theoretically bail out after doing the
  pre notification, but that codepath would only come into play
  if the hardware is seriously misprogrammed, so should never happen
- cdclk hw readout is still done from .set_cdclk(), so that now
  happens before the post notify vs. previously the readout happened
  before it. This should not matter as the readout is not affected
  by the post notify (since we can't actually read out anything from
  pcode).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 33 ++++++----------------
 1 file changed, 9 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4154b4888eff..617ad154505c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -209,7 +209,12 @@ static void intel_cdclk_set_cdclk(struct intel_display *display,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
 {
+	if (intel_cdclk_pre_notify(display))
+		return;
+
 	display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
+
+	intel_cdclk_post_notify(display, cdclk_config);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
@@ -933,10 +938,6 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
-
 	intel_de_rmw(display, LCPLL_CTL,
 		     0, LCPLL_CD_SOURCE_FCLK);
 
@@ -960,8 +961,6 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 
@@ -1218,7 +1217,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	int cdclk = cdclk_config->cdclk;
 	int vco = cdclk_config->vco;
 	u32 freq_select, cdclk_ctl;
-	int ret;
 
 	/*
 	 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
@@ -1231,10 +1229,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
-
 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
 
 	if (display->cdclk.hw.vco != 0 &&
@@ -1270,8 +1264,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_update_cdclk(display);
 }
 
@@ -1343,7 +1335,7 @@ static void skl_cdclk_init_hw(struct intel_display *display)
 	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 static void skl_cdclk_uninit_hw(struct intel_display *display)
@@ -1354,7 +1346,7 @@ static void skl_cdclk_uninit_hw(struct intel_display *display)
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 struct intel_cdclk_vals {
@@ -2308,11 +2300,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 {
 	struct intel_cdclk_config mid_cdclk_config;
 	int cdclk = cdclk_config->cdclk;
-	int ret;
-
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
 
 	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
@@ -2328,8 +2315,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_update_cdclk(display);
 
 	/*
@@ -2413,7 +2398,7 @@ static void bxt_cdclk_init_hw(struct intel_display *display)
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
 
-	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 static void bxt_cdclk_uninit_hw(struct intel_display *display)
@@ -2425,7 +2410,7 @@ static void bxt_cdclk_uninit_hw(struct intel_display *display)
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
 
-	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 /**
-- 
2.53.0

Re: [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We are currently trying to pass the CDCLK in kHz to the pcode
> on DG2, while the pcode expects a value in MHz units. Adjust
> the units appropriately.

How is it working? :o

Fixes: ?

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9ca56bab281f..9718062d8d6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
>  	 * which basically means we choose the maximum of old and new CDCLK, if we know both
>  	 */
> -	if (change_cdclk)
> +	if (change_cdclk) {
>  		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
> +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> +	}

I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to
emphasize it's not kHz.

>  	/*
>  	 * According to "Sequence For Pipe Count Change",
> @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	 * According to "Sequence After Frequency Change",
>  	 * set bits 25:16 to current CDCLK
>  	 */
> -	if (update_cdclk)
> +	if (update_cdclk) {
>  		cdclk = new_cdclk_state->actual.cdclk;
> +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> +	}

Ditto.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  
>  	/*
>  	 * According to "Sequence For Pipe Count Change",

-- 
Jani Nikula, Intel

Re: [PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already changed the actual cdclk frequency by the time we do
> the pcode post notify. So skipping the subsequent readout is plain
> wrong.

Fixes: ?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 189ae2d3cfc9..9ca56bab281f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2301,12 +2301,10 @@ static void bxt_set_cdclk(struct intel_display *display,
>  						       HSW_PCODE_DE_WRITE_FREQ_REQ,
>  						       cdclk_config->voltage_level, 2);
>  	}
> -	if (ret) {
> +	if (ret)
>  		drm_err(display->drm,
>  			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
>  			ret, cdclk);
> -		return;
> -	}
>  
>  	intel_update_cdclk(display);

-- 
Jani Nikula, Intel

Re: [PATCH 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_pcode_*notify() are all DG2 specific code. Rename them
> to have a dg2_ namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 31 ++++++++++------------
>  1 file changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index bbf3603f889b..659c1c0e3432 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2575,19 +2575,16 @@ void intel_cdclk_dump_config(struct intel_display *display,
>  		    cdclk_config->voltage_level);
>  }
>  
> -static void intel_pcode_notify(struct intel_display *display,
> -			       u8 voltage_level,
> -			       u8 active_pipe_count,
> -			       u16 cdclk,
> -			       bool cdclk_update_valid,
> -			       bool pipe_count_update_valid)
> +static void dg2_cdclk_pcode_notify(struct intel_display *display,
> +				   u8 voltage_level,
> +				   u8 active_pipe_count,
> +				   u16 cdclk,
> +				   bool cdclk_update_valid,
> +				   bool pipe_count_update_valid)
>  {
>  	int ret;
>  	u32 update_mask = 0;
>  
> -	if (!display->platform.dg2)
> -		return;
> -
>  	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
>  
>  	if (cdclk_update_valid)
> @@ -2672,7 +2669,7 @@ static bool dg2_power_well_count(struct intel_display *display,
>  	return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
>  }
>  
> -static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> +static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	const struct intel_cdclk_state *old_cdclk_state =
> @@ -2715,11 +2712,11 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			   change_cdclk, update_pipe_count);
> +	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +			       change_cdclk, update_pipe_count);
>  }
>  
> -static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> +static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
> @@ -2754,8 +2751,8 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			   update_cdclk, update_pipe_count);
> +	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +			       update_cdclk, update_pipe_count);
>  }
>  
>  bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
> @@ -2821,7 +2818,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>  	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>  
>  	if (display->platform.dg2)
> -		intel_cdclk_pcode_pre_notify(state);
> +		dg2_cdclk_pcode_pre_notify(state);
>  
>  	intel_set_cdclk(display, &cdclk_config, pipe,
>  			"Pre changing CDCLK to");
> @@ -2865,7 +2862,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  			"Post changing CDCLK to");
>  
>  	if (display->platform.dg2)
> -		intel_cdclk_pcode_post_notify(state);
> +		dg2_cdclk_pcode_post_notify(state);
>  }
>  
>  /* pixels per CDCLK */

-- 
Jani Nikula, Intel

Re: [PATCH 09/14] drm/i915/cdclk: Unify pcode related debugs

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The debug spew for the cdclk pcode per/post notify is very
> inconsistent between different platforms. Unify it all to
> the same form.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 65 ++++++++++++----------
>  1 file changed, 36 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 09981a112db4..542724256d0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -891,7 +891,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
>  	if (ret) {
>  		drm_err(display->drm,
> -			"failed to inform pcode about cdclk change\n");
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -918,8 +918,11 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> -				 cdclk_config->voltage_level);
> +	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +				       cdclk_config->voltage_level);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_de_write(display, CDCLK_FREQ,
>  		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1181,7 +1184,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  					 SKL_CDCLK_READY_FOR_CHANGE, 3);
>  	if (ret) {
>  		drm_err(display->drm,
> -			"Failed to inform PCU about cdclk change (%d)\n", ret);
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -1221,8 +1224,11 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
>  	/* inform PCU of the change */
> -	intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -				 cdclk_config->voltage_level);
> +	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> +				       cdclk_config->voltage_level);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_update_cdclk(display);
>  }
> @@ -2263,8 +2269,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  
>  	if (ret) {
>  		drm_err(display->drm,
> -			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> -			ret, cdclk);
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -2299,8 +2304,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  						       cdclk_config->voltage_level, 2);
>  	if (ret)
>  		drm_err(display->drm,
> -			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
> -			ret, cdclk);
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_update_cdclk(display);
>  
> @@ -2571,14 +2575,13 @@ void intel_cdclk_dump_config(struct intel_display *display,
>  		    cdclk_config->voltage_level);
>  }
>  
> -static void dg2_cdclk_pcode_notify(struct intel_display *display,
> -				   u8 voltage_level,
> -				   u8 active_pipe_count,
> -				   u16 cdclk,
> -				   bool cdclk_update_valid,
> -				   bool pipe_count_update_valid)
> +static int dg2_cdclk_pcode_notify(struct intel_display *display,
> +				  u8 voltage_level,
> +				  u8 active_pipe_count,
> +				  u16 cdclk,
> +				  bool cdclk_update_valid,
> +				  bool pipe_count_update_valid)
>  {
> -	int ret;
>  	u32 update_mask = 0;
>  
>  	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
> @@ -2589,14 +2592,10 @@ static void dg2_cdclk_pcode_notify(struct intel_display *display,
>  	if (pipe_count_update_valid)
>  		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
>  
> -	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 update_mask,
> -					 SKL_CDCLK_READY_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE, 3);
> -	if (ret)
> -		drm_err(display->drm,
> -			"Failed to inform PCU about display config (err %d)\n",
> -			ret);
> +	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> +					  update_mask,
> +					  SKL_CDCLK_READY_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE, 3);
>  }
>  
>  static void intel_set_cdclk(struct intel_display *display,
> @@ -2674,6 +2673,7 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  		intel_atomic_get_new_cdclk_state(state);
>  	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
>  	bool change_cdclk, update_pipe_count;
> +	int ret;
>  
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual) &&
> @@ -2708,8 +2708,11 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			       change_cdclk, update_pipe_count);
> +	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +				     change_cdclk, update_pipe_count);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  }
>  
>  static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> @@ -2721,6 +2724,7 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
>  	bool update_cdclk, update_pipe_count;
> +	int ret;
>  
>  	/* According to "Sequence After Frequency Change", set voltage to used level */
>  	voltage_level = new_cdclk_state->actual.voltage_level;
> @@ -2747,8 +2751,11 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			       update_cdclk, update_pipe_count);
> +	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +				     update_cdclk, update_pipe_count);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  }
>  
>  bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)

-- 
Jani Nikula, Intel

Re: [PATCH 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the BSW pcode notify stuff to a few small helpers. The
> plan is to unify these between all the platforms and turn them
> into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 542724256d0f..041b1fc8b3ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -872,6 +872,19 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
>  	}
>  }
>  
> +static int bdw_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ,
> +					0x0);
> +}
> +
> +static int bdw_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +					cdclk_config->voltage_level);
> +}
> +
>  static void bdw_set_cdclk(struct intel_display *display,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -888,7 +901,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  		     "trying to change cdclk frequency with cdclk not enabled\n"))
>  		return;
>  
> -	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> +	ret = bdw_cdclk_pcode_pre_notify(display);
>  	if (ret) {
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> @@ -918,8 +931,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> -				       cdclk_config->voltage_level);
> +	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);

-- 
Jani Nikula, Intel

Re: [PATCH 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the SKL/ICL+ pcode notify stuff to a few small helpers.
> The plan is to unify these between all the platforms and turn
> them into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++---------
>  1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 041b1fc8b3ee..bb47fc4c86ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1170,6 +1170,21 @@ static u32 skl_cdclk_freq_sel(struct intel_display *display,
>  	}
>  }
>  
> +static int skl_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> +					  SKL_CDCLK_PREPARE_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE, 3);
> +}
> +
> +static int skl_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	return intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> +					cdclk_config->voltage_level);
> +}
> +
>  static void skl_set_cdclk(struct intel_display *display,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1190,10 +1205,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  	drm_WARN_ON_ONCE(display->drm,
>  			 display->platform.skylake && vco == 8640000);
>  
> -	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 SKL_CDCLK_PREPARE_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE, 3);
> +	ret = skl_cdclk_pcode_pre_notify(display);
>  	if (ret) {
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> @@ -1235,9 +1247,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
> -	/* inform PCU of the change */
> -	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -				       cdclk_config->voltage_level);
> +	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
> @@ -2266,10 +2276,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>  		ret = 0; /* NOOP */
>  	else if (DISPLAY_VER(display) >= 11)
> -		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -						 SKL_CDCLK_PREPARE_FOR_CHANGE,
> -						 SKL_CDCLK_READY_FOR_CHANGE,
> -						 SKL_CDCLK_READY_FOR_CHANGE, 3);
> +		ret = skl_cdclk_pcode_pre_notify(display);
>  	else
>  		/*
>  		 * BSpec requires us to wait up to 150usec, but that leads to
> @@ -2302,8 +2309,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>  		ret = 0; /* NOOP */
>  	else if (DISPLAY_VER(display) >= 11)
> -		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -					       cdclk_config->voltage_level);
> +		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	else
>  		/*
>  		 * The timeout isn't specified, the 2ms used here is based on

-- 
Jani Nikula, Intel

Re: [PATCH 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the BXT/GLK pcode notify stuff to a few small helpers.
> The plan is to unify these between all the platforms and turn
> them into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 42 +++++++++++++---------
>  1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index bb47fc4c86ee..749e366e60ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2226,6 +2226,29 @@ static u32 bxt_cdclk_ctl(struct intel_display *display,
>  	return val;
>  }
>  
> +static int bxt_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	/*
> +	 * BSpec requires us to wait up to 150usec, but that leads to
> +	 * timeouts; the 2ms used here is based on experiment.
> +	 */
> +	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +						0x80000000, 2);
> +}
> +
> +static int bxt_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	/*
> +	 * The timeout isn't specified, the 2ms used here is based on
> +	 * experiment.
> +	 * FIXME: Waiting for the request completion could be delayed
> +	 * until the next PCODE request based on BSpec.
> +	 */
> +	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +						cdclk_config->voltage_level, 2);
> +}
> +
>  static void _bxt_set_cdclk(struct intel_display *display,
>  			   const struct intel_cdclk_config *cdclk_config,
>  			   enum pipe pipe)
> @@ -2278,13 +2301,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	else if (DISPLAY_VER(display) >= 11)
>  		ret = skl_cdclk_pcode_pre_notify(display);
>  	else
> -		/*
> -		 * BSpec requires us to wait up to 150usec, but that leads to
> -		 * timeouts; the 2ms used here is based on experiment.
> -		 */
> -		ret = intel_parent_pcode_write_timeout(display,
> -						       HSW_PCODE_DE_WRITE_FREQ_REQ,
> -						       0x80000000, 2);
> +		ret = bxt_cdclk_pcode_pre_notify(display);
>  
>  	if (ret) {
>  		drm_err(display->drm,
> @@ -2311,15 +2328,8 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	else if (DISPLAY_VER(display) >= 11)
>  		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	else
> -		/*
> -		 * The timeout isn't specified, the 2ms used here is based on
> -		 * experiment.
> -		 * FIXME: Waiting for the request completion could be delayed
> -		 * until the next PCODE request based on BSpec.
> -		 */
> -		ret = intel_parent_pcode_write_timeout(display,
> -						       HSW_PCODE_DE_WRITE_FREQ_REQ,
> -						       cdclk_config->voltage_level, 2);
> +		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
> +
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);

-- 
Jani Nikula, Intel

Re: [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Ville Syrjälä]

On Wed, Jun 10, 2026 at 08:31:48PM +0300, Jani Nikula wrote:
> On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We are currently trying to pass the CDCLK in kHz to the pcode
> > on DG2, while the pcode expects a value in MHz units. Adjust
> > the units appropriately.
> 
> How is it working? :o

I don't think DG2 pcode does all that much a with the information.
Eg. AFAIK it doesn't actually adjust any voltages due to this stuff.
I think it's more for some internal power usage estimates or something,
but dunno what that really means in practice.

> 
> Fixes: ?
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 9ca56bab281f..9718062d8d6c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> >  	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
> >  	 * which basically means we choose the maximum of old and new CDCLK, if we know both
> >  	 */
> > -	if (change_cdclk)
> > +	if (change_cdclk) {
> >  		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
> > +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> > +	}
> 
> I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to
> emphasize it's not kHz.
> 
> >  	/*
> >  	 * According to "Sequence For Pipe Count Change",
> > @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> >  	 * According to "Sequence After Frequency Change",
> >  	 * set bits 25:16 to current CDCLK
> >  	 */
> > -	if (update_cdclk)
> > +	if (update_cdclk) {
> >  		cdclk = new_cdclk_state->actual.cdclk;
> > +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> > +	}
> 
> Ditto.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> >  
> >  	/*
> >  	 * According to "Sequence For Pipe Count Change",
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

✓ i915.CI.BAT: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1016 bytes --]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168274/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18656 -> Patchwork_168274v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_18656 -> Patchwork_168274v1

  CI-20190529: 20190529
  CI_DRM_18656: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8956: 8956
  Patchwork_168274v1: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/index.html

[-- Attachment #2: Type: text/html, Size: 1581 bytes --]

Re: [PATCH 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The pcode post notufy needs to happen after the CDCLK has been

*notify

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> changed, not before. Also move the pre_notify call a bit for the
> sake of symmetry.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9718062d8d6c..d60b3369b4d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2796,9 +2796,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>  				 &new_cdclk_state->actual))
>  		return;
>  
> -	if (display->platform.dg2)
> -		intel_cdclk_pcode_pre_notify(state);
> -
>  	if (new_cdclk_state->disable_pipes) {
>  		cdclk_config = new_cdclk_state->actual;
>  		pipe = INVALID_PIPE;
> @@ -2823,6 +2820,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>  
>  	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>  
> +	if (display->platform.dg2)
> +		intel_cdclk_pcode_pre_notify(state);
> +
>  	intel_set_cdclk(display, &cdclk_config, pipe,
>  			"Pre changing CDCLK to");
>  }
> @@ -2851,9 +2851,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  				 &new_cdclk_state->actual))
>  		return;
>  
> -	if (display->platform.dg2)
> -		intel_cdclk_pcode_post_notify(state);
> -
>  	if (!new_cdclk_state->disable_pipes &&
>  	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
>  		pipe = new_cdclk_state->pipe;
> @@ -2864,6 +2861,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  
>  	intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
>  			"Post changing CDCLK to");
> +
> +	if (display->platform.dg2)
> +		intel_cdclk_pcode_post_notify(state);
>  }
>  
>  /* pixels per CDCLK */

-- 
Jani Nikula, Intel

Re: [PATCH 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We're currently skipping the pcode notifies on DG2 if the CDCLK isn't
> changing while the power well counts would still need updating.
> Do the pcode notifications also for pure pipe power well changes.

This kind of does more than just change the pcode stuff, since the
conditions are higher up. Might mention something about that here.

Anyway,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d60b3369b4d2..7259048361a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2793,7 +2793,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>  		return;
>  
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
> -				 &new_cdclk_state->actual))
> +				 &new_cdclk_state->actual) &&
> +	    dg2_power_well_count(display, old_cdclk_state) ==
> +	    dg2_power_well_count(display, new_cdclk_state))
>  		return;
>  
>  	if (new_cdclk_state->disable_pipes) {
> @@ -2848,7 +2850,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  		return;
>  
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
> -				 &new_cdclk_state->actual))
> +				 &new_cdclk_state->actual) &&
> +	    dg2_power_well_count(display, old_cdclk_state) ==
> +	    dg2_power_well_count(display, new_cdclk_state))
>  		return;
>  
>  	if (!new_cdclk_state->disable_pipes &&

-- 
Jani Nikula, Intel

Re: [PATCH 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
> we are currently forcing the voltage level to 3 all the time on
> DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
> this.

Fixes: ?

The pcode mailbox defines are a mess.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7259048361a7..ecb6be3383ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2598,7 +2598,6 @@ static void intel_pcode_notify(struct intel_display *display,
>  		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
>  
>  	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 SKL_CDCLK_PREPARE_FOR_CHANGE |
>  					 update_mask,
>  					 SKL_CDCLK_READY_FOR_CHANGE,
>  					 SKL_CDCLK_READY_FOR_CHANGE, 3);

-- 
Jani Nikula, Intel

Re: [PATCH 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Overwrite cdclk.hw.voltage_level from intel_update_cdclk() at the
> end on bxt_set_cdclk() also on bxt/glk. While this isn't actually
> necessary due to bxt/glk not having any extra DDI based voltage
> level requirements, it does avoid one less silly 'if' in the code.
>
> On icl+ the value derived by bxt_get_cdclk() may not be correct
> if the voltage level was bumped up due to DDI requirements, thus
> overwriting the assumed value is crucial there.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ecb6be3383ca..bbf3603f889b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2308,12 +2308,11 @@ static void bxt_set_cdclk(struct intel_display *display,
>  
>  	intel_update_cdclk(display);
>  
> -	if (DISPLAY_VER(display) >= 11)
> -		/*
> -		 * Can't read out the voltage level :(
> -		 * Let's just assume everything is as expected.
> -		 */
> -		display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
> +	/*
> +	 * Can't read out the voltage level :(
> +	 * Let's just assume everything is as expected.
> +	 */
> +	display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
>  }
>  
>  static void bxt_sanitize_cdclk(struct intel_display *display)

-- 
Jani Nikula, Intel

✗ i915.CI.Full: failure for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 130405 bytes --]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168274/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18656_full -> Patchwork_168274v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_168274v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_168274v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_168274v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-dg1:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-17/igt@kms_cursor_crc@cursor-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-15/igt@kms_cursor_crc@cursor-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_168274v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-tglu-1:       NOTRUN -> [SKIP][3] ([i915#6230])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@api_intel_bb@crc32.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg2:          NOTRUN -> [SKIP][4] ([i915#11078])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#11078])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_buddy@drm_buddy:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#15678])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@drm_buddy@drm_buddy.html

  * igt@gem_basic@multigpu-create-close:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#7697])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@gem_basic@multigpu-create-close.html
    - shard-dg2:          NOTRUN -> [SKIP][8] ([i915#7697])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_ccs@ctrl-surf-copy.html
    - shard-tglu:         NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#13008])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [PASS][12] -> [INCOMPLETE][13] ([i915#13356] / [i915#16348]) +1 other test incomplete
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-8/igt@gem_ccs@suspend-resume.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-5/igt@gem_ccs@suspend-resume.html
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#9323])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-tglu-1:       NOTRUN -> [SKIP][15] ([i915#6335])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][16] ([i915#13356]) +1 other test incomplete
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#8555])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#5882]) +7 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#4036])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@parallel:
    - shard-tglu:         NOTRUN -> [SKIP][20] ([i915#4525])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#4812]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#6334]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@gem_exec_capture@capture-invisible@smem0.html
    - shard-tglu:         NOTRUN -> [SKIP][23] ([i915#6334]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#3539] / [i915#4852])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_reloc@basic-cpu-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@gem_exec_reloc@basic-cpu-gtt.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#3281]) +6 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4860]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][28] ([i915#4613])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-tglu:         NOTRUN -> [SKIP][29] ([i915#4613]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][30] ([i915#4613]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][31] ([i915#4613]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_mmap_wc@write-read-distinct:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4083]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_mmap_wc@write-read-distinct.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][33] ([i915#3282]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk11:        NOTRUN -> [WARN][34] ([i915#14702] / [i915#2658])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk11/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-regular-context-2:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4270]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_pxp@create-regular-context-2.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][36] ([i915#13398])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_readwrite@beyond-eob:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#3282]) +6 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_readwrite@beyond-eob.html

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#5190] / [i915#8428]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs.html

  * igt@gem_tiled_pread_basic@basic:
    - shard-rkl:          NOTRUN -> [SKIP][39] ([i915#15656])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_tiled_pread_basic@basic.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][40] ([i915#3297]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#3282] / [i915#3297])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#3297]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#2527] / [i915#2856])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#2527]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#2527] / [i915#2856]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#2856])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@i915_drm_fdinfo@all-busy-idle-check-all:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#14123])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@i915_drm_fdinfo@all-busy-idle-check-all.html

  * igt@i915_drm_fdinfo@busy-idle-check-all@vcs0:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#11527]) +7 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@i915_drm_fdinfo@busy-idle-check-all@vcs0.html

  * igt@i915_drm_fdinfo@virtual-busy-idle-all:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#14118]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@i915_drm_fdinfo@virtual-busy-idle-all.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#8399])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@media-rc6-accuracy:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#16080] / [i915#16166])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@i915_pm_rc6_residency@media-rc6-accuracy.html

  * igt@i915_pm_rpm@gem-evict-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#4077]) +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@i915_pm_rpm@gem-evict-pwrite.html

  * igt@i915_pm_rps@thresholds:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#11681]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@i915_pm_rps@thresholds.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#16109])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_query@query-topology-unsupported:
    - shard-tglu-1:       NOTRUN -> [SKIP][55] ([i915#16079])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@i915_query@query-topology-unsupported.html

  * igt@i915_selftest@live:
    - shard-dg1:          [PASS][56] -> [DMESG-FAIL][57] ([i915#15560])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-16/igt@i915_selftest@live.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-19/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gem_contexts:
    - shard-dg1:          [PASS][58] -> [DMESG-FAIL][59] ([i915#15433])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-16/igt@i915_selftest@live@gem_contexts.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-19/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_suspend@forcewake:
    - shard-glk:          NOTRUN -> [INCOMPLETE][60] ([i915#16182] / [i915#4817])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@i915_suspend@forcewake.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#4212]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3:
    - shard-dg2:          [PASS][62] -> [FAIL][63] ([i915#14888]) +1 other test fail
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-5/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3.html

  * igt@kms_atomic_transition@modeset-transition-fencing:
    - shard-dg1:          [PASS][64] -> [DMESG-WARN][65] ([i915#4423])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-14/igt@kms_atomic_transition@modeset-transition-fencing.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-16/igt@kms_atomic_transition@modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][66] ([i915#1769])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-tglu:         NOTRUN -> [SKIP][67] ([i915#5286]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][68] ([i915#5286]) +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][69] ([i915#5286]) +3 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][70] -> [FAIL][71] ([i915#15733] / [i915#5138])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#3638]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#3828])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#5190])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#4538] / [i915#5190]) +5 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][76] ([i915#6095]) +24 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#14098] / [i915#14544] / [i915#6095]) +6 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][78] ([i915#12313])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#6095]) +50 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#4423] / [i915#6095])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-12/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#12313]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][82] ([i915#6095]) +54 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#10307] / [i915#6095]) +95 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#12805])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#6095]) +7 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#14544] / [i915#6095]) +12 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#14098] / [i915#6095]) +35 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][89] ([i915#6095]) +254 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-15/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#12313])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][91] +323 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#3742]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#3742])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#13781]) +3 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#11151] / [i915#7828]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@dp-mode-timings:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#11151] / [i915#7828]) +5 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_chamelium_edid@dp-mode-timings.html

  * igt@kms_chamelium_frames@dp-frame-dump:
    - shard-tglu-1:       NOTRUN -> [SKIP][97] ([i915#11151] / [i915#7828]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_chamelium_frames@dp-frame-dump.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#11151] / [i915#7828]) +6 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#15865]) +2 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#15330] / [i915#3116]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#15865]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-1:
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#15865])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#15865]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][104] ([i915#7173]) +1 other test fail
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_content_protection@suspend-resume@pipe-a-dp-3.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#13049])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-rkl:          [PASS][106] -> [FAIL][107] ([i915#13566])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-tglu:         NOTRUN -> [SKIP][108] ([i915#3555]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][109] ([i915#13566]) +7 other tests fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#3555]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#13049])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([i915#3555]) +4 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#13049])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
    - shard-tglu:         NOTRUN -> [SKIP][114] ([i915#13049])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][115] ([i915#13566]) +1 other test fail
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][116] ([i915#4103]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#13046] / [i915#5354]) +5 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#9833])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dp_aux_dev@basic:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#1257])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_dp_aux_dev@basic.html
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#1257])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_dp_aux_dev@basic.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-tglu-1:       NOTRUN -> [SKIP][121] ([i915#13749])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#13748])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_draw_crc@draw-method-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#8812])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_draw_crc@draw-method-mmap-gtt.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#16361]) +4 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-ultrajoiner:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#16361]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_dsc@dsc-with-output-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#16361]) +3 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html
    - shard-tglu:         NOTRUN -> [SKIP][127] ([i915#16361])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#3955])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([i915#16084])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#16081]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#8381]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-tglu-1:       NOTRUN -> [SKIP][132] ([i915#3637] / [i915#9934]) +6 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#9934]) +5 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-rkl:          NOTRUN -> [SKIP][134] ([i915#9934]) +8 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_flip@2x-wf_vblank-ts-check.html
    - shard-tglu:         NOTRUN -> [SKIP][135] ([i915#3637] / [i915#9934]) +6 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#15643])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
    - shard-glk10:        NOTRUN -> [SKIP][137] +172 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#15643] / [i915#5190])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#15643]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#15643]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-p010-4tile-to-p016-4tile:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#15643]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-p010-4tile-to-p016-4tile.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#15104] / [i915#15990])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#15990] / [i915#8708]) +7 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#15991] / [i915#5354]) +17 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#1825]) +8 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][146] ([i915#10056])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk11/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#5439])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#10055]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#15989]) +22 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-indfb-plflip-blt:
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#15989]) +9 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-glk:          [PASS][151] -> [SKIP][152]
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk9/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt:
    - shard-tglu:         NOTRUN -> [SKIP][153] +52 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy:
    - shard-dg2:          [PASS][154] -> [SKIP][155] ([i915#15989]) +7 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbchdr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#15989]) +10 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-stridechange:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#15989]) +15 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-stridechange.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#15102] / [i915#3023]) +14 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][159] +83 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#10433] / [i915#15102]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#15990]) +15 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][162] ([i915#15102]) +32 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][163] ([i915#5439])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt:
    - shard-rkl:          [PASS][164] -> [SKIP][165] ([i915#15989]) +15 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][166] ([i915#16056])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk11/igt@kms_frontbuffer_tracking@hdr-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#15102]) +26 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#15102]) +20 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#15102]) +20 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#15991]) +33 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][171] +89 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt:
    - shard-glk11:        NOTRUN -> [SKIP][172] +139 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk11/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch:
    - shard-tglu-1:       NOTRUN -> [SKIP][173] ([i915#16012] / [i915#3555] / [i915#8228])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#16012] / [i915#3555] / [i915#8228])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][175] ([i915#16012]) +7 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-15/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@bpc-switch@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#16012]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_hdr@bpc-switch@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@bpc-switch@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#16012]) +3 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_hdr@bpc-switch@pipe-a-hdmi-a-1-xrgb2101010.html
    - shard-tglu-1:       NOTRUN -> [SKIP][178] ([i915#16012]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_hdr@bpc-switch@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-2-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#14544] / [i915#16076]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-2-xrgb16161616f.html

  * igt@kms_hdr@invalid-hdr@pipe-a-dp-3-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#16025]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_hdr@invalid-hdr@pipe-a-dp-3-xrgb2101010.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#16011] / [i915#3555] / [i915#8228])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#16011]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-swap:
    - shard-rkl:          NOTRUN -> [SKIP][183] ([i915#16011] / [i915#3555] / [i915#8228]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][184] ([i915#16011] / [i915#3555] / [i915#8228]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#16011] / [i915#3555] / [i915#8228])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#16011]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#16011]) +7 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f.html
    - shard-tglu:         NOTRUN -> [SKIP][188] ([i915#16011]) +3 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#16011]) +7 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-13/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#15458])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-tglu:         NOTRUN -> [SKIP][191] ([i915#15458])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][192] ([i915#13688])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#15638] / [i915#15722])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#6301])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-dg2:          NOTRUN -> [SKIP][195] +9 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-rkl:          [PASS][196] -> [INCOMPLETE][197] ([i915#12756] / [i915#13476])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-8/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][198] ([i915#13476])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#14712])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][200] ([i915#15709]) +3 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][201] ([i915#15709]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
    - shard-rkl:          NOTRUN -> [SKIP][202] ([i915#15709]) +3 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][203] ([i915#15709]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y:
    - shard-tglu-1:       NOTRUN -> [SKIP][204] ([i915#16112])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][205] ([i915#10647] / [i915#12169])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][206] ([i915#10647]) +1 other test fail
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb:
    - shard-glk10:        NOTRUN -> [FAIL][207] ([i915#10647] / [i915#12177])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@kms_plane_alpha_blend@alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [FAIL][208] ([i915#10647]) +1 other test fail
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-rkl:          NOTRUN -> [SKIP][209] ([i915#13958])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][210] ([i915#13958]) +1 other test skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][211] ([i915#14259])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#14259])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-tglu-1:       NOTRUN -> [SKIP][213] ([i915#15329]) +4 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][214] ([i915#12343])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-rkl:          NOTRUN -> [SKIP][215] ([i915#15948])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][216] ([i915#15739])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg1:          [PASS][217] -> [SKIP][218] ([i915#15073])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-15/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-13/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-rkl:          NOTRUN -> [SKIP][219] ([i915#15403])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_pm_rpm@package-g7.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-tglu-1:       NOTRUN -> [SKIP][220] ([i915#6524])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2:          NOTRUN -> [SKIP][221] ([i915#6524] / [i915#6805])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-glk10:        NOTRUN -> [SKIP][222] ([i915#11520]) +3 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([i915#11520]) +6 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][224] ([i915#11520]) +6 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#11520]) +6 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][226] ([i915#11520]) +8 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-glk11:        NOTRUN -> [SKIP][227] ([i915#11520]) +4 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk11/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][228] ([i915#11520]) +3 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-rkl:          NOTRUN -> [SKIP][229] ([i915#9683]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_psr2_su@page_flip-xrgb8888.html
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#9683])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-9/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#1072] / [i915#9732]) +20 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][232] ([i915#9732]) +14 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#1072] / [i915#9732]) +12 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr@psr-sprite-blt:
    - shard-tglu:         NOTRUN -> [SKIP][234] ([i915#9732]) +8 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_psr@psr-sprite-blt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2:          NOTRUN -> [SKIP][235] ([i915#15949])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#4235])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk:          NOTRUN -> [INCOMPLETE][237] ([i915#15492] / [i915#16184])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][238] ([i915#5289])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][239] ([i915#12755] / [i915#15867] / [i915#5190])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
    - shard-tglu-1:       NOTRUN -> [SKIP][240] ([i915#5289])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][241] ([i915#12755] / [i915#15867]) +1 other test skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-tglu-1:       NOTRUN -> [SKIP][242] ([i915#3555]) +2 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu-1:       NOTRUN -> [SKIP][243] ([i915#8623])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2:          NOTRUN -> [SKIP][244] ([i915#8623])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][245] ([i915#12276]) +1 other test incomplete
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][246] ([i915#15132])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-rkl:          [PASS][247] -> [INCOMPLETE][248] ([i915#12276])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_vblank@ts-continuation-suspend.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_vblank@ts-continuation-suspend.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][249] ([i915#12276])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@flip-basic:
    - shard-rkl:          NOTRUN -> [SKIP][250] ([i915#15243] / [i915#3555])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#9906])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          NOTRUN -> [SKIP][252] ([i915#3555] / [i915#9906])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@kms_vrr@negative-basic.html
    - shard-rkl:          NOTRUN -> [SKIP][253] ([i915#3555] / [i915#9906])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@kms_vrr@negative-basic.html
    - shard-mtlp:         [PASS][254] -> [FAIL][255] ([i915#15420]) +1 other test fail
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-mtlp-3/igt@kms_vrr@negative-basic.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-mtlp-5/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-tglu-1:       NOTRUN -> [SKIP][256] ([i915#9906])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-dg2:          NOTRUN -> [SKIP][257] ([i915#2436])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@mi-rpc:
    - shard-rkl:          NOTRUN -> [SKIP][258] ([i915#2434])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@perf@mi-rpc.html

  * igt@perf_pmu@module-unload:
    - shard-glk10:        NOTRUN -> [ABORT][259] ([i915#15778])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk10/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6-suspend:
    - shard-rkl:          [PASS][260] -> [INCOMPLETE][261] ([i915#13520])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-7/igt@perf_pmu@rc6-suspend.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@perf_pmu@rc6-suspend.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          NOTRUN -> [SKIP][262] ([i915#3291] / [i915#3708])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#3708])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@prime_vgem@fence-read-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#3708])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-rkl:          NOTRUN -> [SKIP][265] ([i915#9917])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@sriov_basic@bind-unbind-vf.html

  * igt@sriov_basic@bind-unbind-vf@vf-4:
    - shard-tglu:         NOTRUN -> [SKIP][266] ([i915#16066]) +9 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@sriov_basic@bind-unbind-vf@vf-4.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#4818])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_exec_big@single:
    - shard-mtlp:         [FAIL][268] ([i915#15871]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-mtlp-5/igt@gem_exec_big@single.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-mtlp-5/igt@gem_exec_big@single.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [INCOMPLETE][270] ([i915#13356]) -> [PASS][271] +1 other test pass
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-6/igt@gem_exec_suspend@basic-s0.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-4/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [INCOMPLETE][272] ([i915#16021] / [i915#16108] / [i915#16202]) -> [PASS][273] +1 other test pass
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-mtlp-3/igt@gem_mmap_offset@clear-via-pagefault.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-mtlp-7/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [INCOMPLETE][274] ([i915#13809] / [i915#16226]) -> [PASS][275]
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-4/igt@gem_softpin@noreloc-s3.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-5/igt@gem_softpin@noreloc-s3.html

  * igt@i915_suspend@debugfs-reader:
    - shard-glk:          [INCOMPLETE][276] ([i915#16182] / [i915#4817]) -> [PASS][277] +1 other test pass
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-glk5/igt@i915_suspend@debugfs-reader.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk6/igt@i915_suspend@debugfs-reader.html
    - shard-rkl:          [INCOMPLETE][278] ([i915#4817]) -> [PASS][279]
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-3/igt@i915_suspend@debugfs-reader.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@sysfs-reader:
    - shard-rkl:          [ABORT][280] ([i915#15140]) -> [PASS][281]
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-1/igt@i915_suspend@sysfs-reader.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@i915_suspend@sysfs-reader.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-rkl:          [INCOMPLETE][282] ([i915#14694] / [i915#15582]) -> [PASS][283] +1 other test pass
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2:          [SKIP][284] ([i915#13749]) -> [PASS][285]
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-1/igt@kms_dp_link_training@non-uhbr-sst.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][286] ([i915#15989]) -> [PASS][287] +13 other tests pass
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-mmap-gtt:
    - shard-glk:          [SKIP][288] -> [PASS][289] +14 other tests pass
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-glk4/igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-mmap-gtt.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][290] ([i915#15989]) -> [PASS][291] +3 other tests pass
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-4/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-mtlp:         [SKIP][292] ([i915#15725]) -> [PASS][293]
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-mtlp-1/igt@kms_hdmi_inject@inject-audio.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-mtlp-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          [SKIP][294] ([i915#16011] / [i915#3555] / [i915#8228]) -> [PASS][295]
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_hdr@invalid-metadata-sizes.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [DMESG-WARN][296] ([i915#4423]) -> [PASS][297]
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-17/igt@kms_pm_rpm@i2c.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-15/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][298] ([i915#14544] / [i915#15073]) -> [PASS][299]
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][300] ([i915#15073]) -> [PASS][301]
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
    - shard-dg1:          [SKIP][302] ([i915#15073]) -> [PASS][303]
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-16/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][304] ([i915#12276]) -> [PASS][305]
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][306] ([i915#4349]) -> [PASS][307] +4 other tests pass
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@api_intel_bb@crc32:
    - shard-rkl:          [SKIP][308] ([i915#6230]) -> [SKIP][309] ([i915#14544] / [i915#6230])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@api_intel_bb@crc32.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][310] ([i915#11078]) -> [SKIP][311] ([i915#11078] / [i915#14544])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@device_reset@unbind-cold-reset-rebind.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-rkl:          [SKIP][312] ([i915#14544] / [i915#3281]) -> [SKIP][313] ([i915#3281]) +4 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          [SKIP][314] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][315] ([i915#3555] / [i915#9323])
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-rkl:          [SKIP][316] ([i915#14544] / [i915#280]) -> [SKIP][317] ([i915#280])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_ctx_sseu@mmap-args.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-rkl:          [SKIP][318] ([i915#4525]) -> [SKIP][319] ([i915#14544] / [i915#4525])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_reloc@basic-write-read:
    - shard-rkl:          [SKIP][320] ([i915#3281]) -> [SKIP][321] ([i915#14544] / [i915#3281]) +7 other tests skip
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@gem_exec_reloc@basic-write-read.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          [SKIP][322] ([i915#14544] / [i915#4613]) -> [SKIP][323] ([i915#4613]) +2 other tests skip
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_lmem_swapping@heavy-multi.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          [SKIP][324] ([i915#4613]) -> [SKIP][325] ([i915#14544] / [i915#4613]) +2 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-rkl:          [SKIP][326] ([i915#14544] / [i915#3282]) -> [SKIP][327] ([i915#3282]) +3 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_partial_pwrite_pread@reads.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          [SKIP][328] ([i915#13717] / [i915#14544]) -> [SKIP][329] ([i915#13717])
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_pxp@hw-rejects-pxp-buffer.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][330] ([i915#3282]) -> [SKIP][331] ([i915#14544] / [i915#3282]) +4 other tests skip
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@gem_set_tiling_vs_pwrite.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-rkl:          [SKIP][332] ([i915#14544] / [i915#3297]) -> [SKIP][333] ([i915#3297])
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gem_userptr_blits@dmabuf-unsync.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [SKIP][334] ([i915#14544] / [i915#2527]) -> [SKIP][335] ([i915#2527]) +1 other test skip
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@gen9_exec_parse@bb-start-param.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          [SKIP][336] ([i915#2527]) -> [SKIP][337] ([i915#14544] / [i915#2527])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@gen9_exec_parse@shadow-peek.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-rkl:          [SKIP][338] ([i915#14544] / [i915#8399]) -> [SKIP][339] ([i915#8399])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@i915_pm_freq_api@freq-reset.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          [SKIP][340] ([i915#6590]) -> [SKIP][341] ([i915#14544] / [i915#6590]) +1 other test skip
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@i915_pm_freq_mult@media-freq@gt0.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_power@sanity:
    - shard-rkl:          [SKIP][342] ([i915#14544] / [i915#7984]) -> [SKIP][343] ([i915#7984])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@i915_power@sanity.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@i915_power@sanity.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          [SKIP][344] ([i915#6245]) -> [SKIP][345] ([i915#14544] / [i915#6245])
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@i915_query@hwconfig_table.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@i915_query@hwconfig_table.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          [SKIP][346] ([i915#14544] / [i915#7707]) -> [SKIP][347] ([i915#7707])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@intel_hwmon@hwmon-write.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@intel_hwmon@hwmon-write.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][348] ([i915#14544] / [i915#1769] / [i915#3555]) -> [SKIP][349] ([i915#1769] / [i915#3555])
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-rkl:          [SKIP][350] ([i915#14544] / [i915#5286]) -> [SKIP][351] ([i915#5286]) +2 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][352] ([i915#5286]) -> [SKIP][353] ([i915#14544] / [i915#5286]) +2 other tests skip
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][354] ([i915#3828]) -> [SKIP][355] ([i915#14544] / [i915#3828])
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][356] ([i915#14544] / [i915#3638]) -> [SKIP][357] ([i915#3638])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][358] ([i915#3638]) -> [SKIP][359] ([i915#14544] / [i915#3638]) +3 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-dg1:          [SKIP][360] ([i915#6095]) -> [SKIP][361] ([i915#4423] / [i915#6095]) +1 other test skip
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-16/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-19/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-dg1:          [SKIP][362] ([i915#12313]) -> [SKIP][363] ([i915#12313] / [i915#4423])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-15/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs:
    - shard-rkl:          [SKIP][364] ([i915#14098] / [i915#6095]) -> [SKIP][365] ([i915#14098] / [i915#14544] / [i915#6095]) +6 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][366] ([i915#12805]) -> [SKIP][367] ([i915#12805] / [i915#14544])
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][368] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][369] ([i915#14098] / [i915#6095]) +12 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][370] ([i915#14544] / [i915#6095]) -> [SKIP][371] ([i915#6095]) +8 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-rkl:          [SKIP][372] ([i915#11151] / [i915#7828]) -> [SKIP][373] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-8/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-rkl:          [SKIP][374] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][375] ([i915#11151] / [i915#7828]) +5 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@atomic:
    - shard-dg2:          [SKIP][376] ([i915#15865]) -> [FAIL][377] ([i915#7173]) +1 other test fail
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-1/igt@kms_content_protection@atomic.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-rkl:          [SKIP][378] ([i915#14544] / [i915#15330]) -> [SKIP][379] ([i915#15330]) +1 other test skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][380] ([i915#15865]) -> [SKIP][381] ([i915#9433])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-15/igt@kms_content_protection@mei-interface.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-13/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          [SKIP][382] ([i915#15865]) -> [SKIP][383] ([i915#14544] / [i915#15865]) +3 other tests skip
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_content_protection@type1.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          [SKIP][384] ([i915#13049] / [i915#14544]) -> [SKIP][385] ([i915#13049])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][386] ([i915#14544] / [i915#4103]) -> [SKIP][387] ([i915#4103])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][388] ([i915#4103]) -> [SKIP][389] ([i915#14544] / [i915#4103]) +1 other test skip
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          [SKIP][390] ([i915#13691]) -> [SKIP][391] ([i915#13691] / [i915#14544])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_display_modes@extended-mode-basic.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-rkl:          [SKIP][392] ([i915#13707] / [i915#14544]) -> [SKIP][393] ([i915#13707])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          [SKIP][394] ([i915#14544] / [i915#16361]) -> [SKIP][395] ([i915#16361]) +1 other test skip
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-rkl:          [SKIP][396] ([i915#16361]) -> [SKIP][397] ([i915#14544] / [i915#16361]) +2 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][398] ([i915#14544] / [i915#3955]) -> [SKIP][399] ([i915#3955])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][400] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][401] ([i915#12314] / [i915#12745] / [i915#4839])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-glk4/igt@kms_flip@2x-flip-vs-suspend.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk8/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][402] ([i915#12745]) -> [INCOMPLETE][403] ([i915#12314] / [i915#12745])
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-glk4/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-glk8/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          [SKIP][404] ([i915#9934]) -> [SKIP][405] ([i915#14544] / [i915#9934]) +4 other tests skip
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-rkl:          [SKIP][406] ([i915#14544] / [i915#9934]) -> [SKIP][407] ([i915#9934]) +3 other tests skip
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-rkl:          [SKIP][408] ([i915#14544] / [i915#15643]) -> [SKIP][409] ([i915#15643]) +1 other test skip
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][410] ([i915#15643]) -> [SKIP][411] ([i915#14544] / [i915#15643]) +1 other test skip
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][412] ([i915#14544]) -> [SKIP][413] +54 other tests skip
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-tiling-4:
    - shard-rkl:          [SKIP][414] ([i915#14544] / [i915#5439]) -> [SKIP][415] ([i915#5439])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-tiling-4.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-rkl:          [SKIP][416] ([i915#15102] / [i915#3023]) -> [SKIP][417] ([i915#14544] / [i915#15102] / [i915#3023]) +11 other tests skip
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg1:          [SKIP][418] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][419] ([i915#15990] / [i915#8708])
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          [SKIP][420] ([i915#10433] / [i915#15102]) -> [SKIP][421] ([i915#15102]) +1 other test skip
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][422] ([i915#1825]) -> [SKIP][423] ([i915#14544] / [i915#1825]) +2 other tests skip
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][424] ([i915#14544] / [i915#1825]) -> [SKIP][425] ([i915#1825]) +2 other tests skip
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          [SKIP][426] ([i915#5439]) -> [SKIP][427] ([i915#14544] / [i915#5439])
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][428] ([i915#14544] / [i915#15102]) -> [SKIP][429] ([i915#15102]) +14 other tests skip
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-shrfb-pgflip-blt.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][430] ([i915#15102]) -> [SKIP][431] ([i915#14544] / [i915#15102]) +12 other tests skip
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff:
    - shard-rkl:          [SKIP][432] -> [SKIP][433] ([i915#14544]) +60 other tests skip
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@hdr-suspend:
    - shard-dg2:          [ABORT][434] ([i915#15132]) -> [SKIP][435] ([i915#15989])
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-10/igt@kms_frontbuffer_tracking@hdr-suspend.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_frontbuffer_tracking@hdr-suspend.html
    - shard-rkl:          [SKIP][436] ([i915#15989]) -> [INCOMPLETE][437] ([i915#16056])
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_frontbuffer_tracking@hdr-suspend.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-suspend.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-rkl:          [SKIP][438] ([i915#14544] / [i915#9766]) -> [SKIP][439] ([i915#9766])
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][440] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][441] ([i915#15102] / [i915#3023]) +12 other tests skip
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-blt:
    - shard-dg1:          [SKIP][442] -> [SKIP][443] ([i915#4423])
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg1-16/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-blt.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg1-18/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          [SKIP][444] ([i915#16011]) -> [SKIP][445] ([i915#14544] / [i915#16076])
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_hdr@brightness-with-hdr.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2:          [SKIP][446] ([i915#16012] / [i915#3555] / [i915#8228]) -> [SKIP][447] ([i915#3555] / [i915#8228])
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-1/igt@kms_hdr@invalid-hdr.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-10/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          [SKIP][448] ([i915#13688]) -> [SKIP][449] ([i915#13688] / [i915#14544])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_joiner@basic-max-non-joiner.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-rkl:          [SKIP][450] ([i915#15458]) -> [SKIP][451] ([i915#14544] / [i915#15458])
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          [SKIP][452] ([i915#14544] / [i915#15709]) -> [SKIP][453] ([i915#15709]) +1 other test skip
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
    - shard-rkl:          [SKIP][454] ([i915#15709]) -> [SKIP][455] ([i915#14544] / [i915#15709]) +2 other tests skip
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          [SKIP][456] ([i915#14544] / [i915#3555]) -> [SKIP][457] ([i915#3555]) +3 other tests skip
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][458] ([i915#13958]) -> [SKIP][459] ([i915#13958] / [i915#14544])
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_plane_multiple@2x-tiling-none.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][460] ([i915#15329]) -> [SKIP][461] ([i915#14544] / [i915#15329]) +3 other tests skip
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-rkl:          [SKIP][462] ([i915#14544] / [i915#15329] / [i915#3555]) -> [SKIP][463] ([i915#15329] / [i915#3555])
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
    - shard-rkl:          [SKIP][464] ([i915#14544] / [i915#15329]) -> [SKIP][465] ([i915#15329]) +2 other tests skip
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          [SKIP][466] ([i915#12343] / [i915#14544] / [i915#5354]) -> [SKIP][467] ([i915#12343] / [i915#5354])
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_pm_backlight@basic-brightness.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          [SKIP][468] ([i915#14544] / [i915#15948]) -> [SKIP][469] ([i915#15948])
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_pm_dc@dc5-psr.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][470] ([i915#15752]) -> [SKIP][471] ([i915#15128])
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-tglu-2/igt@kms_pm_dc@dc6-dpms.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          [SKIP][472] ([i915#6524]) -> [SKIP][473] ([i915#14544] / [i915#6524])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_prime@basic-modeset-hybrid.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][474] ([i915#11520]) -> [SKIP][475] ([i915#11520] / [i915#14544]) +2 other tests skip
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-rkl:          [SKIP][476] ([i915#11520] / [i915#14544]) -> [SKIP][477] ([i915#11520]) +4 other tests skip
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-sprite-mmap-gtt:
    - shard-rkl:          [SKIP][478] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][479] ([i915#1072] / [i915#9732]) +10 other tests skip
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-rkl:          [SKIP][480] ([i915#1072] / [i915#9732]) -> [SKIP][481] ([i915#1072] / [i915#14544] / [i915#9732]) +14 other tests skip
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-2/igt@kms_psr@psr-sprite-plane-move.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          [SKIP][482] ([i915#14544] / [i915#15949]) -> [SKIP][483] ([i915#15949])
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          [SKIP][484] ([i915#15867]) -> [SKIP][485] ([i915#12755] / [i915#15867])
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-10/igt@kms_rotation_crc@bad-tiling.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2:          [SKIP][486] ([i915#15867] / [i915#5190]) -> [SKIP][487] ([i915#12755] / [i915#15867] / [i915#5190])
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-dg2-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-dg2-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-rkl:          [INCOMPLETE][488] ([i915#12276]) -> [ABORT][489] ([i915#15132])
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-3/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-1/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vrr@flipline:
    - shard-rkl:          [SKIP][490] ([i915#14544] / [i915#15243] / [i915#3555]) -> [SKIP][491] ([i915#15243] / [i915#3555])
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_vrr@flipline.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@kms_vrr@flipline.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-rkl:          [SKIP][492] ([i915#14544] / [i915#9906]) -> [SKIP][493] ([i915#9906])
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-vrr.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-2/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][494] ([i915#2436]) -> [SKIP][495] ([i915#14544] / [i915#2436])
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-8/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-6/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@prime_vgem@coherency-gtt:
    - shard-rkl:          [SKIP][496] ([i915#14544] / [i915#3708]) -> [SKIP][497] ([i915#3708])
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@prime_vgem@coherency-gtt.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-3/igt@prime_vgem@coherency-gtt.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          [SKIP][498] ([i915#14544] / [i915#9917]) -> [SKIP][499] ([i915#9917])
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18656/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/shard-rkl-4/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11527
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12756]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12756
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14694]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14694
  [i915#14702]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14702
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15420
  [i915#15433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15433
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15560]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15560
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15656
  [i915#15678]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15678
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15722]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15722
  [i915#15725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15725
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15739
  [i915#15752]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15752
  [i915#15778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15778
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15871]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15871
  [i915#15948]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15948
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16011]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16011
  [i915#16012]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16012
  [i915#16021]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16021
  [i915#16025]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16025
  [i915#16056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16056
  [i915#16066]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16066
  [i915#16076]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16076
  [i915#16079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16079
  [i915#16080]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16080
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16084]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16084
  [i915#16108]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16108
  [i915#16109]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16109
  [i915#16112]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16112
  [i915#16166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16166
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16202
  [i915#16226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16226
  [i915#16348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16348
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18656 -> Patchwork_168274v1

  CI-20190529: 20190529
  CI_DRM_18656: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8956: 8956
  Patchwork_168274v1: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/index.html

[-- Attachment #2: Type: text/html, Size: 173284 bytes --]

Re: [PATCH 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The control flow between the pcode pre and post notifications ibn

*in

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> bxt_set_cdclk() is written in two different ways, even though
> they end up doing the same thing. Unify the code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++----------
>  1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 659c1c0e3432..09981a112db4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2237,7 +2237,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  {
>  	struct intel_cdclk_config mid_cdclk_config;
>  	int cdclk = cdclk_config->cdclk;
> -	int ret = 0;
> +	int ret;
>  
>  	/*
>  	 * Inform power controller of upcoming frequency change.
> @@ -2246,7 +2246,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	 * this step.
>  	 */
>  	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> -		; /* NOOP */
> +		ret = 0; /* NOOP */
>  	else if (DISPLAY_VER(display) >= 11)
>  		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
>  						 SKL_CDCLK_PREPARE_FOR_CHANGE,
> @@ -2282,15 +2282,12 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
>  		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
>  
> -	if (DISPLAY_VER(display) >= 14)
> -		/*
> -		 * NOOP - No Pcode communication needed for
> -		 * Display versions 14 and beyond
> -		 */;
> -	else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
> +	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> +		ret = 0; /* NOOP */
> +	else if (DISPLAY_VER(display) >= 11)
>  		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
>  					       cdclk_config->voltage_level);
> -	if (DISPLAY_VER(display) < 11) {
> +	else
>  		/*
>  		 * The timeout isn't specified, the 2ms used here is based on
>  		 * experiment.
> @@ -2300,7 +2297,6 @@ static void bxt_set_cdclk(struct intel_display *display,
>  		ret = intel_parent_pcode_write_timeout(display,
>  						       HSW_PCODE_DE_WRITE_FREQ_REQ,
>  						       cdclk_config->voltage_level, 2);
> -	}
>  	if (ret)
>  		drm_err(display->drm,
>  			"PCode CDCLK freq set failed, (err %d, freq %d)\n",

-- 
Jani Nikula, Intel

Re: [PATCH 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Turn the cdclk pcode pre/post notify functiosn into vfuncs.

*functions

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Mainly to get rid of the hideous if-ladders in bxt_set_cdclk().
>
> DG2 is currently doing its own thing with its pcode notify funcs so
> can't be converted yet. And MTL+ go via the pmdemand stuff so this
> is all supposedly handled elsewhere.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 122 ++++++++++++---------
>  1 file changed, 73 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 749e366e60ab..4154b4888eff 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -163,6 +163,9 @@ struct intel_cdclk_funcs {
>  	void (*set_cdclk)(struct intel_display *display,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe);
> +	int (*pre_notify)(struct intel_display *display);
> +	int (*post_notify)(struct intel_display *display,
> +			   const struct intel_cdclk_config *cdclk_config);
>  	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
>  	u8 (*calc_voltage_level)(int cdclk);
>  };
> @@ -173,6 +176,35 @@ void intel_cdclk_get_cdclk(struct intel_display *display,
>  	display->cdclk.funcs->get_cdclk(display, cdclk_config);
>  }
>  
> +static int intel_cdclk_pre_notify(struct intel_display *display)
> +{
> +	int ret;
> +
> +	if (!display->cdclk.funcs->pre_notify)
> +		return 0;
> +
> +	ret = display->cdclk.funcs->pre_notify(display);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform system about start of CDCLK change (%d)\n", ret);
> +
> +	return ret;
> +}
> +
> +static void intel_cdclk_post_notify(struct intel_display *display,
> +				    const struct intel_cdclk_config *cdclk_config)
> +{
> +	int ret;
> +
> +	if (!display->cdclk.funcs->post_notify)
> +		return;
> +
> +	ret = display->cdclk.funcs->post_notify(display, cdclk_config);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform system about end of CDCLK change (%d)\n", ret);
> +}
> +
>  static void intel_cdclk_set_cdclk(struct intel_display *display,
>  				  const struct intel_cdclk_config *cdclk_config,
>  				  enum pipe pipe)
> @@ -901,12 +933,9 @@ static void bdw_set_cdclk(struct intel_display *display,
>  		     "trying to change cdclk frequency with cdclk not enabled\n"))
>  		return;
>  
> -	ret = bdw_cdclk_pcode_pre_notify(display);
> -	if (ret) {
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> +	ret = intel_cdclk_pre_notify(display);
> +	if (ret)
>  		return;
> -	}
>  
>  	intel_de_rmw(display, LCPLL_CTL,
>  		     0, LCPLL_CD_SOURCE_FCLK);
> @@ -931,10 +960,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
> -	if (ret)
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
> +	intel_cdclk_post_notify(display, cdclk_config);
>  
>  	intel_de_write(display, CDCLK_FREQ,
>  		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1205,12 +1231,9 @@ static void skl_set_cdclk(struct intel_display *display,
>  	drm_WARN_ON_ONCE(display->drm,
>  			 display->platform.skylake && vco == 8640000);
>  
> -	ret = skl_cdclk_pcode_pre_notify(display);
> -	if (ret) {
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> +	ret = intel_cdclk_pre_notify(display);
> +	if (ret)
>  		return;
> -	}
>  
>  	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
>  
> @@ -1247,10 +1270,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
> -	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
> -	if (ret)
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
> +	intel_cdclk_post_notify(display, cdclk_config);
>  
>  	intel_update_cdclk(display);
>  }
> @@ -2290,24 +2310,9 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	int cdclk = cdclk_config->cdclk;
>  	int ret;
>  
> -	/*
> -	 * Inform power controller of upcoming frequency change.
> -	 * Display versions 14 and beyond do not follow the PUnit
> -	 * mailbox communication, skip
> -	 * this step.
> -	 */
> -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> -		ret = 0; /* NOOP */
> -	else if (DISPLAY_VER(display) >= 11)
> -		ret = skl_cdclk_pcode_pre_notify(display);
> -	else
> -		ret = bxt_cdclk_pcode_pre_notify(display);
> -
> -	if (ret) {
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> +	ret = intel_cdclk_pre_notify(display);
> +	if (ret)
>  		return;
> -	}
>  
>  	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
>  		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
> @@ -2323,16 +2328,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
>  		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
>  
> -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> -		ret = 0; /* NOOP */
> -	else if (DISPLAY_VER(display) >= 11)
> -		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
> -	else
> -		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
> -
> -	if (ret)
> -		drm_err(display->drm,
> -			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
> +	intel_cdclk_post_notify(display, cdclk_config);
>  
>  	intel_update_cdclk(display);
>  
> @@ -3929,9 +3925,25 @@ static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
>  	.calc_voltage_level = xe3lpd_calc_voltage_level,
>  };
>  
> +static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = rplu_calc_voltage_level,
> +};
> +
> +static const struct intel_cdclk_funcs dg2_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = tgl_calc_voltage_level,
> +};
> +
>  static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> +	.pre_notify = skl_cdclk_pcode_pre_notify,
> +	.post_notify = skl_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = rplu_calc_voltage_level,
>  };
> @@ -3939,6 +3951,8 @@ static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
>  static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> +	.pre_notify = skl_cdclk_pcode_pre_notify,
> +	.post_notify = skl_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = tgl_calc_voltage_level,
>  };
> @@ -3946,6 +3960,8 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> +	.pre_notify = skl_cdclk_pcode_pre_notify,
> +	.post_notify = skl_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = ehl_calc_voltage_level,
>  };
> @@ -3953,6 +3969,8 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs icl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> +	.pre_notify = skl_cdclk_pcode_pre_notify,
> +	.post_notify = skl_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = icl_calc_voltage_level,
>  };
> @@ -3960,6 +3978,8 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> +	.pre_notify = bxt_cdclk_pcode_pre_notify,
> +	.post_notify = bxt_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = bxt_calc_voltage_level,
>  };
> @@ -3967,12 +3987,16 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
>  static const struct intel_cdclk_funcs skl_cdclk_funcs = {
>  	.get_cdclk = skl_get_cdclk,
>  	.set_cdclk = skl_set_cdclk,
> +	.pre_notify = skl_cdclk_pcode_pre_notify,
> +	.post_notify = skl_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
>  	.get_cdclk = bdw_get_cdclk,
>  	.set_cdclk = bdw_set_cdclk,
> +	.pre_notify = bdw_cdclk_pcode_pre_notify,
> +	.post_notify = bdw_cdclk_pcode_post_notify,
>  	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
>  };
>  
> @@ -4078,16 +4102,16 @@ void intel_init_cdclk_hooks(struct intel_display *display)
>  		display->cdclk.funcs = &xe3lpd_cdclk_funcs;
>  		display->cdclk.table = xe3lpd_cdclk_table;
>  	} else if (DISPLAY_VER(display) >= 20) {
> -		display->cdclk.funcs = &rplu_cdclk_funcs;
> +		display->cdclk.funcs = &mtl_cdclk_funcs;
>  		display->cdclk.table = xe2lpd_cdclk_table;
>  	} else if (DISPLAY_VERx100(display) >= 1401) {
> -		display->cdclk.funcs = &rplu_cdclk_funcs;
> +		display->cdclk.funcs = &mtl_cdclk_funcs;
>  		display->cdclk.table = xe2hpd_cdclk_table;
>  	} else if (DISPLAY_VER(display) >= 14) {
> -		display->cdclk.funcs = &rplu_cdclk_funcs;
> +		display->cdclk.funcs = &mtl_cdclk_funcs;
>  		display->cdclk.table = mtl_cdclk_table;
>  	} else if (display->platform.dg2) {
> -		display->cdclk.funcs = &tgl_cdclk_funcs;
> +		display->cdclk.funcs = &dg2_cdclk_funcs;
>  		display->cdclk.table = dg2_cdclk_table;
>  	} else if (display->platform.alderlake_p) {
>  		/* Wa_22011320316:adl-p[a0] */

-- 
Jani Nikula, Intel

Re: [PATCH 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that intel_cdclk_{pre,post}_notify() are implemented via vfuncs
> there is no need to keep them inside the .set_cdclk() hooks. Move
> the calls one level up to intel_cdclk_set_cdclk().
>
> We do need to adjust {skl,bxt}_cdclk_(un)init_hw() to call the wrapper
> rather than the low level implementation directly, or else they would
> not do the pcode notification anymore.
>
> The two slight functions changes here are:
> - bdw_set_cdclk() might theoretically bail out after doing the
>   pre notification, but that codepath would only come into play
>   if the hardware is seriously misprogrammed, so should never happen
> - cdclk hw readout is still done from .set_cdclk(), so that now
>   happens before the post notify vs. previously the readout happened
>   before it. This should not matter as the readout is not affected
>   by the post notify (since we can't actually read out anything from
>   pcode).

Fingers crossed.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 33 ++++++----------------
>  1 file changed, 9 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4154b4888eff..617ad154505c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -209,7 +209,12 @@ static void intel_cdclk_set_cdclk(struct intel_display *display,
>  				  const struct intel_cdclk_config *cdclk_config,
>  				  enum pipe pipe)
>  {
> +	if (intel_cdclk_pre_notify(display))
> +		return;
> +
>  	display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
> +
> +	intel_cdclk_post_notify(display, cdclk_config);
>  }
>  
>  static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
> @@ -933,10 +938,6 @@ static void bdw_set_cdclk(struct intel_display *display,
>  		     "trying to change cdclk frequency with cdclk not enabled\n"))
>  		return;
>  
> -	ret = intel_cdclk_pre_notify(display);
> -	if (ret)
> -		return;
> -
>  	intel_de_rmw(display, LCPLL_CTL,
>  		     0, LCPLL_CD_SOURCE_FCLK);
>  
> @@ -960,8 +961,6 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	intel_cdclk_post_notify(display, cdclk_config);
> -
>  	intel_de_write(display, CDCLK_FREQ,
>  		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>  
> @@ -1218,7 +1217,6 @@ static void skl_set_cdclk(struct intel_display *display,
>  	int cdclk = cdclk_config->cdclk;
>  	int vco = cdclk_config->vco;
>  	u32 freq_select, cdclk_ctl;
> -	int ret;
>  
>  	/*
>  	 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
> @@ -1231,10 +1229,6 @@ static void skl_set_cdclk(struct intel_display *display,
>  	drm_WARN_ON_ONCE(display->drm,
>  			 display->platform.skylake && vco == 8640000);
>  
> -	ret = intel_cdclk_pre_notify(display);
> -	if (ret)
> -		return;
> -
>  	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
>  
>  	if (display->cdclk.hw.vco != 0 &&
> @@ -1270,8 +1264,6 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
> -	intel_cdclk_post_notify(display, cdclk_config);
> -
>  	intel_update_cdclk(display);
>  }
>  
> @@ -1343,7 +1335,7 @@ static void skl_cdclk_init_hw(struct intel_display *display)
>  	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
>  	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
>  
> -	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> +	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
>  }
>  
>  static void skl_cdclk_uninit_hw(struct intel_display *display)
> @@ -1354,7 +1346,7 @@ static void skl_cdclk_uninit_hw(struct intel_display *display)
>  	cdclk_config.vco = 0;
>  	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
>  
> -	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> +	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
>  }
>  
>  struct intel_cdclk_vals {
> @@ -2308,11 +2300,6 @@ static void bxt_set_cdclk(struct intel_display *display,
>  {
>  	struct intel_cdclk_config mid_cdclk_config;
>  	int cdclk = cdclk_config->cdclk;
> -	int ret;
> -
> -	ret = intel_cdclk_pre_notify(display);
> -	if (ret)
> -		return;
>  
>  	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
>  		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
> @@ -2328,8 +2315,6 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
>  		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
>  
> -	intel_cdclk_post_notify(display, cdclk_config);
> -
>  	intel_update_cdclk(display);
>  
>  	/*
> @@ -2413,7 +2398,7 @@ static void bxt_cdclk_init_hw(struct intel_display *display)
>  	cdclk_config.voltage_level =
>  		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
>  
> -	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> +	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
>  }
>  
>  static void bxt_cdclk_uninit_hw(struct intel_display *display)
> @@ -2425,7 +2410,7 @@ static void bxt_cdclk_uninit_hw(struct intel_display *display)
>  	cdclk_config.voltage_level =
>  		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
>  
> -	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
> +	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
>  }
>  
>  /**

-- 
Jani Nikula, Intel

Re: [PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Jani Nikula]

On Wed, 10 Jun 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> We already changed the actual cdclk frequency by the time we do
>> the pcode post notify. So skipping the subsequent readout is plain
>> wrong.
>
> Fixes: ?

Turns out posing the question about Fixes: trailer like that leads to b4
shazam literally adding that trailer. Please clean them up before
pushing!

Cc: tools@k.o and Konstantin, FYI


BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Konstantin Ryabitsev]

On Wed, Jun 17, 2026 at 04:29:16PM +0300, Jani Nikula wrote:
> >> We already changed the actual cdclk frequency by the time we do
> >> the pcode post notify. So skipping the subsequent readout is plain
> >> wrong.
> >
> > Fixes: ?
> 
> Turns out posing the question about Fixes: trailer like that leads to b4
> shazam literally adding that trailer. Please clean them up before
> pushing!
> 
> Cc: tools@k.o and Konstantin, FYI

We now recognize this and properly change this to:

| Fixes: ¯\_(ツ)_/¯

(Just kidding... I'll see if I can clean this up to be more discerning of the
actual Fixes: format.)

Thanks,
-K